1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
|
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h,v 1.15 2003/04/23 21:51:29 tsi Exp $ */
/*
* Copyright 2000 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that copyright
* notice and this permission notice appear in supporting documentation, and
* that the name of Marc Aurele La France not be used in advertising or
* publicity pertaining to distribution of the software without specific,
* written prior permission. Marc Aurele La France makes no representations
* about the suitability of this software for any purpose. It is provided
* "as-is" without express or implied warranty.
*
* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* DRI support by:
* Manuel Teira
* Leif Delgass <ldelgass@retinalburn.net>
*/
#ifndef ___ATIMACH64IO_H___
#if !defined(___ATI_H___) && defined(XFree86Module)
# error Missing #include "ati.h" before #include "atimach64io.h"
# undef XFree86Module
#endif
#define ___ATIMACH64IO_H___ 1
#include "atiio.h"
#include "atistruct.h"
/*
* A few important notes on some of the I/O statements provided:
*
* inl/outl 32-bit R/W through PIO space. The register is specified as the
* actual PIO address. These are actually defined in compiler.h.
*
* inw/outw 16-bit counterparts to inl/outl. Not used for Mach64 support.
*
* inb/outb 8-bit counterparts to inl/outl.
*
* inm/outm 32-bit R/W through MMIO space. The register is specified as
* the actual MMIO offset (with Block 1 following Block 0), which,
* in this case, is equivalent to the register's IOPortTag from
* atiregs.h. Can be used for those few non-FIFO'ed registers
* outside of Block 0's first 256 bytes. inm() can also be used
* for FIFO'ed registers if, and only if, it can be guaranteed to
* not have been previously FIFO'ed (e.g. when the engine is
* idle). pATI->pBlock array elements must have been previously
* set up by ATIMapApertures().
*
* outf 32-bit write through MMIO cache. Identical to outm() but
* intended for FIFO'ed registers. There is no inf() provided.
*
* inr/outr 32-bit R/W through PIO or MMIO. Which one depends on the
* machine architecture. The register is specified as a IOPortTag
* from atiregs.h. Can only be used for registers in the first
* 256 bytes of MMIO space (in Block 0). Note that all of these
* registers are non-FIFO'ed.
*
* in8/out8 8-bit counterparts to inr/outr.
*
* For portability reasons, inr/outr/in8/out8 should be used in preference to
* inl/outl/inb/outb to/from any register space starting with CRTC_H_TOTAL_DISP
* but before DST_OFF_PITCH (in the order defined by atiregs.h). None of
* inm/outm/outf should ever be used for these registers.
*
* outf()'s should be grouped together as much as possible, while respecting
* any ordering constraints the engine might impose. Groups larger than 16
* outf()'s should be split up into two or more groups as needed (but not
* necessarily wanted). The outf() groups that result should be immediately
* preceeded by an ATIMach64WaitForFIFO(n) call, where "n" is the number of
* outf()'s in the group with the exception that groups containing a single
* outf() should not be thus preceeded. This means "n" should not be less than
* 2, nor larger than 16.
*/
/*
* Cave canem (or it WILL bite you): All Mach64 non-VGA registers are
* ================================ little-endian, no matter how they are
* accessed (nor by what).
*/
#define inm(_Register) \
MMIO_IN32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
(_Register) & MM_IO_SELECT)
#define outm(_Register, _Value) \
MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
(_Register) & MM_IO_SELECT, _Value)
#ifdef AVOID_CPIO
# define inr(_Register) \
MMIO_IN32(pATI->pBlock[0], (_Register) & MM_IO_SELECT)
# define outr(_Register, _Value) \
MMIO_OUT32(pATI->pBlock[0], (_Register) & MM_IO_SELECT, _Value)
# define in8(_Register) \
MMIO_IN8(pATI->pBlock[0], \
(_Register) & (MM_IO_SELECT | IO_BYTE_SELECT))
# define out8(_Register, _Value) \
MMIO_OUT8(pATI->pBlock[0], \
(_Register) & (MM_IO_SELECT | IO_BYTE_SELECT), _Value)
/* Cause a cpp syntax error if any of these are used */
#undef inb
#undef inw
#undef inl
#undef outb
#undef outw
#undef outl
#define inb() /* Nothing */
#define inw() /* Nothing */
#define inl() /* Nothing */
#define outb() /* Nothing */
#define outw() /* Nothing */
#define outl() /* Nothing */
#else /* AVOID_CPIO */
# define ATIIOPort(_PortTag) \
(((pATI->CPIODecoding == SPARSE_IO) ? \
((_PortTag) & (SPARSE_IO_SELECT | IO_BYTE_SELECT)) : \
((_PortTag) & (BLOCK_IO_SELECT | IO_BYTE_SELECT))) | \
pATI->CPIOBase)
# define inr(_Register) \
inl(ATIIOPort(_Register))
# define outr(_Register, _Value) \
outl(ATIIOPort(_Register), _Value)
# define in8(_Register) \
inb(ATIIOPort(_Register))
# define out8(_Register, _Value) \
outb(ATIIOPort(_Register), _Value)
#endif /* AVOID_CPIO */
extern void ATIMach64PollEngineStatus FunctionPrototype((ATIPtr));
/*
* MMIO cache definitions.
*
* Many FIFO'ed registers can be cached by the driver. Registers that qualify
* for caching must not contain values that can change without driver
* intervention. Thus registers that contain hardware counters, strobe lines,
* etc., cannot be cached. This caching is intended to minimise FIFO use.
* There is therefore not much point to enable it for non-FIFO'ed registers.
*
* The cache for a particular 32-bit register is enabled by coding a
* CacheRegister() line for that register in the ATIMach64Set() function. The
* integrity of the cache for a particular register should be verified by the
* ATIMach64Sync() function. This code should be kept in register order, as
* defined in atiregs.h.
*/
#define CacheByte(___Register) pATI->MMIOCached[CacheSlotOf(___Register) >> 3]
#define CacheBit(___Register) (0x80U >> (CacheSlotOf(___Register) & 0x07U))
#define RegisterIsCached(__Register) \
(CacheByte(__Register) & CacheBit(__Register))
#define CacheSlot(__Register) pATI->MMIOCache[CacheSlotOf(__Register)]
#define CacheRegister(__Register) \
CacheByte(__Register) |= CacheBit(__Register)
#define UncacheRegister(__Register) \
CacheByte(__Register) &= ~CacheBit(__Register)
/* This would be quite a bit slower as a function */
#define outf(_Register, _Value) \
do \
{ \
CARD32 _IOValue = (_Value); \
\
if (!RegisterIsCached(_Register) || \
(_IOValue != CacheSlot(_Register))) \
{ \
while (!pATI->nAvailableFIFOEntries--) \
ATIMach64PollEngineStatus(pATI); \
MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
(_Register) & MM_IO_SELECT, _IOValue); \
CacheSlot(_Register) = _IOValue; \
pATI->EngineIsBusy = TRUE; \
} \
} while (0)
/*
* This is no longer as critical, especially for _n == 1. However,
* there is still a need to ensure _n <= pATI->nFIFOEntries.
*/
#define ATIMach64WaitForFIFO(_pATI, _n) \
while ((_pATI)->nAvailableFIFOEntries < (_n)) \
ATIMach64PollEngineStatus(_pATI)
#define ATIMach64WaitForIdle(_pATI) \
while ((_pATI)->EngineIsBusy) \
ATIMach64PollEngineStatus(_pATI)
#ifdef XF86DRI
#define ATIDRIWaitForIdle(_pATI) \
do { \
ATIDRIServerInfoPtr pATIDRIServer = _pATI->pDRIServerInfo; \
int ret; \
\
if (pATIDRIServer && pATI->directRenderingEnabled) { \
/* Wait for DMA to complete */ \
ret = drmCommandNone(_pATI->drmFD, DRM_MACH64_IDLE); \
if (ret) { \
drmCommandNone(_pATI->drmFD, DRM_MACH64_RESET); \
} \
\
/* Force updating of FIFO entry counters */ \
pATI->EngineIsBusy = TRUE; \
ATIMach64PollEngineStatus(_pATI); \
} else { \
ATIMach64WaitForIdle(_pATI); \
} \
} while (0)
#define ATIDRILock(_pScrInfo) \
do \
{ \
ATIPtr _pATI=ATIPTR(_pScrInfo); \
if (_pATI->directRenderingEnabled) \
{ \
DRILock(_pScrInfo->pScreen, 0); \
pATI->NeedDRISync = TRUE; \
} \
} while (0)
#define ATIDRIUnlock(_pScrInfo) \
do \
{ \
ATIPtr _pATI=ATIPTR(_pScrInfo); \
if (_pATI->directRenderingEnabled) \
{ \
DRIUnlock(_pScrInfo->pScreen); \
} \
} while (0)
#define ATIDRISync(_pScrInfo) \
do \
{ \
ATIPtr _pATI=ATIPTR(_pScrInfo); \
if (_pATI->directRenderingEnabled && _pATI->pXAAInfo) \
{ \
if (_pATI->NeedDRISync) (*_pATI->pXAAInfo->Sync)(_pScrInfo); \
} \
} while (0)
#else /* XF86DRI */
#define ATIDRIWaitForIdle(_pATI)
#define ATIDRILock(_pScrInfo)
#define ATIDRIUnlock(_pScrInfo)
#define ATIDRISync(_pScrInfo)
#endif /* XF86DRI */
/*
* An outf() variant to write two registers such that the second register is
* is always written whenever either is to be changed.
*/
#define outq(_Register1, _Register2, _Value1, _Value2) \
do \
{ \
CARD32 _IOValue1 = (_Value1), \
_IOValue2 = (_Value2); \
\
if (!RegisterIsCached(_Register1) || \
(_IOValue1 != CacheSlot(_Register1))) \
{ \
ATIMach64WaitForFIFO(pATI, 2); \
pATI->nAvailableFIFOEntries -= 2; \
MMIO_OUT32(pATI->pBlock[GetBits(_Register1, BLOCK_SELECT)], \
(_Register1) & MM_IO_SELECT, _IOValue1); \
MMIO_OUT32(pATI->pBlock[GetBits(_Register2, BLOCK_SELECT)], \
(_Register2) & MM_IO_SELECT, _IOValue2); \
CacheSlot(_Register1) = _IOValue1; \
CacheSlot(_Register2) = _IOValue2; \
pATI->EngineIsBusy = TRUE; \
} \
else if (!RegisterIsCached(_Register2) || \
(_IOValue2 != CacheSlot(_Register2))) \
{ \
while (!pATI->nAvailableFIFOEntries--) \
ATIMach64PollEngineStatus(pATI); \
MMIO_OUT32(pATI->pBlock[GetBits(_Register2, BLOCK_SELECT)], \
(_Register2) & MM_IO_SELECT, _IOValue2); \
CacheSlot(_Register2) = _IOValue2; \
pATI->EngineIsBusy = TRUE; \
} \
} while (0)
extern void ATIMach64AccessPLLReg FunctionPrototype((ATIPtr, const CARD8,
const Bool));
#define ATIMach64GetPLLReg(_Index) \
( \
ATIMach64AccessPLLReg(pATI, _Index, FALSE), \
in8(CLOCK_CNTL + 2) \
)
#define ATIMach64PutPLLReg(_Index, _Value) \
do \
{ \
ATIMach64AccessPLLReg(pATI, _Index, TRUE); \
out8(CLOCK_CNTL + 2, _Value); \
} while (0)
#define ATIMach64GetLCDReg(_Index) \
( \
out8(LCD_INDEX, SetBits(_Index, LCD_REG_INDEX)), \
inr(LCD_DATA) \
)
#define ATIMach64PutLCDReg(_Index, _Value) \
do \
{ \
out8(LCD_INDEX, SetBits(_Index, LCD_REG_INDEX)); \
outr(LCD_DATA, _Value); \
} while (0)
#define ATIMach64GetTVReg(_Index) \
( \
out8(TV_OUT_INDEX, SetBits(_Index, TV_REG_INDEX)), \
inr(TV_OUT_DATA) \
)
#define ATIMach64PutTVReg(_Index, _Value) \
do \
{ \
out8(TV_OUT_INDEX, SetBits(_Index, TV_REG_INDEX)); \
outr(TV_OUT_DATA, _Value); \
} while (0)
/*
* Block transfer definitions.
*/
#if defined(GCCUSESGAS) && \
(defined(i386) || defined(__i386) || defined(__i386__))
#define ATIMove32(_pDst, _pSrc, _nCount) \
do \
{ \
long d0, d1, d2; \
__asm__ __volatile__ \
( \
"cld\n\t" \
"rep ; movsl" \
: "=&c" (d0), \
"=&D" (d1), \
"=&S" (d2) \
: "0" (_nCount), \
"1" (_pDst), \
"2" (_pSrc) \
: "memory" \
); \
} while (0)
#endif
#endif /* ___ATIMACH64IO_H___ */
|
