diff options
Diffstat (limited to 'src/r6xx_accel.c')
| -rw-r--r-- | src/r6xx_accel.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index b34b6c5e..86817bdb 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -260,3 +260,3 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_ END_BATCH(); - BEGIN_BATCH(12); + BEGIN_BATCH(9); // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib @@ -266,3 +266,2 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_ (0 << SLICE_MAX_shift))); - EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | @@ -270,2 +269,8 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_ END_BATCH(); + + BEGIN_BATCH(3 + 2); + EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); + RELOC_BATCH(cb_conf->bo, 0, domain); + END_BATCH(); + } @@ -887,3 +892,9 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) - BEGIN_BATCH(83); + /* set fake reloc for unused depth */ + BEGIN_BATCH(3 + 2); + EREG(ib, DB_DEPTH_INFO, 0); + RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); + END_BATCH(); + + BEGIN_BATCH(80); if (info->ChipFamily < CHIP_FAMILY_RV770) { @@ -930,3 +941,2 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) // DB - EREG(ib, DB_DEPTH_INFO, 0); EREG(ib, DB_DEPTH_CONTROL, 0); |