radeon: add shared support to pixmaps.

this just adds the interface and shared support to the pixmap.

Signed-off-by: Dave Airlie <airlied@redhat.com>

4 files changed, 41 insertions, 7 deletions

diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index f906cbf2..40e2e96e 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -480,7 +480,10 @@ EVERGREENPrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
     dst_obj.width = pDst->drawable.width;
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = pDst->drawable.bitsPerPixel;
-    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
+    if (radeon_get_pixmap_shared(pDst) == TRUE)
+        dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+    else
+        dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 
     if (!R600SetAccelState(pScrn,
                            &src_obj,
@@ -1157,7 +1160,10 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     dst_obj.width = pDst->drawable.width;
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = pDst->drawable.bitsPerPixel;
-    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
+    if (radeon_get_pixmap_shared(pDst) == TRUE)
+        dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+    else
+        dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 
     if (pMaskPicture) {
         if (!pMask) {
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 61b6315c..be0a9fae 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -551,7 +551,10 @@ R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
     dst_obj.width = pDst->drawable.width;
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = pDst->drawable.bitsPerPixel;
-    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
+    if (radeon_get_pixmap_shared(pDst) == TRUE) {
+        dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+    } else
+        dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 
     if (!R600SetAccelState(pScrn,
                            &src_obj,
@@ -1203,7 +1206,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
     dst_obj.width = pDst->drawable.width;
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = pDst->drawable.bitsPerPixel;
-    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
+    if (radeon_get_pixmap_shared(pDst) == TRUE)
+        dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+    else
+        dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 
     if (pMaskPicture) {
         if (!pMask) {
diff --git a/src/radeon.h b/src/radeon.h
index 2f05249e..2eac38e5 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -249,6 +249,7 @@ struct radeon_exa_pixmap_priv {
     uint32_t tiling_flags;
     struct radeon_surface surface;
     Bool bo_mapped;
+    Bool shared;
 };
 
 #define RADEON_2D_EXA_COPY 1
@@ -266,6 +267,7 @@ struct radeon_2d_state {
     uint32_t dp_src_frgd_clr;
     uint32_t dp_src_bkgd_clr;
     uint32_t default_sc_bottom_right;
+    uint32_t dst_domain;
     struct radeon_bo *dst_bo;
     struct radeon_bo *src_bo;
 };
@@ -624,6 +626,23 @@ static inline struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
     return NULL;
 }
 
+static inline Bool radeon_get_pixmap_shared(PixmapPtr pPix)
+{
+#ifdef USE_GLAMOR
+    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
+
+    if (info->use_glamor) {
+        ErrorF("glamor sharing todo\n");
+        return FALSE:
+    } else
+#endif
+    {
+        struct radeon_exa_pixmap_priv *driver_priv;
+        driver_priv = exaGetPixmapDriverPrivate(pPix);
+        return driver_priv->shared;
+    }
+    return FALSE;
+}
 
 #define CP_PACKET0(reg, n)                                              \
         (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 4c13a000..db44d948 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -80,7 +80,7 @@ static void Emit2DState(ScrnInfoPtr pScrn, int op)
     OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
 
     OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
-    OUT_RING_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+    OUT_RING_RELOC(info->state_2d.dst_bo, 0, info->state_2d.dst_domain);
 
     if (has_src) {
         OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
@@ -145,8 +145,10 @@ RADEONPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
         RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
 
     driver_priv = exaGetPixmapDriverPrivate(pPix);
-    if (driver_priv)
+    if (driver_priv) {
         info->state_2d.dst_bo = driver_priv->bo;
+        info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
+    }
 
     info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX |
                                                RADEON_DEFAULT_SC_BOTTOM_MAX);
@@ -258,8 +260,9 @@ RADEONPrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
     info->state_2d.src_bo = driver_priv->bo;
 
     driver_priv = exaGetPixmapDriverPrivate(pDst);
-    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
     info->state_2d.dst_bo = driver_priv->bo;
+    info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
+    radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, info->state_2d.dst_domain);
 
     ret = radeon_cs_space_check(info->cs);
     if (ret)