r6xx/r7xx: add support for tiling with kms (v3)

Requires radeon drm 2.6.0 and updated mesa.

v2: - fix lockup due to not emiting DB_DEPTH_INFO
https://bugs.freedesktop.org/show_bug.cgi?id=28342
    - fix drm minor version to deal with evergreen accel
v3: rebase on current ddx git

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>

8 files changed, 150 insertions, 26 deletions

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e2d516b4..6a4a32d1 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1103,4 +1103,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 
-	if (info->allowColorTiling)
-	    tiling_flags |= RADEON_TILING_MACRO;
+	/* no tiled scanout on r6xx+ yet */
+	if (info->allowColorTiling) {
+		if (info->ChipFamily < CHIP_FAMILY_R600)
+			tiling_flags |= RADEON_TILING_MACRO;
+	}
 #if X_BYTE_ORDER == X_BIG_ENDIAN
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 638bd382..911dba08 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2153,2 +2153,5 @@ R600DrawInit(ScreenPtr pScreen)
 	info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
+#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5)
+        info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
+#endif
     } else
diff --git a/src/r600_state.h b/src/r600_state.h
index 4e65bc1f..151f402a 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -332,2 +332,5 @@ extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
 extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
+extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
+				    int depth, int usage_hint, int bitsPerPixel,
+				    int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index b34b6c5e..86817bdb 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -260,3 +260,3 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
     END_BATCH();
-    BEGIN_BATCH(12);
+    BEGIN_BATCH(9);
     // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
@@ -266,3 +266,2 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
 						    (0    << SLICE_MAX_shift)));
-    EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
     EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0    << CMASK_BLOCK_MAX_shift)	|
@@ -270,2 +269,8 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
     END_BATCH();
+
+    BEGIN_BATCH(3 + 2);
+    EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
+    RELOC_BATCH(cb_conf->bo, 0, domain);
+    END_BATCH();
+
 }
@@ -887,3 +892,9 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 
-    BEGIN_BATCH(83);
+    /* set fake reloc for unused depth */
+    BEGIN_BATCH(3 + 2);
+    EREG(ib, DB_DEPTH_INFO, 0);
+    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+    END_BATCH();
+
+    BEGIN_BATCH(80);
     if (info->ChipFamily < CHIP_FAMILY_RV770) {
@@ -930,3 +941,2 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
     // DB
-    EREG(ib, DB_DEPTH_INFO,                       0);
     EREG(ib, DB_DEPTH_CONTROL,                    0);
diff --git a/src/radeon.h b/src/radeon.h
index 55d673a3..d66cdd93 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1037,2 +1037,8 @@ typedef struct {
     drmmode_rec drmmode;
+    /* r6xx+ tile config */
+    uint32_t tile_config;
+    int group_bytes;
+    int num_channels;
+    int num_banks;
+    int r7xx_bank_op;
 #else
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index a0ed0857..9697bbc8 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -103,3 +103,6 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
 	    case DRI2BufferDepthStencil:
-		flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+		if (info->ChipFamily >= CHIP_FAMILY_R600)
+		    flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+		else
+		    flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
 		break;
@@ -185,3 +188,6 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
 	case DRI2BufferDepthStencil:
-	    flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+		if (info->ChipFamily >= CHIP_FAMILY_R600)
+		    flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+		else
+		    flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
 	    break;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 7dd792e6..814c8641 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -432,7 +432,23 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 
-    if (tiling) {
-	height = RADEON_ALIGN(height, 16);
-	pixmap_align = 256;
-    } else
-	pixmap_align = 64;
+    if (info->ChipFamily >= CHIP_FAMILY_R600) {
+	int bpe = bitsPerPixel / 8;
+
+	if (tiling & RADEON_TILING_MACRO) {
+	    height = RADEON_ALIGN(height, info->num_banks * 8);
+	    pixmap_align = MAX(info->num_banks,
+			       (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8 * bpe;
+	} else if (tiling & RADEON_TILING_MICRO) {
+	    height = RADEON_ALIGN(height, 8);
+	    pixmap_align = MAX(8, (info->group_bytes / (8 * bpe))) * bpe;
+	} else {
+	    height = RADEON_ALIGN(height, 8);
+	    pixmap_align = 256; /* 8 * bpe */
+	}
+    } else {
+	if (tiling) {
+	    height = RADEON_ALIGN(height, 16);
+	    pixmap_align = 256;
+	} else
+	    pixmap_align = 64;
+    }
 
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 772be8ff..ba13071f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -423,2 +423,70 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
 
+static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info   = RADEONPTR(pScrn);
+    struct drm_radeon_info ginfo;
+    int r;
+    uint32_t tmp;
+
+    if (info->ChipFamily < CHIP_FAMILY_R600)
+	return FALSE;
+
+#ifndef RADEON_INFO_TILING_CONFIG
+#define RADEON_INFO_TILING_CONFIG 0x6
+#endif
+
+    memset(&ginfo, 0, sizeof(ginfo));
+    ginfo.request = RADEON_INFO_TILING_CONFIG;
+    ginfo.value = (uintptr_t)&tmp;
+    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
+    if (r)
+	return FALSE;
+
+    info->tile_config = tmp;
+    info->r7xx_bank_op = 0;
+    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+	/* for now */
+	return FALSE;
+    } else {
+	switch((info->tile_config & 0xe) >> 1) {
+	case 0:
+	    info->num_channels = 1;
+	    break;
+	case 1:
+	    info->num_channels = 2;
+	    break;
+	case 2:
+	    info->num_channels = 4;
+	    break;
+	case 3:
+	    info->num_channels = 8;
+	    break;
+	default:
+	    return FALSE;
+	}
+	switch((info->tile_config & 0x30) >> 4) {
+	case 0:
+	    info->num_banks = 4;
+	    break;
+	case 1:
+	    info->num_banks = 8;
+	    break;
+	default:
+	    return FALSE;
+	}
+	switch((info->tile_config & 0xc0) >> 6) {
+	case 0:
+	    info->group_bytes = 256;
+	    break;
+	case 1:
+	    info->group_bytes = 512;
+	    break;
+	default:
+	    return FALSE;
+	}
+    }
+
+    return TRUE;
+}
+
 Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
@@ -486,14 +554,2 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
 
-    colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
-                         info->ChipFamily <= CHIP_FAMILY_RS740;
-
-    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
-                                        OPTION_COLOR_TILING, colorTilingDefault);
-    if (info->ChipFamily >= CHIP_FAMILY_R600) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Color tiling is not yet supported on R600/R700\n");
-	    info->allowColorTiling = FALSE;
-    }
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
-
     if (radeon_open_drm_master(pScrn) == FALSE) {
@@ -511,2 +567,21 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
 
+    colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
+                         info->ChipFamily <= CHIP_FAMILY_RS740;
+
+    if (info->ChipFamily >= CHIP_FAMILY_R600) {
+	if (info->dri->pKernelDRMVersion->version_minor >= 6) {
+	    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+							  OPTION_COLOR_TILING, colorTilingDefault);
+	    if (info->allowColorTiling)
+		info->allowColorTiling = r600_get_tile_config(pScrn);
+	} else
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+		       "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
+    } else
+	info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+						      OPTION_COLOR_TILING, colorTilingDefault);
+
+    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
+
     if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
@@ -1040,4 +1115,6 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
         }
+	/* no tiled scanout on r6xx+ yet */
         if (info->allowColorTiling) {
-	    tiling_flags |= RADEON_TILING_MACRO;
+	    if (info->ChipFamily < CHIP_FAMILY_R600)
+		tiling_flags |= RADEON_TILING_MACRO;
         }