vmwgfx: Standardise modesetting

4 files changed, 44 insertions, 53 deletions

diff --git a/vmwgfx_drv.h b/vmwgfx_drv.h
index 0322a2b..28a0041 100644
--- a/vmwgfx_drv.h
+++ b/vmwgfx_drv.h
@@ -468,6 +468,9 @@ void vmw_kms_cursor_snoop(struct vmw_surface *srf,
 			  struct ttm_object_file *tfile,
 			  struct ttm_buffer_object *bo,
 			  SVGA3dCmdHeader *header);
+void vmw_kms_write_svga(struct vmw_private *vmw_priv,
+			unsigned width, unsigned height, unsigned pitch,
+			unsigned bbp, unsigned depth);
 
 /**
  * Overlay control - vmwgfx_overlay.c
diff --git a/vmwgfx_fb.c b/vmwgfx_fb.c
index ebf54ab..ca6fe58 100644
--- a/vmwgfx_fb.c
+++ b/vmwgfx_fb.c
@@ -165,17 +165,9 @@ static int vmw_fb_set_par(struct fb_info *info)
 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, 0);
 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
 
-		if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
-			vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, info->fix.line_length);
-		else if (vmw_fifo_have_pitchlock(vmw_priv))
-			iowrite32(info->fix.line_length, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
-		vmw_write(vmw_priv, SVGA_REG_WIDTH, par->max_width);
-		vmw_write(vmw_priv, SVGA_REG_HEIGHT, par->max_height);
-		vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, par->bpp);
-		vmw_write(vmw_priv, SVGA_REG_DEPTH, par->depth);
-		vmw_write(vmw_priv, SVGA_REG_RED_MASK, 0x00ff0000);
-		vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
-		vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
+		vmw_kms_write_svga(vmw_priv, info->var.xres, info->var.yres,
+				   info->fix.line_length,
+				   par->bpp, par->depth);
 
 		/* TODO check if pitch and offset changes */
 		vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, 0);
@@ -189,18 +181,11 @@ static int vmw_fb_set_par(struct fb_info *info)
 		vmw_write(vmw_priv, SVGA_REG_ENABLE, 1);
 	} else {
 		vmw_write(vmw_priv, SVGA_REG_ENABLE, 0);
-		if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
-			vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, info->fix.line_length);
-		else if (vmw_fifo_have_pitchlock(vmw_priv))
-			iowrite32(info->fix.line_length, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
-		vmw_write(vmw_priv, SVGA_REG_WIDTH, info->var.xres);
-		vmw_write(vmw_priv, SVGA_REG_HEIGHT, info->var.yres);
-		vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, par->bpp);
-		vmw_write(vmw_priv, SVGA_REG_DEPTH, par->depth);
-		vmw_write(vmw_priv, SVGA_REG_RED_MASK, 0x00ff0000);
-		vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
-		vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
+		vmw_kms_write_svga(vmw_priv, info->var.xres, info->var.yres,
+				   info->fix.line_length,
+				   par->bpp, par->depth);
 		vmw_write(vmw_priv, SVGA_REG_ENABLE, 1);
+
 	}
 
 	/* This is really helpfull as if this is fails the user
diff --git a/vmwgfx_kms.c b/vmwgfx_kms.c
index a527837..d10f0db 100644
--- a/vmwgfx_kms.c
+++ b/vmwgfx_kms.c
@@ -601,24 +601,6 @@ static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
 
 	ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer);
 
-	if (dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) {
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, 0);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, true);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, 0);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, 0);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, 0);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, 0);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
-
-		vmw_write(dev_priv, SVGA_REG_WIDTH, vfb->base.width);
-		vmw_write(dev_priv, SVGA_REG_HEIGHT, vfb->base.height);
-		vmw_write(dev_priv, SVGA_REG_BITS_PER_PIXEL, vfb->base.bits_per_pixel);
-		vmw_write(dev_priv, SVGA_REG_DEPTH, vfb->base.depth);
-		vmw_write(dev_priv, SVGA_REG_RED_MASK, 0x00ff0000);
-		vmw_write(dev_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
-		vmw_write(dev_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
-	} /* ldu code takes care of !DISPLAY_TOPOLOGY case */
-
 	vmw_overlay_resume_all(dev_priv);
 
 	return 0;
@@ -830,6 +812,23 @@ out:
 	return ret;
 }
 
+void vmw_kms_write_svga(struct vmw_private *vmw_priv,
+			unsigned width, unsigned height, unsigned pitch,
+			unsigned bbp, unsigned depth)
+{
+	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
+		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
+	else if (vmw_fifo_have_pitchlock(vmw_priv))
+		iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
+	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
+	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
+	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bbp);
+	vmw_write(vmw_priv, SVGA_REG_DEPTH, depth);
+	vmw_write(vmw_priv, SVGA_REG_RED_MASK, 0x00ff0000);
+	vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
+	vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
+}
+
 int vmw_kms_save_vga(struct vmw_private *vmw_priv)
 {
 	vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
diff --git a/vmwgfx_ldu.c b/vmwgfx_ldu.c
index a101f3e..a661b32 100644
--- a/vmwgfx_ldu.c
+++ b/vmwgfx_ldu.c
@@ -89,6 +89,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
 {
 	struct vmw_legacy_display *lds = dev_priv->ldu_priv;
 	struct vmw_legacy_display_unit *entry;
+	struct drm_framebuffer *fb = NULL;
 	struct drm_crtc *crtc = NULL;
 	int i = 0;
 
@@ -106,25 +107,18 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
 
 		if (crtc == NULL)
 			return 0;
+		fb = entry->base.crtc.fb;
 
 		vmw_write(dev_priv, SVGA_REG_ENABLE, 0);
-		if (dev_priv->capabilities & SVGA_CAP_PITCHLOCK)
-			vmw_write(dev_priv, SVGA_REG_PITCHLOCK, crtc->fb->pitch);
-		else if (vmw_fifo_have_pitchlock(dev_priv))
-			iowrite32(crtc->fb->pitch, dev_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
-
-		vmw_write(dev_priv, SVGA_REG_WIDTH, w);
-		vmw_write(dev_priv, SVGA_REG_HEIGHT, h);
-		vmw_write(dev_priv, SVGA_REG_BITS_PER_PIXEL, crtc->fb->bits_per_pixel);
-		vmw_write(dev_priv, SVGA_REG_DEPTH, crtc->fb->depth);
-		vmw_write(dev_priv, SVGA_REG_RED_MASK, 0x00ff0000);
-		vmw_write(dev_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
-		vmw_write(dev_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
+		vmw_kms_write_svga(dev_priv, w, h, fb->pitch,
+				   fb->bits_per_pixel, fb->depth);
 		vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 
 		return 0;
 	}
 
+	vmw_write(dev_priv, SVGA_REG_ENABLE, 0);
+
 	for (i = 0; i < lds->last_num_active; i++) {
 		vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i);
 		vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i);
@@ -135,6 +129,14 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
 		vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
 	}
 
+	if (!list_empty(&lds->active)) {
+		entry = list_entry(lds->active.next, typeof(*entry), active);
+		fb = entry->base.crtc.fb;
+
+		vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitch,
+				   fb->bits_per_pixel, fb->depth);
+	}
+
 	i = 0;
 	list_for_each_entry(entry, &lds->active, active) {
 		crtc = &entry->base.crtc;
@@ -150,7 +152,9 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
 		i++;
 	}
 
-	vmw_write(dev_priv, SVGA_REG_ENABLE, i ? 1 : 0);
+	/* Make sure we always show something */
+	vmw_write(vmw_priv, SVGA_REG_NUM_GUEST_DISPLAYS, i ? i : 1);
+	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 
 	BUG_ON(i != lds->num_active);