From 2591a52560cc26a74e1a937f4e1429a11e54bb66 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 18 Mar 2022 08:34:26 +0100 Subject: radv: fix enabling adjust_frag_coord_z and apply per-pipeline Fossilize always enables all supported extensions, that means that adjust_frag_coord_z would always be enabled on RDNA2, even if the application doesn't enable it. The pipeline key would then be different and precompilation wouldn't work. Move this per-pipeline since we can know if VRS will be used. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_device.c | 6 ------ src/amd/vulkan/radv_pipeline.c | 8 +++++++- src/amd/vulkan/radv_private.h | 5 ----- src/amd/vulkan/radv_shader.c | 4 ++-- src/amd/vulkan/radv_shader.h | 2 +- src/amd/vulkan/radv_shader_info.c | 2 +- 6 files changed, 11 insertions(+), 16 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index b72e1091270..48cfcaf7998 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3419,12 +3419,6 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr } } - device->adjust_frag_coord_z = - (device->vk.enabled_extensions.KHR_fragment_shading_rate || device->force_vrs_enabled) && - (device->physical_device->rad_info.family == CHIP_SIENNA_CICHLID || - device->physical_device->rad_info.family == CHIP_NAVY_FLOUNDER || - device->physical_device->rad_info.family == CHIP_VANGOGH); - /* PKT3_LOAD_SH_REG_INDEX is supported on GFX8+, but it hangs with compute queues until GFX10.3. */ device->load_grid_size_from_user_sgpr = device->physical_device->rad_info.chip_class >= GFX10_3; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 703cb7a3489..b0ef066d375 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2940,6 +2940,7 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_blend_state *blend) { + struct radv_device *device = pipeline->device; const VkPipelineRenderingCreateInfo *render_create_info = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO); bool uses_dynamic_stride = false; @@ -3083,7 +3084,12 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, key.invariant_geom = true; key.use_ngg = pipeline->device->physical_device->use_ngg; - key.adjust_frag_coord_z = pipeline->device->adjust_frag_coord_z; + + if ((radv_is_vrs_enabled(pipeline, pCreateInfo) || device->force_vrs_enabled) && + (device->physical_device->rad_info.family == CHIP_SIENNA_CICHLID || + device->physical_device->rad_info.family == CHIP_NAVY_FLOUNDER || + device->physical_device->rad_info.family == CHIP_VANGOGH)) + key.adjust_frag_coord_z = true; return key; } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 4f2581c33d8..b12da2d248b 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -818,11 +818,6 @@ struct radv_device { bool robust_buffer_access; bool robust_buffer_access2; - /* Whether gl_FragCoord.z should be adjusted for VRS due to a hw bug - * on some GFX10.3 chips. - */ - bool adjust_frag_coord_z; - /* Whether to inline the compute dispatch size in user sgprs. */ bool load_grid_size_from_user_sgpr; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index f846445f950..9e9101632e8 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -2356,7 +2356,7 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader, } unsigned -radv_compute_spi_ps_input(const struct radv_device *device, +radv_compute_spi_ps_input(const struct radv_pipeline_key *pipeline_key, const struct radv_shader_info *info) { unsigned spi_ps_input; @@ -2379,7 +2379,7 @@ radv_compute_spi_ps_input(const struct radv_device *device, spi_ps_input |= S_0286CC_POS_X_FLOAT_ENA(1) << i; } - if (device->adjust_frag_coord_z && info->ps.reads_frag_coord_mask & (1 << 2)) { + if (pipeline_key->adjust_frag_coord_z && info->ps.reads_frag_coord_mask & (1 << 2)) { spi_ps_input |= S_0286CC_ANCILLARY_ENA(1); } } diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 6cccc10e34d..85733377500 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -574,7 +574,7 @@ unsigned radv_get_max_waves(const struct radv_device *device, struct radv_shader const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage); -unsigned radv_compute_spi_ps_input(const struct radv_device *device, +unsigned radv_compute_spi_ps_input(const struct radv_pipeline_key *pipeline_key, const struct radv_shader_info *info); bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir, bool meta_shader); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index a7e56e27642..0b9ca2ace14 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -676,6 +676,6 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) || BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION)); - info->ps.spi_ps_input = radv_compute_spi_ps_input(device, info); + info->ps.spi_ps_input = radv_compute_spi_ps_input(pipeline_key, info); } } -- cgit v1.2.3