From 0472aa3efe325ba53dc25a20a541f18d30d31b0c Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 13 Feb 2018 18:13:51 -0800 Subject: intel: Drop SURFACE_FORMAT enum from genxml. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen Reviewed-by: Samuel Iglesias Gonsálvez --- src/intel/blorp/blorp_genX_exec.h | 14 +- src/intel/genxml/gen10.xml | 229 +------------------------- src/intel/genxml/gen11.xml | 229 +------------------------- src/intel/genxml/gen4.xml | 222 +------------------------ src/intel/genxml/gen45.xml | 222 +------------------------ src/intel/genxml/gen5.xml | 226 +------------------------ src/intel/genxml/gen6.xml | 228 +------------------------ src/intel/genxml/gen7.xml | 228 +------------------------ src/intel/genxml/gen75.xml | 228 +------------------------ src/intel/genxml/gen8.xml | 228 +------------------------ src/intel/genxml/gen9.xml | 228 +------------------------ src/intel/isl/isl_surface_state.c | 6 +- src/intel/vulkan/genX_gpu_memcpy.c | 2 +- src/intel/vulkan/genX_pipeline.c | 6 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 8 +- 15 files changed, 35 insertions(+), 2269 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 7182399c9c2..1348659233c 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -390,7 +390,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { .VertexBufferIndex = 1, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32A32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, .SourceElementOffset = 0, .Component0Control = VFCOMP_STORE_SRC, @@ -422,7 +422,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { .VertexBufferIndex = 0, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT, .SourceElementOffset = 0, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_SRC, @@ -436,7 +436,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { .VertexBufferIndex = 0, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT, .SourceElementOffset = 0, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_SRC, @@ -461,13 +461,13 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, .SourceElementOffset = 0, .Component0Control = VFCOMP_STORE_SRC, #if GEN_GEN >= 9 - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32A32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, .Component1Control = VFCOMP_STORE_SRC, .Component2Control = VFCOMP_STORE_SRC, .Component3Control = VFCOMP_STORE_SRC, #else /* Clear colors on gen7-8 are for bits out of one dword */ - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32_FLOAT, .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, @@ -479,7 +479,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { .VertexBufferIndex = 1, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32A32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, .SourceElementOffset = 16 + i * 4 * sizeof(float), .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_SRC, @@ -1356,7 +1356,7 @@ blorp_emit_null_surface_state(struct blorp_batch *batch, { struct GENX(RENDER_SURFACE_STATE) ss = { .SurfaceType = SURFTYPE_NULL, - .SurfaceFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R8G8B8A8_UNORM, + .SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM, .Width = surface->surf.logical_level0_px.width - 1, .Height = surface->surf.logical_level0_px.height - 1, .MIPCountLOD = surface->view.base_level, diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 47c679a3fa9..2d36957c2a5 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -180,231 +180,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -462,7 +237,7 @@ - + @@ -685,7 +460,7 @@ - + diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 9a8a2fe21e3..a93b62aa4cf 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -180,231 +180,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -463,7 +238,7 @@ - + @@ -686,7 +461,7 @@ - + diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml index fc24329535d..e1ca810f236 100644 --- a/src/intel/genxml/gen4.xml +++ b/src/intel/genxml/gen4.xml @@ -106,226 +106,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -724,7 +504,7 @@ - + diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index 136cc6f68a3..91dc3634801 100644 --- a/src/intel/genxml/gen45.xml +++ b/src/intel/genxml/gen45.xml @@ -106,226 +106,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -738,7 +518,7 @@ - + diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index 82cda909572..650692f6bda 100644 --- a/src/intel/genxml/gen5.xml +++ b/src/intel/genxml/gen5.xml @@ -106,230 +106,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -834,7 +610,7 @@ - + diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 971cd48352e..088f46f05f1 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -106,230 +106,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -363,7 +139,7 @@ - + @@ -552,7 +328,7 @@ - + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 9e34c169e23..430c2ba73a2 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -138,230 +138,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -407,7 +183,7 @@ - + @@ -610,7 +386,7 @@ - + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index be537aff0ae..e18a49ac4db 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -138,230 +138,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -426,7 +202,7 @@ - + @@ -629,7 +405,7 @@ - + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index c075eecc34a..c0e837906ca 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -154,230 +154,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -452,7 +228,7 @@ - + @@ -651,7 +427,7 @@ - + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 7eef4bee013..faee2acca15 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -180,230 +180,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -461,7 +237,7 @@ - + @@ -683,7 +459,7 @@ - + diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 1f729f89f4f..32a5429f2bf 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -270,7 +270,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, assert(surf_fmtl->bh == view_fmtl->bh); } - s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->view->format; + s.SurfaceFormat = info->view->format; #if GEN_GEN <= 5 s.ColorBufferComponentWriteDisables = info->write_disables; @@ -718,7 +718,7 @@ isl_genX(buffer_fill_state_s)(void *state, struct GENX(RENDER_SURFACE_STATE) s = { 0, }; s.SurfaceType = SURFTYPE_BUFFER; - s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->format; + s.SurfaceFormat = info->format; #if GEN_GEN >= 6 s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; @@ -776,7 +776,7 @@ isl_genX(null_fill_state)(void *state, struct isl_extent3d size) { struct GENX(RENDER_SURFACE_STATE) s = { .SurfaceType = SURFTYPE_NULL, - .SurfaceFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_B8G8R8A8_UNORM, + .SurfaceFormat = ISL_FORMAT_B8G8R8A8_UNORM, #if GEN_GEN >= 7 .SurfaceArray = size.depth > 0, #endif diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 1d527fb1549..eaafcfa3b22 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -172,7 +172,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, &(struct GENX(VERTEX_ELEMENT_STATE)) { .VertexBufferIndex = 32, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) format, + .SourceElementFormat = format, .SourceElementOffset = 0, .Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, .Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 89cbe293b86..412fb6ac0f9 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -138,7 +138,7 @@ emit_vertex_input(struct anv_pipeline *pipeline, struct GENX(VERTEX_ELEMENT_STATE) element = { .VertexBufferIndex = desc->binding, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) format, + .SourceElementFormat = format, .EdgeFlagEnable = false, .SourceElementOffset = desc->offset, .Component0Control = vertex_element_comp_control(format, 0), @@ -184,7 +184,7 @@ emit_vertex_input(struct anv_pipeline *pipeline, struct GENX(VERTEX_ELEMENT_STATE) element = { .VertexBufferIndex = ANV_SVGS_VB_INDEX, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32_UINT, + .SourceElementFormat = ISL_FORMAT_R32G32_UINT, .Component0Control = base_ctrl, .Component1Control = base_ctrl, #if GEN_GEN >= 8 @@ -214,7 +214,7 @@ emit_vertex_input(struct anv_pipeline *pipeline, struct GENX(VERTEX_ELEMENT_STATE) element = { .VertexBufferIndex = ANV_DRAWID_VB_INDEX, .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32_UINT, + .SourceElementFormat = ISL_FORMAT_R32_UINT, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 0abe8e2d557..211fae58e9d 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -572,7 +572,7 @@ genX(emit_vertices)(struct brw_context *brw) 1 + GENX(VERTEX_ELEMENT_STATE_length)); struct GENX(VERTEX_ELEMENT_STATE) elem = { .Valid = true, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32A32_FLOAT, + .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, .Component0Control = VFCOMP_STORE_0, .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, @@ -766,13 +766,13 @@ genX(emit_vertices)(struct brw_context *brw) if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) { elem_state.VertexBufferIndex = brw->vb.nr_buffers; - elem_state.SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32_UINT; + elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT; elem_state.Component0Control = VFCOMP_STORE_SRC; elem_state.Component1Control = VFCOMP_STORE_SRC; } #else elem_state.VertexBufferIndex = brw->vb.nr_buffers; - elem_state.SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32_UINT; + elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT; if (vs_prog_data->uses_basevertex) elem_state.Component0Control = VFCOMP_STORE_SRC; @@ -794,7 +794,7 @@ genX(emit_vertices)(struct brw_context *brw) struct GENX(VERTEX_ELEMENT_STATE) elem_state = { .Valid = true, .VertexBufferIndex = brw->vb.nr_buffers + 1, - .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32_UINT, + .SourceElementFormat = ISL_FORMAT_R32_UINT, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, -- cgit v1.2.3