path: root/src
AgeCommit message (Expand)AuthorFilesLines
3 hoursdri/radeon: nuke the remaining references to sareaHEADmasterEmil Velikov3-11/+0
3 hoursdri/radeon: cleanup the radeon_context vtblEmil Velikov8-163/+0
3 hoursinclude: move sarea.h next to it's only userEmil Velikov2-1/+93
3 hoursdri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov7-248/+2
5 hoursSCons: Rename dri2_query_renderer.c to dri_common_query_renderer.c.Vinson Lee1-1/+1
5 hoursglsl/linker: pass through the is_intrinsic flagConnor Abbott1-0/+2
7 hoursllvmpipe: change LP_MAX_SHADER_INSTRUCTIONS definitionRoland Scheidegger1-1/+1
8 hoursglx: Fix build since 679c2ef "glx/drisw: add support for DRI2rendererQueryExt...Jon TURNEY5-20/+20
10 hoursr600g: Fix flat/smooth shade state toggle10.3-branchpointGlenn Kennard1-1/+3
11 hoursr600g/compute: Don't initialize vertex_buffer_state masks to 0x2Tom Stellard1-3/+0
11 hoursr600g/compute: Use the first parameter in evergreen_set_global_binding()Tom Stellard1-2/+3
11 hourspipe-loader: Fix memory leak v2Tom Stellard2-2/+2
11 hoursradeon: Add work-around for missing Hainan support in clang < 3.6 v2Tom Stellard1-1/+14
12 hoursst/clover: Fix build against LLVM SVN >= r215967 v2Michel Dänzer1-2/+14
23 hoursi965,meta: Stop unlocking the texture to try and prevent deadlocks.Kenneth Graunke2-22/+0
23 hoursmesa: Use a recursive mutex for the texture lock.Kenneth Graunke1-1/+1
24 hoursglcpp: Fix glcpp-test-cr-lf "make check" test for Mac OS XCarl Worth1-2/+2
24 hoursglcpp: Use printf instead of "echo -n" in glcpp-testCarl Worth1-2/+2
28 hoursi965/vec4: Allow reswizzling writemasks when swizzle is single-valued.Matt Turner1-27/+33
32 hoursTeach os_get_total_physical_memory about CygwinJon TURNEY1-2/+2
41 hoursr300g: Fix path to test programs for out-of-tree buildsMichel Dänzer2-1/+2
42 hoursgallivm: Fix build with LLVM >= 3.6 r215967.Vinson Lee1-0/+4
47 hoursglsl: Use the without_array predicate in some more placesTimothy Arceri2-4/+2
48 hoursi965: Flush the RC and TC before doing a fast clear resolveKristian Høgsberg1-2/+2
2 daysi965: Enable ARB_conditional_render_inverted on Gen6+.Chris Forbes1-0/+1
2 daysmesa: Add support for inverted s/w conditional renderingChris Forbes1-0/+13
2 daysi965/vec4: Add a pass to reduce swizzles.Matt Turner2-0/+99
2 daysvc4: Plumb the texture index from TGSI through to the sampler uniforms.Eric Anholt1-15/+11
2 daysvc4: Avoid a null-deref if a sampler index isn't used.Eric Anholt1-2/+5
2 daysmesa: fix NULL pointer deref bug in _mesa_drawbuffers()Brian Paul1-1/+1
2 daysr600g: Fix missing SET_TEXTURE_OFFSETSGlenn Kennard4-57/+87
2 daysgallium/target: Add needed mesautil lib to haiku-softpipeAlexander von Gluck IV1-0/+1
2 daysgallium/aux: Fill in Haiku get process name codeAlexander von Gluck IV1-0/+7
2 dayshaiku/swrast: Add missing src include search path for missing util/macros.hAlexander von Gluck IV1-0/+1
2 daysllvmpipe/softpipe: enable ARB_conditional_render_invertedTobias Klausmann2-2/+3
2 daysnvc0: Handle ARB_conditional_render_inverted and enable itTobias Klausmann4-32/+37
2 daysmesa/st: Support ARB_conditional_render_inverted modesTobias Klausmann2-1/+20
2 daysgallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTEDTobias Klausmann15-0/+18
2 daysmesa: add ARB_conditional_render_inverted flagsTobias Klausmann3-2/+10
2 daysglapi: add GL_ARB_conditional_render_invertedTobias Klausmann2-1/+14
3 daysilo: fix PIPE_CAP_VIDEO_MEMORYChia-I Wu1-2/+2
3 daysilo: enable HiZ in more cases on GEN6Chia-I Wu3-31/+44
3 daysilo: remove layer offsettingChia-I Wu7-393/+27
3 daysilo: migrate to ilo_layoutChia-I Wu8-1454/+213
3 daysilo: add new resource layout codeChia-I Wu3-0/+1779
3 daysgallium/radeon: Do not use u_upload_mgr for buffer downloadsNiels Ole Salscheider1-12/+8
3 daysr600g: copy IA_MULTI_VGT_PARAM programming from radeonsi for CaymanMarek Olšák4-3/+36
3 daysradeonsi: bump PRIMGROUP_SIZE for some casesMarek Olšák1-1/+4
3 daysradeonsi: set PARTIAL_VS_WAVE(0) when appropriateMarek Olšák1-1/+6
3 daysradeonsi: set IA_MULTI_VGT_PARAM on SI the same as on CIK (v2)Marek Olšák2-46/+50