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13 daysr600g/llvm: Parse config values in register / value pairsTom Stellard2-4/+31
13 daysr600g/llvm: Don't feed LLVM output through r600_bytecode_build()Tom Stellard4-395/+21
13 daysr600g/llvm: Don't emit CALL_FS for vertex shadersTom Stellard2-8/+10
13 daysr600g/llvm: Update radeon family mappings for LLVM backendTom Stellard2-4/+8
2013-05-04r600g/llvm: Undefines unrequired texture coord valuesVincent Lejeune1-1/+28
2013-04-30r600g/llvm: Fix opencl buildVincent Lejeune1-1/+1
2013-04-30r600g/llvm: get use_kill from compiler shaderVincent Lejeune4-2/+9
2013-04-24r600g/llvm: Pass struct r600_bytecode to r600_llvm_compileTom Stellard3-8/+7
2013-04-17r600g/llvm: Use gprcount from llvmVincent Lejeune4-2/+5
2013-04-08r600g/llvm: Add support for native isa for pre EGVincent Lejeune2-2/+6
2013-04-04r600g/llvm: Workaround for wrong tex.offset_*Vincent Lejeune1-0/+3
2013-04-03r600g/llvm: Do not override llvm provided stack_sizeVincent Lejeune1-1/+2
2013-04-03r600g/llvm: Do not change cf_alu inst when adding alusVincent Lejeune1-7/+2
2013-04-01r600g/llvm: Update LLVM_REVISION.txtVincent Lejeune1-1/+1
2013-04-01r600g/llvm: Use stack_size provided from llvm.Vincent Lejeune1-0/+1
2013-04-01r600g/llvm: uses function attribute to pass shader typeVincent Lejeune1-0/+1
2013-04-01r600g/llvm: Add support for cf_alu native encodeVincent Lejeune3-1/+16
2013-03-31r600g/llvm: Update LLVM_REVISIONVincent Lejeune1-1/+1
2013-03-31r600g/llvm: use native encode for texVincent Lejeune1-23/+27
2013-03-13r600g/llvm: Move llvm wrapper functions into the radeon directoryTom Stellard7-38/+35
2013-03-11r600g/llvm: Fix buildTom Stellard1-1/+1
2013-03-07r600g/llvm: Update CONSTANT_BUFFER address space definitionChristian König1-1/+1
2013-02-18r600g/llvm: Support for TBOVincent Lejeune1-0/+28
2013-02-18r600g/llvm: Set Inputs/Outputs count to 32 (api reported value)Vincent Lejeune1-2/+2
2013-02-18r600g/llvm: Fix alpha_to_one piglit testsVincent Lejeune3-0/+4
2013-02-18r600g/llvm: Add support for UBOVincent Lejeune2-1/+22
2013-02-01r600g/llvm: Select the correct GPU type for RV670Tom Stellard1-1/+1
2013-01-28r600g/llvm: Add dummy export for vs outputVincent Lejeune1-2/+20
2013-01-19r600g/llvm: Fixes addressspace of basevectors for clipvertexVincent Lejeune1-1/+2
2013-01-18r600g/llvm: tgsi to llvm emits store.swizzle intrinsic for vs/fs outputVincent Lejeune3-58/+146
2013-01-18r600g/llvm: tgsi to llvm emits stream output intrinsics.Vincent Lejeune5-1/+39
2013-01-18r600g/llvm:translate ARL opcode to a simple castVincent Lejeune1-2/+12
2013-01-18r600g/llvm: rework handling of the constantsVadim Girlin3-16/+54
2012-09-20r600g/llvm: rs780/rs880 are r600 asicsAlex Deucher1-2/+2
2012-05-03r600g/llvm: Mask write of pred_inst in llvm_if()Tom Stellard1-0/+1
2012-05-03r600g/llvm: Lower ULT A, B, C to SETGT_UINT A, C, BTom Stellard1-0/+7
2012-05-03r600g/llvm: Don't duplicate R600 intrinsics installed by LLVMTom Stellard4-0/+26
2012-04-30r600g/llvm: Remove unnecessary dynamic castsDragomir Ivanov1-5/+5
2012-04-30r600g/llvm: Add pattern for llvm.AMDGPU.kill v2Dragomir Ivanov2-1/+6
2012-04-30r600g/llvm: Fix handling of MASK_WRITE instructionsTom Stellard2-1/+3
2012-04-23r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREGTom Stellard6-88/+37
2012-04-23r600g/llvm: Only emit an instruction's explicit operandsTom Stellard1-2/+2
2012-04-23r600g/llvm: Handle copies between vector registersTom Stellard2-2/+21
2012-04-23r600g/llvm: Remove debugging hack from R600InstrInfo::copyPhysReg()Tom Stellard1-4/+0
2012-04-23r600g/llvm: Tell the code emitter to ignore KILL and BUNDLETom Stellard1-1/+3
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