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48 hoursilo: fix format of edge flag pointerChia-I Wu1-3/+5
48 hoursilo: add a pass to finalize ilo_ve_stateChia-I Wu8-158/+190
48 hoursilo: precalculate aligned depth buffer sizeChia-I Wu7-48/+43
48 hoursilo: use dynamic bo for rectlist verticesChia-I Wu10-73/+92
3 daysilo: fix a missing 'else'Chia-I Wu1-1/+1
6 daysilo: give gen6_draw_session a better prefixChia-I Wu6-74/+74
6 daysilo: make ilo_render opaqueChia-I Wu7-94/+90
6 daysilo: make ilo_render_emit_draw() directChia-I Wu8-295/+174
6 daysilo: make ilo_render_emit_rectlist() directChia-I Wu6-53/+84
6 daysilo: clean up draw and rectlist state emissionChia-I Wu6-812/+972
6 daysilo: sanity check ilo_render_get_*_len()Chia-I Wu1-5/+12
6 daysilo: simplify ilo_render_get_query_len()Chia-I Wu1-25/+12
6 daysilo: make ilo_render_emit_query() directChia-I Wu6-173/+159
6 daysilo: make ilo_render_emit_flush() directChia-I Wu6-54/+61
6 daysilo: simplify ilo_render invalidationChia-I Wu7-86/+83
6 daysilo: add ilo_builder_{dynamic,surface}_used()Chia-I Wu1-0/+15
6 daysilo: rename state buffer to dynamic bufferChia-I Wu4-26/+26
6 daysilo: constify ilo_render in ilo_render_get_sample_position()Chia-I Wu2-2/+2
6 daysilo: rename 3d_pipeline to renderChia-I Wu10-883/+884
6 daysilo: remove struct ilo_3dChia-I Wu6-232/+167
6 daysilo: rename ilo_3d_pipeline*.[ch] to ilo_render*.[ch]Chia-I Wu8-24/+24
6 daysilo: rename ilo_3d.[ch] to ilo_draw.[ch]Chia-I Wu6-9/+9
8 daysgallium/ilo: add automake target 'template'Emil Velikov5-29/+15
9 daysilo: rework pipeline workaroundsChia-I Wu3-228/+339
9 daysilo: remove handle_invalid_batch_bo()Chia-I Wu3-67/+32
9 daysilo: make gen6_pipeline_update_max_svbi() staticChia-I Wu3-8/+1
9 daysdraw: use tgsi transform prolog/epilog callbacks in AA line codeBrian Paul1-90/+92
9 daysdraw: use tgsi transform prolog/epilog callbacks in AA point codeBrian Paul1-305/+316
9 daystgsi: fix tgsi transform's epilog callbackBrian Paul1-7/+15
10 daysilo: clean up fallback path for primitive restartChia-I Wu1-160/+74
10 daysilo: handle conditional rendering in the contextChia-I Wu8-65/+58
10 daysilo: create the pipeline from the builderChia-I Wu5-15/+7
10 daysilo: move aperture checks out of pipelineChia-I Wu3-72/+69
10 daysilo: flush before setting SOL_RESETChia-I Wu2-5/+8
10 daysilo: move size estimation check out of pipelineChia-I Wu3-10/+10
11 daysilo: use a single list for queriesChia-I Wu2-69/+8
11 daysilo: replace software queries by hardware onesChia-I Wu4-83/+47
11 daysilo: support prim queries in ilo_3d_pipeline_emit_query()Chia-I Wu1-0/+24
11 daysilo: add ilo_3d_pipeline_emit_query()Chia-I Wu6-180/+123
11 daysilo: rework query supportChia-I Wu8-402/+357
11 daysilo: clarify cp owning/releasingChia-I Wu3-13/+20
12 daysilo: add a pointer to builder in ilo_3d_pipelineChia-I Wu4-187/+190
12 daysilo: add a helper for RECTLIST blitterChia-I Wu3-33/+43
12 daysilo: no direct ilo_context access in BLT blitterChia-I Wu1-21/+20
12 daysilo: fix headers in Makefile.sourcesChia-I Wu1-5/+4
12 daysilo: add a new struct for context statesChia-I Wu20-654/+672
12 daysilo: merge ilo_gpe.h to ilo_state*.hChia-I Wu13-544/+513
12 daysilo: rename ilo_gpe_gen*.[ch]Chia-I Wu5-9/+9
12 daysilo: make ilo_fence opaqueChia-I Wu2-5/+7
13 daysilo: rename ILO_DEBUG=3dChia-I Wu5-6/+6