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10 daysilo: remove GPE state size estimationChia-I Wu7-326/+97
10 daysilo: remove GPE command size estimationChia-I Wu6-403/+87
10 daysilo: remove unused headersChia-I Wu3-566/+0
10 daysilo: use only defines from genhw headersChia-I Wu7-106/+87
10 daysilo: scripted conversion to genhw headersChia-I Wu25-1626/+1626
10 daysilo: add genhw headersChia-I Wu22-131/+3504
10 daysilo: avoid brw_wm_barycentric_interp_mode in compilerChia-I Wu1-17/+46
10 daysilo: add TOY_OPCODE_DOChia-I Wu6-7/+10
2014-03-16targets/dri-ilo: make the driver installableChia-I Wu1-4/+3
2014-03-10ilo: do not set I915_EXEC_NO_RELOCChia-I Wu1-11/+1
2014-03-10ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu4-3/+108
2014-03-10ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu5-0/+90
2014-03-10ilo: add some MI commands to GPEChia-I Wu4-0/+116
2014-03-10ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2-2/+16
2014-03-10ilo: print a warning when PPGTT is disabledChia-I Wu4-0/+24
2014-03-10ilo: require hardware logical context supportChia-I Wu7-14/+32
2014-03-10ilo: protect the decode context with a mutexChia-I Wu1-7/+20
2014-03-10ilo: set I915_EXEC_NO_RELOC when availableChia-I Wu2-3/+15
2014-03-10ilo: move ring types to winsysChia-I Wu8-49/+30
2014-03-10ilo: winsys may limit the batch buffer sizeChia-I Wu7-4/+15
2014-03-10ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supportedChia-I Wu4-1/+19
2014-03-10ilo: rework winsys batch buffer functionsChia-I Wu5-54/+58
2014-03-10ilo: replace bo alloc flags by initial domainsChia-I Wu8-27/+28
2014-03-10ilo: remove intel_bo_get_size()Chia-I Wu4-27/+18
2014-03-10ilo: remove intel_bo_get_virtual()Chia-I Wu6-114/+141
2014-03-10ilo: rework winsys bo reloc functionsChia-I Wu6-34/+35
2014-03-10ilo: add a wrapper to cast struct intel_boChia-I Wu1-23/+28
2014-03-10ilo: fix DRM_API_HANDLE_TYPE_FD exportChia-I Wu1-2/+0
2014-03-10ilo: improve winsys documentation/commentsChia-I Wu2-15/+107
2014-03-10ilo: remove intel_winsys_enable_reuse()Chia-I Wu3-13/+3
2014-03-06st/mesa: make winsys fbo sRGB-capable when supportedChia-I Wu3-12/+66
2014-03-01dri/i9*5: correctly calculate the amount of system memoryEmil Velikov2-2/+2
2014-02-26ilo: create u_upload_mgr lastChia-I Wu1-8/+11
2014-02-22ilo: fix and enable fast depth clearChia-I Wu2-9/+38
2014-02-22ilo: add slice clear valueChia-I Wu5-7/+78
2014-02-22ilo: better readability and doc for texture flagsChia-I Wu3-36/+58
2014-02-22ilo: fix for stencil only rectlist opsChia-I Wu2-2/+8
2014-02-22ilo: fix a false assertion failure on GEN6Chia-I Wu1-4/+12
2014-02-22ilo: pipe_texture::usage is not a bitfieldChia-I Wu1-1/+1
2014-02-22ilo: set ILO_TEXTURE_CPU_WRITE for imported texturesChia-I Wu1-3/+10
2014-01-29ilo: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi1-1/+1
2014-01-14ilo: handle NULL renderbuffers correctlyChia-I Wu6-27/+45
2014-01-14ilo: disable HiZ for misaligned levelsChia-I Wu4-82/+215
2014-01-14ilo: use a helper to determine if HiZ is enabledChia-I Wu5-8/+19
2014-01-14ilo: decide on hiz first in texture allocationChia-I Wu1-64/+64
2014-01-14ilo: emit gen7_wa_pipe_control_wm_max_threads_stall on HaswellChia-I Wu1-7/+9
2014-01-14ilo: use HALIGN_4 on GEN7 for depth buffersChia-I Wu1-11/+1
2014-01-14ilo: OOM for HiZ is fatal on GEN6Chia-I Wu1-2/+7
2014-01-14ilo: fix a HiZ bo leakageChia-I Wu1-0/+3
2014-01-14ilo: simplify ilo_texture_set_slice_flags()Chia-I Wu1-5/+3