i965: Create a macro for setting all dirty bits.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

4 files changed, 18 insertions, 7 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 6b161c9373a..c5cc8232616 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -273,8 +273,8 @@ retry:
    /* We've smashed all state compared to what the normal 3D pipeline
     * rendering tracks for GL.
     */
-   brw->state.dirty.brw = ~0;
-   brw->state.dirty.cache = ~0;
+   SET_DIRTY_ALL(brw);
+   SET_DIRTY_ALL(cache);
    brw->no_depth_or_stencil = false;
    brw->ib.type = -1;
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 7475135f3e8..5ffd9604a9c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -248,6 +248,17 @@ struct brw_state_flags {
 #define SET_DIRTY_BIT(FIELD, FLAG) brw->state.dirty.FIELD |= (FLAG)
 
 
+/**
+ * Set all of the bits in a field of brw_state_flags.
+ */
+#define SET_DIRTY_ALL(FIELD) \
+   do { \
+      /* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
+      STATIC_ASSERT(sizeof(brw->state.dirty.FIELD) == 4); \
+      brw->state.dirty.FIELD = ~0; \
+   } while (false)
+
+
 /** Subclass of Mesa vertex program */
 struct brw_vertex_program {
    struct gl_vertex_program program;
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index df2d806e7f6..fcb7277bf27 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -379,9 +379,9 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
    /* We need to make sure that the programs get regenerated, since
     * any offsets leftover in brw_context will no longer be valid.
     */
-   brw->state.dirty.mesa |= ~0;
-   brw->state.dirty.brw |= ~0;
-   brw->state.dirty.cache |= ~0;
+   SET_DIRTY_ALL(mesa);
+   SET_DIRTY_ALL(brw);
+   SET_DIRTY_ALL(cache);
    intel_batchbuffer_flush(brw);
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index b945e85bcf3..7324274a406 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -383,8 +383,8 @@ void brw_init_state( struct brw_context *brw )
 
    brw_upload_initial_gpu_state(brw);
 
-   brw->state.dirty.mesa = ~0;
-   brw->state.dirty.brw = ~0;
+   SET_DIRTY_ALL(mesa);
+   SET_DIRTY_ALL(brw);
 
    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
     * dirty flags.