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| author | Marek Olšák <marek.olsak@amd.com> | 2014-03-09 20:05:54 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2014-03-11 18:51:20 +0100 |
| commit | e2198422820fd076adccde2f72b821a2c05e8fcc (patch) | |
| tree | 0b2d3734224cdb0db963ce9bcf7b0387146571d4 /src/gallium/drivers/radeonsi | |
| parent | f549129564e018e21f58483f697cc7073854247b (diff) | |
radeonsi: set correct alignment for texture buffers and constant buffers
I think these are all equivalent to vertex buffer fetches which should be
dword-aligned. Scalar loads are also dword-aligned.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 0efd4ebcb85..08502698d39 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -265,13 +265,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 64; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: - return 256; + case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + return 4; case PIPE_CAP_GLSL_FEATURE_LEVEL: return HAVE_LLVM >= 0x0305 ? 330 : 140; - case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - return 1; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF); |