radeonsi: move DB registers from draw_vbo into new db_render_state

It's called db_misc_state in r600g.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

5 files changed, 82 insertions, 66 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 9f95a8a08a7..4744154c7e2 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -146,6 +146,7 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
 				struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
 
 				sctx->dbcb_copy_sample = sample;
+				sctx->db_render_state.dirty = true;
 
 				surf_tmpl.format = texture->resource.b.b.format;
 				surf_tmpl.u.tex.level = level;
@@ -179,6 +180,7 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
 
 	sctx->dbcb_depth_copy_enabled = false;
 	sctx->dbcb_stencil_copy_enabled = false;
+	sctx->db_render_state.dirty = true;
 }
 
 static void si_blit_decompress_depth_in_place(struct si_context *sctx,
@@ -190,6 +192,7 @@ static void si_blit_decompress_depth_in_place(struct si_context *sctx,
 	unsigned layer, max_layer, checked_last_layer, level;
 
 	sctx->db_inplace_flush_enabled = true;
+	sctx->db_render_state.dirty = true;
 
 	surf_tmpl.format = texture->resource.b.b.format;
 
@@ -227,6 +230,7 @@ static void si_blit_decompress_depth_in_place(struct si_context *sctx,
 	}
 
 	sctx->db_inplace_flush_enabled = false;
+	sctx->db_render_state.dirty = true;
 }
 
 void si_flush_depth_textures(struct si_context *sctx,
@@ -372,6 +376,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		zstex->depth_clear_value = depth;
 		sctx->framebuffer.atom.dirty = true; /* updates DB_DEPTH_CLEAR */
 		sctx->db_depth_clear = true;
+		sctx->db_render_state.dirty = true;
 	}
 
 	si_blitter_begin(ctx, SI_CLEAR);
@@ -384,6 +389,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		sctx->db_depth_clear = false;
 		sctx->db_depth_disable_expclear = false;
 		zstex->depth_cleared = true;
+		sctx->db_render_state.dirty = true;
 	}
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index bd8409bfa62..eaefa6a40e9 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -161,6 +161,7 @@ void si_begin_new_cs(struct si_context *ctx)
 
 	ctx->framebuffer.atom.dirty = true;
 	ctx->msaa_config.dirty = true;
+	ctx->db_render_state.dirty = true;
 	ctx->b.streamout.enable_atom.dirty = true;
 	si_all_descriptors_begin_new_cs(ctx);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 6ec8d5dba9d..df81e1fcb64 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -106,6 +106,7 @@ struct si_context {
 			struct r600_atom *streamout_begin;
 			struct r600_atom *streamout_enable; /* must be after streamout_begin */
 			struct r600_atom *framebuffer;
+			struct r600_atom *db_render_state;
 			struct r600_atom *msaa_config;
 		} s;
 		struct r600_atom *array[0];
@@ -159,13 +160,14 @@ struct si_context {
 	union si_state	queued;
 	union si_state	emitted;
 
-	/* Additional DB state. */
-	bool dbcb_depth_copy_enabled;
-	bool dbcb_stencil_copy_enabled;
-	unsigned dbcb_copy_sample;
-	bool db_inplace_flush_enabled;
-	bool db_depth_clear;
-	bool db_depth_disable_expclear;
+	/* DB render state. */
+	struct r600_atom	db_render_state;
+	bool			dbcb_depth_copy_enabled;
+	bool			dbcb_stencil_copy_enabled;
+	unsigned		dbcb_copy_sample;
+	bool			db_inplace_flush_enabled;
+	bool			db_depth_clear;
+	bool			db_depth_disable_expclear;
 };
 
 /* si_blit.c */
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1d6ae864836..c66eac9449c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -833,6 +833,71 @@ static void *si_create_db_flush_dsa(struct si_context *sctx)
 	return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
 }
 
+/* DB RENDER STATE */
+
+static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
+{
+	struct si_context *sctx = (struct si_context*)ctx;
+
+	sctx->db_render_state.dirty = true;
+}
+
+static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
+{
+	struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+
+	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
+
+	/* DB_RENDER_CONTROL */
+	if (sctx->dbcb_depth_copy_enabled ||
+	    sctx->dbcb_stencil_copy_enabled) {
+		radeon_emit(cs,
+			    S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
+			    S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
+			    S_028000_COPY_CENTROID(1) |
+			    S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
+	} else if (sctx->db_inplace_flush_enabled) {
+		radeon_emit(cs,
+			    S_028000_DEPTH_COMPRESS_DISABLE(1) |
+			    S_028000_STENCIL_COMPRESS_DISABLE(1));
+	} else if (sctx->db_depth_clear) {
+		radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
+	} else {
+		radeon_emit(cs, 0);
+	}
+
+	/* DB_COUNT_CONTROL (occlusion queries) */
+	if (sctx->b.num_occlusion_queries > 0) {
+		if (sctx->b.chip_class >= CIK) {
+			radeon_emit(cs,
+				    S_028004_PERFECT_ZPASS_COUNTS(1) |
+				    S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
+				    S_028004_ZPASS_ENABLE(1) |
+				    S_028004_SLICE_EVEN_ENABLE(1) |
+				    S_028004_SLICE_ODD_ENABLE(1));
+		} else {
+			radeon_emit(cs,
+				    S_028004_PERFECT_ZPASS_COUNTS(1) |
+				    S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
+		}
+	} else {
+		/* Disable occlusion queries. */
+		if (sctx->b.chip_class >= CIK) {
+			radeon_emit(cs, 0);
+		} else {
+			radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
+		}
+	}
+
+	/* DB_RENDER_OVERRIDE2 */
+	if (sctx->db_depth_disable_expclear) {
+		r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
+			S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
+	} else {
+		r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
+	}
+}
+
 /*
  * format translation
  */
@@ -2909,13 +2974,6 @@ static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
 	return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
 }
 
-static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
-{
-	/* XXX Turn this into a proper state. Right now the queries are
-	 * enabled in draw_vbo, which snoops r600_common_context to see
-	 * if any occlusion queries are active. */
-}
-
 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
 				 bool include_draw_vbo)
 {
@@ -2925,6 +2983,7 @@ static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
 void si_init_state_functions(struct si_context *sctx)
 {
 	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
+	si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 7);
 
 	sctx->b.b.create_blend_state = si_create_blend_state;
 	sctx->b.b.bind_blend_state = si_bind_blend_state;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9eeda9de34c..fb1ddc09f08 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -713,58 +713,6 @@ static void si_state_draw(struct si_context *sctx,
 	if (pm4 == NULL)
 		return;
 
-	/* queries need some special values
-	 * (this is non-zero if any query is active) */
-	if (sctx->b.num_occlusion_queries > 0) {
-		if (sctx->b.chip_class >= CIK) {
-			si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
-				       S_028004_PERFECT_ZPASS_COUNTS(1) |
-				       S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
-				       S_028004_ZPASS_ENABLE(1) |
-				       S_028004_SLICE_EVEN_ENABLE(1) |
-				       S_028004_SLICE_ODD_ENABLE(1));
-		} else {
-			si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
-				       S_028004_PERFECT_ZPASS_COUNTS(1) |
-				       S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
-		}
-	} else {
-		/* Disable occlusion queries. */
-		if (sctx->b.chip_class >= CIK) {
-			si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL, 0);
-		} else {
-			si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
-				       S_028004_ZPASS_INCREMENT_DISABLE(1));
-		}
-	}
-
-	/* DB_RENDER_CONTROL */
-	if (sctx->dbcb_depth_copy_enabled ||
-	    sctx->dbcb_stencil_copy_enabled) {
-		si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
-			       S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
-			       S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
-			       S_028000_COPY_CENTROID(1) |
-			       S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
-	} else if (sctx->db_inplace_flush_enabled) {
-		si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
-			       S_028000_DEPTH_COMPRESS_DISABLE(1) |
-			       S_028000_STENCIL_COMPRESS_DISABLE(1));
-	} else if (sctx->db_depth_clear) {
-		si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
-			       S_028000_DEPTH_CLEAR_ENABLE(1));
-	} else {
-		si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
-	}
-
-	/* DB_RENDER_OVERRIDE2 */
-	if (sctx->db_depth_disable_expclear) {
-		si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2,
-			       S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
-	} else {
-		si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2, 0);
-	}
-
 	if (info->count_from_stream_output) {
 		struct r600_so_target *t =
 			(struct r600_so_target*)info->count_from_stream_output;