diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-04-05 11:19:21 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-04-06 19:46:18 +0200 |
| commit | f1d7c16e8504a941ae481a20aa5294b964c801ce (patch) | |
| tree | af2dc80df1451fb91b6386fd982878fdc2954600 | |
| parent | 7fe586f6fb69cd829d687dd58562ef5922667905 (diff) | |
radv: fix prefetching compute shaders on CIK and older chips
Because the check was moved to radv_emit_prefetch_L2().
Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c0f60ac0d27..cbf3320a054 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -646,9 +646,6 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_cmd_state *state = &cmd_buffer->state; uint32_t mask = state->prefetch_L2_mask; - if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK) - return; - if (vertex_stage_only) { /* Fast prefetch path for starting draws as soon as possible. */ @@ -3042,6 +3039,8 @@ static void radv_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info) { + bool has_prefetch = + cmd_buffer->device->physical_device->rad_info.chip_class >= CIK; bool pipeline_is_dirty = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) && cmd_buffer->state.pipeline && @@ -3079,7 +3078,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer, * run in parallel, but starting the draw first is more * important. */ - if (cmd_buffer->state.prefetch_L2_mask) { + if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) { radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, false); } @@ -3106,7 +3105,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer, /* Prefetch the remaining shaders after the draw has been * started. */ - if (cmd_buffer->state.prefetch_L2_mask) { + if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) { radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, false); } @@ -3409,6 +3408,8 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info) { struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; + bool has_prefetch = + cmd_buffer->device->physical_device->rad_info.chip_class >= CIK; bool pipeline_is_dirty = pipeline && pipeline != cmd_buffer->state.emitted_compute_pipeline; @@ -3436,7 +3437,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, * will run in parallel, but starting the dispatch first is * more important. */ - if (pipeline_is_dirty) { + if (has_prefetch && pipeline_is_dirty) { radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]); } @@ -3446,7 +3447,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, */ si_emit_cache_flush(cmd_buffer); - if (pipeline_is_dirty) { + if (has_prefetch && pipeline_is_dirty) { radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]); } |