diff options
author | Jerome Glisse <jglisse@redhat.com> | 2013-03-22 17:55:49 -0400 |
---|---|---|
committer | Jerome Glisse <jglisse@redhat.com> | 2013-04-18 17:25:38 -0400 |
commit | dc21e30a6283629bed6db282caff0af13f3b88ec (patch) | |
tree | 9548d9d194adb63bb185d3261c6a9e9b5a7ca911 | |
parent | f732036f12d67a96f546c11236fa635b3eda6e9c (diff) |
radeonsi: add 2d tiling support for texture v3
v2: Remove left over code
v3: Restage properly the commit so hunk of first one are not in
second one.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
-rw-r--r-- | configure.ac | 2 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/r600_texture.c | 11 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 81 |
3 files changed, 21 insertions, 73 deletions
diff --git a/configure.ac b/configure.ac index 70c598e0882..6ffe3f20c93 100644 --- a/configure.ac +++ b/configure.ac | |||
@@ -31,7 +31,7 @@ AC_SUBST([OSMESA_VERSION]) | |||
31 | 31 | ||
32 | dnl Versions for external dependencies | 32 | dnl Versions for external dependencies |
33 | LIBDRM_REQUIRED=2.4.24 | 33 | LIBDRM_REQUIRED=2.4.24 |
34 | LIBDRM_RADEON_REQUIRED=2.4.42 | 34 | LIBDRM_RADEON_REQUIRED=2.4.44 |
35 | LIBDRM_INTEL_REQUIRED=2.4.38 | 35 | LIBDRM_INTEL_REQUIRED=2.4.38 |
36 | LIBDRM_NVVIEUX_REQUIRED=2.4.33 | 36 | LIBDRM_NVVIEUX_REQUIRED=2.4.33 |
37 | LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41" | 37 | LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41" |
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 1b8382fd308..8992f9a1fa2 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c | |||
@@ -47,7 +47,6 @@ static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_t | |||
47 | &transfer->box); | 47 | &transfer->box); |
48 | } | 48 | } |
49 | 49 | ||
50 | |||
51 | /* Copy from a transfer's staging texture to a full GPU one. */ | 50 | /* Copy from a transfer's staging texture to a full GPU one. */ |
52 | static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) | 51 | static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) |
53 | { | 52 | { |
@@ -152,12 +151,12 @@ static int r600_init_surface(struct r600_screen *rscreen, | |||
152 | 151 | ||
153 | if (!is_flushed_depth && is_depth) { | 152 | if (!is_flushed_depth && is_depth) { |
154 | surface->flags |= RADEON_SURF_ZBUFFER; | 153 | surface->flags |= RADEON_SURF_ZBUFFER; |
155 | |||
156 | if (is_stencil) { | 154 | if (is_stencil) { |
157 | surface->flags |= RADEON_SURF_SBUFFER | | 155 | surface->flags |= RADEON_SURF_SBUFFER | |
158 | RADEON_SURF_HAS_SBUFFER_MIPTREE; | 156 | RADEON_SURF_HAS_SBUFFER_MIPTREE; |
159 | } | 157 | } |
160 | } | 158 | } |
159 | surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; | ||
161 | return 0; | 160 | return 0; |
162 | } | 161 | } |
163 | 162 | ||
@@ -530,7 +529,11 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, | |||
530 | 529 | ||
531 | if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && | 530 | if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && |
532 | !(templ->bind & PIPE_BIND_SCANOUT)) { | 531 | !(templ->bind & PIPE_BIND_SCANOUT)) { |
533 | array_mode = V_009910_ARRAY_1D_TILED_THIN1; | 532 | if (util_format_is_compressed(templ->format)) { |
533 | array_mode = V_009910_ARRAY_1D_TILED_THIN1; | ||
534 | } else { | ||
535 | array_mode = V_009910_ARRAY_2D_TILED_THIN1; | ||
536 | } | ||
534 | } | 537 | } |
535 | 538 | ||
536 | r = r600_init_surface(rscreen, &surface, templ, array_mode, | 539 | r = r600_init_surface(rscreen, &surface, templ, array_mode, |
@@ -620,6 +623,8 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, | |||
620 | if (r) { | 623 | if (r) { |
621 | return NULL; | 624 | return NULL; |
622 | } | 625 | } |
626 | /* always set the scanout flags */ | ||
627 | surface.flags |= RADEON_SURF_SCANOUT; | ||
623 | return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, | 628 | return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, |
624 | stride, 0, buf, FALSE, &surface); | 629 | stride, 0, buf, FALSE, &surface); |
625 | } | 630 | } |
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ca9e8b43902..61ede6453f0 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c | |||
@@ -1541,67 +1541,16 @@ boolean si_is_format_supported(struct pipe_screen *screen, | |||
1541 | return retval == usage; | 1541 | return retval == usage; |
1542 | } | 1542 | } |
1543 | 1543 | ||
1544 | static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level) | 1544 | static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil) |
1545 | { | 1545 | { |
1546 | if (util_format_is_depth_or_stencil(rtex->real_format)) { | 1546 | unsigned tile_mode_index = 0; |
1547 | if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) { | ||
1548 | return 4; | ||
1549 | } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) { | ||
1550 | switch (rtex->real_format) { | ||
1551 | case PIPE_FORMAT_Z16_UNORM: | ||
1552 | return 5; | ||
1553 | case PIPE_FORMAT_S8_UINT_Z24_UNORM: | ||
1554 | case PIPE_FORMAT_X8Z24_UNORM: | ||
1555 | case PIPE_FORMAT_Z24X8_UNORM: | ||
1556 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: | ||
1557 | case PIPE_FORMAT_Z32_FLOAT: | ||
1558 | case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: | ||
1559 | return 6; | ||
1560 | default: | ||
1561 | return 7; | ||
1562 | } | ||
1563 | } | ||
1564 | } | ||
1565 | 1547 | ||
1566 | switch (rtex->surface.level[level].mode) { | 1548 | if (stencil) { |
1567 | default: | 1549 | tile_mode_index = rtex->surface.stencil_tiling_index[level]; |
1568 | assert(!"Invalid surface mode"); | 1550 | } else { |
1569 | /* Fall through */ | 1551 | tile_mode_index = rtex->surface.tiling_index[level]; |
1570 | case RADEON_SURF_MODE_LINEAR_ALIGNED: | ||
1571 | return 8; | ||
1572 | case RADEON_SURF_MODE_1D: | ||
1573 | if (rtex->surface.flags & RADEON_SURF_SCANOUT) | ||
1574 | return 9; | ||
1575 | else | ||
1576 | return 13; | ||
1577 | case RADEON_SURF_MODE_2D: | ||
1578 | if (rtex->surface.flags & RADEON_SURF_SCANOUT) { | ||
1579 | switch (util_format_get_blocksize(rtex->real_format)) { | ||
1580 | case 1: | ||
1581 | return 10; | ||
1582 | case 2: | ||
1583 | return 11; | ||
1584 | default: | ||
1585 | assert(!"Invalid block size"); | ||
1586 | /* Fall through */ | ||
1587 | case 4: | ||
1588 | return 12; | ||
1589 | } | ||
1590 | } else { | ||
1591 | switch (util_format_get_blocksize(rtex->real_format)) { | ||
1592 | case 1: | ||
1593 | return 14; | ||
1594 | case 2: | ||
1595 | return 15; | ||
1596 | case 4: | ||
1597 | return 16; | ||
1598 | case 8: | ||
1599 | return 17; | ||
1600 | default: | ||
1601 | return 13; | ||
1602 | } | ||
1603 | } | ||
1604 | } | 1552 | } |
1553 | return tile_mode_index; | ||
1605 | } | 1554 | } |
1606 | 1555 | ||
1607 | /* | 1556 | /* |
@@ -1638,7 +1587,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, | |||
1638 | slice = slice - 1; | 1587 | slice = slice - 1; |
1639 | } | 1588 | } |
1640 | 1589 | ||
1641 | tile_mode_index = si_tile_mode_index(rtex, level); | 1590 | tile_mode_index = si_tile_mode_index(rtex, level, false); |
1642 | 1591 | ||
1643 | desc = util_format_description(surf->base.format); | 1592 | desc = util_format_description(surf->base.format); |
1644 | for (i = 0; i < 4; i++) { | 1593 | for (i = 0; i < 4; i++) { |
@@ -1780,15 +1729,9 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, | |||
1780 | else | 1729 | else |
1781 | s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); | 1730 | s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); |
1782 | 1731 | ||
1783 | tile_mode_index = si_tile_mode_index(rtex, level); | 1732 | tile_mode_index = si_tile_mode_index(rtex, level, false); |
1784 | if (tile_mode_index < 4 || tile_mode_index > 7) { | ||
1785 | R600_ERR("Invalid DB tiling mode %d!\n", | ||
1786 | rtex->surface.level[level].mode); | ||
1787 | si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); | ||
1788 | si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); | ||
1789 | return; | ||
1790 | } | ||
1791 | z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); | 1733 | z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); |
1734 | tile_mode_index = si_tile_mode_index(rtex, level, true); | ||
1792 | s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); | 1735 | s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); |
1793 | 1736 | ||
1794 | si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, | 1737 | si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, |
@@ -2231,7 +2174,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx | |||
2231 | S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | | 2174 | S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | |
2232 | S_008F1C_BASE_LEVEL(state->u.tex.first_level) | | 2175 | S_008F1C_BASE_LEVEL(state->u.tex.first_level) | |
2233 | S_008F1C_LAST_LEVEL(state->u.tex.last_level) | | 2176 | S_008F1C_LAST_LEVEL(state->u.tex.last_level) | |
2234 | S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) | | 2177 | S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | |
2235 | S_008F1C_POW2_PAD(texture->last_level > 0) | | 2178 | S_008F1C_POW2_PAD(texture->last_level > 0) | |
2236 | S_008F1C_TYPE(si_tex_dim(texture->target))); | 2179 | S_008F1C_TYPE(si_tex_dim(texture->target))); |
2237 | view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); | 2180 | view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); |