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authorEric Anholt <eric@anholt.net>2011-12-29 18:12:48 -0800
committerEric Anholt <eric@anholt.net>2012-01-06 09:16:32 -0800
commitc4089d444a1736dba0c3d9c389ac216ce8711da8 (patch)
tree5a71ad91a0d6479811e3d421a556aca9ff23c937
parente60daf7e25daaaae34c803834079201ef1cc3900 (diff)
i965/gen7: Use the updated interface for SO write pointer resetting.
The new kernel patch I submitted makes the interface opt-in, so all batchbuffers aren't preceded by the 4 MI_LOAD_REGISTER_IMMs. This requires the updated i915_drm.h present in libdrm 2.4.30. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
-rw-r--r--configure.ac2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_sol_state.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.c13
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h1
4 files changed, 13 insertions, 5 deletions
diff --git a/configure.ac b/configure.ac
index cc139ada577..e5a5e884258 100644
--- a/configure.ac
+++ b/configure.ac
@@ -25,7 +25,7 @@ USER_CXXFLAGS="$CXXFLAGS"
dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.24
LIBDRM_RADEON_REQUIRED=2.4.24
-LIBDRM_INTEL_REQUIRED=2.4.27
+LIBDRM_INTEL_REQUIRED=2.4.30
LIBDRM_NOUVEAU_REQUIRED=0.6
DRI2PROTO_REQUIRED=2.6
GLPROTO_REQUIRED=1.4.14
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 674e14f1252..c4e0622a6e0 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -240,6 +240,8 @@ upload_sol_state(struct brw_context *brw)
if (active) {
upload_3dstate_so_buffers(brw);
upload_3dstate_so_decl_list(brw, &vue_map);
+
+ intel->batch.needs_sol_reset = true;
}
/* Finally, set up the SOL stage. This command must always follow updates to
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index cb23dbc3548..90effd289b8 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -85,6 +85,7 @@ intel_batchbuffer_reset(struct intel_context *intel)
intel->batch.reserved_space = BATCH_RESERVED;
intel->batch.state_batch_offset = intel->batch.bo->size;
intel->batch.used = 0;
+ intel->batch.needs_sol_reset = false;
}
void
@@ -135,16 +136,20 @@ do_flush_locked(struct intel_context *intel)
}
if (!intel->intelScreen->no_hw) {
- int ring;
+ int flags;
if (intel->gen < 6 || !batch->is_blit) {
- ring = I915_EXEC_RENDER;
+ flags = I915_EXEC_RENDER;
} else {
- ring = I915_EXEC_BLT;
+ flags = I915_EXEC_BLT;
}
+ if (batch->needs_sol_reset)
+ flags |= I915_EXEC_GEN7_SOL_RESET;
+
if (ret == 0)
- ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
+ ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0,
+ flags);
}
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 5fe8e249690..9fb2902a45b 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -233,6 +233,7 @@ struct intel_context
uint32_t state_batch_offset;
bool is_blit;
+ bool needs_sol_reset;
struct {
uint16_t used;