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authorAlex Deucher <alexander.deucher@amd.com>2012-03-20 23:43:59 (GMT)
committerAlex Deucher <alexander.deucher@amd.com>2012-03-20 23:43:59 (GMT)
commitb4082f492b4b55df4c636445e47b97d1f1e4b5b2 (patch)
treea58855f68f0801e9438992546ac29be426b95630
parentd09fce51f0cf91c9c07f69063fe2180cc319d8df (diff)
r600g: add support for TN (trinity) APUs
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--include/pci_ids/r600_pci_ids.h8
-rw-r--r--src/gallium/drivers/r600/evergreen_hw_context.c4
-rw-r--r--src/gallium/drivers/r600/r600.h1
-rw-r--r--src/gallium/drivers/r600/r600_hw_context.c3
-rw-r--r--src/gallium/drivers/r600/r600_pipe.c3
5 files changed, 15 insertions, 4 deletions
diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h
index a55d45c..360c73d 100644
--- a/include/pci_ids/r600_pci_ids.h
+++ b/include/pci_ids/r600_pci_ids.h
@@ -279,3 +279,11 @@ CHIPSET(0x6772, CAICOS_6772, CAICOS)
CHIPSET(0x6778, CAICOS_6778, CAICOS)
CHIPSET(0x6779, CAICOS_6779, CAICOS)
CHIPSET(0x677B, CAICOS_677B, CAICOS)
+
+CHIPSET(0x9900, ARUBA_9900, ARUBA)
+CHIPSET(0x9901, ARUBA_9901, ARUBA)
+CHIPSET(0x9903, ARUBA_9903, ARUBA)
+CHIPSET(0x9904, ARUBA_9904, ARUBA)
+CHIPSET(0x990F, ARUBA_990F, ARUBA)
+CHIPSET(0x9990, ARUBA_9990, ARUBA)
+CHIPSET(0x9991, ARUBA_9991, ARUBA)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index a05f3f3..0d2228d 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -669,7 +669,7 @@ int evergreen_context_init(struct r600_context *ctx)
int r;
/* add blocks */
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_config_reg_list,
Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
else
@@ -677,7 +677,7 @@ int evergreen_context_init(struct r600_context *ctx)
Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
if (r)
goto out_err;
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_context_reg_list,
Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
else
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index e0d81d8..e77e185 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -61,6 +61,7 @@ enum radeon_family {
CHIP_TURKS,
CHIP_CAICOS,
CHIP_CAYMAN,
+ CHIP_ARUBA,
CHIP_LAST,
};
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 1e1b782..6205a20 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1173,7 +1173,8 @@ void r600_inval_vertex_cache(struct r600_context *ctx)
ctx->family == CHIP_SUMO ||
ctx->family == CHIP_SUMO2 ||
ctx->family == CHIP_CAICOS ||
- ctx->family == CHIP_CAYMAN) {
+ ctx->family == CHIP_CAYMAN ||
+ ctx->family == CHIP_ARUBA) {
/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
} else {
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 113dad6..8daa67a 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -347,6 +347,7 @@ static const char *r600_get_family_name(enum radeon_family family)
case CHIP_TURKS: return "AMD TURKS";
case CHIP_CAICOS: return "AMD CAICOS";
case CHIP_CAYMAN: return "AMD CAYMAN";
+ case CHIP_ARUBA: return "AMD ARUBA";
default: return "AMD unknown";
}
}
@@ -803,7 +804,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
}
/* setup class */
- if (rscreen->family == CHIP_CAYMAN) {
+ if (rscreen->family >= CHIP_CAYMAN) {
rscreen->chip_class = CAYMAN;
} else if (rscreen->family >= CHIP_CEDAR) {
rscreen->chip_class = EVERGREEN;