r300g: enable MSAA on r300-r400, be careful about using color compression

MSAA was tested by one user on RS690 and it works for him with color
compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM.

Since we don't have hardware documentation about which chipsets actually have
CMASK RAM, I had to take a guess based on the presence of HiZ.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

4 files changed, 14 insertions, 5 deletions

diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c
index 30e085ac517..c1f5e3cee1f 100644
--- a/src/gallium/drivers/r300/r300_chipset.c
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -81,19 +81,21 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
 
     /* Defaults. */
     caps->high_second_pipe = FALSE;
     caps->num_vert_fpus = 0;
     caps->hiz_ram = 0;
     caps->zmask_ram = 0;
+    caps->has_cmask = FALSE;
 
 
     switch (caps->family) {
     case CHIP_R300:
     case CHIP_R350:
         caps->high_second_pipe = TRUE;
         caps->num_vert_fpus = 4;
+        caps->has_cmask = TRUE; /* guessed because there is also HiZ */
         caps->hiz_ram = R300_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
 
     case CHIP_RV350:
     case CHIP_RV370:
@@ -102,12 +104,13 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
         caps->zmask_ram = RV3xx_ZMASK_SIZE;
         break;
 
     case CHIP_RV380:
         caps->high_second_pipe = TRUE;
         caps->num_vert_fpus = 2;
+        caps->has_cmask = TRUE; /* guessed because there is also HiZ */
         caps->hiz_ram = R300_HIZ_LIMIT;
         caps->zmask_ram = RV3xx_ZMASK_SIZE;
         break;
 
     case CHIP_RS400:
     case CHIP_RS600:
@@ -124,38 +127,43 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
     case CHIP_R423:
     case CHIP_R430:
     case CHIP_R480:
     case CHIP_R481:
     case CHIP_RV410:
         caps->num_vert_fpus = 6;
+        caps->has_cmask = TRUE; /* guessed because there is also HiZ */
         caps->hiz_ram = R300_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
 
     case CHIP_R520:
         caps->num_vert_fpus = 8;
+        caps->has_cmask = TRUE;
         caps->hiz_ram = R300_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
 
     case CHIP_RV515:
         caps->num_vert_fpus = 2;
+        caps->has_cmask = TRUE;
         caps->hiz_ram = R300_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
 
     case CHIP_RV530:
         caps->num_vert_fpus = 5;
+        caps->has_cmask = TRUE;
         caps->hiz_ram = RV530_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
 
     case CHIP_R580:
     case CHIP_RV560:
     case CHIP_RV570:
         caps->num_vert_fpus = 8;
+        caps->has_cmask = TRUE;
         caps->hiz_ram = RV530_HIZ_LIMIT;
         caps->zmask_ram = PIPE_ZMASK_SIZE;
         break;
     }
 
     caps->num_tex_units = 16;
diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h
index f8b5d4e3d3e..8e9deb6057c 100644
--- a/src/gallium/drivers/r300/r300_chipset.h
+++ b/src/gallium/drivers/r300/r300_chipset.h
@@ -52,12 +52,14 @@ struct r300_capabilities {
     /* Whether or not TCL is physically present */
     boolean has_tcl;
     /* Some chipsets do not have HiZ RAM - other have varying amounts. */
     int hiz_ram;
     /* Some chipsets have zmask ram per pipe some don't. */
     int zmask_ram;
+    /* CMASK is for MSAA colorbuffer compression and fast clear. */
+    boolean has_cmask;
     /* Compression mode for ZMASK. */
     enum r300_zmask_compression z_compress;
     /* Whether or not this is RV350 or newer, including all r400 and r500
      * chipsets. The differences compared to the oldest r300 chips are:
      * - Blend LTE/GTE thresholds
      * - Better MACRO_SWITCH in texture tiling
diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
index 5a388970c9b..063bc0922a1 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -441,17 +441,12 @@ static boolean r300_is_format_supported(struct pipe_screen* screen,
         case 4:
         case 6:
             /* We need DRM 2.8.0. */
             if (!drm_2_8_0) {
                 return FALSE;
             }
-            /* Only support R500, because I didn't test older chipsets,
-             * but MSAA should work there too. */
-            if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
-                return FALSE;
-            }
             /* No texturing and scanout. */
             if (usage & (PIPE_BIND_SAMPLER_VIEW |
                          PIPE_BIND_DISPLAY_TARGET |
                          PIPE_BIND_SCANOUT)) {
                 return FALSE;
             }
diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c
index 8d96b5684ad..8fa98c5804e 100644
--- a/src/gallium/drivers/r300/r300_texture_desc.c
+++ b/src/gallium/drivers/r300/r300_texture_desc.c
@@ -414,12 +414,16 @@ static void r300_setup_cmask_properties(struct r300_screen *screen,
                                         struct r300_resource *tex)
 {
     static unsigned cmask_align_x[4] = {16, 32, 48, 32};
     static unsigned cmask_align_y[4] = {16, 16, 16, 32};
     unsigned pipes, stride, cmask_num_dw, cmask_max_size;
 
+    if (!screen->caps.has_cmask) {
+        return;
+    }
+
     /* We need an AA colorbuffer, no mipmaps. */
     if (tex->b.b.nr_samples <= 1 ||
         tex->b.b.last_level > 0 ||
         util_format_is_depth_or_stencil(tex->b.b.format)) {
         return;
     }