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| author | Jose Maria Casanova Crespo <jmcasanova@igalia.com> | 2017-07-01 08:11:58 +0200 |
|---|---|---|
| committer | Jose Maria Casanova Crespo <jmcasanova@igalia.com> | 2017-12-06 08:57:18 +0100 |
| commit | ac8d4734f695b718ae072c2ad961a2cc546b21e0 (patch) | |
| tree | c24505b7b512fcb603c5738acef6fc9986d1f0e7 | |
| parent | 5d5ee507fb4a385f98ba19bd901ce4e3aca7def4 (diff) | |
i965: Add support for control register
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields such as the
floating-point mode ... "
Floating-point Rounding mode is changed at bits 5:4 of cr0.0:
"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
00b = Round to Nearest or Even (RTNE)
01b = Round Up, toward +inf (RU)
10b = Round Down, toward -inf (RD)
11b = Round Toward Zero (RTZ)"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
| -rw-r--r-- | src/intel/compiler/brw_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index a039c6f676c..17d5b97bf31 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -817,6 +817,12 @@ brw_notification_reg(void) } static inline struct brw_reg +brw_cr0_reg(unsigned subnr) +{ + return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr); +} + +static inline struct brw_reg brw_sr0_reg(unsigned subnr) { return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_STATE, subnr); |