winsys/radeon: move managing GEM domains back to drivers

This partially reverts commit 363ff844753c46ac9c13866627e096b091ea81f8.

It caused severe performance drops in Nexuiz. Reported by Phoronix.

Tested by me on r300g and by IRC people on r600g.

14 files changed, 106 insertions, 76 deletions

diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index e1c12d9c516..5c0f53e9aad 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -299,12 +299,14 @@ struct r300_surface {
     struct pipe_surface base;
 
     /* Winsys buffer backing the texture. */
     struct pb_buffer *buf;
     struct radeon_winsys_cs_handle *cs_buf;
 
+    enum radeon_bo_domain domain;
+
     uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
     uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
     uint32_t pitch_zmask; /* ZMASK_PITCH */
     uint32_t pitch_hiz;   /* HIZ_PITCH */
     uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
 
@@ -382,12 +384,13 @@ struct r300_resource
 {
     struct u_vbuf_resource b;
 
     /* Winsys buffer backing this resource. */
     struct pb_buffer *buf;
     struct radeon_winsys_cs_handle *cs_buf;
+    enum radeon_bo_domain domain;
 
     /* Constant buffers are in user memory. */
     uint8_t *constant_buffer;
 
     /* Texture description (addressing, layout, special features). */
     struct r300_texture_desc tex;
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index d93a5786ff8..3897e990b1c 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -1187,60 +1187,66 @@ validate:
     if (r300->fb_state.dirty) {
         /* Color buffers... */
         for (i = 0; i < fb->nr_cbufs; i++) {
             tex = r300_resource(fb->cbufs[i]->texture);
             assert(tex && tex->buf && "cbuf is marked, but NULL!");
             r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
-                                    RADEON_USAGE_READWRITE);
+                                    RADEON_USAGE_READWRITE,
+                                    r300_surface(fb->cbufs[i])->domain);
         }
         /* ...depth buffer... */
         if (fb->zsbuf) {
             tex = r300_resource(fb->zsbuf->texture);
             assert(tex && tex->buf && "zsbuf is marked, but NULL!");
             r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
-                                    RADEON_USAGE_READWRITE);
+                                    RADEON_USAGE_READWRITE,
+                                    r300_surface(fb->zsbuf)->domain);
         }
     }
     if (r300->textures_state.dirty) {
         /* ...textures... */
         for (i = 0; i < texstate->count; i++) {
             if (!(texstate->tx_enable & (1 << i))) {
                 continue;
             }
 
             tex = r300_resource(texstate->sampler_views[i]->base.texture);
-            r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ);
+            r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ,
+                                    tex->domain);
         }
     }
     /* ...occlusion query buffer... */
     if (r300->query_current)
         r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
-                                RADEON_USAGE_WRITE);
+                                RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
     /* ...vertex buffer for SWTCL path... */
     if (r300->vbo)
         r300->rws->cs_add_reloc(r300->cs, r300_resource(r300->vbo)->cs_buf,
-                                RADEON_USAGE_READ);
+                                RADEON_USAGE_READ,
+                                r300_resource(r300->vbo)->domain);
     /* ...vertex buffers for HWTCL path... */
     if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
         struct pipe_vertex_buffer *vbuf = r300->vbuf_mgr->real_vertex_buffer;
         struct pipe_vertex_buffer *last = r300->vbuf_mgr->real_vertex_buffer +
                                       r300->vbuf_mgr->nr_real_vertex_buffers;
         struct pipe_resource *buf;
         for (; vbuf != last; vbuf++) {
             buf = vbuf->buffer;
             if (!buf)
                 continue;
 
             r300->rws->cs_add_reloc(r300->cs, r300_resource(buf)->cs_buf,
-                                    RADEON_USAGE_READ);
+                                    RADEON_USAGE_READ,
+                                    r300_resource(buf)->domain);
         }
     }
     /* ...and index buffer for HWTCL path. */
     if (index_buffer)
         r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
-                                RADEON_USAGE_READ);
+                                RADEON_USAGE_READ,
+                                r300_resource(index_buffer)->domain);
 
     /* Now do the validation (flush is called inside cs_validate on failure). */
     if (!r300->rws->cs_validate(r300->cs)) {
         /* Ooops, an infinite loop, give up. */
         if (flushed)
             return FALSE;
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index 9459a95cd73..f8546443692 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -77,17 +77,17 @@ void r300_flush(struct pipe_context *pipe,
     }
 
     if (rfence) {
         /* Create a fence, which is a dummy BO. */
         *rfence = r300->rws->buffer_create(r300->rws, 1, 1,
                                            PIPE_BIND_CUSTOM,
-                                           PIPE_USAGE_IMMUTABLE);
+                                           RADEON_DOMAIN_GTT);
         /* Add the fence as a dummy relocation. */
         r300->rws->cs_add_reloc(r300->cs,
                                 r300->rws->buffer_get_cs_handle(*rfence),
-                                RADEON_USAGE_READWRITE);
+                                RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT);
     }
 
     if (r300->dirty_hw) {
         r300_flush_and_cleanup(r300, flags);
     } else {
         if (rfence) {
diff --git a/src/gallium/drivers/r300/r300_query.c b/src/gallium/drivers/r300/r300_query.c
index 8f7de79538d..bcf6d0eb475 100644
--- a/src/gallium/drivers/r300/r300_query.c
+++ b/src/gallium/drivers/r300/r300_query.c
@@ -55,13 +55,13 @@ static struct pipe_query *r300_create_query(struct pipe_context *pipe,
     if (r300screen->caps.family == CHIP_FAMILY_RV530)
         q->num_pipes = r300screen->info.r300_num_z_pipes;
     else
         q->num_pipes = r300screen->info.r300_num_gb_pipes;
 
     q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096,
-                                      PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING);
+                                      PIPE_BIND_CUSTOM, RADEON_DOMAIN_GTT);
     if (!q->buf) {
         FREE(q);
         return NULL;
     }
     q->cs_buf = r300->rws->buffer_get_cs_handle(q->buf);
 
diff --git a/src/gallium/drivers/r300/r300_screen_buffer.c b/src/gallium/drivers/r300/r300_screen_buffer.c
index a5ec8ef9656..a8392d2dc52 100644
--- a/src/gallium/drivers/r300/r300_screen_buffer.c
+++ b/src/gallium/drivers/r300/r300_screen_buffer.c
@@ -184,31 +184,26 @@ struct pipe_resource *r300_buffer_create(struct pipe_screen *screen,
 
     rbuf->b.b.b = *templ;
     rbuf->b.b.vtbl = &r300_buffer_vtbl;
     pipe_reference_init(&rbuf->b.b.b.reference, 1);
     rbuf->b.b.b.screen = screen;
     rbuf->b.user_ptr = NULL;
+    rbuf->domain = RADEON_DOMAIN_GTT;
     rbuf->buf = NULL;
     rbuf->constant_buffer = NULL;
 
     /* Alloc constant buffers in RAM. */
     if (templ->bind & PIPE_BIND_CONSTANT_BUFFER) {
         rbuf->constant_buffer = MALLOC(templ->width0);
         return &rbuf->b.b.b;
     }
 
-#ifdef PIPE_ARCH_BIG_ENDIAN
-    /* Force buffer placement to GTT on big endian machines, because
-     * the vertex fetcher can't swap bytes from VRAM. */
-    rbuf->b.b.b.usage = PIPE_USAGE_STAGING;
-#endif
-
     rbuf->buf =
         r300screen->rws->buffer_create(r300screen->rws,
                                        rbuf->b.b.b.width0, alignment,
-                                       rbuf->b.b.b.bind, rbuf->b.b.b.usage);
+                                       rbuf->b.b.b.bind, rbuf->domain);
     if (!rbuf->buf) {
         util_slab_free(&r300screen->pool_buffers, rbuf);
         return NULL;
     }
 
     rbuf->cs_buf =
@@ -236,10 +231,11 @@ struct pipe_resource *r300_user_buffer_create(struct pipe_screen *screen,
     rbuf->b.b.b.height0 = 1;
     rbuf->b.b.b.depth0 = 1;
     rbuf->b.b.b.array_size = 1;
     rbuf->b.b.b.flags = 0;
     rbuf->b.b.vtbl = &r300_buffer_vtbl;
     rbuf->b.user_ptr = ptr;
+    rbuf->domain = RADEON_DOMAIN_GTT;
     rbuf->buf = NULL;
     rbuf->constant_buffer = NULL;
     return &rbuf->b.b.b;
 }
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 2738f582f69..6fc60fb60d6 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -898,20 +898,23 @@ r300_texture_create_object(struct r300_screen *rscreen,
     tex->b.b.b.bind = base->bind;
     tex->b.b.b.flags = base->flags;
     tex->b.b.vtbl = &r300_texture_vtbl;
     tex->tex.microtile = microtile;
     tex->tex.macrotile[0] = macrotile;
     tex->tex.stride_in_bytes_override = stride_in_bytes_override;
+    tex->domain = base->flags & R300_RESOURCE_FLAG_TRANSFER ?
+                  RADEON_DOMAIN_GTT :
+                  RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT;
     tex->buf = buffer;
 
     r300_resource_set_properties(&rscreen->screen, &tex->b.b.b, base);
 
     /* Create the backing buffer if needed. */
     if (!tex->buf) {
         tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
-                                      base->bind, base->usage);
+                                      base->bind, tex->domain);
 
         if (!tex->buf) {
             FREE(tex);
             return NULL;
         }
     }
@@ -1016,12 +1019,17 @@ struct pipe_surface* r300_create_surface(struct pipe_context * ctx,
         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 
         surface->buf = tex->buf;
         surface->cs_buf = tex->cs_buf;
 
+        /* Prefer VRAM if there are multiple domains to choose from. */
+        surface->domain = tex->domain;
+        if (surface->domain & RADEON_DOMAIN_VRAM)
+            surface->domain &= ~RADEON_DOMAIN_GTT;
+
         surface->offset = r300_texture_get_offset(tex, level,
                                                   surf_tmpl->u.tex.first_layer);
         r300_texture_setup_fb_state(surface);
 
         /* Parameters for the CBZB clear. */
         surface->cbzb_allowed = tex->tex.cbzb_allowed[level];
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index fbd12fbe1b7..4bfb5a980f1 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -85,12 +85,15 @@ struct r600_tiling_info {
 struct r600_resource {
 	struct u_vbuf_resource		b;
 
 	/* Winsys objects. */
 	struct pb_buffer		*buf;
 	struct radeon_winsys_cs_handle	*cs_buf;
+
+	/* Resource state. */
+	unsigned			domains;
 };
 
 /* R600/R700 STATES */
 #define R600_GROUP_MAX			16
 #define R600_BLOCK_MAX_BO		32
 #define R600_BLOCK_MAX_REG		128
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index f4388867a92..a0386fe4b26 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -148,18 +148,46 @@ static const struct u_resource_vtbl r600_buffer_vtbl =
 
 bool r600_init_resource(struct r600_screen *rscreen,
 			struct r600_resource *res,
 			unsigned size, unsigned alignment,
 			unsigned bind, unsigned usage)
 {
-	res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, bind, usage);
+	uint32_t initial_domain, domains;
+
+	/* Staging resources particpate in transfers and blits only
+	 * and are used for uploads and downloads from regular
+	 * resources.  We generate them internally for some transfers.
+	 */
+	if (usage == PIPE_USAGE_STAGING) {
+		domains = RADEON_DOMAIN_GTT;
+		initial_domain = RADEON_DOMAIN_GTT;
+	} else {
+		domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
+
+		switch(usage) {
+		case PIPE_USAGE_DYNAMIC:
+		case PIPE_USAGE_STREAM:
+		case PIPE_USAGE_STAGING:
+			initial_domain = RADEON_DOMAIN_GTT;
+			break;
+		case PIPE_USAGE_DEFAULT:
+		case PIPE_USAGE_STATIC:
+		case PIPE_USAGE_IMMUTABLE:
+		default:
+			initial_domain = RADEON_DOMAIN_VRAM;
+			break;
+		}
+	}
+
+	res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, bind, initial_domain);
 	if (!res->buf) {
 		return false;
 	}
 
 	res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
+	res->domains = domains;
 	return true;
 }
 
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 					 const struct pipe_resource *templ)
 {
diff --git a/src/gallium/drivers/r600/r600_hw_context_priv.h b/src/gallium/drivers/r600/r600_hw_context_priv.h
index 206de7e819f..2ad56242059 100644
--- a/src/gallium/drivers/r600/r600_hw_context_priv.h
+++ b/src/gallium/drivers/r600/r600_hw_context_priv.h
@@ -87,13 +87,13 @@ static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r6
 					     enum radeon_bo_usage usage)
 {
 	unsigned reloc_index;
 
 	assert(usage);
 
-	reloc_index = ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage);
+	reloc_index = ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains);
 	if (reloc_index >= ctx->creloc)
 		ctx->creloc = reloc_index+1;
 
 	pipe_resource_reference((struct pipe_resource**)&ctx->bo[reloc_index], &rbo->b.b.b);
 	return reloc_index * 4;
 }
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 2d041b04e49..8fe54c8a539 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -466,17 +466,19 @@ r600_texture_create_object(struct pipe_screen *screen,
 			FREE(rtex);
 			return NULL;
 		}
 	} else if (buf) {
 		resource->buf = buf;
 		resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
+		resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
 	}
 
 	if (rtex->stencil) {
 		pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
 		rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
+		rtex->stencil->resource.domains = rtex->resource.domains;
 	}
 	return rtex;
 }
 
 DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index ccf9c4f5dc6..d4746ffc535 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -343,17 +343,15 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
     struct radeon_bo *bo;
     struct drm_radeon_gem_create args;
     struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc;
 
     memset(&args, 0, sizeof(args));
 
-    assert(rdesc->initial_domains && rdesc->reloc_domains);
+    assert(rdesc->initial_domains);
     assert((rdesc->initial_domains &
             ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
-    assert((rdesc->reloc_domains &
-            ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
 
     args.size = size;
     args.alignment = desc->alignment;
     args.initial_domain = rdesc->initial_domains;
 
     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
@@ -374,13 +372,12 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
     bo->base.usage = desc->usage;
     bo->base.size = size;
     bo->base.vtbl = &radeon_bo_vtbl;
     bo->mgr = mgr;
     bo->rws = mgr->rws;
     bo->handle = args.handle;
-    bo->reloc_domains = rdesc->reloc_domains;
     pipe_mutex_init(bo->map_mutex);
 
     return &bo->base;
 }
 
 static void radeon_bomgr_flush(struct pb_manager *mgr)
@@ -523,47 +520,26 @@ static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 }
 
 static struct pb_buffer *
 radeon_winsys_bo_create(struct radeon_winsys *rws,
                         unsigned size,
                         unsigned alignment,
-                        unsigned bind, unsigned usage)
+                        unsigned bind,
+                        enum radeon_bo_domain domain)
 {
     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
     struct radeon_bo_desc desc;
     struct pb_manager *provider;
     struct pb_buffer *buffer;
 
     memset(&desc, 0, sizeof(desc));
     desc.base.alignment = alignment;
 
-    /* Determine the memory domains. */
-    switch (usage) {
-    case PIPE_USAGE_STAGING:
-    case PIPE_USAGE_STREAM:
-    case PIPE_USAGE_DYNAMIC:
-            desc.initial_domains = RADEON_GEM_DOMAIN_GTT;
-            desc.reloc_domains = RADEON_GEM_DOMAIN_GTT;
-            break;
-    case PIPE_USAGE_IMMUTABLE:
-    case PIPE_USAGE_STATIC:
-            desc.initial_domains = RADEON_GEM_DOMAIN_VRAM;
-            desc.reloc_domains = RADEON_GEM_DOMAIN_VRAM;
-            break;
-    default:
-            if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
-                        PIPE_BIND_CONSTANT_BUFFER)) {
-                desc.initial_domains = RADEON_GEM_DOMAIN_GTT;
-            } else {
-                desc.initial_domains = RADEON_GEM_DOMAIN_VRAM;
-            }
-            desc.reloc_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
-    }
-
     /* Additional criteria for the cache manager. */
-    desc.base.usage = desc.initial_domains;
+    desc.base.usage = domain;
+    desc.initial_domains = domain;
 
     /* Assign a buffer manager. */
     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
                 PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_CUSTOM))
         provider = ws->cman;
     else
@@ -615,13 +591,12 @@ static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
         FREE(bo);
         goto fail;
     }
     bo->handle = open_arg.handle;
     bo->name = whandle->handle;
-    bo->reloc_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
 
     /* Initialize it. */
     pipe_reference_init(&bo->base.reference, 1);
     bo->base.alignment = 0;
     bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
     bo->base.size = open_arg.size;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
index ba71cfb3440..35d25e87eb3 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
@@ -39,13 +39,12 @@
 struct radeon_bomgr;
 
 struct radeon_bo_desc {
     struct pb_desc base;
 
     unsigned initial_domains;
-    unsigned reloc_domains;
 };
 
 struct radeon_bo {
     struct pb_buffer base;
 
     /* Don't move these! */
@@ -55,13 +54,12 @@ struct radeon_bo {
     struct radeon_bomgr *mgr;
     struct radeon_drm_winsys *rws;
 
     void *ptr;
     pipe_mutex map_mutex;
 
-    uint32_t reloc_domains;
     uint32_t handle;
     uint32_t name;
 
     /* how many command streams is this bo referenced in? */
     int num_cs_references;
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 2239059cc53..e6109afd7ea 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -178,19 +178,20 @@ static struct radeon_winsys_cs *radeon_drm_cs_create(struct radeon_winsys *rws)
     return &cs->base;
 }
 
 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 
 static INLINE void update_reloc_domains(struct drm_radeon_cs_reloc *reloc,
-                                        enum radeon_bo_usage usage,
-                                        unsigned domains)
+                                        enum radeon_bo_domain rd,
+                                        enum radeon_bo_domain wd,
+                                        enum radeon_bo_domain *added_domains)
 {
-    if (usage & RADEON_USAGE_READ)
-        reloc->read_domains |= domains;
-    if (usage & RADEON_USAGE_WRITE)
-        reloc->write_domain |= domains;
+    *added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
+
+    reloc->read_domains |= rd;
+    reloc->write_domain |= wd;
 }
 
 int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
 {
     struct drm_radeon_cs_reloc *reloc;
     unsigned i;
@@ -206,13 +207,13 @@ int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
         for (i = csc->crelocs; i != 0;) {
             --i;
             reloc = &csc->relocs[i];
             if (reloc->handle == bo->handle) {
                 /* Put this reloc in the hash list.
                  * This will prevent additional hash collisions if there are
-                 * several subsequent get_reloc calls of the same buffer.
+                 * several consecutive get_reloc calls for the same buffer.
                  *
                  * Example: Assuming buffers A,B,C collide in the hash list,
                  * the following sequence of relocs:
                  *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
                  * will collide here: ^ and here:   ^,
                  * meaning that we should get very few collisions in the end. */
@@ -227,31 +228,34 @@ int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
     return -1;
 }
 
 static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
                                  struct radeon_bo *bo,
                                  enum radeon_bo_usage usage,
-                                 unsigned *added_domains)
+                                 enum radeon_bo_domain domains,
+                                 enum radeon_bo_domain *added_domains)
 {
     struct drm_radeon_cs_reloc *reloc;
     unsigned i;
     unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1);
+    enum radeon_bo_domain rd = usage & RADEON_USAGE_READ ? domains : 0;
+    enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
 
     if (csc->is_handle_added[hash]) {
         reloc = csc->relocs_hashlist[hash];
         if (reloc->handle == bo->handle) {
-            update_reloc_domains(reloc, usage, bo->reloc_domains);
+            update_reloc_domains(reloc, rd, wd, added_domains);
             return csc->reloc_indices_hashlist[hash];
         }
 
         /* Hash collision, look for the BO in the list of relocs linearly. */
         for (i = csc->crelocs; i != 0;) {
             --i;
             reloc = &csc->relocs[i];
             if (reloc->handle == bo->handle) {
-                update_reloc_domains(reloc, usage, bo->reloc_domains);
+                update_reloc_domains(reloc, rd, wd, added_domains);
 
                 csc->relocs_hashlist[hash] = reloc;
                 csc->reloc_indices_hashlist[hash] = i;
                 /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
                 return i;
             }
@@ -275,41 +279,40 @@ static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
     /* Initialize the new relocation. */
     csc->relocs_bo[csc->crelocs] = NULL;
     radeon_bo_reference(&csc->relocs_bo[csc->crelocs], bo);
     p_atomic_inc(&bo->num_cs_references);
     reloc = &csc->relocs[csc->crelocs];
     reloc->handle = bo->handle;
-    if (usage & RADEON_USAGE_READ)
-        reloc->read_domains = bo->reloc_domains;
-    if (usage & RADEON_USAGE_WRITE)
-        reloc->write_domain = bo->reloc_domains;
+    reloc->read_domains = rd;
+    reloc->write_domain = wd;
     reloc->flags = 0;
 
     csc->is_handle_added[hash] = TRUE;
     csc->relocs_hashlist[hash] = reloc;
     csc->reloc_indices_hashlist[hash] = csc->crelocs;
 
     csc->chunks[1].length_dw += RELOC_DWORDS;
 
-    *added_domains = bo->reloc_domains;
+    *added_domains = rd | wd;
     return csc->crelocs++;
 }
 
 static unsigned radeon_drm_cs_add_reloc(struct radeon_winsys_cs *rcs,
                                         struct radeon_winsys_cs_handle *buf,
-                                        enum radeon_bo_usage usage)
+                                        enum radeon_bo_usage usage,
+                                        enum radeon_bo_domain domains)
 {
     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
     struct radeon_bo *bo = (struct radeon_bo*)buf;
-    unsigned added_domains = 0;
+    enum radeon_bo_domain added_domains;
 
-    unsigned index = radeon_add_reloc(cs->csc, bo, usage, &added_domains);
+    unsigned index = radeon_add_reloc(cs->csc, bo, usage, domains, &added_domains);
 
-    if (added_domains & RADEON_GEM_DOMAIN_GTT)
+    if (added_domains & RADEON_DOMAIN_GTT)
         cs->csc->used_gart += bo->base.size;
-    if (added_domains & RADEON_GEM_DOMAIN_VRAM)
+    if (added_domains & RADEON_DOMAIN_VRAM)
         cs->csc->used_vram += bo->base.size;
 
     return index;
 }
 
 static boolean radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index ea335d87113..59c1aad3308 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -55,12 +55,17 @@ enum radeon_bo_layout {
     RADEON_LAYOUT_TILED,
     RADEON_LAYOUT_SQUARETILED,
 
     RADEON_LAYOUT_UNKNOWN
 };
 
+enum radeon_bo_domain { /* bitfield */
+    RADEON_DOMAIN_GTT  = 2,
+    RADEON_DOMAIN_VRAM = 4
+};
+
 enum radeon_bo_usage { /* bitfield */
     RADEON_USAGE_READ = 2,
     RADEON_USAGE_WRITE = 4,
     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
 };
 
@@ -134,19 +139,20 @@ struct radeon_winsys {
      * Create a buffer object.
      *
      * \param ws        The winsys this function is called from.
      * \param size      The size to allocate.
      * \param alignment An alignment of the buffer in memory.
      * \param bind      A bitmask of the PIPE_BIND_* flags.
-     * \param usage     A bitmask of the PIPE_USAGE_* flags.
+     * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
      * \return          The created buffer object.
      */
     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
                                        unsigned size,
                                        unsigned alignment,
-                                       unsigned bind, unsigned usage);
+                                       unsigned bind,
+                                       enum radeon_bo_domain domain);
 
     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
             struct pb_buffer *buf);
 
     /**
      * Map the entire data store of a buffer object into the client's address
@@ -268,18 +274,20 @@ struct radeon_winsys {
     /**
      * Add a new buffer relocation. Every relocation must first be added
      * before it can be written.
      *
      * \param cs  A command stream to add buffer for validation against.
      * \param buf A winsys buffer to validate.
-     * \param usage  Whether the buffer is used for read and/or write.
+     * \param usage   Whether the buffer is used for read and/or write.
+     * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
      * \return Relocation index.
      */
     unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
                              struct radeon_winsys_cs_handle *buf,
-                             enum radeon_bo_usage usage);
+                             enum radeon_bo_usage usage,
+                             enum radeon_bo_domain domain);
 
     /**
      * Return TRUE if there is enough memory in VRAM and GTT for the relocs
      * added so far. If the validation fails, all the relocations which have
      * been added since the last call of cs_validate will be removed and
      * the CS will be flushed (provided there are still any relocations).