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authorKenneth Graunke <kenneth@whitecape.org>2011-03-29 17:03:22 -0700
committerIan Romanick <ian.d.romanick@intel.com>2011-04-20 15:28:45 -0700
commit62fad6cb302cfb2cb4e0af102486ae8e567047d1 (patch)
treeaa341c95decca005abe7afd8f5276ff28f72c57a
parent0f02b4253d5b3a3bbdfc72711bb9a7c0781061f4 (diff)
intel: Add IS_GT2 macro for recognizing Sandybridge GT2 systems.
Also, refactor IS_GEN6 to use the IS_GT1 and IS_GT2 macros. (cherry picked from commit ee8d182426d4ecda7b9f5089d19d36f7de2a4dfe)
-rw-r--r--src/mesa/drivers/dri/intel/intel_chipset.h13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 4fecdbed203..a3f40effc35 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -125,14 +125,17 @@
/* Compat macro for intel_decode.c */
#define IS_IRONLAKE(devid) IS_GEN5(devid)
-#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+#define IS_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S)
+#define IS_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+ devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+ devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
+
+#define IS_GEN6(devid) (IS_GT1(devid) || IS_GT2(devid))
+
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
IS_GEN5(devid) || \