diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2014-10-02 16:04:57 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2014-10-02 16:38:25 -0700 |
| commit | 493bfa54a57e2feddd887ba0ec3d5ef139e82f3b (patch) | |
| tree | fd7c83b06ab7f98c8223965af272694889b7f9d2 | |
| parent | 50d0e2e118fb3e42dc83c83de34da3eac0a0d8a1 (diff) | |
i965/fs: Use the correct base_mrf for spilling pairs in SIMD8
Before, we were hard-coding the base_mrf based on dispatch width not number
of registers spilled at a time. This caused us to emit instructions with a
base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
register. This fixes the problem.
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 176f91e11d7..32669f689d6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -656,11 +656,12 @@ void fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src, uint32_t spill_offset, int count) { - int spill_base_mrf = dispatch_width > 8 ? 13 : 14; - int reg_size = 1; - if (count % 2 == 0) + int spill_base_mrf = 14; + if (count % 2 == 0) { + spill_base_mrf = 13; reg_size = 2; + } for (int i = 0; i < count / reg_size; i++) { fs_inst *spill_inst = |