diff options
author | Kai Wasserbäch <kai@dev.carbon-project.org> | 2011-11-29 15:04:58 +0100 |
---|---|---|
committer | José Fonseca <jfonseca@vmware.com> | 2011-11-29 15:44:09 +0000 |
commit | 2c27f204f1ca6f09f9520712be1da9a13ed5c01d (patch) | |
tree | 72aa79b2e6680172efe116b51640337f640f8e28 | |
parent | 76ba431b97087e2d5ca0351e0d613f0812fd1425 (diff) |
i965g: Delete this driver.
Never completed, and no plans to do so.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: José Fonseca <jfonseca@vmware.com>
122 files changed, 3 insertions, 37280 deletions
diff --git a/configs/default b/configs/default index 2b1bf9bef3d..48fbbf366e0 100644 --- a/configs/default +++ b/configs/default | |||
@@ -119,7 +119,7 @@ GBM_BACKEND_DIRS = dri | |||
119 | # Gallium directories and | 119 | # Gallium directories and |
120 | GALLIUM_DIRS = auxiliary drivers state_trackers | 120 | GALLIUM_DIRS = auxiliary drivers state_trackers |
121 | GALLIUM_AUXILIARIES = $(TOP)/src/gallium/auxiliary/libgallium.a | 121 | GALLIUM_AUXILIARIES = $(TOP)/src/gallium/auxiliary/libgallium.a |
122 | GALLIUM_DRIVERS_DIRS = softpipe trace rbug noop identity galahad i915 i965 svga r300 nvfx nv50 failover | 122 | GALLIUM_DRIVERS_DIRS = softpipe trace rbug noop identity galahad i915 svga r300 nvfx nv50 failover |
123 | GALLIUM_DRIVERS = $(foreach DIR,$(GALLIUM_DRIVERS_DIRS),$(TOP)/src/gallium/drivers/$(DIR)/lib$(DIR).a) | 123 | GALLIUM_DRIVERS = $(foreach DIR,$(GALLIUM_DRIVERS_DIRS),$(TOP)/src/gallium/drivers/$(DIR)/lib$(DIR).a) |
124 | GALLIUM_WINSYS_DIRS = sw sw/xlib | 124 | GALLIUM_WINSYS_DIRS = sw sw/xlib |
125 | GALLIUM_TARGET_DIRS = libgl-xlib | 125 | GALLIUM_TARGET_DIRS = libgl-xlib |
diff --git a/configs/linux-dri b/configs/linux-dri index 44c0c3d1d9b..6990c3a7a80 100644 --- a/configs/linux-dri +++ b/configs/linux-dri | |||
@@ -58,7 +58,7 @@ SRC_DIRS := glx egl $(SRC_DIRS) | |||
58 | EGL_DRIVERS_DIRS = glx | 58 | EGL_DRIVERS_DIRS = glx |
59 | 59 | ||
60 | DRIVER_DIRS = dri | 60 | DRIVER_DIRS = dri |
61 | GALLIUM_WINSYS_DIRS = sw sw/xlib drm/vmware drm/intel drm/i965 svga/drm | 61 | GALLIUM_WINSYS_DIRS = sw sw/xlib drm/vmware drm/intel svga/drm |
62 | GALLIUM_TARGET_DIRS = dri-vmwgfx | 62 | GALLIUM_TARGET_DIRS = dri-vmwgfx |
63 | GALLIUM_STATE_TRACKERS_DIRS = egl dri | 63 | GALLIUM_STATE_TRACKERS_DIRS = egl dri |
64 | 64 | ||
diff --git a/configs/linux-i965 b/configs/linux-i965 deleted file mode 100644 index 7656a2adc5e..00000000000 --- a/configs/linux-i965 +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | # Configuration for standalone mode i965 debug | ||
2 | |||
3 | include $(TOP)/configs/linux-debug | ||
4 | |||
5 | CONFIG_NAME = linux-i965 | ||
6 | |||
7 | GALLIUM_DRIVER_DIRS = i965 | ||
8 | GALLIUM_WINSYS_DIRS = drm/i965/xlib | ||
9 | GALLIUM_TARGET_DIRS = | ||
diff --git a/configure.ac b/configure.ac index 39d4e0f552e..748df90abf4 100644 --- a/configure.ac +++ b/configure.ac | |||
@@ -1844,14 +1844,6 @@ if test "x$with_gallium_drivers" != x; then | |||
1844 | GALLIUM_WINSYS_DIRS="$GALLIUM_WINSYS_DIRS i915/sw" | 1844 | GALLIUM_WINSYS_DIRS="$GALLIUM_WINSYS_DIRS i915/sw" |
1845 | gallium_check_st "i915/drm" "dri-i915" "xorg-i915" | 1845 | gallium_check_st "i915/drm" "dri-i915" "xorg-i915" |
1846 | ;; | 1846 | ;; |
1847 | xi965) | ||
1848 | PKG_CHECK_MODULES([INTEL], [libdrm_intel >= $LIBDRM_INTEL_REQUIRED]) | ||
1849 | GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS i965 softpipe" | ||
1850 | if test "x$MESA_LLVM" = x1; then | ||
1851 | GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS llvmpipe" | ||
1852 | fi | ||
1853 | gallium_check_st "i965/drm" "dri-i965" "xorg-i965" | ||
1854 | ;; | ||
1855 | xr300) | 1847 | xr300) |
1856 | gallium_require_llvm "Gallium R300" | 1848 | gallium_require_llvm "Gallium R300" |
1857 | GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS r300" | 1849 | GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS r300" |
@@ -2019,12 +2011,6 @@ if echo "$SRC_DIRS" | grep 'gallium' >/dev/null 2>&1; then | |||
2019 | echo " Winsys dirs: $GALLIUM_WINSYS_DIRS" | 2011 | echo " Winsys dirs: $GALLIUM_WINSYS_DIRS" |
2020 | echo " Driver dirs: $GALLIUM_DRIVERS_DIRS" | 2012 | echo " Driver dirs: $GALLIUM_DRIVERS_DIRS" |
2021 | echo " Trackers dirs: $GALLIUM_STATE_TRACKERS_DIRS" | 2013 | echo " Trackers dirs: $GALLIUM_STATE_TRACKERS_DIRS" |
2022 | if echo "$GALLIUM_DRIVERS_DIRS" | grep i965 > /dev/null 2>&1; then | ||
2023 | echo | ||
2024 | echo " WARNING: enabling i965 gallium driver" | ||
2025 | echo " the i965g driver is currently utterly broken, only for adventurous developers" | ||
2026 | echo | ||
2027 | fi | ||
2028 | else | 2014 | else |
2029 | echo " Gallium: no" | 2015 | echo " Gallium: no" |
2030 | fi | 2016 | fi |
diff --git a/src/gallium/SConscript b/src/gallium/SConscript index d9fd48425a0..f65bc2daac3 100644 --- a/src/gallium/SConscript +++ b/src/gallium/SConscript | |||
@@ -25,7 +25,6 @@ if not env['msvc']: | |||
25 | # These drivers do not build on MSVC compilers | 25 | # These drivers do not build on MSVC compilers |
26 | SConscript([ | 26 | SConscript([ |
27 | 'drivers/i915/SConscript', | 27 | 'drivers/i915/SConscript', |
28 | 'drivers/i965/SConscript', | ||
29 | 'drivers/r300/SConscript', | 28 | 'drivers/r300/SConscript', |
30 | ]) | 29 | ]) |
31 | 30 | ||
@@ -112,7 +111,6 @@ if not env['embedded']: | |||
112 | if env['drm_intel']: | 111 | if env['drm_intel']: |
113 | SConscript([ | 112 | SConscript([ |
114 | 'targets/dri-i915/SConscript', | 113 | 'targets/dri-i915/SConscript', |
115 | 'targets/dri-i965/SConscript', | ||
116 | ]) | 114 | ]) |
117 | if env['drm_radeon']: | 115 | if env['drm_radeon']: |
118 | SConscript([ | 116 | SConscript([ |
@@ -123,7 +121,6 @@ if not env['embedded']: | |||
123 | if env['xorg'] and env['drm']: | 121 | if env['xorg'] and env['drm']: |
124 | SConscript([ | 122 | SConscript([ |
125 | #'targets/xorg-i915/SConscript', | 123 | #'targets/xorg-i915/SConscript', |
126 | #'targets/xorg-i965/SConscript', | ||
127 | #'targets/xorg-nouveau/SConscript', | 124 | #'targets/xorg-nouveau/SConscript', |
128 | #'targets/xorg-radeon/SConscript', | 125 | #'targets/xorg-radeon/SConscript', |
129 | ]) | 126 | ]) |
diff --git a/src/gallium/docs/source/distro.rst b/src/gallium/docs/source/distro.rst index 08c8eab890a..c69ab23a97d 100644 --- a/src/gallium/docs/source/distro.rst +++ b/src/gallium/docs/source/distro.rst | |||
@@ -23,11 +23,6 @@ Intel i915 | |||
23 | 23 | ||
24 | Driver for Intel i915 and i945 chipsets. | 24 | Driver for Intel i915 and i945 chipsets. |
25 | 25 | ||
26 | Intel i965 | ||
27 | ^^^^^^^^^^ | ||
28 | |||
29 | Highly experimental driver for Intel i965 chipsets. | ||
30 | |||
31 | Identity | 26 | Identity |
32 | ^^^^^^^^ | 27 | ^^^^^^^^ |
33 | 28 | ||
diff --git a/src/gallium/drivers/i965/Makefile b/src/gallium/drivers/i965/Makefile deleted file mode 100644 index a0331f80581..00000000000 --- a/src/gallium/drivers/i965/Makefile +++ /dev/null | |||
@@ -1,74 +0,0 @@ | |||
1 | TOP = ../../../.. | ||
2 | include $(TOP)/configs/current | ||
3 | |||
4 | LIBNAME = i965 | ||
5 | |||
6 | C_SOURCES = \ | ||
7 | brw_cc.c \ | ||
8 | brw_clip.c \ | ||
9 | brw_clip_line.c \ | ||
10 | brw_clip_point.c \ | ||
11 | brw_clip_state.c \ | ||
12 | brw_clip_tri.c \ | ||
13 | brw_clip_unfilled.c \ | ||
14 | brw_clip_util.c \ | ||
15 | brw_context.c \ | ||
16 | brw_curbe.c \ | ||
17 | brw_disasm.c \ | ||
18 | brw_draw.c \ | ||
19 | brw_draw_upload.c \ | ||
20 | brw_eu.c \ | ||
21 | brw_eu_debug.c \ | ||
22 | brw_eu_emit.c \ | ||
23 | brw_eu_util.c \ | ||
24 | brw_gs.c \ | ||
25 | brw_gs_emit.c \ | ||
26 | brw_gs_state.c \ | ||
27 | brw_misc_state.c \ | ||
28 | brw_pipe_blend.c \ | ||
29 | brw_pipe_depth.c \ | ||
30 | brw_pipe_fb.c \ | ||
31 | brw_pipe_query.c \ | ||
32 | brw_pipe_shader.c \ | ||
33 | brw_pipe_flush.c \ | ||
34 | brw_pipe_misc.c \ | ||
35 | brw_pipe_sampler.c \ | ||
36 | brw_pipe_surface.c \ | ||
37 | brw_pipe_vertex.c \ | ||
38 | brw_pipe_clear.c \ | ||
39 | brw_pipe_rast.c \ | ||
40 | brw_resource.c \ | ||
41 | brw_sf.c \ | ||
42 | brw_sf_emit.c \ | ||
43 | brw_sf_state.c \ | ||
44 | brw_state_batch.c \ | ||
45 | brw_state_debug.c \ | ||
46 | brw_state_cache.c \ | ||
47 | brw_state_upload.c \ | ||
48 | brw_structs_dump.c \ | ||
49 | brw_swtnl.c \ | ||
50 | brw_urb.c \ | ||
51 | brw_vs.c \ | ||
52 | brw_vs_emit.c \ | ||
53 | brw_vs_state.c \ | ||
54 | brw_vs_surface_state.c \ | ||
55 | brw_wm.c \ | ||
56 | brw_wm_debug.c \ | ||
57 | brw_wm_emit.c \ | ||
58 | brw_wm_fp.c \ | ||
59 | brw_wm_iz.c \ | ||
60 | brw_wm_pass0.c \ | ||
61 | brw_wm_pass1.c \ | ||
62 | brw_wm_pass2.c \ | ||
63 | brw_wm_sampler_state.c \ | ||
64 | brw_wm_state.c \ | ||
65 | brw_wm_surface_state.c \ | ||
66 | brw_screen.c \ | ||
67 | brw_resource_buffer.c \ | ||
68 | brw_resource_texture.c \ | ||
69 | brw_resource_texture_layout.c \ | ||
70 | brw_batchbuffer.c \ | ||
71 | brw_winsys_debug.c \ | ||
72 | intel_decode.c | ||
73 | |||
74 | include ../../Makefile.template | ||
diff --git a/src/gallium/drivers/i965/SConscript b/src/gallium/drivers/i965/SConscript deleted file mode 100644 index 3ef6c880305..00000000000 --- a/src/gallium/drivers/i965/SConscript +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | Import('*') | ||
2 | |||
3 | env = env.Clone() | ||
4 | |||
5 | i965 = env.ConvenienceLibrary( | ||
6 | target = 'i965', | ||
7 | source = [ | ||
8 | 'brw_batchbuffer.c', | ||
9 | 'brw_cc.c', | ||
10 | 'brw_clip.c', | ||
11 | 'brw_clip_line.c', | ||
12 | 'brw_clip_point.c', | ||
13 | 'brw_clip_state.c', | ||
14 | 'brw_clip_tri.c', | ||
15 | 'brw_clip_unfilled.c', | ||
16 | 'brw_clip_util.c', | ||
17 | 'brw_context.c', | ||
18 | 'brw_curbe.c', | ||
19 | 'brw_disasm.c', | ||
20 | 'brw_draw.c', | ||
21 | 'brw_draw_upload.c', | ||
22 | 'brw_eu.c', | ||
23 | 'brw_eu_debug.c', | ||
24 | 'brw_eu_emit.c', | ||
25 | 'brw_eu_util.c', | ||
26 | 'brw_gs.c', | ||
27 | 'brw_gs_emit.c', | ||
28 | 'brw_gs_state.c', | ||
29 | 'brw_misc_state.c', | ||
30 | 'brw_pipe_blend.c', | ||
31 | 'brw_pipe_clear.c', | ||
32 | 'brw_pipe_depth.c', | ||
33 | 'brw_pipe_fb.c', | ||
34 | 'brw_pipe_flush.c', | ||
35 | 'brw_pipe_misc.c', | ||
36 | 'brw_pipe_query.c', | ||
37 | 'brw_pipe_rast.c', | ||
38 | 'brw_pipe_sampler.c', | ||
39 | 'brw_pipe_surface.c', | ||
40 | 'brw_pipe_surface.c', | ||
41 | 'brw_pipe_shader.c', | ||
42 | 'brw_pipe_vertex.c', | ||
43 | 'brw_resource.c', | ||
44 | 'brw_resource_buffer.c', | ||
45 | 'brw_resource_texture.c', | ||
46 | 'brw_resource_texture_layout.c', | ||
47 | 'brw_screen.c', | ||
48 | 'brw_structs_dump.c', | ||
49 | 'brw_sf.c', | ||
50 | 'brw_sf_emit.c', | ||
51 | 'brw_sf_state.c', | ||
52 | 'brw_state_batch.c', | ||
53 | 'brw_state_cache.c', | ||
54 | 'brw_state_debug.c', | ||
55 | 'brw_state_upload.c', | ||
56 | 'brw_swtnl.c', | ||
57 | 'brw_urb.c', | ||
58 | 'brw_vs.c', | ||
59 | 'brw_vs_emit.c', | ||
60 | 'brw_vs_state.c', | ||
61 | 'brw_vs_surface_state.c', | ||
62 | 'brw_winsys_debug.c', | ||
63 | 'brw_wm.c', | ||
64 | # 'brw_wm_constant_buffer.c', | ||
65 | 'brw_wm_debug.c', | ||
66 | 'brw_wm_emit.c', | ||
67 | 'brw_wm_fp.c', | ||
68 | # 'brw_wm_glsl.c', | ||
69 | 'brw_wm_iz.c', | ||
70 | 'brw_wm_pass0.c', | ||
71 | 'brw_wm_pass1.c', | ||
72 | 'brw_wm_pass2.c', | ||
73 | 'brw_wm_sampler_state.c', | ||
74 | 'brw_wm_state.c', | ||
75 | 'brw_wm_surface_state.c', | ||
76 | 'intel_decode.c', | ||
77 | ]) | ||
78 | |||
79 | Export('i965') | ||
diff --git a/src/gallium/drivers/i965/brw_batchbuffer.c b/src/gallium/drivers/i965/brw_batchbuffer.c deleted file mode 100644 index 3c935792465..00000000000 --- a/src/gallium/drivers/i965/brw_batchbuffer.c +++ /dev/null | |||
@@ -1,200 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #include "util/u_memory.h" | ||
29 | |||
30 | #include "brw_batchbuffer.h" | ||
31 | #include "brw_reg.h" | ||
32 | #include "brw_winsys.h" | ||
33 | #include "brw_debug.h" | ||
34 | #include "brw_structs.h" | ||
35 | |||
36 | #define ALWAYS_EMIT_MI_FLUSH 1 | ||
37 | |||
38 | enum pipe_error | ||
39 | brw_batchbuffer_reset(struct brw_batchbuffer *batch) | ||
40 | { | ||
41 | enum pipe_error ret; | ||
42 | |||
43 | ret = batch->sws->bo_alloc( batch->sws, | ||
44 | BRW_BUFFER_TYPE_BATCH, | ||
45 | BRW_BATCH_SIZE, 4096, | ||
46 | &batch->buf ); | ||
47 | if (ret) | ||
48 | return ret; | ||
49 | |||
50 | batch->size = BRW_BATCH_SIZE; | ||
51 | |||
52 | /* With map_range semantics, the winsys can decide whether to | ||
53 | * inject a malloc'ed bounce buffer instead of mapping directly. | ||
54 | */ | ||
55 | batch->map = batch->sws->bo_map(batch->buf, | ||
56 | BRW_DATA_BATCH_BUFFER, | ||
57 | 0, batch->size, | ||
58 | GL_TRUE, | ||
59 | GL_TRUE, | ||
60 | GL_TRUE); | ||
61 | |||
62 | batch->ptr = batch->map; | ||
63 | return PIPE_OK; | ||
64 | } | ||
65 | |||
66 | struct brw_batchbuffer * | ||
67 | brw_batchbuffer_alloc(struct brw_winsys_screen *sws) | ||
68 | { | ||
69 | struct brw_batchbuffer *batch = CALLOC_STRUCT(brw_batchbuffer); | ||
70 | |||
71 | batch->sws = sws; | ||
72 | brw_batchbuffer_reset(batch); | ||
73 | |||
74 | return batch; | ||
75 | } | ||
76 | |||
77 | void | ||
78 | brw_batchbuffer_free(struct brw_batchbuffer *batch) | ||
79 | { | ||
80 | if (batch->map) { | ||
81 | batch->sws->bo_unmap(batch->buf); | ||
82 | batch->map = NULL; | ||
83 | } | ||
84 | |||
85 | bo_reference(&batch->buf, NULL); | ||
86 | FREE(batch); | ||
87 | } | ||
88 | |||
89 | |||
90 | void | ||
91 | _brw_batchbuffer_flush(struct brw_batchbuffer *batch, | ||
92 | const char *file, | ||
93 | int line) | ||
94 | { | ||
95 | GLuint used = batch->ptr - batch->map; | ||
96 | |||
97 | if (used == 0) | ||
98 | return; | ||
99 | |||
100 | /* Post-swap throttling done by the state tracker. | ||
101 | */ | ||
102 | |||
103 | if (BRW_DEBUG & DEBUG_BATCH) | ||
104 | debug_printf("%s:%d: Batchbuffer flush with %db used\n", | ||
105 | file, line, used); | ||
106 | |||
107 | if (ALWAYS_EMIT_MI_FLUSH) { | ||
108 | *(GLuint *) (batch->ptr) = MI_FLUSH | BRW_FLUSH_STATE_CACHE; | ||
109 | batch->ptr += 4; | ||
110 | used = batch->ptr - batch->map; | ||
111 | } | ||
112 | |||
113 | /* Round batchbuffer usage to 2 DWORDs. | ||
114 | */ | ||
115 | if ((used & 4) == 0) { | ||
116 | *(GLuint *) (batch->ptr) = 0; /* noop */ | ||
117 | batch->ptr += 4; | ||
118 | used = batch->ptr - batch->map; | ||
119 | } | ||
120 | |||
121 | /* Mark the end of the buffer. | ||
122 | */ | ||
123 | *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; | ||
124 | batch->ptr += 4; | ||
125 | used = batch->ptr - batch->map; | ||
126 | |||
127 | batch->sws->bo_flush_range(batch->buf, 0, used); | ||
128 | batch->sws->bo_unmap(batch->buf); | ||
129 | batch->map = NULL; | ||
130 | batch->ptr = NULL; | ||
131 | |||
132 | batch->sws->bo_exec(batch->buf, used ); | ||
133 | |||
134 | if (BRW_DEBUG & DEBUG_SYNC) { | ||
135 | /* Abuse map/unmap to achieve wait-for-fence. | ||
136 | * | ||
137 | * XXX: hide this inside the winsys and export a fence | ||
138 | * interface. | ||
139 | */ | ||
140 | debug_printf("waiting for idle\n"); | ||
141 | batch->sws->bo_wait_idle(batch->buf); | ||
142 | } | ||
143 | |||
144 | /* Reset the buffer: | ||
145 | */ | ||
146 | brw_batchbuffer_reset(batch); | ||
147 | } | ||
148 | |||
149 | |||
150 | /* The OUT_RELOC() macro ends up here, generating a relocation within | ||
151 | * the batch buffer. | ||
152 | */ | ||
153 | enum pipe_error | ||
154 | brw_batchbuffer_emit_reloc(struct brw_batchbuffer *batch, | ||
155 | struct brw_winsys_buffer *buffer, | ||
156 | enum brw_buffer_usage usage, | ||
157 | uint32_t delta) | ||
158 | { | ||
159 | int ret; | ||
160 | |||
161 | if (batch->ptr - batch->map > batch->buf->size) { | ||
162 | debug_printf("bad relocation ptr %p map %p offset %li size %i\n", | ||
163 | batch->ptr, batch->map, (long) (batch->ptr - batch->map), batch->buf->size); | ||
164 | |||
165 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
166 | } | ||
167 | |||
168 | ret = batch->sws->bo_emit_reloc(batch->buf, | ||
169 | usage, | ||
170 | delta, | ||
171 | batch->ptr - batch->map, | ||
172 | buffer); | ||
173 | if (ret != 0) | ||
174 | return ret; | ||
175 | |||
176 | /* bo_emit_reloc was resposible for writing a zero into the | ||
177 | * batchbuffer if necessary. Just need to update our pointer. | ||
178 | */ | ||
179 | batch->ptr += 4; | ||
180 | |||
181 | return 0; | ||
182 | } | ||
183 | |||
184 | enum pipe_error | ||
185 | brw_batchbuffer_data(struct brw_batchbuffer *batch, | ||
186 | const void *data, GLuint bytes, | ||
187 | enum cliprect_mode cliprect_mode) | ||
188 | { | ||
189 | enum pipe_error ret; | ||
190 | |||
191 | assert((bytes & 3) == 0); | ||
192 | |||
193 | ret = brw_batchbuffer_require_space(batch, bytes); | ||
194 | if (ret) | ||
195 | return ret; | ||
196 | |||
197 | memcpy(batch->ptr, data, bytes); | ||
198 | batch->ptr += bytes; | ||
199 | return 0; | ||
200 | } | ||
diff --git a/src/gallium/drivers/i965/brw_batchbuffer.h b/src/gallium/drivers/i965/brw_batchbuffer.h deleted file mode 100644 index 6ecb91857dd..00000000000 --- a/src/gallium/drivers/i965/brw_batchbuffer.h +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | #ifndef BRW_BATCHBUFFER_H | ||
2 | #define BRW_BATCHBUFFER_H | ||
3 | |||
4 | #include "util/u_debug.h" | ||
5 | |||
6 | #include "brw_types.h" | ||
7 | #include "brw_winsys.h" | ||
8 | #include "brw_reg.h" | ||
9 | |||
10 | #define BATCH_SZ 16384 | ||
11 | #define BATCH_RESERVED 16 | ||
12 | |||
13 | /* All ignored: | ||
14 | */ | ||
15 | enum cliprect_mode { | ||
16 | IGNORE_CLIPRECTS, | ||
17 | LOOP_CLIPRECTS, | ||
18 | NO_LOOP_CLIPRECTS, | ||
19 | REFERENCES_CLIPRECTS | ||
20 | }; | ||
21 | |||
22 | |||
23 | |||
24 | |||
25 | struct brw_batchbuffer { | ||
26 | |||
27 | struct brw_winsys_screen *sws; | ||
28 | struct brw_winsys_buffer *buf; | ||
29 | |||
30 | /** | ||
31 | * Values exported to speed up the writing the batchbuffer, | ||
32 | * instead of having to go trough a accesor function for | ||
33 | * each dword written. | ||
34 | */ | ||
35 | /*{@*/ | ||
36 | uint8_t *map; | ||
37 | uint8_t *ptr; | ||
38 | size_t size; | ||
39 | struct { | ||
40 | uint8_t *end_ptr; | ||
41 | } emit; | ||
42 | |||
43 | |||
44 | size_t relocs; | ||
45 | size_t max_relocs; | ||
46 | /*@}*/ | ||
47 | }; | ||
48 | |||
49 | struct brw_batchbuffer *brw_batchbuffer_alloc( struct brw_winsys_screen *sws ); | ||
50 | |||
51 | |||
52 | void brw_batchbuffer_free(struct brw_batchbuffer *batch); | ||
53 | |||
54 | void _brw_batchbuffer_flush(struct brw_batchbuffer *batch, | ||
55 | const char *file, int line); | ||
56 | |||
57 | |||
58 | enum pipe_error | ||
59 | brw_batchbuffer_reset(struct brw_batchbuffer *batch); | ||
60 | |||
61 | |||
62 | /* Unlike bmBufferData, this currently requires the buffer be mapped. | ||
63 | * Consider it a convenience function wrapping multple | ||
64 | * intel_buffer_dword() calls. | ||
65 | */ | ||
66 | enum pipe_error brw_batchbuffer_data(struct brw_batchbuffer *batch, | ||
67 | const void *data, GLuint bytes, | ||
68 | enum cliprect_mode cliprect_mode); | ||
69 | |||
70 | |||
71 | enum pipe_error brw_batchbuffer_emit_reloc(struct brw_batchbuffer *batch, | ||
72 | struct brw_winsys_buffer *buffer, | ||
73 | enum brw_buffer_usage usage, | ||
74 | uint32_t offset); | ||
75 | |||
76 | /* Inline functions - might actually be better off with these | ||
77 | * non-inlined. Certainly better off switching all command packets to | ||
78 | * be passed as structs rather than dwords, but that's a little bit of | ||
79 | * work... | ||
80 | */ | ||
81 | static INLINE GLint | ||
82 | brw_batchbuffer_space(struct brw_batchbuffer *batch) | ||
83 | { | ||
84 | return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map); | ||
85 | } | ||
86 | |||
87 | |||
88 | static INLINE void | ||
89 | brw_batchbuffer_emit_dword(struct brw_batchbuffer *batch, GLuint dword) | ||
90 | { | ||
91 | assert(batch->map); | ||
92 | assert(brw_batchbuffer_space(batch) >= 4); | ||
93 | *(GLuint *) (batch->ptr) = dword; | ||
94 | batch->ptr += 4; | ||
95 | } | ||
96 | |||
97 | static INLINE enum pipe_error | ||
98 | brw_batchbuffer_require_space(struct brw_batchbuffer *batch, | ||
99 | GLuint sz) | ||
100 | { | ||
101 | assert(sz < batch->size - 8); | ||
102 | if (brw_batchbuffer_space(batch) < sz) { | ||
103 | assert(0); | ||
104 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
105 | } | ||
106 | #ifdef DEBUG | ||
107 | batch->emit.end_ptr = batch->ptr + sz; | ||
108 | #endif | ||
109 | return 0; | ||
110 | } | ||
111 | |||
112 | /* Here are the crusty old macros, to be removed: | ||
113 | */ | ||
114 | #define BEGIN_BATCH(n, cliprect_mode) do { \ | ||
115 | brw_batchbuffer_require_space(brw->batch, (n)*4); \ | ||
116 | } while (0) | ||
117 | |||
118 | #define OUT_BATCH(d) brw_batchbuffer_emit_dword(brw->batch, d) | ||
119 | |||
120 | #define OUT_RELOC(buf, usage, delta) do { \ | ||
121 | assert((unsigned) (delta) < buf->size); \ | ||
122 | brw_batchbuffer_emit_reloc(brw->batch, buf, \ | ||
123 | usage, delta); \ | ||
124 | } while (0) | ||
125 | |||
126 | #ifdef DEBUG | ||
127 | #define ADVANCE_BATCH() do { \ | ||
128 | unsigned int _n = brw->batch->ptr - brw->batch->emit.end_ptr; \ | ||
129 | if (_n != 0) { \ | ||
130 | debug_printf("%s: %d too many bytes emitted to batch\n", \ | ||
131 | __FUNCTION__, _n); \ | ||
132 | abort(); \ | ||
133 | } \ | ||
134 | brw->batch->emit.end_ptr = NULL; \ | ||
135 | } while(0) | ||
136 | #else | ||
137 | #define ADVANCE_BATCH() | ||
138 | #endif | ||
139 | |||
140 | static INLINE void | ||
141 | brw_batchbuffer_emit_mi_flush(struct brw_batchbuffer *batch) | ||
142 | { | ||
143 | brw_batchbuffer_require_space(batch, 4); | ||
144 | brw_batchbuffer_emit_dword(batch, MI_FLUSH); | ||
145 | } | ||
146 | |||
147 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_cc.c b/src/gallium/drivers/i965/brw_cc.c deleted file mode 100644 index cc8e380c68b..00000000000 --- a/src/gallium/drivers/i965/brw_cc.c +++ /dev/null | |||
@@ -1,129 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_context.h" | ||
34 | #include "brw_state.h" | ||
35 | |||
36 | |||
37 | static enum pipe_error prepare_cc_vp( struct brw_context *brw ) | ||
38 | { | ||
39 | return brw_cache_data( &brw->cache, | ||
40 | BRW_CC_VP, | ||
41 | &brw->curr.ccv, | ||
42 | NULL, 0, | ||
43 | &brw->cc.reloc[CC_RELOC_VP].bo ); | ||
44 | } | ||
45 | |||
46 | const struct brw_tracked_state brw_cc_vp = { | ||
47 | .dirty = { | ||
48 | .mesa = PIPE_NEW_VIEWPORT, | ||
49 | .brw = BRW_NEW_CONTEXT, | ||
50 | .cache = 0 | ||
51 | }, | ||
52 | .prepare = prepare_cc_vp | ||
53 | }; | ||
54 | |||
55 | |||
56 | /* A long-winded way to OR two unsigned integers together: | ||
57 | */ | ||
58 | static INLINE struct brw_cc3 | ||
59 | combine_cc3( struct brw_cc3 a, struct brw_cc3 b ) | ||
60 | { | ||
61 | union { struct brw_cc3 cc3; unsigned i; } ca, cb; | ||
62 | ca.cc3 = a; | ||
63 | cb.cc3 = b; | ||
64 | ca.i |= cb.i; | ||
65 | return ca.cc3; | ||
66 | } | ||
67 | |||
68 | static INLINE struct brw_cc1 | ||
69 | combine_cc1( struct brw_cc1 a, struct brw_cc1 b ) | ||
70 | { | ||
71 | union { struct brw_cc1 cc1; unsigned i; } ca, cb; | ||
72 | ca.cc1 = a; | ||
73 | cb.cc1 = b; | ||
74 | ca.i |= cb.i; | ||
75 | return ca.cc1; | ||
76 | } | ||
77 | |||
78 | static INLINE struct brw_cc2 | ||
79 | combine_cc2( struct brw_cc2 a, struct brw_cc2 b ) | ||
80 | { | ||
81 | union { struct brw_cc2 cc2; unsigned i; } ca, cb; | ||
82 | ca.cc2 = a; | ||
83 | cb.cc2 = b; | ||
84 | ca.i |= cb.i; | ||
85 | return ca.cc2; | ||
86 | } | ||
87 | |||
88 | static int prepare_cc_unit( struct brw_context *brw ) | ||
89 | { | ||
90 | brw->cc.cc.cc0 = brw->curr.zstencil->cc0; | ||
91 | brw->cc.cc.cc1 = combine_cc1( brw->curr.zstencil->cc1, brw->curr.cc1_stencil_ref ); | ||
92 | brw->cc.cc.cc2 = combine_cc2( brw->curr.zstencil->cc2, brw->curr.blend->cc2 ); | ||
93 | brw->cc.cc.cc3 = combine_cc3( brw->curr.zstencil->cc3, brw->curr.blend->cc3 ); | ||
94 | |||
95 | brw->cc.cc.cc5 = brw->curr.blend->cc5; | ||
96 | brw->cc.cc.cc6 = brw->curr.blend->cc6; | ||
97 | brw->cc.cc.cc7 = brw->curr.zstencil->cc7; | ||
98 | |||
99 | return brw_cache_data_sz(&brw->cache, BRW_CC_UNIT, | ||
100 | &brw->cc.cc, sizeof(brw->cc.cc), | ||
101 | brw->cc.reloc, 1, | ||
102 | &brw->cc.state_bo); | ||
103 | } | ||
104 | |||
105 | const struct brw_tracked_state brw_cc_unit = { | ||
106 | .dirty = { | ||
107 | .mesa = PIPE_NEW_DEPTH_STENCIL_ALPHA | PIPE_NEW_BLEND, | ||
108 | .brw = 0, | ||
109 | .cache = CACHE_NEW_CC_VP | ||
110 | }, | ||
111 | .prepare = prepare_cc_unit, | ||
112 | }; | ||
113 | |||
114 | |||
115 | void brw_hw_cc_init( struct brw_context *brw ) | ||
116 | { | ||
117 | make_reloc(&brw->cc.reloc[0], | ||
118 | BRW_USAGE_STATE, | ||
119 | 0, | ||
120 | offsetof(struct brw_cc_unit_state, cc4), | ||
121 | NULL); | ||
122 | } | ||
123 | |||
124 | |||
125 | void brw_hw_cc_cleanup( struct brw_context *brw ) | ||
126 | { | ||
127 | bo_reference(&brw->cc.state_bo, NULL); | ||
128 | bo_reference(&brw->cc.reloc[0].bo, NULL); | ||
129 | } | ||
diff --git a/src/gallium/drivers/i965/brw_clip.c b/src/gallium/drivers/i965/brw_clip.c deleted file mode 100644 index 66b13ea58e2..00000000000 --- a/src/gallium/drivers/i965/brw_clip.c +++ /dev/null | |||
@@ -1,221 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "pipe/p_state.h" | ||
33 | |||
34 | #include "util/u_math.h" | ||
35 | |||
36 | #include "brw_screen.h" | ||
37 | #include "brw_batchbuffer.h" | ||
38 | #include "brw_defines.h" | ||
39 | #include "brw_context.h" | ||
40 | #include "brw_eu.h" | ||
41 | #include "brw_state.h" | ||
42 | #include "brw_pipe_rast.h" | ||
43 | #include "brw_clip.h" | ||
44 | |||
45 | |||
46 | #define FRONT_UNFILLED_BIT 0x1 | ||
47 | #define BACK_UNFILLED_BIT 0x2 | ||
48 | |||
49 | |||
50 | static enum pipe_error | ||
51 | compile_clip_prog( struct brw_context *brw, | ||
52 | struct brw_clip_prog_key *key, | ||
53 | struct brw_winsys_buffer **bo_out ) | ||
54 | { | ||
55 | enum pipe_error ret; | ||
56 | struct brw_clip_compile c; | ||
57 | const GLuint *program; | ||
58 | GLuint program_size; | ||
59 | GLuint delta; | ||
60 | |||
61 | memset(&c, 0, sizeof(c)); | ||
62 | |||
63 | /* Begin the compilation: | ||
64 | */ | ||
65 | brw_init_compile(brw, &c.func); | ||
66 | |||
67 | c.func.single_program_flow = 1; | ||
68 | |||
69 | c.key = *key; | ||
70 | |||
71 | /* Need to locate the two positions present in vertex + header. | ||
72 | * These are currently hardcoded: | ||
73 | */ | ||
74 | c.header_position_offset = ATTR_SIZE; | ||
75 | |||
76 | if (brw->gen == 5) | ||
77 | delta = 3 * REG_SIZE; | ||
78 | else | ||
79 | delta = REG_SIZE; | ||
80 | |||
81 | c.offset_hpos = delta + c.key.output_hpos * ATTR_SIZE; | ||
82 | |||
83 | if (c.key.output_color0 != BRW_OUTPUT_NOT_PRESENT) | ||
84 | c.offset_color0 = delta + c.key.output_color0 * ATTR_SIZE; | ||
85 | |||
86 | if (c.key.output_color1 != BRW_OUTPUT_NOT_PRESENT) | ||
87 | c.offset_color1 = delta + c.key.output_color1 * ATTR_SIZE; | ||
88 | |||
89 | if (c.key.output_bfc0 != BRW_OUTPUT_NOT_PRESENT) | ||
90 | c.offset_bfc0 = delta + c.key.output_bfc0 * ATTR_SIZE; | ||
91 | |||
92 | if (c.key.output_bfc1 != BRW_OUTPUT_NOT_PRESENT) | ||
93 | c.offset_bfc1 = delta + c.key.output_bfc1 * ATTR_SIZE; | ||
94 | |||
95 | if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT) | ||
96 | c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE; | ||
97 | |||
98 | if (brw->gen == 5) | ||
99 | c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ | ||
100 | else | ||
101 | c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ | ||
102 | |||
103 | c.nr_bytes = c.nr_regs * REG_SIZE; | ||
104 | |||
105 | c.prog_data.clip_mode = c.key.clip_mode; /* XXX */ | ||
106 | |||
107 | /* For some reason the thread is spawned with only 4 channels | ||
108 | * unmasked. | ||
109 | */ | ||
110 | brw_set_mask_control(&c.func, BRW_MASK_DISABLE); | ||
111 | |||
112 | |||
113 | /* Would ideally have the option of producing a program which could | ||
114 | * do all three: | ||
115 | */ | ||
116 | switch (key->primitive) { | ||
117 | case PIPE_PRIM_TRIANGLES: | ||
118 | if (key->do_unfilled) | ||
119 | brw_emit_unfilled_clip( &c ); | ||
120 | else | ||
121 | brw_emit_tri_clip( &c ); | ||
122 | break; | ||
123 | case PIPE_PRIM_LINES: | ||
124 | brw_emit_line_clip( &c ); | ||
125 | break; | ||
126 | case PIPE_PRIM_POINTS: | ||
127 | brw_emit_point_clip( &c ); | ||
128 | break; | ||
129 | default: | ||
130 | assert(0); | ||
131 | return PIPE_ERROR_BAD_INPUT; | ||
132 | } | ||
133 | |||
134 | |||
135 | |||
136 | /* get the program | ||
137 | */ | ||
138 | ret = brw_get_program(&c.func, &program, &program_size); | ||
139 | if (ret) | ||
140 | return ret; | ||
141 | |||
142 | /* Upload | ||
143 | */ | ||
144 | ret = brw_upload_cache( &brw->cache, | ||
145 | BRW_CLIP_PROG, | ||
146 | &c.key, sizeof(c.key), | ||
147 | NULL, 0, | ||
148 | program, program_size, | ||
149 | &c.prog_data, | ||
150 | &brw->clip.prog_data, | ||
151 | bo_out ); | ||
152 | if (ret) | ||
153 | return ret; | ||
154 | |||
155 | return PIPE_OK; | ||
156 | } | ||
157 | |||
158 | /* Calculate interpolants for triangle and line rasterization. | ||
159 | */ | ||
160 | static enum pipe_error | ||
161 | upload_clip_prog(struct brw_context *brw) | ||
162 | { | ||
163 | const struct brw_vertex_shader *vs = brw->curr.vertex_shader; | ||
164 | struct brw_clip_prog_key key; | ||
165 | enum pipe_error ret; | ||
166 | |||
167 | /* Populate the key, starting from the almost-complete version from | ||
168 | * the rast state. | ||
169 | */ | ||
170 | |||
171 | /* PIPE_NEW_RAST */ | ||
172 | key = brw->curr.rast->clip_key; | ||
173 | |||
174 | /* BRW_NEW_REDUCED_PRIMITIVE */ | ||
175 | key.primitive = brw->reduced_primitive; | ||
176 | |||
177 | /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove | ||
178 | * dependency on CACHE_NEW_VS_PROG | ||
179 | */ | ||
180 | /* CACHE_NEW_VS_PROG */ | ||
181 | key.nr_attrs = brw->vs.prog_data->nr_outputs; | ||
182 | |||
183 | /* PIPE_NEW_VS */ | ||
184 | key.output_hpos = vs->output_hpos; | ||
185 | key.output_color0 = vs->output_color0; | ||
186 | key.output_color1 = vs->output_color1; | ||
187 | key.output_bfc0 = vs->output_bfc0; | ||
188 | key.output_bfc1 = vs->output_bfc1; | ||
189 | key.output_edgeflag = vs->output_edgeflag; | ||
190 | |||
191 | /* PIPE_NEW_CLIP */ | ||
192 | key.nr_userclip = brw->curr.ucp.nr; | ||
193 | |||
194 | /* Already cached? | ||
195 | */ | ||
196 | if (brw_search_cache(&brw->cache, BRW_CLIP_PROG, | ||
197 | &key, sizeof(key), | ||
198 | NULL, 0, | ||
199 | &brw->clip.prog_data, | ||
200 | &brw->clip.prog_bo)) | ||
201 | return PIPE_OK; | ||
202 | |||
203 | /* Compile new program: | ||
204 | */ | ||
205 | ret = compile_clip_prog( brw, &key, &brw->clip.prog_bo ); | ||
206 | if (ret) | ||
207 | return ret; | ||
208 | |||
209 | return PIPE_OK; | ||
210 | } | ||
211 | |||
212 | |||
213 | const struct brw_tracked_state brw_clip_prog = { | ||
214 | .dirty = { | ||
215 | .mesa = (PIPE_NEW_RAST | | ||
216 | PIPE_NEW_CLIP), | ||
217 | .brw = (BRW_NEW_REDUCED_PRIMITIVE), | ||
218 | .cache = CACHE_NEW_VS_PROG | ||
219 | }, | ||
220 | .prepare = upload_clip_prog | ||
221 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_clip.h b/src/gallium/drivers/i965/brw_clip.h deleted file mode 100644 index f123b73c063..00000000000 --- a/src/gallium/drivers/i965/brw_clip.h +++ /dev/null | |||
@@ -1,197 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #ifndef BRW_CLIP_H | ||
33 | #define BRW_CLIP_H | ||
34 | |||
35 | #include "pipe/p_state.h" | ||
36 | #include "brw_reg.h" | ||
37 | #include "brw_eu.h" | ||
38 | |||
39 | #define MAX_VERTS (3+6+6) | ||
40 | |||
41 | /* Note that if unfilled primitives are being emitted, we have to fix | ||
42 | * up polygon offset and flatshading at this point: | ||
43 | */ | ||
44 | struct brw_clip_prog_key { | ||
45 | GLuint nr_attrs:6; | ||
46 | GLuint primitive:4; | ||
47 | GLuint nr_userclip:3; | ||
48 | GLuint do_flat_shading:1; | ||
49 | GLuint do_unfilled:1; | ||
50 | GLuint fill_cw:2; /* includes cull information */ | ||
51 | GLuint fill_ccw:2; /* includes cull information */ | ||
52 | GLuint offset_cw:1; | ||
53 | GLuint offset_ccw:1; | ||
54 | GLuint copy_bfc_cw:1; | ||
55 | GLuint copy_bfc_ccw:1; | ||
56 | GLuint clip_mode:3; | ||
57 | GLuint output_hpos:6; /* not always zero? */ | ||
58 | |||
59 | GLuint output_color0:6; | ||
60 | GLuint output_color1:6; | ||
61 | GLuint output_bfc0:6; | ||
62 | GLuint output_bfc1:6; | ||
63 | GLuint output_edgeflag:6; | ||
64 | GLuint pad1:2; | ||
65 | |||
66 | GLfloat offset_factor; | ||
67 | GLfloat offset_units; | ||
68 | }; | ||
69 | |||
70 | struct brw_clip_prog_data { | ||
71 | GLuint curb_read_length; /* user planes? */ | ||
72 | GLuint clip_mode; | ||
73 | GLuint urb_read_length; | ||
74 | GLuint total_grf; | ||
75 | }; | ||
76 | |||
77 | #define CLIP_LINE 0 | ||
78 | #define CLIP_POINT 1 | ||
79 | #define CLIP_FILL 2 | ||
80 | #define CLIP_CULL 3 | ||
81 | |||
82 | |||
83 | #define PRIM_MASK (0x1f) | ||
84 | |||
85 | struct brw_clip_compile { | ||
86 | struct brw_compile func; | ||
87 | struct brw_clip_prog_key key; | ||
88 | struct brw_clip_prog_data prog_data; | ||
89 | |||
90 | struct { | ||
91 | struct brw_reg R0; | ||
92 | struct brw_reg vertex[MAX_VERTS]; | ||
93 | |||
94 | struct brw_reg t; | ||
95 | struct brw_reg t0, t1; | ||
96 | struct brw_reg dp0, dp1; | ||
97 | |||
98 | struct brw_reg dpPrev; | ||
99 | struct brw_reg dp; | ||
100 | struct brw_reg loopcount; | ||
101 | struct brw_reg nr_verts; | ||
102 | struct brw_reg planemask; | ||
103 | |||
104 | struct brw_reg inlist; | ||
105 | struct brw_reg outlist; | ||
106 | struct brw_reg freelist; | ||
107 | |||
108 | struct brw_reg dir; | ||
109 | struct brw_reg tmp0, tmp1; | ||
110 | struct brw_reg offset; | ||
111 | |||
112 | struct brw_reg fixed_planes; | ||
113 | struct brw_reg plane_equation; | ||
114 | |||
115 | struct brw_reg ff_sync; | ||
116 | } reg; | ||
117 | |||
118 | /* 3 different ways of expressing vertex size, including | ||
119 | * key.nr_attrs. | ||
120 | */ | ||
121 | GLuint nr_regs; | ||
122 | GLuint nr_bytes; | ||
123 | |||
124 | GLuint first_tmp; | ||
125 | GLuint last_tmp; | ||
126 | |||
127 | GLboolean need_direction; | ||
128 | |||
129 | GLuint last_mrf; | ||
130 | |||
131 | GLuint header_position_offset; | ||
132 | |||
133 | GLuint nr_color_attrs; | ||
134 | GLuint offset_color0; | ||
135 | GLuint offset_color1; | ||
136 | GLuint offset_bfc0; | ||
137 | GLuint offset_bfc1; | ||
138 | |||
139 | GLuint offset_hpos; | ||
140 | GLuint offset_edgeflag; | ||
141 | }; | ||
142 | |||
143 | #define ATTR_SIZE (4*4) | ||
144 | |||
145 | /* Points are only culled, so no need for a clip routine, however it | ||
146 | * works out easier to have a dummy one. | ||
147 | */ | ||
148 | void brw_emit_unfilled_clip( struct brw_clip_compile *c ); | ||
149 | void brw_emit_tri_clip( struct brw_clip_compile *c ); | ||
150 | void brw_emit_line_clip( struct brw_clip_compile *c ); | ||
151 | void brw_emit_point_clip( struct brw_clip_compile *c ); | ||
152 | |||
153 | /* brw_clip_tri.c, for use by the unfilled clip routine: | ||
154 | */ | ||
155 | void brw_clip_tri_init_vertices( struct brw_clip_compile *c ); | ||
156 | void brw_clip_tri_flat_shade( struct brw_clip_compile *c ); | ||
157 | void brw_clip_tri( struct brw_clip_compile *c ); | ||
158 | void brw_clip_tri_emit_polygon( struct brw_clip_compile *c ); | ||
159 | void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, | ||
160 | GLuint nr_verts ); | ||
161 | |||
162 | |||
163 | /* Utils: | ||
164 | */ | ||
165 | |||
166 | void brw_clip_interp_vertex( struct brw_clip_compile *c, | ||
167 | struct brw_indirect dest_ptr, | ||
168 | struct brw_indirect v0_ptr, /* from */ | ||
169 | struct brw_indirect v1_ptr, /* to */ | ||
170 | struct brw_reg t0, | ||
171 | GLboolean force_edgeflag ); | ||
172 | |||
173 | void brw_clip_init_planes( struct brw_clip_compile *c ); | ||
174 | |||
175 | void brw_clip_emit_vue(struct brw_clip_compile *c, | ||
176 | struct brw_indirect vert, | ||
177 | GLboolean allocate, | ||
178 | GLboolean eot, | ||
179 | GLuint header); | ||
180 | |||
181 | void brw_clip_kill_thread(struct brw_clip_compile *c); | ||
182 | |||
183 | struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ); | ||
184 | struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c ); | ||
185 | |||
186 | void brw_clip_copy_colors( struct brw_clip_compile *c, | ||
187 | GLuint to, GLuint from ); | ||
188 | |||
189 | void brw_clip_init_clipmask( struct brw_clip_compile *c ); | ||
190 | |||
191 | struct brw_reg get_tmp( struct brw_clip_compile *c ); | ||
192 | |||
193 | void brw_clip_project_position(struct brw_clip_compile *c, | ||
194 | struct brw_reg pos ); | ||
195 | void brw_clip_ff_sync(struct brw_clip_compile *c); | ||
196 | void brw_clip_init_ff_sync(struct brw_clip_compile *c); | ||
197 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_clip_line.c b/src/gallium/drivers/i965/brw_clip_line.c deleted file mode 100644 index 4ed7362171b..00000000000 --- a/src/gallium/drivers/i965/brw_clip_line.c +++ /dev/null | |||
@@ -1,272 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_debug.h" | ||
33 | |||
34 | #include "brw_defines.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_eu.h" | ||
37 | #include "brw_clip.h" | ||
38 | |||
39 | |||
40 | |||
41 | |||
42 | static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) | ||
43 | { | ||
44 | GLuint i = 0,j; | ||
45 | struct brw_context *brw = c->func.brw; | ||
46 | /* Register usage is static, precompute here: | ||
47 | */ | ||
48 | c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; | ||
49 | |||
50 | if (c->key.nr_userclip) { | ||
51 | c->reg.fixed_planes = brw_vec4_grf(i, 0); | ||
52 | i += (6 + c->key.nr_userclip + 1) / 2; | ||
53 | |||
54 | c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2; | ||
55 | } | ||
56 | else | ||
57 | c->prog_data.curb_read_length = 0; | ||
58 | |||
59 | |||
60 | /* Payload vertices plus space for more generated vertices: | ||
61 | */ | ||
62 | for (j = 0; j < 4; j++) { | ||
63 | c->reg.vertex[j] = brw_vec4_grf(i, 0); | ||
64 | i += c->nr_regs; | ||
65 | } | ||
66 | |||
67 | c->reg.t = brw_vec1_grf(i, 0); | ||
68 | c->reg.t0 = brw_vec1_grf(i, 1); | ||
69 | c->reg.t1 = brw_vec1_grf(i, 2); | ||
70 | c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); | ||
71 | c->reg.plane_equation = brw_vec4_grf(i, 4); | ||
72 | i++; | ||
73 | |||
74 | c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ | ||
75 | c->reg.dp1 = brw_vec1_grf(i, 4); | ||
76 | i++; | ||
77 | |||
78 | if (!c->key.nr_userclip) { | ||
79 | c->reg.fixed_planes = brw_vec8_grf(i, 0); | ||
80 | i++; | ||
81 | } | ||
82 | |||
83 | if (brw->needs_ff_sync) { | ||
84 | c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); | ||
85 | i++; | ||
86 | } | ||
87 | |||
88 | c->first_tmp = i; | ||
89 | c->last_tmp = i; | ||
90 | |||
91 | c->prog_data.urb_read_length = c->nr_regs; /* ? */ | ||
92 | c->prog_data.total_grf = i; | ||
93 | } | ||
94 | |||
95 | |||
96 | |||
97 | /* Line clipping, more or less following the following algorithm: | ||
98 | * | ||
99 | * for (p=0;p<MAX_PLANES;p++) { | ||
100 | * if (clipmask & (1 << p)) { | ||
101 | * GLfloat dp0 = DOTPROD( vtx0, plane[p] ); | ||
102 | * GLfloat dp1 = DOTPROD( vtx1, plane[p] ); | ||
103 | * | ||
104 | * if (IS_NEGATIVE(dp1)) { | ||
105 | * GLfloat t = dp1 / (dp1 - dp0); | ||
106 | * if (t > t1) t1 = t; | ||
107 | * } else { | ||
108 | * GLfloat t = dp0 / (dp0 - dp1); | ||
109 | * if (t > t0) t0 = t; | ||
110 | * } | ||
111 | * | ||
112 | * if (t0 + t1 >= 1.0) | ||
113 | * return; | ||
114 | * } | ||
115 | * } | ||
116 | * | ||
117 | * interp( ctx, newvtx0, vtx0, vtx1, t0 ); | ||
118 | * interp( ctx, newvtx1, vtx1, vtx0, t1 ); | ||
119 | * | ||
120 | */ | ||
121 | static void clip_and_emit_line( struct brw_clip_compile *c ) | ||
122 | { | ||
123 | struct brw_compile *p = &c->func; | ||
124 | struct brw_context *brw = p->brw; | ||
125 | struct brw_indirect vtx0 = brw_indirect(0, 0); | ||
126 | struct brw_indirect vtx1 = brw_indirect(1, 0); | ||
127 | struct brw_indirect newvtx0 = brw_indirect(2, 0); | ||
128 | struct brw_indirect newvtx1 = brw_indirect(3, 0); | ||
129 | struct brw_indirect plane_ptr = brw_indirect(4, 0); | ||
130 | struct brw_instruction *plane_loop; | ||
131 | struct brw_instruction *plane_active; | ||
132 | struct brw_instruction *is_negative; | ||
133 | struct brw_instruction *is_neg2 = NULL; | ||
134 | struct brw_instruction *not_culled; | ||
135 | struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD); | ||
136 | |||
137 | brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0])); | ||
138 | brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1])); | ||
139 | brw_MOV(p, get_addr_reg(newvtx0), brw_address(c->reg.vertex[2])); | ||
140 | brw_MOV(p, get_addr_reg(newvtx1), brw_address(c->reg.vertex[3])); | ||
141 | brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c)); | ||
142 | |||
143 | /* Note: init t0, t1 together: | ||
144 | */ | ||
145 | brw_MOV(p, vec2(c->reg.t0), brw_imm_f(0)); | ||
146 | |||
147 | brw_clip_init_planes(c); | ||
148 | brw_clip_init_clipmask(c); | ||
149 | |||
150 | /* -ve rhw workaround */ | ||
151 | if (brw->has_negative_rhw_bug) { | ||
152 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
153 | brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), | ||
154 | brw_imm_ud(1<<20)); | ||
155 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); | ||
156 | } | ||
157 | |||
158 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
159 | |||
160 | plane_loop = brw_DO(p, BRW_EXECUTE_1); | ||
161 | { | ||
162 | /* if (planemask & 1) | ||
163 | */ | ||
164 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
165 | brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1)); | ||
166 | |||
167 | plane_active = brw_IF(p, BRW_EXECUTE_1); | ||
168 | { | ||
169 | if (c->key.nr_userclip) | ||
170 | brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); | ||
171 | else | ||
172 | brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); | ||
173 | |||
174 | /* dp = DP4(vtx->position, plane) | ||
175 | */ | ||
176 | brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, c->offset_hpos), c->reg.plane_equation); | ||
177 | |||
178 | /* if (IS_NEGATIVE(dp1)) | ||
179 | */ | ||
180 | brw_set_conditionalmod(p, BRW_CONDITIONAL_L); | ||
181 | brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, c->offset_hpos), c->reg.plane_equation); | ||
182 | is_negative = brw_IF(p, BRW_EXECUTE_1); | ||
183 | { | ||
184 | /* | ||
185 | * Both can be negative on GM965/G965 due to RHW workaround | ||
186 | * if so, this object should be rejected. | ||
187 | */ | ||
188 | if (brw->has_negative_rhw_bug) { | ||
189 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0)); | ||
190 | is_neg2 = brw_IF(p, BRW_EXECUTE_1); | ||
191 | { | ||
192 | brw_clip_kill_thread(c); | ||
193 | } | ||
194 | brw_ENDIF(p, is_neg2); | ||
195 | } | ||
196 | |||
197 | brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0)); | ||
198 | brw_math_invert(p, c->reg.t, c->reg.t); | ||
199 | brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1); | ||
200 | |||
201 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t1 ); | ||
202 | brw_MOV(p, c->reg.t1, c->reg.t); | ||
203 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
204 | } | ||
205 | is_negative = brw_ELSE(p, is_negative); | ||
206 | { | ||
207 | /* Coming back in. We know that both cannot be negative | ||
208 | * because the line would have been culled in that case. | ||
209 | */ | ||
210 | |||
211 | /* If both are positive, do nothing */ | ||
212 | /* Only on GM965/G965 */ | ||
213 | if (brw->has_negative_rhw_bug) { | ||
214 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0)); | ||
215 | is_neg2 = brw_IF(p, BRW_EXECUTE_1); | ||
216 | } | ||
217 | |||
218 | { | ||
219 | brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1)); | ||
220 | brw_math_invert(p, c->reg.t, c->reg.t); | ||
221 | brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0); | ||
222 | |||
223 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 ); | ||
224 | brw_MOV(p, c->reg.t0, c->reg.t); | ||
225 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
226 | } | ||
227 | |||
228 | if (brw->has_negative_rhw_bug) { | ||
229 | brw_ENDIF(p, is_neg2); | ||
230 | } | ||
231 | } | ||
232 | brw_ENDIF(p, is_negative); | ||
233 | } | ||
234 | brw_ENDIF(p, plane_active); | ||
235 | |||
236 | /* plane_ptr++; | ||
237 | */ | ||
238 | brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c)); | ||
239 | |||
240 | /* while (planemask>>=1) != 0 | ||
241 | */ | ||
242 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
243 | brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); | ||
244 | } | ||
245 | brw_WHILE(p, plane_loop); | ||
246 | |||
247 | brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1); | ||
248 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0)); | ||
249 | not_culled = brw_IF(p, BRW_EXECUTE_1); | ||
250 | { | ||
251 | brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, FALSE); | ||
252 | brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, FALSE); | ||
253 | |||
254 | brw_clip_emit_vue(c, newvtx0, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START); | ||
255 | brw_clip_emit_vue(c, newvtx1, 0, 1, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END); | ||
256 | } | ||
257 | brw_ENDIF(p, not_culled); | ||
258 | brw_clip_kill_thread(c); | ||
259 | } | ||
260 | |||
261 | |||
262 | |||
263 | void brw_emit_line_clip( struct brw_clip_compile *c ) | ||
264 | { | ||
265 | brw_clip_line_alloc_regs(c); | ||
266 | brw_clip_init_ff_sync(c); | ||
267 | |||
268 | if (c->key.do_flat_shading) | ||
269 | brw_clip_copy_colors(c, 0, 1); | ||
270 | |||
271 | clip_and_emit_line(c); | ||
272 | } | ||
diff --git a/src/gallium/drivers/i965/brw_clip_point.c b/src/gallium/drivers/i965/brw_clip_point.c deleted file mode 100644 index 124156c1b50..00000000000 --- a/src/gallium/drivers/i965/brw_clip_point.c +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "brw_defines.h" | ||
33 | #include "brw_eu.h" | ||
34 | #include "brw_clip.h" | ||
35 | |||
36 | |||
37 | /* Point clipping, nothing to do? | ||
38 | */ | ||
39 | void brw_emit_point_clip( struct brw_clip_compile *c ) | ||
40 | { | ||
41 | /* Send an empty message to kill the thread: | ||
42 | */ | ||
43 | brw_clip_tri_alloc_regs(c, 0); | ||
44 | brw_clip_init_ff_sync(c); | ||
45 | |||
46 | brw_clip_kill_thread(c); | ||
47 | } | ||
diff --git a/src/gallium/drivers/i965/brw_clip_state.c b/src/gallium/drivers/i965/brw_clip_state.c deleted file mode 100644 index f56edf3177c..00000000000 --- a/src/gallium/drivers/i965/brw_clip_state.c +++ /dev/null | |||
@@ -1,209 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_clip.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_defines.h" | ||
38 | #include "brw_debug.h" | ||
39 | |||
40 | struct brw_clip_unit_key { | ||
41 | unsigned int total_grf; | ||
42 | unsigned int urb_entry_read_length; | ||
43 | unsigned int curb_entry_read_length; | ||
44 | unsigned int clip_mode; | ||
45 | |||
46 | unsigned int curbe_offset; | ||
47 | |||
48 | unsigned int nr_urb_entries, urb_size; | ||
49 | |||
50 | GLboolean depth_clamp; | ||
51 | }; | ||
52 | |||
53 | static void | ||
54 | clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key) | ||
55 | { | ||
56 | memset(key, 0, sizeof(*key)); | ||
57 | |||
58 | /* CACHE_NEW_CLIP_PROG */ | ||
59 | key->total_grf = brw->clip.prog_data->total_grf; | ||
60 | key->urb_entry_read_length = brw->clip.prog_data->urb_read_length; | ||
61 | key->curb_entry_read_length = brw->clip.prog_data->curb_read_length; | ||
62 | key->clip_mode = brw->clip.prog_data->clip_mode; | ||
63 | |||
64 | /* BRW_NEW_CURBE_OFFSETS */ | ||
65 | key->curbe_offset = brw->curbe.clip_start; | ||
66 | |||
67 | /* BRW_NEW_URB_FENCE */ | ||
68 | key->nr_urb_entries = brw->urb.nr_clip_entries; | ||
69 | key->urb_size = brw->urb.vsize; | ||
70 | |||
71 | /* */ | ||
72 | key->depth_clamp = 0; /* XXX: add this to gallium: ctx->Transform.DepthClamp; */ | ||
73 | } | ||
74 | |||
75 | static enum pipe_error | ||
76 | clip_unit_create_from_key(struct brw_context *brw, | ||
77 | struct brw_clip_unit_key *key, | ||
78 | struct brw_winsys_reloc *reloc, | ||
79 | struct brw_winsys_buffer **bo_out) | ||
80 | { | ||
81 | struct brw_clip_unit_state clip; | ||
82 | enum pipe_error ret; | ||
83 | |||
84 | memset(&clip, 0, sizeof(clip)); | ||
85 | |||
86 | clip.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1; | ||
87 | /* reloc */ | ||
88 | clip.thread0.kernel_start_pointer = 0; | ||
89 | |||
90 | clip.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; | ||
91 | clip.thread1.single_program_flow = 1; | ||
92 | |||
93 | clip.thread3.urb_entry_read_length = key->urb_entry_read_length; | ||
94 | clip.thread3.const_urb_entry_read_length = key->curb_entry_read_length; | ||
95 | clip.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; | ||
96 | clip.thread3.dispatch_grf_start_reg = 1; | ||
97 | clip.thread3.urb_entry_read_offset = 0; | ||
98 | |||
99 | clip.thread4.nr_urb_entries = key->nr_urb_entries; | ||
100 | clip.thread4.urb_entry_allocation_size = key->urb_size - 1; | ||
101 | /* If we have enough clip URB entries to run two threads, do so. | ||
102 | */ | ||
103 | if (key->nr_urb_entries >= 10) { | ||
104 | /* Half of the URB entries go to each thread, and it has to be an | ||
105 | * even number. | ||
106 | */ | ||
107 | assert(key->nr_urb_entries % 2 == 0); | ||
108 | |||
109 | /* Although up to 16 concurrent Clip threads are allowed on IGDNG, | ||
110 | * only 2 threads can output VUEs at a time. | ||
111 | */ | ||
112 | if (brw->gen == 5) | ||
113 | clip.thread4.max_threads = 16 - 1; | ||
114 | else | ||
115 | clip.thread4.max_threads = 2 - 1; | ||
116 | } else { | ||
117 | assert(key->nr_urb_entries >= 5); | ||
118 | clip.thread4.max_threads = 1 - 1; | ||
119 | } | ||
120 | |||
121 | if (BRW_DEBUG & DEBUG_SINGLE_THREAD) | ||
122 | clip.thread4.max_threads = 0; | ||
123 | |||
124 | if (BRW_DEBUG & DEBUG_STATS) | ||
125 | clip.thread4.stats_enable = 1; | ||
126 | |||
127 | clip.clip5.userclip_enable_flags = 0x7f; | ||
128 | clip.clip5.userclip_must_clip = 1; | ||
129 | clip.clip5.guard_band_enable = 0; | ||
130 | if (!key->depth_clamp) | ||
131 | clip.clip5.viewport_z_clip_enable = 1; | ||
132 | clip.clip5.viewport_xy_clip_enable = 1; | ||
133 | clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE; | ||
134 | clip.clip5.api_mode = BRW_CLIP_API_OGL; | ||
135 | clip.clip5.clip_mode = key->clip_mode; | ||
136 | |||
137 | if (brw->is_g4x) | ||
138 | clip.clip5.negative_w_clip_test = 1; | ||
139 | |||
140 | clip.clip6.clipper_viewport_state_ptr = 0; | ||
141 | clip.viewport_xmin = -1; | ||
142 | clip.viewport_xmax = 1; | ||
143 | clip.viewport_ymin = -1; | ||
144 | clip.viewport_ymax = 1; | ||
145 | |||
146 | ret = brw_upload_cache(&brw->cache, BRW_CLIP_UNIT, | ||
147 | key, sizeof(*key), | ||
148 | reloc, 1, | ||
149 | &clip, sizeof(clip), | ||
150 | NULL, NULL, | ||
151 | bo_out); | ||
152 | if (ret) | ||
153 | return ret; | ||
154 | |||
155 | return PIPE_OK; | ||
156 | } | ||
157 | |||
158 | static int upload_clip_unit( struct brw_context *brw ) | ||
159 | { | ||
160 | struct brw_clip_unit_key key; | ||
161 | struct brw_winsys_reloc reloc[1]; | ||
162 | unsigned grf_reg_count; | ||
163 | enum pipe_error ret; | ||
164 | |||
165 | clip_unit_populate_key(brw, &key); | ||
166 | |||
167 | grf_reg_count = align(key.total_grf, 16) / 16 - 1; | ||
168 | |||
169 | /* clip program relocation | ||
170 | * | ||
171 | * XXX: these reloc structs are long lived and only need to be | ||
172 | * updated when the bound BO changes. Hopefully the stuff mixed in | ||
173 | * in the delta's is non-orthogonal. | ||
174 | */ | ||
175 | assert(brw->clip.prog_bo); | ||
176 | make_reloc(&reloc[0], | ||
177 | BRW_USAGE_STATE, | ||
178 | grf_reg_count << 1, | ||
179 | offsetof(struct brw_clip_unit_state, thread0), | ||
180 | brw->clip.prog_bo); | ||
181 | |||
182 | |||
183 | if (brw_search_cache(&brw->cache, BRW_CLIP_UNIT, | ||
184 | &key, sizeof(key), | ||
185 | reloc, 1, | ||
186 | NULL, | ||
187 | &brw->clip.state_bo)) | ||
188 | return PIPE_OK; | ||
189 | |||
190 | /* Create new: | ||
191 | */ | ||
192 | ret = clip_unit_create_from_key(brw, &key, | ||
193 | reloc, | ||
194 | &brw->clip.state_bo); | ||
195 | if (ret) | ||
196 | return ret; | ||
197 | |||
198 | return PIPE_OK; | ||
199 | } | ||
200 | |||
201 | const struct brw_tracked_state brw_clip_unit = { | ||
202 | .dirty = { | ||
203 | .mesa = 0, | ||
204 | .brw = (BRW_NEW_CURBE_OFFSETS | | ||
205 | BRW_NEW_URB_FENCE), | ||
206 | .cache = CACHE_NEW_CLIP_PROG | ||
207 | }, | ||
208 | .prepare = upload_clip_unit, | ||
209 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_clip_tri.c b/src/gallium/drivers/i965/brw_clip_tri.c deleted file mode 100644 index 7d400e6028b..00000000000 --- a/src/gallium/drivers/i965/brw_clip_tri.c +++ /dev/null | |||
@@ -1,596 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "brw_defines.h" | ||
33 | #include "brw_context.h" | ||
34 | #include "brw_eu.h" | ||
35 | #include "brw_clip.h" | ||
36 | |||
37 | static void release_tmps( struct brw_clip_compile *c ) | ||
38 | { | ||
39 | c->last_tmp = c->first_tmp; | ||
40 | } | ||
41 | |||
42 | |||
43 | void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, | ||
44 | GLuint nr_verts ) | ||
45 | { | ||
46 | GLuint i = 0,j; | ||
47 | struct brw_context *brw = c->func.brw; | ||
48 | |||
49 | /* Register usage is static, precompute here: | ||
50 | */ | ||
51 | c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; | ||
52 | |||
53 | if (c->key.nr_userclip) { | ||
54 | c->reg.fixed_planes = brw_vec4_grf(i, 0); | ||
55 | i += (6 + c->key.nr_userclip + 1) / 2; | ||
56 | |||
57 | c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2; | ||
58 | } | ||
59 | else | ||
60 | c->prog_data.curb_read_length = 0; | ||
61 | |||
62 | |||
63 | /* Payload vertices plus space for more generated vertices: | ||
64 | */ | ||
65 | for (j = 0; j < nr_verts; j++) { | ||
66 | c->reg.vertex[j] = brw_vec4_grf(i, 0); | ||
67 | i += c->nr_regs; | ||
68 | } | ||
69 | |||
70 | if (c->key.nr_attrs & 1) { | ||
71 | for (j = 0; j < 3; j++) { | ||
72 | GLuint delta = c->key.nr_attrs*16 + 32; | ||
73 | |||
74 | if (brw->gen == 5) | ||
75 | delta = c->key.nr_attrs * 16 + 32 * 3; | ||
76 | |||
77 | brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); | ||
78 | } | ||
79 | } | ||
80 | |||
81 | c->reg.t = brw_vec1_grf(i, 0); | ||
82 | c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); | ||
83 | c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); | ||
84 | c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); | ||
85 | c->reg.plane_equation = brw_vec4_grf(i, 4); | ||
86 | i++; | ||
87 | |||
88 | c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ | ||
89 | c->reg.dp = brw_vec1_grf(i, 4); | ||
90 | i++; | ||
91 | |||
92 | c->reg.inlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); | ||
93 | i++; | ||
94 | |||
95 | c->reg.outlist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); | ||
96 | i++; | ||
97 | |||
98 | c->reg.freelist = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, i, 0); | ||
99 | i++; | ||
100 | |||
101 | if (!c->key.nr_userclip) { | ||
102 | c->reg.fixed_planes = brw_vec8_grf(i, 0); | ||
103 | i++; | ||
104 | } | ||
105 | |||
106 | if (c->key.do_unfilled) { | ||
107 | c->reg.dir = brw_vec4_grf(i, 0); | ||
108 | c->reg.offset = brw_vec4_grf(i, 4); | ||
109 | i++; | ||
110 | c->reg.tmp0 = brw_vec4_grf(i, 0); | ||
111 | c->reg.tmp1 = brw_vec4_grf(i, 4); | ||
112 | i++; | ||
113 | } | ||
114 | |||
115 | if (brw->needs_ff_sync) { | ||
116 | c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); | ||
117 | i++; | ||
118 | } | ||
119 | |||
120 | c->first_tmp = i; | ||
121 | c->last_tmp = i; | ||
122 | |||
123 | c->prog_data.urb_read_length = c->nr_regs; /* ? */ | ||
124 | c->prog_data.total_grf = i; | ||
125 | } | ||
126 | |||
127 | |||
128 | |||
129 | void brw_clip_tri_init_vertices( struct brw_clip_compile *c ) | ||
130 | { | ||
131 | struct brw_compile *p = &c->func; | ||
132 | struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ | ||
133 | struct brw_instruction *is_rev; | ||
134 | |||
135 | /* Initial list of indices for incoming vertexes: | ||
136 | */ | ||
137 | brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); | ||
138 | brw_CMP(p, | ||
139 | vec1(brw_null_reg()), | ||
140 | BRW_CONDITIONAL_EQ, | ||
141 | tmp0, | ||
142 | brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE)); | ||
143 | |||
144 | /* XXX: Is there an easier way to do this? Need to reverse every | ||
145 | * second tristrip element: Can ignore sometimes? | ||
146 | */ | ||
147 | is_rev = brw_IF(p, BRW_EXECUTE_1); | ||
148 | { | ||
149 | brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[1]) ); | ||
150 | brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[0]) ); | ||
151 | if (c->need_direction) | ||
152 | brw_MOV(p, c->reg.dir, brw_imm_f(-1)); | ||
153 | } | ||
154 | is_rev = brw_ELSE(p, is_rev); | ||
155 | { | ||
156 | brw_MOV(p, get_element(c->reg.inlist, 0), brw_address(c->reg.vertex[0]) ); | ||
157 | brw_MOV(p, get_element(c->reg.inlist, 1), brw_address(c->reg.vertex[1]) ); | ||
158 | if (c->need_direction) | ||
159 | brw_MOV(p, c->reg.dir, brw_imm_f(1)); | ||
160 | } | ||
161 | brw_ENDIF(p, is_rev); | ||
162 | |||
163 | brw_MOV(p, get_element(c->reg.inlist, 2), brw_address(c->reg.vertex[2]) ); | ||
164 | brw_MOV(p, brw_vec8_grf(c->reg.outlist.nr, 0), brw_imm_f(0)); | ||
165 | brw_MOV(p, c->reg.nr_verts, brw_imm_ud(3)); | ||
166 | } | ||
167 | |||
168 | |||
169 | |||
170 | void brw_clip_tri_flat_shade( struct brw_clip_compile *c ) | ||
171 | { | ||
172 | struct brw_compile *p = &c->func; | ||
173 | struct brw_instruction *is_poly; | ||
174 | struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ | ||
175 | |||
176 | brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); | ||
177 | brw_CMP(p, | ||
178 | vec1(brw_null_reg()), | ||
179 | BRW_CONDITIONAL_EQ, | ||
180 | tmp0, | ||
181 | brw_imm_ud(_3DPRIM_POLYGON)); | ||
182 | |||
183 | is_poly = brw_IF(p, BRW_EXECUTE_1); | ||
184 | { | ||
185 | brw_clip_copy_colors(c, 1, 0); | ||
186 | brw_clip_copy_colors(c, 2, 0); | ||
187 | } | ||
188 | is_poly = brw_ELSE(p, is_poly); | ||
189 | { | ||
190 | brw_clip_copy_colors(c, 0, 2); | ||
191 | brw_clip_copy_colors(c, 1, 2); | ||
192 | } | ||
193 | brw_ENDIF(p, is_poly); | ||
194 | } | ||
195 | |||
196 | |||
197 | |||
198 | /* Use mesa's clipping algorithms, translated to GEN4 assembly. | ||
199 | */ | ||
200 | void brw_clip_tri( struct brw_clip_compile *c ) | ||
201 | { | ||
202 | struct brw_compile *p = &c->func; | ||
203 | struct brw_indirect vtx = brw_indirect(0, 0); | ||
204 | struct brw_indirect vtxPrev = brw_indirect(1, 0); | ||
205 | struct brw_indirect vtxOut = brw_indirect(2, 0); | ||
206 | struct brw_indirect plane_ptr = brw_indirect(3, 0); | ||
207 | struct brw_indirect inlist_ptr = brw_indirect(4, 0); | ||
208 | struct brw_indirect outlist_ptr = brw_indirect(5, 0); | ||
209 | struct brw_indirect freelist_ptr = brw_indirect(6, 0); | ||
210 | struct brw_instruction *plane_loop; | ||
211 | struct brw_instruction *plane_active; | ||
212 | struct brw_instruction *vertex_loop; | ||
213 | struct brw_instruction *next_test; | ||
214 | struct brw_instruction *prev_test; | ||
215 | |||
216 | brw_MOV(p, get_addr_reg(vtxPrev), brw_address(c->reg.vertex[2]) ); | ||
217 | brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c)); | ||
218 | brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist)); | ||
219 | brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist)); | ||
220 | |||
221 | brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) ); | ||
222 | |||
223 | plane_loop = brw_DO(p, BRW_EXECUTE_1); | ||
224 | { | ||
225 | /* if (planemask & 1) | ||
226 | */ | ||
227 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
228 | brw_AND(p, vec1(brw_null_reg()), c->reg.planemask, brw_imm_ud(1)); | ||
229 | |||
230 | plane_active = brw_IF(p, BRW_EXECUTE_1); | ||
231 | { | ||
232 | /* vtxOut = freelist_ptr++ | ||
233 | */ | ||
234 | brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(freelist_ptr) ); | ||
235 | brw_ADD(p, get_addr_reg(freelist_ptr), get_addr_reg(freelist_ptr), brw_imm_uw(c->nr_regs * REG_SIZE)); | ||
236 | |||
237 | if (c->key.nr_userclip) | ||
238 | brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0)); | ||
239 | else | ||
240 | brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0)); | ||
241 | |||
242 | brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); | ||
243 | brw_MOV(p, c->reg.nr_verts, brw_imm_ud(0)); | ||
244 | |||
245 | vertex_loop = brw_DO(p, BRW_EXECUTE_1); | ||
246 | { | ||
247 | /* vtx = *input_ptr; | ||
248 | */ | ||
249 | brw_MOV(p, get_addr_reg(vtx), deref_1uw(inlist_ptr, 0)); | ||
250 | |||
251 | /* IS_NEGATIVE(prev) */ | ||
252 | brw_set_conditionalmod(p, BRW_CONDITIONAL_L); | ||
253 | brw_DP4(p, vec4(c->reg.dpPrev), deref_4f(vtxPrev, c->offset_hpos), c->reg.plane_equation); | ||
254 | prev_test = brw_IF(p, BRW_EXECUTE_1); | ||
255 | { | ||
256 | /* IS_POSITIVE(next) | ||
257 | */ | ||
258 | brw_set_conditionalmod(p, BRW_CONDITIONAL_GE); | ||
259 | brw_DP4(p, vec4(c->reg.dp), deref_4f(vtx, c->offset_hpos), c->reg.plane_equation); | ||
260 | next_test = brw_IF(p, BRW_EXECUTE_1); | ||
261 | { | ||
262 | |||
263 | /* Coming back in. | ||
264 | */ | ||
265 | brw_ADD(p, c->reg.t, c->reg.dpPrev, negate(c->reg.dp)); | ||
266 | brw_math_invert(p, c->reg.t, c->reg.t); | ||
267 | brw_MUL(p, c->reg.t, c->reg.t, c->reg.dpPrev); | ||
268 | |||
269 | /* If (vtxOut == 0) vtxOut = vtxPrev | ||
270 | */ | ||
271 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) ); | ||
272 | brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtxPrev) ); | ||
273 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
274 | |||
275 | brw_clip_interp_vertex(c, vtxOut, vtxPrev, vtx, c->reg.t, GL_FALSE); | ||
276 | |||
277 | /* *outlist_ptr++ = vtxOut; | ||
278 | * nr_verts++; | ||
279 | * vtxOut = 0; | ||
280 | */ | ||
281 | brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); | ||
282 | brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); | ||
283 | brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); | ||
284 | brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) ); | ||
285 | } | ||
286 | brw_ENDIF(p, next_test); | ||
287 | |||
288 | } | ||
289 | prev_test = brw_ELSE(p, prev_test); | ||
290 | { | ||
291 | /* *outlist_ptr++ = vtxPrev; | ||
292 | * nr_verts++; | ||
293 | */ | ||
294 | brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxPrev)); | ||
295 | brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); | ||
296 | brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); | ||
297 | |||
298 | /* IS_NEGATIVE(next) | ||
299 | */ | ||
300 | brw_set_conditionalmod(p, BRW_CONDITIONAL_L); | ||
301 | brw_DP4(p, vec4(c->reg.dp), deref_4f(vtx, c->offset_hpos), c->reg.plane_equation); | ||
302 | next_test = brw_IF(p, BRW_EXECUTE_1); | ||
303 | { | ||
304 | /* Going out of bounds. Avoid division by zero as we | ||
305 | * know dp != dpPrev from DIFFERENT_SIGNS, above. | ||
306 | */ | ||
307 | brw_ADD(p, c->reg.t, c->reg.dp, negate(c->reg.dpPrev)); | ||
308 | brw_math_invert(p, c->reg.t, c->reg.t); | ||
309 | brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp); | ||
310 | |||
311 | /* If (vtxOut == 0) vtxOut = vtx | ||
312 | */ | ||
313 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_EQ, get_addr_reg(vtxOut), brw_imm_uw(0) ); | ||
314 | brw_MOV(p, get_addr_reg(vtxOut), get_addr_reg(vtx) ); | ||
315 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
316 | |||
317 | brw_clip_interp_vertex(c, vtxOut, vtx, vtxPrev, c->reg.t, GL_TRUE); | ||
318 | |||
319 | /* *outlist_ptr++ = vtxOut; | ||
320 | * nr_verts++; | ||
321 | * vtxOut = 0; | ||
322 | */ | ||
323 | brw_MOV(p, deref_1uw(outlist_ptr, 0), get_addr_reg(vtxOut)); | ||
324 | brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_uw(sizeof(short))); | ||
325 | brw_ADD(p, c->reg.nr_verts, c->reg.nr_verts, brw_imm_ud(1)); | ||
326 | brw_MOV(p, get_addr_reg(vtxOut), brw_imm_uw(0) ); | ||
327 | } | ||
328 | brw_ENDIF(p, next_test); | ||
329 | } | ||
330 | brw_ENDIF(p, prev_test); | ||
331 | |||
332 | /* vtxPrev = vtx; | ||
333 | * inlist_ptr++; | ||
334 | */ | ||
335 | brw_MOV(p, get_addr_reg(vtxPrev), get_addr_reg(vtx)); | ||
336 | brw_ADD(p, get_addr_reg(inlist_ptr), get_addr_reg(inlist_ptr), brw_imm_uw(sizeof(short))); | ||
337 | |||
338 | /* while (--loopcount != 0) | ||
339 | */ | ||
340 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
341 | brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); | ||
342 | } | ||
343 | brw_WHILE(p, vertex_loop); | ||
344 | |||
345 | /* vtxPrev = *(outlist_ptr-1) OR: outlist[nr_verts-1] | ||
346 | * inlist = outlist | ||
347 | * inlist_ptr = &inlist[0] | ||
348 | * outlist_ptr = &outlist[0] | ||
349 | */ | ||
350 | brw_ADD(p, get_addr_reg(outlist_ptr), get_addr_reg(outlist_ptr), brw_imm_w(-2)); | ||
351 | brw_MOV(p, get_addr_reg(vtxPrev), deref_1uw(outlist_ptr, 0)); | ||
352 | brw_MOV(p, brw_vec8_grf(c->reg.inlist.nr, 0), brw_vec8_grf(c->reg.outlist.nr, 0)); | ||
353 | brw_MOV(p, get_addr_reg(inlist_ptr), brw_address(c->reg.inlist)); | ||
354 | brw_MOV(p, get_addr_reg(outlist_ptr), brw_address(c->reg.outlist)); | ||
355 | } | ||
356 | brw_ENDIF(p, plane_active); | ||
357 | |||
358 | /* plane_ptr++; | ||
359 | */ | ||
360 | brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c)); | ||
361 | |||
362 | /* nr_verts >= 3 | ||
363 | */ | ||
364 | brw_CMP(p, | ||
365 | vec1(brw_null_reg()), | ||
366 | BRW_CONDITIONAL_GE, | ||
367 | c->reg.nr_verts, | ||
368 | brw_imm_ud(3)); | ||
369 | |||
370 | /* && (planemask>>=1) != 0 | ||
371 | */ | ||
372 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
373 | brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); | ||
374 | } | ||
375 | brw_WHILE(p, plane_loop); | ||
376 | } | ||
377 | |||
378 | |||
379 | |||
380 | void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) | ||
381 | { | ||
382 | struct brw_compile *p = &c->func; | ||
383 | struct brw_instruction *loop, *if_insn; | ||
384 | |||
385 | /* for (loopcount = nr_verts-2; loopcount > 0; loopcount--) | ||
386 | */ | ||
387 | brw_set_conditionalmod(p, BRW_CONDITIONAL_G); | ||
388 | brw_ADD(p, | ||
389 | c->reg.loopcount, | ||
390 | c->reg.nr_verts, | ||
391 | brw_imm_d(-2)); | ||
392 | |||
393 | if_insn = brw_IF(p, BRW_EXECUTE_1); | ||
394 | { | ||
395 | struct brw_indirect v0 = brw_indirect(0, 0); | ||
396 | struct brw_indirect vptr = brw_indirect(1, 0); | ||
397 | |||
398 | brw_MOV(p, get_addr_reg(vptr), brw_address(c->reg.inlist)); | ||
399 | brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); | ||
400 | |||
401 | brw_clip_emit_vue(c, v0, 1, 0, ((_3DPRIM_TRIFAN << 2) | R02_PRIM_START)); | ||
402 | |||
403 | brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); | ||
404 | brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); | ||
405 | |||
406 | loop = brw_DO(p, BRW_EXECUTE_1); | ||
407 | { | ||
408 | brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_TRIFAN << 2)); | ||
409 | |||
410 | brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); | ||
411 | brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); | ||
412 | |||
413 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
414 | brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); | ||
415 | } | ||
416 | brw_WHILE(p, loop); | ||
417 | |||
418 | brw_clip_emit_vue(c, v0, 0, 1, ((_3DPRIM_TRIFAN << 2) | R02_PRIM_END)); | ||
419 | } | ||
420 | brw_ENDIF(p, if_insn); | ||
421 | } | ||
422 | |||
423 | static void do_clip_tri( struct brw_clip_compile *c ) | ||
424 | { | ||
425 | brw_clip_init_planes(c); | ||
426 | |||
427 | brw_clip_tri(c); | ||
428 | } | ||
429 | |||
430 | |||
431 | static void maybe_do_clip_tri( struct brw_clip_compile *c ) | ||
432 | { | ||
433 | struct brw_compile *p = &c->func; | ||
434 | struct brw_instruction *do_clip; | ||
435 | |||
436 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0)); | ||
437 | do_clip = brw_IF(p, BRW_EXECUTE_1); | ||
438 | { | ||
439 | do_clip_tri(c); | ||
440 | } | ||
441 | brw_ENDIF(p, do_clip); | ||
442 | } | ||
443 | |||
444 | static void brw_clip_test( struct brw_clip_compile *c ) | ||
445 | { | ||
446 | struct brw_reg t = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); | ||
447 | struct brw_reg t1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); | ||
448 | struct brw_reg t2 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); | ||
449 | struct brw_reg t3 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); | ||
450 | |||
451 | struct brw_reg v0 = get_tmp(c); | ||
452 | struct brw_reg v1 = get_tmp(c); | ||
453 | struct brw_reg v2 = get_tmp(c); | ||
454 | |||
455 | struct brw_indirect vt0 = brw_indirect(0, 0); | ||
456 | struct brw_indirect vt1 = brw_indirect(1, 0); | ||
457 | struct brw_indirect vt2 = brw_indirect(2, 0); | ||
458 | |||
459 | struct brw_compile *p = &c->func; | ||
460 | struct brw_instruction *is_outside; | ||
461 | struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ | ||
462 | |||
463 | brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0])); | ||
464 | brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1])); | ||
465 | brw_MOV(p, get_addr_reg(vt2), brw_address(c->reg.vertex[2])); | ||
466 | brw_MOV(p, v0, deref_4f(vt0, c->offset_hpos)); | ||
467 | brw_MOV(p, v1, deref_4f(vt1, c->offset_hpos)); | ||
468 | brw_MOV(p, v2, deref_4f(vt2, c->offset_hpos)); | ||
469 | brw_AND(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(~0x3f)); | ||
470 | |||
471 | /* test nearz, xmin, ymin plane */ | ||
472 | /* clip.xyz < -clip.w */ | ||
473 | brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, negate(get_element(v0, 3))); | ||
474 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
475 | brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, negate(get_element(v1, 3))); | ||
476 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
477 | brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, negate(get_element(v2, 3))); | ||
478 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
479 | |||
480 | /* All vertices are outside of a plane, rejected */ | ||
481 | brw_AND(p, t, t1, t2); | ||
482 | brw_AND(p, t, t, t3); | ||
483 | brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); | ||
484 | brw_OR(p, tmp0, tmp0, get_element(t, 2)); | ||
485 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
486 | brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); | ||
487 | is_outside = brw_IF(p, BRW_EXECUTE_1); | ||
488 | { | ||
489 | brw_clip_kill_thread(c); | ||
490 | } | ||
491 | brw_ENDIF(p, is_outside); | ||
492 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
493 | |||
494 | /* some vertices are inside a plane, some are outside,need to clip */ | ||
495 | brw_XOR(p, t, t1, t2); | ||
496 | brw_XOR(p, t1, t2, t3); | ||
497 | brw_OR(p, t, t, t1); | ||
498 | brw_AND(p, t, t, brw_imm_ud(0x1)); | ||
499 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
500 | get_element(t, 0), brw_imm_ud(0)); | ||
501 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5))); | ||
502 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
503 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
504 | get_element(t, 1), brw_imm_ud(0)); | ||
505 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3))); | ||
506 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
507 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
508 | get_element(t, 2), brw_imm_ud(0)); | ||
509 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1))); | ||
510 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
511 | |||
512 | /* test farz, xmax, ymax plane */ | ||
513 | /* clip.xyz > clip.w */ | ||
514 | brw_CMP(p, t1, BRW_CONDITIONAL_G, v0, get_element(v0, 3)); | ||
515 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
516 | brw_CMP(p, t2, BRW_CONDITIONAL_G, v1, get_element(v1, 3)); | ||
517 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
518 | brw_CMP(p, t3, BRW_CONDITIONAL_G, v2, get_element(v2, 3)); | ||
519 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
520 | |||
521 | /* All vertices are outside of a plane, rejected */ | ||
522 | brw_AND(p, t, t1, t2); | ||
523 | brw_AND(p, t, t, t3); | ||
524 | brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); | ||
525 | brw_OR(p, tmp0, tmp0, get_element(t, 2)); | ||
526 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
527 | brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); | ||
528 | is_outside = brw_IF(p, BRW_EXECUTE_1); | ||
529 | { | ||
530 | brw_clip_kill_thread(c); | ||
531 | } | ||
532 | brw_ENDIF(p, is_outside); | ||
533 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
534 | |||
535 | /* some vertices are inside a plane, some are outside,need to clip */ | ||
536 | brw_XOR(p, t, t1, t2); | ||
537 | brw_XOR(p, t1, t2, t3); | ||
538 | brw_OR(p, t, t, t1); | ||
539 | brw_AND(p, t, t, brw_imm_ud(0x1)); | ||
540 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
541 | get_element(t, 0), brw_imm_ud(0)); | ||
542 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4))); | ||
543 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
544 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
545 | get_element(t, 1), brw_imm_ud(0)); | ||
546 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2))); | ||
547 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
548 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, | ||
549 | get_element(t, 2), brw_imm_ud(0)); | ||
550 | brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0))); | ||
551 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
552 | |||
553 | release_tmps(c); | ||
554 | } | ||
555 | |||
556 | |||
557 | void brw_emit_tri_clip( struct brw_clip_compile *c ) | ||
558 | { | ||
559 | struct brw_instruction *neg_rhw; | ||
560 | struct brw_compile *p = &c->func; | ||
561 | brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); | ||
562 | brw_clip_tri_init_vertices(c); | ||
563 | brw_clip_init_clipmask(c); | ||
564 | brw_clip_init_ff_sync(c); | ||
565 | |||
566 | /* if -ve rhw workaround bit is set, | ||
567 | do cliptest */ | ||
568 | if (p->brw->has_negative_rhw_bug) { | ||
569 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
570 | brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), | ||
571 | brw_imm_ud(1<<20)); | ||
572 | neg_rhw = brw_IF(p, BRW_EXECUTE_1); | ||
573 | { | ||
574 | brw_clip_test(c); | ||
575 | } | ||
576 | brw_ENDIF(p, neg_rhw); | ||
577 | } | ||
578 | /* Can't push into do_clip_tri because with polygon (or quad) | ||
579 | * flatshading, need to apply the flatshade here because we don't | ||
580 | * respect the PV when converting to trifan for emit: | ||
581 | */ | ||
582 | if (c->key.do_flat_shading) | ||
583 | brw_clip_tri_flat_shade(c); | ||
584 | |||
585 | if ((c->key.clip_mode == BRW_CLIPMODE_NORMAL) || | ||
586 | (c->key.clip_mode == BRW_CLIPMODE_KERNEL_CLIP)) | ||
587 | do_clip_tri(c); | ||
588 | else | ||
589 | maybe_do_clip_tri(c); | ||
590 | |||
591 | brw_clip_tri_emit_polygon(c); | ||
592 | |||
593 | /* Send an empty message to kill the thread: | ||
594 | */ | ||
595 | brw_clip_kill_thread(c); | ||
596 | } | ||
diff --git a/src/gallium/drivers/i965/brw_clip_unfilled.c b/src/gallium/drivers/i965/brw_clip_unfilled.c deleted file mode 100644 index aec835b8cec..00000000000 --- a/src/gallium/drivers/i965/brw_clip_unfilled.c +++ /dev/null | |||
@@ -1,497 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "brw_defines.h" | ||
33 | #include "brw_eu.h" | ||
34 | #include "brw_util.h" | ||
35 | #include "brw_clip.h" | ||
36 | |||
37 | |||
38 | |||
39 | /* This is performed against the original triangles, so no indirection | ||
40 | * required: | ||
41 | BZZZT! | ||
42 | */ | ||
43 | static void compute_tri_direction( struct brw_clip_compile *c ) | ||
44 | { | ||
45 | struct brw_compile *p = &c->func; | ||
46 | struct brw_reg e = c->reg.tmp0; | ||
47 | struct brw_reg f = c->reg.tmp1; | ||
48 | struct brw_reg v0 = byte_offset(c->reg.vertex[0], c->offset_hpos); | ||
49 | struct brw_reg v1 = byte_offset(c->reg.vertex[1], c->offset_hpos); | ||
50 | struct brw_reg v2 = byte_offset(c->reg.vertex[2], c->offset_hpos); | ||
51 | |||
52 | |||
53 | struct brw_reg v0n = get_tmp(c); | ||
54 | struct brw_reg v1n = get_tmp(c); | ||
55 | struct brw_reg v2n = get_tmp(c); | ||
56 | |||
57 | /* Convert to NDC. | ||
58 | * NOTE: We can't modify the original vertex coordinates, | ||
59 | * as it may impact further operations. | ||
60 | * So, we have to keep normalized coordinates in temp registers. | ||
61 | * | ||
62 | * TBD-KC | ||
63 | * Try to optimize unnecessary MOV's. | ||
64 | */ | ||
65 | brw_MOV(p, v0n, v0); | ||
66 | brw_MOV(p, v1n, v1); | ||
67 | brw_MOV(p, v2n, v2); | ||
68 | |||
69 | brw_clip_project_position(c, v0n); | ||
70 | brw_clip_project_position(c, v1n); | ||
71 | brw_clip_project_position(c, v2n); | ||
72 | |||
73 | /* Calculate the vectors of two edges of the triangle: | ||
74 | */ | ||
75 | brw_ADD(p, e, v0n, negate(v2n)); | ||
76 | brw_ADD(p, f, v1n, negate(v2n)); | ||
77 | |||
78 | /* Take their crossproduct: | ||
79 | */ | ||
80 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
81 | brw_MUL(p, vec4(brw_null_reg()), brw_swizzle(e, 1,2,0,3), brw_swizzle(f,2,0,1,3)); | ||
82 | brw_MAC(p, vec4(e), negate(brw_swizzle(e, 2,0,1,3)), brw_swizzle(f,1,2,0,3)); | ||
83 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
84 | |||
85 | brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e)); | ||
86 | } | ||
87 | |||
88 | |||
89 | static void cull_direction( struct brw_clip_compile *c ) | ||
90 | { | ||
91 | struct brw_compile *p = &c->func; | ||
92 | struct brw_instruction *ccw; | ||
93 | GLuint conditional; | ||
94 | |||
95 | assert (!(c->key.fill_ccw == CLIP_CULL && | ||
96 | c->key.fill_cw == CLIP_CULL)); | ||
97 | |||
98 | if (c->key.fill_ccw == CLIP_CULL) | ||
99 | conditional = BRW_CONDITIONAL_GE; | ||
100 | else | ||
101 | conditional = BRW_CONDITIONAL_L; | ||
102 | |||
103 | brw_CMP(p, | ||
104 | vec1(brw_null_reg()), | ||
105 | conditional, | ||
106 | get_element(c->reg.dir, 2), | ||
107 | brw_imm_f(0)); | ||
108 | |||
109 | ccw = brw_IF(p, BRW_EXECUTE_1); | ||
110 | { | ||
111 | brw_clip_kill_thread(c); | ||
112 | } | ||
113 | brw_ENDIF(p, ccw); | ||
114 | } | ||
115 | |||
116 | |||
117 | |||
118 | static void copy_bfc( struct brw_clip_compile *c ) | ||
119 | { | ||
120 | struct brw_compile *p = &c->func; | ||
121 | struct brw_instruction *ccw; | ||
122 | GLuint conditional; | ||
123 | |||
124 | /* Do we have any colors to copy? | ||
125 | */ | ||
126 | if ((c->offset_color0 == 0 || c->offset_bfc0 == 0) && | ||
127 | (c->offset_color1 == 0 || c->offset_bfc1 == 0)) | ||
128 | return; | ||
129 | |||
130 | /* In some wierd degnerate cases we can end up testing the | ||
131 | * direction twice, once for culling and once for bfc copying. Oh | ||
132 | * well, that's what you get for setting wierd GL state. | ||
133 | */ | ||
134 | if (c->key.copy_bfc_ccw) | ||
135 | conditional = BRW_CONDITIONAL_GE; | ||
136 | else | ||
137 | conditional = BRW_CONDITIONAL_L; | ||
138 | |||
139 | brw_CMP(p, | ||
140 | vec1(brw_null_reg()), | ||
141 | conditional, | ||
142 | get_element(c->reg.dir, 2), | ||
143 | brw_imm_f(0)); | ||
144 | |||
145 | ccw = brw_IF(p, BRW_EXECUTE_1); | ||
146 | { | ||
147 | GLuint i; | ||
148 | |||
149 | for (i = 0; i < 3; i++) { | ||
150 | if (c->offset_color0 && c->offset_bfc0) | ||
151 | brw_MOV(p, | ||
152 | byte_offset(c->reg.vertex[i], c->offset_color0), | ||
153 | byte_offset(c->reg.vertex[i], c->offset_bfc0)); | ||
154 | |||
155 | if (c->offset_color1 && c->offset_bfc1) | ||
156 | brw_MOV(p, | ||
157 | byte_offset(c->reg.vertex[i], c->offset_color0), | ||
158 | byte_offset(c->reg.vertex[i], c->offset_bfc0)); | ||
159 | } | ||
160 | } | ||
161 | brw_ENDIF(p, ccw); | ||
162 | } | ||
163 | |||
164 | |||
165 | |||
166 | |||
167 | /* | ||
168 | GLfloat iz = 1.0 / dir.z; | ||
169 | GLfloat ac = dir.x * iz; | ||
170 | GLfloat bc = dir.y * iz; | ||
171 | offset = ctx->Polygon.OffsetUnits * DEPTH_SCALE; | ||
172 | offset += MAX2( abs(ac), abs(bc) ) * ctx->Polygon.OffsetFactor; | ||
173 | offset *= MRD; | ||
174 | */ | ||
175 | static void compute_offset( struct brw_clip_compile *c ) | ||
176 | { | ||
177 | struct brw_compile *p = &c->func; | ||
178 | struct brw_reg off = c->reg.offset; | ||
179 | struct brw_reg dir = c->reg.dir; | ||
180 | |||
181 | brw_math_invert(p, get_element(off, 2), get_element(dir, 2)); | ||
182 | brw_MUL(p, vec2(off), dir, get_element(off, 2)); | ||
183 | |||
184 | brw_CMP(p, | ||
185 | vec1(brw_null_reg()), | ||
186 | BRW_CONDITIONAL_GE, | ||
187 | brw_abs(get_element(off, 0)), | ||
188 | brw_abs(get_element(off, 1))); | ||
189 | |||
190 | brw_SEL(p, vec1(off), brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1))); | ||
191 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
192 | |||
193 | brw_MUL(p, vec1(off), off, brw_imm_f(c->key.offset_factor)); | ||
194 | brw_ADD(p, vec1(off), off, brw_imm_f(c->key.offset_units)); | ||
195 | } | ||
196 | |||
197 | |||
198 | static void merge_edgeflags( struct brw_clip_compile *c ) | ||
199 | { | ||
200 | struct brw_compile *p = &c->func; | ||
201 | struct brw_instruction *is_poly; | ||
202 | struct brw_reg tmp0 = get_element_ud(c->reg.tmp0, 0); | ||
203 | |||
204 | brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); | ||
205 | brw_CMP(p, | ||
206 | vec1(brw_null_reg()), | ||
207 | BRW_CONDITIONAL_EQ, | ||
208 | tmp0, | ||
209 | brw_imm_ud(_3DPRIM_POLYGON)); | ||
210 | |||
211 | /* Get away with using reg.vertex because we know that this is not | ||
212 | * a _3DPRIM_TRISTRIP_REVERSE: | ||
213 | */ | ||
214 | is_poly = brw_IF(p, BRW_EXECUTE_1); | ||
215 | { | ||
216 | brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ); | ||
217 | brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8)); | ||
218 | brw_MOV(p, byte_offset(c->reg.vertex[0], c->offset_edgeflag), brw_imm_f(0)); | ||
219 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
220 | |||
221 | brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ); | ||
222 | brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9)); | ||
223 | brw_MOV(p, byte_offset(c->reg.vertex[2], c->offset_edgeflag), brw_imm_f(0)); | ||
224 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
225 | } | ||
226 | brw_ENDIF(p, is_poly); | ||
227 | } | ||
228 | |||
229 | |||
230 | |||
231 | static void apply_one_offset( struct brw_clip_compile *c, | ||
232 | struct brw_indirect vert ) | ||
233 | { | ||
234 | struct brw_compile *p = &c->func; | ||
235 | struct brw_reg z = deref_1f(vert, c->header_position_offset + | ||
236 | 2 * type_sz(BRW_REGISTER_TYPE_F)); | ||
237 | |||
238 | brw_ADD(p, z, z, vec1(c->reg.offset)); | ||
239 | } | ||
240 | |||
241 | |||
242 | |||
243 | /*********************************************************************** | ||
244 | * Output clipped polygon as an unfilled primitive: | ||
245 | */ | ||
246 | static void emit_lines(struct brw_clip_compile *c, | ||
247 | GLboolean do_offset) | ||
248 | { | ||
249 | struct brw_compile *p = &c->func; | ||
250 | struct brw_instruction *loop; | ||
251 | struct brw_instruction *draw_edge; | ||
252 | struct brw_indirect v0 = brw_indirect(0, 0); | ||
253 | struct brw_indirect v1 = brw_indirect(1, 0); | ||
254 | struct brw_indirect v0ptr = brw_indirect(2, 0); | ||
255 | struct brw_indirect v1ptr = brw_indirect(3, 0); | ||
256 | |||
257 | /* Need a seperate loop for offset: | ||
258 | */ | ||
259 | if (do_offset) { | ||
260 | brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); | ||
261 | brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); | ||
262 | |||
263 | loop = brw_DO(p, BRW_EXECUTE_1); | ||
264 | { | ||
265 | brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); | ||
266 | brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); | ||
267 | |||
268 | apply_one_offset(c, v0); | ||
269 | |||
270 | brw_set_conditionalmod(p, BRW_CONDITIONAL_G); | ||
271 | brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); | ||
272 | } | ||
273 | brw_WHILE(p, loop); | ||
274 | } | ||
275 | |||
276 | /* v1ptr = &inlist[nr_verts] | ||
277 | * *v1ptr = v0 | ||
278 | */ | ||
279 | brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); | ||
280 | brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); | ||
281 | brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v0ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW)); | ||
282 | brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr), retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW)); | ||
283 | brw_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0)); | ||
284 | |||
285 | loop = brw_DO(p, BRW_EXECUTE_1); | ||
286 | { | ||
287 | brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); | ||
288 | brw_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2)); | ||
289 | brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); | ||
290 | |||
291 | /* draw edge if edgeflag != 0 */ | ||
292 | brw_CMP(p, | ||
293 | vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, | ||
294 | deref_1f(v0, c->offset_edgeflag), | ||
295 | brw_imm_f(0)); | ||
296 | draw_edge = brw_IF(p, BRW_EXECUTE_1); | ||
297 | { | ||
298 | brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START); | ||
299 | brw_clip_emit_vue(c, v1, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END); | ||
300 | } | ||
301 | brw_ENDIF(p, draw_edge); | ||
302 | |||
303 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
304 | brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); | ||
305 | } | ||
306 | brw_WHILE(p, loop); | ||
307 | } | ||
308 | |||
309 | |||
310 | |||
311 | static void emit_points(struct brw_clip_compile *c, | ||
312 | GLboolean do_offset ) | ||
313 | { | ||
314 | struct brw_compile *p = &c->func; | ||
315 | struct brw_instruction *loop; | ||
316 | struct brw_instruction *draw_point; | ||
317 | |||
318 | struct brw_indirect v0 = brw_indirect(0, 0); | ||
319 | struct brw_indirect v0ptr = brw_indirect(2, 0); | ||
320 | |||
321 | brw_MOV(p, c->reg.loopcount, c->reg.nr_verts); | ||
322 | brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist)); | ||
323 | |||
324 | loop = brw_DO(p, BRW_EXECUTE_1); | ||
325 | { | ||
326 | brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0)); | ||
327 | brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2)); | ||
328 | |||
329 | /* draw if edgeflag != 0 | ||
330 | */ | ||
331 | brw_CMP(p, | ||
332 | vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, | ||
333 | deref_1f(v0, c->offset_edgeflag), | ||
334 | brw_imm_f(0)); | ||
335 | draw_point = brw_IF(p, BRW_EXECUTE_1); | ||
336 | { | ||
337 | if (do_offset) | ||
338 | apply_one_offset(c, v0); | ||
339 | |||
340 | brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_POINTLIST << 2) | R02_PRIM_START | R02_PRIM_END); | ||
341 | } | ||
342 | brw_ENDIF(p, draw_point); | ||
343 | |||
344 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
345 | brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); | ||
346 | } | ||
347 | brw_WHILE(p, loop); | ||
348 | } | ||
349 | |||
350 | |||
351 | |||
352 | |||
353 | |||
354 | |||
355 | |||
356 | static void emit_primitives( struct brw_clip_compile *c, | ||
357 | GLuint mode, | ||
358 | GLboolean do_offset ) | ||
359 | { | ||
360 | switch (mode) { | ||
361 | case CLIP_FILL: | ||
362 | brw_clip_tri_emit_polygon(c); | ||
363 | break; | ||
364 | |||
365 | case CLIP_LINE: | ||
366 | emit_lines(c, do_offset); | ||
367 | break; | ||
368 | |||
369 | case CLIP_POINT: | ||
370 | emit_points(c, do_offset); | ||
371 | break; | ||
372 | |||
373 | case CLIP_CULL: | ||
374 | assert(0); | ||
375 | break; | ||
376 | } | ||
377 | } | ||
378 | |||
379 | |||
380 | |||
381 | static void emit_unfilled_primitives( struct brw_clip_compile *c ) | ||
382 | { | ||
383 | struct brw_compile *p = &c->func; | ||
384 | struct brw_instruction *ccw; | ||
385 | |||
386 | /* Direction culling has already been done. | ||
387 | */ | ||
388 | if (c->key.fill_ccw != c->key.fill_cw && | ||
389 | c->key.fill_ccw != CLIP_CULL && | ||
390 | c->key.fill_cw != CLIP_CULL) | ||
391 | { | ||
392 | brw_CMP(p, | ||
393 | vec1(brw_null_reg()), | ||
394 | BRW_CONDITIONAL_GE, | ||
395 | get_element(c->reg.dir, 2), | ||
396 | brw_imm_f(0)); | ||
397 | |||
398 | ccw = brw_IF(p, BRW_EXECUTE_1); | ||
399 | { | ||
400 | emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw); | ||
401 | } | ||
402 | ccw = brw_ELSE(p, ccw); | ||
403 | { | ||
404 | emit_primitives(c, c->key.fill_cw, c->key.offset_cw); | ||
405 | } | ||
406 | brw_ENDIF(p, ccw); | ||
407 | } | ||
408 | else if (c->key.fill_cw != CLIP_CULL) { | ||
409 | emit_primitives(c, c->key.fill_cw, c->key.offset_cw); | ||
410 | } | ||
411 | else if (c->key.fill_ccw != CLIP_CULL) { | ||
412 | emit_primitives(c, c->key.fill_ccw, c->key.offset_ccw); | ||
413 | } | ||
414 | } | ||
415 | |||
416 | |||
417 | |||
418 | |||
419 | static void check_nr_verts( struct brw_clip_compile *c ) | ||
420 | { | ||
421 | struct brw_compile *p = &c->func; | ||
422 | struct brw_instruction *if_insn; | ||
423 | |||
424 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.nr_verts, brw_imm_d(3)); | ||
425 | if_insn = brw_IF(p, BRW_EXECUTE_1); | ||
426 | { | ||
427 | brw_clip_kill_thread(c); | ||
428 | } | ||
429 | brw_ENDIF(p, if_insn); | ||
430 | } | ||
431 | |||
432 | |||
433 | void brw_emit_unfilled_clip( struct brw_clip_compile *c ) | ||
434 | { | ||
435 | struct brw_compile *p = &c->func; | ||
436 | struct brw_instruction *do_clip; | ||
437 | |||
438 | |||
439 | c->need_direction = ((c->key.offset_ccw || c->key.offset_cw) || | ||
440 | (c->key.fill_ccw != c->key.fill_cw) || | ||
441 | c->key.fill_ccw == CLIP_CULL || | ||
442 | c->key.fill_cw == CLIP_CULL || | ||
443 | c->key.copy_bfc_cw || | ||
444 | c->key.copy_bfc_ccw); | ||
445 | |||
446 | brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); | ||
447 | brw_clip_tri_init_vertices(c); | ||
448 | brw_clip_init_ff_sync(c); | ||
449 | |||
450 | assert(c->offset_edgeflag); | ||
451 | |||
452 | if (c->key.fill_ccw == CLIP_CULL && | ||
453 | c->key.fill_cw == CLIP_CULL) { | ||
454 | brw_clip_kill_thread(c); | ||
455 | return; | ||
456 | } | ||
457 | |||
458 | merge_edgeflags(c); | ||
459 | |||
460 | /* Need to use the inlist indirection here: | ||
461 | */ | ||
462 | if (c->need_direction) | ||
463 | compute_tri_direction(c); | ||
464 | |||
465 | if (c->key.fill_ccw == CLIP_CULL || | ||
466 | c->key.fill_cw == CLIP_CULL) | ||
467 | cull_direction(c); | ||
468 | |||
469 | if (c->key.offset_ccw || | ||
470 | c->key.offset_cw) | ||
471 | compute_offset(c); | ||
472 | |||
473 | if (c->key.copy_bfc_ccw || | ||
474 | c->key.copy_bfc_cw) | ||
475 | copy_bfc(c); | ||
476 | |||
477 | /* Need to do this whether we clip or not: | ||
478 | */ | ||
479 | if (c->key.do_flat_shading) | ||
480 | brw_clip_tri_flat_shade(c); | ||
481 | |||
482 | brw_clip_init_clipmask(c); | ||
483 | brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, c->reg.planemask, brw_imm_ud(0)); | ||
484 | do_clip = brw_IF(p, BRW_EXECUTE_1); | ||
485 | { | ||
486 | brw_clip_init_planes(c); | ||
487 | brw_clip_tri(c); | ||
488 | check_nr_verts(c); | ||
489 | } | ||
490 | brw_ENDIF(p, do_clip); | ||
491 | |||
492 | emit_unfilled_primitives(c); | ||
493 | brw_clip_kill_thread(c); | ||
494 | } | ||
495 | |||
496 | |||
497 | |||
diff --git a/src/gallium/drivers/i965/brw_clip_util.c b/src/gallium/drivers/i965/brw_clip_util.c deleted file mode 100644 index 5713f25da7c..00000000000 --- a/src/gallium/drivers/i965/brw_clip_util.c +++ /dev/null | |||
@@ -1,391 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_defines.h" | ||
34 | #include "brw_context.h" | ||
35 | #include "brw_eu.h" | ||
36 | #include "brw_clip.h" | ||
37 | |||
38 | |||
39 | |||
40 | |||
41 | struct brw_reg get_tmp( struct brw_clip_compile *c ) | ||
42 | { | ||
43 | struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0); | ||
44 | |||
45 | if (++c->last_tmp > c->prog_data.total_grf) | ||
46 | c->prog_data.total_grf = c->last_tmp; | ||
47 | |||
48 | return tmp; | ||
49 | } | ||
50 | |||
51 | static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp ) | ||
52 | { | ||
53 | if (tmp.nr == c->last_tmp-1) | ||
54 | c->last_tmp--; | ||
55 | } | ||
56 | |||
57 | |||
58 | static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w) | ||
59 | { | ||
60 | return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x); | ||
61 | } | ||
62 | |||
63 | |||
64 | void brw_clip_init_planes( struct brw_clip_compile *c ) | ||
65 | { | ||
66 | struct brw_compile *p = &c->func; | ||
67 | |||
68 | if (!c->key.nr_userclip) { | ||
69 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1)); | ||
70 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1)); | ||
71 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1)); | ||
72 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1)); | ||
73 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1)); | ||
74 | brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1)); | ||
75 | } | ||
76 | } | ||
77 | |||
78 | |||
79 | |||
80 | #define W 3 | ||
81 | |||
82 | /* Project 'pos' to screen space (or back again), overwrite with results: | ||
83 | */ | ||
84 | void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos ) | ||
85 | { | ||
86 | struct brw_compile *p = &c->func; | ||
87 | |||
88 | /* calc rhw | ||
89 | */ | ||
90 | brw_math_invert(p, get_element(pos, W), get_element(pos, W)); | ||
91 | |||
92 | /* value.xyz *= value.rhw | ||
93 | */ | ||
94 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
95 | brw_MUL(p, brw_writemask(pos, BRW_WRITEMASK_XYZ), pos, brw_swizzle1(pos, W)); | ||
96 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
97 | } | ||
98 | |||
99 | |||
100 | static void brw_clip_project_vertex( struct brw_clip_compile *c, | ||
101 | struct brw_indirect vert_addr ) | ||
102 | { | ||
103 | struct brw_compile *p = &c->func; | ||
104 | struct brw_reg tmp = get_tmp(c); | ||
105 | |||
106 | /* Fixup position. Extract from the original vertex and re-project | ||
107 | * to screen space: | ||
108 | */ | ||
109 | brw_MOV(p, tmp, deref_4f(vert_addr, c->offset_hpos)); | ||
110 | brw_clip_project_position(c, tmp); | ||
111 | brw_MOV(p, deref_4f(vert_addr, c->header_position_offset), tmp); | ||
112 | |||
113 | release_tmp(c, tmp); | ||
114 | } | ||
115 | |||
116 | |||
117 | |||
118 | |||
119 | /* Interpolate between two vertices and put the result into a0.0. | ||
120 | * Increment a0.0 accordingly. | ||
121 | */ | ||
122 | void brw_clip_interp_vertex( struct brw_clip_compile *c, | ||
123 | struct brw_indirect dest_ptr, | ||
124 | struct brw_indirect v0_ptr, /* from */ | ||
125 | struct brw_indirect v1_ptr, /* to */ | ||
126 | struct brw_reg t0, | ||
127 | GLboolean force_edgeflag) | ||
128 | { | ||
129 | struct brw_compile *p = &c->func; | ||
130 | struct brw_context *brw = p->brw; | ||
131 | struct brw_reg tmp = get_tmp(c); | ||
132 | GLuint i; | ||
133 | |||
134 | /* Just copy the vertex header: | ||
135 | */ | ||
136 | /* | ||
137 | * After CLIP stage, only first 256 bits of the VUE are read | ||
138 | * back on IGDNG, so needn't change it | ||
139 | */ | ||
140 | brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); | ||
141 | |||
142 | /* Iterate over each attribute (could be done in pairs?) | ||
143 | */ | ||
144 | for (i = 0; i < c->key.nr_attrs; i++) { | ||
145 | GLuint delta = i*16 + 32; | ||
146 | |||
147 | if (brw->gen == 5) | ||
148 | delta = i * 16 + 32 * 3; | ||
149 | |||
150 | if (delta == c->offset_edgeflag) { | ||
151 | if (force_edgeflag) | ||
152 | brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1)); | ||
153 | else | ||
154 | brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); | ||
155 | } | ||
156 | else { | ||
157 | /* Interpolate: | ||
158 | * | ||
159 | * New = attr0 + t*attr1 - t*attr0 | ||
160 | */ | ||
161 | brw_MUL(p, | ||
162 | vec4(brw_null_reg()), | ||
163 | deref_4f(v1_ptr, delta), | ||
164 | t0); | ||
165 | |||
166 | brw_MAC(p, | ||
167 | tmp, | ||
168 | negate(deref_4f(v0_ptr, delta)), | ||
169 | t0); | ||
170 | |||
171 | brw_ADD(p, | ||
172 | deref_4f(dest_ptr, delta), | ||
173 | deref_4f(v0_ptr, delta), | ||
174 | tmp); | ||
175 | } | ||
176 | } | ||
177 | |||
178 | if (i & 1) { | ||
179 | GLuint delta = i*16 + 32; | ||
180 | |||
181 | if (brw->gen == 5) | ||
182 | delta = i * 16 + 32 * 3; | ||
183 | |||
184 | brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); | ||
185 | } | ||
186 | |||
187 | release_tmp(c, tmp); | ||
188 | |||
189 | /* Recreate the projected (NDC) coordinate in the new vertex | ||
190 | * header: | ||
191 | */ | ||
192 | brw_clip_project_vertex(c, dest_ptr ); | ||
193 | } | ||
194 | |||
195 | |||
196 | |||
197 | |||
198 | #define MAX_MRF 16 | ||
199 | |||
200 | void brw_clip_emit_vue(struct brw_clip_compile *c, | ||
201 | struct brw_indirect vert, | ||
202 | GLboolean allocate, | ||
203 | GLboolean eot, | ||
204 | GLuint header) | ||
205 | { | ||
206 | struct brw_compile *p = &c->func; | ||
207 | GLuint start = c->last_mrf; | ||
208 | |||
209 | brw_clip_ff_sync(c); | ||
210 | |||
211 | assert(!(allocate && eot)); | ||
212 | |||
213 | /* Cycle through mrf regs - probably futile as we have to wait for | ||
214 | * the allocation response anyway. Also, the order this function | ||
215 | * is invoked doesn't correspond to the order the instructions will | ||
216 | * be executed, so it won't have any effect in many cases. | ||
217 | */ | ||
218 | #if 0 | ||
219 | if (start + c->nr_regs + 1 >= MAX_MRF) | ||
220 | start = 0; | ||
221 | |||
222 | c->last_mrf = start + c->nr_regs + 1; | ||
223 | #endif | ||
224 | |||
225 | /* Copy the vertex from vertn into m1..mN+1: | ||
226 | */ | ||
227 | brw_copy_from_indirect(p, brw_message_reg(start+1), vert, c->nr_regs); | ||
228 | |||
229 | /* Overwrite PrimType and PrimStart in the message header, for | ||
230 | * each vertex in turn: | ||
231 | */ | ||
232 | brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header)); | ||
233 | |||
234 | |||
235 | /* Send each vertex as a seperate write to the urb. This | ||
236 | * is different to the concept in brw_sf_emit.c, where | ||
237 | * subsequent writes are used to build up a single urb | ||
238 | * entry. Each of these writes instantiates a seperate | ||
239 | * urb entry - (I think... what about 'allocate'?) | ||
240 | */ | ||
241 | brw_urb_WRITE(p, | ||
242 | allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), | ||
243 | start, | ||
244 | c->reg.R0, | ||
245 | allocate, | ||
246 | 1, /* used */ | ||
247 | c->nr_regs + 1, /* msg length */ | ||
248 | allocate ? 1 : 0, /* response_length */ | ||
249 | eot, /* eot */ | ||
250 | 1, /* writes_complete */ | ||
251 | 0, /* urb offset */ | ||
252 | BRW_URB_SWIZZLE_NONE); | ||
253 | } | ||
254 | |||
255 | |||
256 | |||
257 | void brw_clip_kill_thread(struct brw_clip_compile *c) | ||
258 | { | ||
259 | struct brw_compile *p = &c->func; | ||
260 | |||
261 | brw_clip_ff_sync(c); | ||
262 | /* Send an empty message to kill the thread and release any | ||
263 | * allocated urb entry: | ||
264 | */ | ||
265 | brw_urb_WRITE(p, | ||
266 | retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), | ||
267 | 0, | ||
268 | c->reg.R0, | ||
269 | 0, /* allocate */ | ||
270 | 0, /* used */ | ||
271 | 1, /* msg len */ | ||
272 | 0, /* response len */ | ||
273 | 1, /* eot */ | ||
274 | 1, /* writes complete */ | ||
275 | 0, | ||
276 | BRW_URB_SWIZZLE_NONE); | ||
277 | } | ||
278 | |||
279 | |||
280 | |||
281 | |||
282 | struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c ) | ||
283 | { | ||
284 | return brw_address(c->reg.fixed_planes); | ||
285 | } | ||
286 | |||
287 | |||
288 | struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ) | ||
289 | { | ||
290 | if (c->key.nr_userclip) { | ||
291 | return brw_imm_uw(16); | ||
292 | } | ||
293 | else { | ||
294 | return brw_imm_uw(4); | ||
295 | } | ||
296 | } | ||
297 | |||
298 | |||
299 | /* If flatshading, distribute color from provoking vertex prior to | ||
300 | * clipping. | ||
301 | */ | ||
302 | void brw_clip_copy_colors( struct brw_clip_compile *c, | ||
303 | GLuint to, GLuint from ) | ||
304 | { | ||
305 | struct brw_compile *p = &c->func; | ||
306 | |||
307 | if (c->offset_color0) | ||
308 | brw_MOV(p, | ||
309 | byte_offset(c->reg.vertex[to], c->offset_color0), | ||
310 | byte_offset(c->reg.vertex[from], c->offset_color0)); | ||
311 | |||
312 | if (c->offset_color1) | ||
313 | brw_MOV(p, | ||
314 | byte_offset(c->reg.vertex[to], c->offset_color1), | ||
315 | byte_offset(c->reg.vertex[from], c->offset_color1)); | ||
316 | |||
317 | if (c->offset_bfc0) | ||
318 | brw_MOV(p, | ||
319 | byte_offset(c->reg.vertex[to], c->offset_bfc0), | ||
320 | byte_offset(c->reg.vertex[from], c->offset_bfc0)); | ||
321 | |||
322 | if (c->offset_bfc1) | ||
323 | brw_MOV(p, | ||
324 | byte_offset(c->reg.vertex[to], c->offset_bfc1), | ||
325 | byte_offset(c->reg.vertex[from], c->offset_bfc1)); | ||
326 | } | ||
327 | |||
328 | |||
329 | |||
330 | void brw_clip_init_clipmask( struct brw_clip_compile *c ) | ||
331 | { | ||
332 | struct brw_compile *p = &c->func; | ||
333 | struct brw_reg incoming = get_element_ud(c->reg.R0, 2); | ||
334 | |||
335 | /* Shift so that lowest outcode bit is rightmost: | ||
336 | */ | ||
337 | brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26)); | ||
338 | |||
339 | if (c->key.nr_userclip) { | ||
340 | struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD); | ||
341 | |||
342 | /* Rearrange userclip outcodes so that they come directly after | ||
343 | * the fixed plane bits. | ||
344 | */ | ||
345 | brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14)); | ||
346 | brw_SHR(p, tmp, tmp, brw_imm_ud(8)); | ||
347 | brw_OR(p, c->reg.planemask, c->reg.planemask, tmp); | ||
348 | |||
349 | release_tmp(c, tmp); | ||
350 | } | ||
351 | } | ||
352 | |||
353 | void brw_clip_ff_sync(struct brw_clip_compile *c) | ||
354 | { | ||
355 | struct brw_context *brw = c->func.brw; | ||
356 | if (brw->needs_ff_sync) { | ||
357 | struct brw_compile *p = &c->func; | ||
358 | struct brw_instruction *need_ff_sync; | ||
359 | |||
360 | brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); | ||
361 | brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1)); | ||
362 | need_ff_sync = brw_IF(p, BRW_EXECUTE_1); | ||
363 | { | ||
364 | brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1)); | ||
365 | brw_ff_sync(p, | ||
366 | c->reg.R0, | ||
367 | 0, | ||
368 | c->reg.R0, | ||
369 | 1, | ||
370 | 1, /* used */ | ||
371 | 1, /* msg length */ | ||
372 | 1, /* response length */ | ||
373 | 0, /* eot */ | ||
374 | 1, /* write compelete */ | ||
375 | 0, /* urb offset */ | ||
376 | BRW_URB_SWIZZLE_NONE); | ||
377 | } | ||
378 | brw_ENDIF(p, need_ff_sync); | ||
379 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
380 | } | ||
381 | } | ||
382 | |||
383 | void brw_clip_init_ff_sync(struct brw_clip_compile *c) | ||
384 | { | ||
385 | struct brw_context *brw = c->func.brw; | ||
386 | if (brw->needs_ff_sync) { | ||
387 | struct brw_compile *p = &c->func; | ||
388 | |||
389 | brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0)); | ||
390 | } | ||
391 | } | ||
diff --git a/src/gallium/drivers/i965/brw_context.c b/src/gallium/drivers/i965/brw_context.c deleted file mode 100644 index 41a468a32f0..00000000000 --- a/src/gallium/drivers/i965/brw_context.c +++ /dev/null | |||
@@ -1,162 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "pipe/p_context.h" | ||
34 | #include "util/u_inlines.h" | ||
35 | #include "util/u_simple_list.h" | ||
36 | |||
37 | #include "brw_context.h" | ||
38 | #include "brw_draw.h" | ||
39 | #include "brw_state.h" | ||
40 | #include "brw_batchbuffer.h" | ||
41 | #include "brw_winsys.h" | ||
42 | #include "brw_resource.h" | ||
43 | #include "brw_screen.h" | ||
44 | |||
45 | |||
46 | static void brw_destroy_context( struct pipe_context *pipe ) | ||
47 | { | ||
48 | struct brw_context *brw = brw_context(pipe); | ||
49 | int i; | ||
50 | |||
51 | brw_context_flush( brw ); | ||
52 | brw_batchbuffer_free( brw->batch ); | ||
53 | brw_destroy_state(brw); | ||
54 | |||
55 | brw_draw_cleanup( brw ); | ||
56 | |||
57 | brw_pipe_blend_cleanup( brw ); | ||
58 | brw_pipe_depth_stencil_cleanup( brw ); | ||
59 | brw_pipe_framebuffer_cleanup( brw ); | ||
60 | brw_pipe_flush_cleanup( brw ); | ||
61 | brw_pipe_misc_cleanup( brw ); | ||
62 | brw_pipe_query_cleanup( brw ); | ||
63 | brw_pipe_rast_cleanup( brw ); | ||
64 | brw_pipe_sampler_cleanup( brw ); | ||
65 | brw_pipe_shader_cleanup( brw ); | ||
66 | brw_pipe_vertex_cleanup( brw ); | ||
67 | brw_pipe_clear_cleanup( brw ); | ||
68 | |||
69 | brw_hw_cc_cleanup( brw ); | ||
70 | |||
71 | |||
72 | FREE(brw->wm.compile_data); | ||
73 | |||
74 | for (i = 0; i < brw->curr.fb.nr_cbufs; i++) | ||
75 | pipe_surface_reference(&brw->curr.fb.cbufs[i], NULL); | ||
76 | brw->curr.fb.nr_cbufs = 0; | ||
77 | pipe_surface_reference(&brw->curr.fb.zsbuf, NULL); | ||
78 | |||
79 | bo_reference(&brw->curbe.curbe_bo, NULL); | ||
80 | bo_reference(&brw->vs.prog_bo, NULL); | ||
81 | bo_reference(&brw->vs.state_bo, NULL); | ||
82 | bo_reference(&brw->vs.bind_bo, NULL); | ||
83 | bo_reference(&brw->gs.prog_bo, NULL); | ||
84 | bo_reference(&brw->gs.state_bo, NULL); | ||
85 | bo_reference(&brw->clip.prog_bo, NULL); | ||
86 | bo_reference(&brw->clip.state_bo, NULL); | ||
87 | bo_reference(&brw->clip.vp_bo, NULL); | ||
88 | bo_reference(&brw->sf.prog_bo, NULL); | ||
89 | bo_reference(&brw->sf.state_bo, NULL); | ||
90 | bo_reference(&brw->sf.vp_bo, NULL); | ||
91 | |||
92 | for (i = 0; i < Elements(brw->wm.sdc_bo); i++) | ||
93 | bo_reference(&brw->wm.sdc_bo[i], NULL); | ||
94 | |||
95 | bo_reference(&brw->wm.bind_bo, NULL); | ||
96 | |||
97 | for (i = 0; i < Elements(brw->wm.surf_bo); i++) | ||
98 | bo_reference(&brw->wm.surf_bo[i], NULL); | ||
99 | |||
100 | bo_reference(&brw->wm.sampler_bo, NULL); | ||
101 | bo_reference(&brw->wm.prog_bo, NULL); | ||
102 | bo_reference(&brw->wm.state_bo, NULL); | ||
103 | } | ||
104 | |||
105 | |||
106 | struct pipe_context *brw_create_context(struct pipe_screen *screen, | ||
107 | void *priv) | ||
108 | { | ||
109 | struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context); | ||
110 | struct brw_screen *brs = brw_screen(screen); | ||
111 | if (!brw) { | ||
112 | debug_printf("%s: failed to alloc context\n", __FUNCTION__); | ||
113 | return NULL; | ||
114 | } | ||
115 | |||
116 | brw->base.screen = screen; | ||
117 | brw->base.priv = priv; | ||
118 | brw->base.destroy = brw_destroy_context; | ||
119 | brw->sws = brw_screen(screen)->sws; | ||
120 | brw->is_g4x = brs->is_g4x; | ||
121 | brw->needs_ff_sync = brs->needs_ff_sync; | ||
122 | brw->has_negative_rhw_bug = brs->has_negative_rhw_bug; | ||
123 | brw->gen = brs->gen; | ||
124 | |||
125 | brw_init_resource_functions( brw ); | ||
126 | brw_pipe_blend_init( brw ); | ||
127 | brw_pipe_depth_stencil_init( brw ); | ||
128 | brw_pipe_framebuffer_init( brw ); | ||
129 | brw_pipe_flush_init( brw ); | ||
130 | brw_pipe_misc_init( brw ); | ||
131 | brw_pipe_query_init( brw ); | ||
132 | brw_pipe_rast_init( brw ); | ||
133 | brw_pipe_sampler_init( brw ); | ||
134 | brw_pipe_shader_init( brw ); | ||
135 | brw_pipe_vertex_init( brw ); | ||
136 | brw_pipe_clear_init( brw ); | ||
137 | brw_pipe_surface_init( brw ); | ||
138 | |||
139 | brw_hw_cc_init( brw ); | ||
140 | |||
141 | brw_init_state( brw ); | ||
142 | brw_draw_init( brw ); | ||
143 | |||
144 | brw->state.dirty.mesa = ~0; | ||
145 | brw->state.dirty.brw = ~0; | ||
146 | |||
147 | brw->flags.always_emit_state = 0; | ||
148 | |||
149 | make_empty_list(&brw->query.active_head); | ||
150 | |||
151 | brw->batch = brw_batchbuffer_alloc( brw->sws ); | ||
152 | if (brw->batch == NULL) | ||
153 | goto fail; | ||
154 | |||
155 | return &brw->base; | ||
156 | |||
157 | fail: | ||
158 | if (brw->batch) | ||
159 | brw_batchbuffer_free( brw->batch ); | ||
160 | return NULL; | ||
161 | } | ||
162 | |||
diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h deleted file mode 100644 index 45fc26dd7d8..00000000000 --- a/src/gallium/drivers/i965/brw_context.h +++ /dev/null | |||
@@ -1,865 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRWCONTEXT_INC | ||
34 | #define BRWCONTEXT_INC | ||
35 | |||
36 | #include "brw_structs.h" | ||
37 | #include "brw_winsys.h" | ||
38 | #include "brw_reg.h" | ||
39 | #include "pipe/p_state.h" | ||
40 | #include "pipe/p_context.h" | ||
41 | #include "tgsi/tgsi_scan.h" | ||
42 | |||
43 | |||
44 | /* Glossary: | ||
45 | * | ||
46 | * URB - uniform resource buffer. A mid-sized buffer which is | ||
47 | * partitioned between the fixed function units and used for passing | ||
48 | * values (vertices, primitives, constants) between them. | ||
49 | * | ||
50 | * CURBE - constant URB entry. An urb region (entry) used to hold | ||
51 | * constant values which the fixed function units can be instructed to | ||
52 | * preload into the GRF when spawning a thread. | ||
53 | * | ||
54 | * VUE - vertex URB entry. An urb entry holding a vertex and usually | ||
55 | * a vertex header. The header contains control information and | ||
56 | * things like primitive type, Begin/end flags and clip codes. | ||
57 | * | ||
58 | * PUE - primitive URB entry. An urb entry produced by the setup (SF) | ||
59 | * unit holding rasterization and interpolation parameters. | ||
60 | * | ||
61 | * GRF - general register file. One of several register files | ||
62 | * addressable by programmed threads. The inputs (r0, payload, curbe, | ||
63 | * urb) of the thread are preloaded to this area before the thread is | ||
64 | * spawned. The registers are individually 8 dwords wide and suitable | ||
65 | * for general usage. Registers holding thread input values are not | ||
66 | * special and may be overwritten. | ||
67 | * | ||
68 | * MRF - message register file. Threads communicate (and terminate) | ||
69 | * by sending messages. Message parameters are placed in contiguous | ||
70 | * MRF registers. All program output is via these messages. URB | ||
71 | * entries are populated by sending a message to the shared URB | ||
72 | * function containing the new data, together with a control word, | ||
73 | * often an unmodified copy of R0. | ||
74 | * | ||
75 | * R0 - GRF register 0. Typically holds control information used when | ||
76 | * sending messages to other threads. | ||
77 | * | ||
78 | * EU or GEN4 EU: The name of the programmable subsystem of the | ||
79 | * i965 hardware. Threads are executed by the EU, the registers | ||
80 | * described above are part of the EU architecture. | ||
81 | * | ||
82 | * Fixed function units: | ||
83 | * | ||
84 | * CS - Command streamer. Notional first unit, little software | ||
85 | * interaction. Holds the URB entries used for constant data, ie the | ||
86 | * CURBEs. | ||
87 | * | ||
88 | * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of | ||
89 | * this unit is responsible for pulling vertices out of vertex buffers | ||
90 | * in vram and injecting them into the processing pipe as VUEs. If | ||
91 | * enabled, it first passes them to a VS thread which is a good place | ||
92 | * for the driver to implement any active vertex shader. | ||
93 | * | ||
94 | * GS - Geometry Shader. This corresponds to a new DX10 concept. If | ||
95 | * enabled, incoming strips etc are passed to GS threads in individual | ||
96 | * line/triangle/point units. The GS thread may perform arbitary | ||
97 | * computation and emit whatever primtives with whatever vertices it | ||
98 | * chooses. This makes GS an excellent place to implement GL's | ||
99 | * unfilled polygon modes, though of course it is capable of much | ||
100 | * more. Additionally, GS is used to translate away primitives not | ||
101 | * handled by latter units, including Quads and Lineloops. | ||
102 | * | ||
103 | * CS - Clipper. Mesa's clipping algorithms are imported to run on | ||
104 | * this unit. The fixed function part performs cliptesting against | ||
105 | * the 6 fixed clipplanes and makes decisions on whether or not the | ||
106 | * incoming primitive needs to be passed to a thread for clipping. | ||
107 | * User clip planes are handled via cooperation with the VS thread. | ||
108 | * | ||
109 | * SF - Strips Fans or Setup: Triangles are prepared for | ||
110 | * rasterization. Interpolation coefficients are calculated. | ||
111 | * Flatshading and two-side lighting usually performed here. | ||
112 | * | ||
113 | * WM - Windower. Interpolation of vertex attributes performed here. | ||
114 | * Fragment shader implemented here. SIMD aspects of EU taken full | ||
115 | * advantage of, as pixels are processed in blocks of 16. | ||
116 | * | ||
117 | * CC - Color Calculator. No EU threads associated with this unit. | ||
118 | * Handles blending and (presumably) depth and stencil testing. | ||
119 | */ | ||
120 | |||
121 | #define BRW_MAX_CURBE (32*16) | ||
122 | |||
123 | |||
124 | /* Need a value to say a particular vertex shader output isn't | ||
125 | * present. Limits us to 63 outputs currently. | ||
126 | */ | ||
127 | #define BRW_OUTPUT_NOT_PRESENT ((1<<6)-1) | ||
128 | |||
129 | |||
130 | struct brw_context; | ||
131 | |||
132 | struct brw_depth_stencil_state { | ||
133 | /* Precalculated hardware state: | ||
134 | */ | ||
135 | struct brw_cc0 cc0; | ||
136 | struct brw_cc1 cc1; | ||
137 | struct brw_cc2 cc2; | ||
138 | struct brw_cc3 cc3; | ||
139 | struct brw_cc7 cc7; | ||
140 | |||
141 | unsigned iz_lookup; | ||
142 | }; | ||
143 | |||
144 | |||
145 | struct brw_blend_state { | ||
146 | /* Precalculated hardware state: | ||
147 | */ | ||
148 | struct brw_cc2 cc2; | ||
149 | struct brw_cc3 cc3; | ||
150 | struct brw_cc5 cc5; | ||
151 | struct brw_cc6 cc6; | ||
152 | |||
153 | struct brw_surf_ss0 ss0; | ||
154 | }; | ||
155 | |||
156 | struct brw_rasterizer_state; | ||
157 | |||
158 | struct brw_immediate_data { | ||
159 | unsigned nr; | ||
160 | float (*data)[4]; | ||
161 | }; | ||
162 | |||
163 | struct brw_vertex_shader { | ||
164 | const struct tgsi_token *tokens; | ||
165 | struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */ | ||
166 | |||
167 | struct tgsi_shader_info info; | ||
168 | struct brw_immediate_data immediates; | ||
169 | |||
170 | GLuint has_flow_control:1; | ||
171 | GLuint use_const_buffer:1; | ||
172 | |||
173 | /* Offsets of special vertex shader outputs required for clipping. | ||
174 | */ | ||
175 | GLuint output_hpos:6; /* not always zero? */ | ||
176 | GLuint output_color0:6; | ||
177 | GLuint output_color1:6; | ||
178 | GLuint output_bfc0:6; | ||
179 | GLuint output_bfc1:6; | ||
180 | GLuint output_edgeflag:6; | ||
181 | |||
182 | unsigned id; | ||
183 | }; | ||
184 | |||
185 | struct brw_fs_signature { | ||
186 | GLuint nr_inputs; | ||
187 | struct { | ||
188 | GLuint interp:3; /* TGSI_INTERPOLATE_x */ | ||
189 | GLuint semantic:5; /* TGSI_SEMANTIC_x */ | ||
190 | GLuint semantic_index:24; | ||
191 | } input[PIPE_MAX_SHADER_INPUTS]; | ||
192 | }; | ||
193 | |||
194 | #define brw_fs_signature_size(s) (offsetof(struct brw_fs_signature, input) + \ | ||
195 | ((s)->nr_inputs * sizeof (s)->input[0])) | ||
196 | |||
197 | |||
198 | struct brw_fragment_shader { | ||
199 | const struct tgsi_token *tokens; | ||
200 | struct tgsi_shader_info info; | ||
201 | |||
202 | struct brw_fs_signature signature; | ||
203 | struct brw_immediate_data immediates; | ||
204 | |||
205 | unsigned iz_lookup; | ||
206 | /*unsigned wm_lookup;*/ | ||
207 | |||
208 | unsigned uses_depth:1; | ||
209 | unsigned has_flow_control:1; | ||
210 | |||
211 | unsigned id; | ||
212 | struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */ | ||
213 | GLboolean use_const_buffer; | ||
214 | }; | ||
215 | |||
216 | |||
217 | struct brw_sampler { | ||
218 | struct brw_ss0 ss0; | ||
219 | struct brw_ss1 ss1; | ||
220 | float border_color[4]; | ||
221 | struct brw_ss3 ss3; | ||
222 | }; | ||
223 | |||
224 | |||
225 | |||
226 | #define PIPE_NEW_DEPTH_STENCIL_ALPHA 0x1 | ||
227 | #define PIPE_NEW_RAST 0x2 | ||
228 | #define PIPE_NEW_BLEND 0x4 | ||
229 | #define PIPE_NEW_VIEWPORT 0x8 | ||
230 | #define PIPE_NEW_SAMPLERS 0x10 | ||
231 | #define PIPE_NEW_VERTEX_BUFFER 0x20 | ||
232 | #define PIPE_NEW_VERTEX_ELEMENT 0x40 | ||
233 | #define PIPE_NEW_FRAGMENT_SHADER 0x80 | ||
234 | #define PIPE_NEW_VERTEX_SHADER 0x100 | ||
235 | #define PIPE_NEW_FRAGMENT_CONSTANTS 0x200 | ||
236 | #define PIPE_NEW_VERTEX_CONSTANTS 0x400 | ||
237 | #define PIPE_NEW_CLIP 0x800 | ||
238 | #define PIPE_NEW_INDEX_BUFFER 0x1000 | ||
239 | #define PIPE_NEW_INDEX_RANGE 0x2000 | ||
240 | #define PIPE_NEW_BLEND_COLOR 0x4000 | ||
241 | #define PIPE_NEW_POLYGON_STIPPLE 0x8000 | ||
242 | #define PIPE_NEW_FRAMEBUFFER_DIMENSIONS 0x10000 | ||
243 | #define PIPE_NEW_DEPTH_BUFFER 0x20000 | ||
244 | #define PIPE_NEW_COLOR_BUFFERS 0x40000 | ||
245 | #define PIPE_NEW_QUERY 0x80000 | ||
246 | #define PIPE_NEW_SCISSOR 0x100000 | ||
247 | #define PIPE_NEW_BOUND_TEXTURES 0x200000 | ||
248 | #define PIPE_NEW_NR_CBUFS 0x400000 | ||
249 | #define PIPE_NEW_FRAGMENT_SIGNATURE 0x800000 | ||
250 | |||
251 | |||
252 | |||
253 | #define BRW_NEW_URB_FENCE 0x1 | ||
254 | #define BRW_NEW_FRAGMENT_PROGRAM 0x2 | ||
255 | #define BRW_NEW_VERTEX_PROGRAM 0x4 | ||
256 | #define BRW_NEW_INPUT_DIMENSIONS 0x8 | ||
257 | #define BRW_NEW_CURBE_OFFSETS 0x10 | ||
258 | #define BRW_NEW_REDUCED_PRIMITIVE 0x20 | ||
259 | #define BRW_NEW_PRIMITIVE 0x40 | ||
260 | #define BRW_NEW_CONTEXT 0x80 | ||
261 | #define BRW_NEW_WM_INPUT_DIMENSIONS 0x100 | ||
262 | #define BRW_NEW_PSP 0x800 | ||
263 | #define BRW_NEW_WM_SURFACES 0x1000 | ||
264 | #define BRW_NEW_xxx 0x2000 /* was FENCE */ | ||
265 | #define BRW_NEW_INDICES 0x4000 | ||
266 | |||
267 | /** | ||
268 | * Used for any batch entry with a relocated pointer that will be used | ||
269 | * by any 3D rendering. Need to re-emit these fresh in each | ||
270 | * batchbuffer as the referenced buffers may be relocated in the | ||
271 | * meantime. | ||
272 | */ | ||
273 | #define BRW_NEW_BATCH 0x10000 | ||
274 | #define BRW_NEW_NR_WM_SURFACES 0x40000 | ||
275 | #define BRW_NEW_NR_VS_SURFACES 0x80000 | ||
276 | #define BRW_NEW_INDEX_BUFFER 0x100000 | ||
277 | |||
278 | struct brw_state_flags { | ||
279 | /** State update flags signalled by mesa internals */ | ||
280 | GLuint mesa; | ||
281 | /** | ||
282 | * State update flags signalled as the result of brw_tracked_state updates | ||
283 | */ | ||
284 | GLuint brw; | ||
285 | /** State update flags signalled by brw_state_cache.c searches */ | ||
286 | GLuint cache; | ||
287 | }; | ||
288 | |||
289 | |||
290 | |||
291 | /* Data about a particular attempt to compile a program. Note that | ||
292 | * there can be many of these, each in a different GL state | ||
293 | * corresponding to a different brw_wm_prog_key struct, with different | ||
294 | * compiled programs: | ||
295 | */ | ||
296 | struct brw_wm_prog_data { | ||
297 | GLuint curb_read_length; | ||
298 | GLuint urb_read_length; | ||
299 | |||
300 | GLuint first_curbe_grf; | ||
301 | GLuint total_grf; | ||
302 | GLuint total_scratch; | ||
303 | |||
304 | GLuint nr_params; /**< number of float params/constants */ | ||
305 | GLboolean error; | ||
306 | |||
307 | /* Pointer to tracked values (only valid once | ||
308 | * _mesa_load_state_parameters has been called at runtime). | ||
309 | */ | ||
310 | const GLfloat *param[BRW_MAX_CURBE]; | ||
311 | }; | ||
312 | |||
313 | struct brw_sf_prog_data { | ||
314 | GLuint urb_read_length; | ||
315 | GLuint total_grf; | ||
316 | |||
317 | /* Each vertex may have upto 12 attributes, 4 components each, | ||
318 | * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11 | ||
319 | * rows. | ||
320 | * | ||
321 | * Actually we use 4 for each, so call it 12 rows. | ||
322 | */ | ||
323 | GLuint urb_entry_size; | ||
324 | }; | ||
325 | |||
326 | |||
327 | struct brw_clip_prog_data; | ||
328 | |||
329 | struct brw_gs_prog_data { | ||
330 | GLuint urb_read_length; | ||
331 | GLuint total_grf; | ||
332 | }; | ||
333 | |||
334 | struct brw_vs_prog_data { | ||
335 | GLuint curb_read_length; | ||
336 | GLuint urb_read_length; | ||
337 | GLuint total_grf; | ||
338 | |||
339 | GLuint nr_outputs; | ||
340 | GLuint nr_inputs; | ||
341 | |||
342 | GLuint nr_params; /**< number of TGSI_FILE_CONSTANT's */ | ||
343 | |||
344 | GLboolean writes_psiz; | ||
345 | |||
346 | /* Used for calculating urb partitions: | ||
347 | */ | ||
348 | GLuint urb_entry_size; | ||
349 | }; | ||
350 | |||
351 | |||
352 | /* Size == 0 if output either not written, or always [0,0,0,1] | ||
353 | */ | ||
354 | struct brw_vs_output_sizes { | ||
355 | GLubyte output_size[PIPE_MAX_SHADER_OUTPUTS]; | ||
356 | }; | ||
357 | |||
358 | |||
359 | /** Number of texture sampler units */ | ||
360 | #define BRW_MAX_TEX_UNIT 16 | ||
361 | |||
362 | /** Max number of render targets in a shader */ | ||
363 | #define BRW_MAX_DRAW_BUFFERS 4 | ||
364 | |||
365 | /** | ||
366 | * Size of our surface binding table for the WM. | ||
367 | * This contains pointers to the drawing surfaces and current texture | ||
368 | * objects and shader constant buffers (+2). | ||
369 | */ | ||
370 | #define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1) | ||
371 | |||
372 | /** | ||
373 | * Helpers to convert drawing buffers, textures and constant buffers | ||
374 | * to surface binding table indexes, for WM. | ||
375 | */ | ||
376 | #define BTI_COLOR_BUF(d) (d) | ||
377 | #define BTI_FRAGMENT_CONSTANTS (BRW_MAX_DRAW_BUFFERS) | ||
378 | #define BTI_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t)) | ||
379 | |||
380 | /** | ||
381 | * Size of surface binding table for the VS. | ||
382 | * Only one constant buffer for now. | ||
383 | */ | ||
384 | #define BRW_VS_MAX_SURF 1 | ||
385 | |||
386 | /** | ||
387 | * Only a VS constant buffer | ||
388 | */ | ||
389 | #define SURF_INDEX_VERT_CONST_BUFFER 0 | ||
390 | |||
391 | |||
392 | /* Bit of a hack to align these with the winsys buffer_data_type enum. | ||
393 | */ | ||
394 | enum brw_cache_id { | ||
395 | BRW_CC_VP = BRW_DATA_GS_CC_VP, | ||
396 | BRW_CC_UNIT = BRW_DATA_GS_CC_UNIT, | ||
397 | BRW_WM_PROG = BRW_DATA_GS_WM_PROG, | ||
398 | BRW_SAMPLER_DEFAULT_COLOR = BRW_DATA_GS_SAMPLER_DEFAULT_COLOR, | ||
399 | BRW_SAMPLER = BRW_DATA_GS_SAMPLER, | ||
400 | BRW_WM_UNIT = BRW_DATA_GS_WM_UNIT, | ||
401 | BRW_SF_PROG = BRW_DATA_GS_SF_PROG, | ||
402 | BRW_SF_VP = BRW_DATA_GS_SF_VP, | ||
403 | BRW_SF_UNIT = BRW_DATA_GS_SF_UNIT, | ||
404 | BRW_VS_UNIT = BRW_DATA_GS_VS_UNIT, | ||
405 | BRW_VS_PROG = BRW_DATA_GS_VS_PROG, | ||
406 | BRW_GS_UNIT = BRW_DATA_GS_GS_UNIT, | ||
407 | BRW_GS_PROG = BRW_DATA_GS_GS_PROG, | ||
408 | BRW_CLIP_VP = BRW_DATA_GS_CLIP_VP, | ||
409 | BRW_CLIP_UNIT = BRW_DATA_GS_CLIP_UNIT, | ||
410 | BRW_CLIP_PROG = BRW_DATA_GS_CLIP_PROG, | ||
411 | BRW_SS_SURFACE = BRW_DATA_SS_SURFACE, | ||
412 | BRW_SS_SURF_BIND = BRW_DATA_SS_SURF_BIND, | ||
413 | |||
414 | BRW_MAX_CACHE | ||
415 | }; | ||
416 | |||
417 | struct brw_cache_item { | ||
418 | /** | ||
419 | * Effectively part of the key, cache_id identifies what kind of state | ||
420 | * buffer is involved, and also which brw->state.dirty.cache flag should | ||
421 | * be set when this cache item is chosen. | ||
422 | */ | ||
423 | enum brw_cache_id cache_id; | ||
424 | /** 32-bit hash of the key data */ | ||
425 | GLuint hash; | ||
426 | GLuint key_size; /* for variable-sized keys */ | ||
427 | const void *key; | ||
428 | struct brw_winsys_reloc *relocs; | ||
429 | GLuint nr_relocs; | ||
430 | |||
431 | struct brw_winsys_buffer *bo; | ||
432 | GLuint data_size; | ||
433 | |||
434 | struct brw_cache_item *next; | ||
435 | }; | ||
436 | |||
437 | |||
438 | |||
439 | struct brw_cache { | ||
440 | struct brw_context *brw; | ||
441 | struct brw_winsys_screen *sws; | ||
442 | |||
443 | struct brw_cache_item **items; | ||
444 | GLuint size, n_items; | ||
445 | |||
446 | enum brw_buffer_type buffer_type; | ||
447 | |||
448 | GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */ | ||
449 | GLuint aux_size[BRW_MAX_CACHE]; | ||
450 | char *name[BRW_MAX_CACHE]; | ||
451 | |||
452 | |||
453 | /* Record of the last BOs chosen for each cache_id. Used to set | ||
454 | * brw->state.dirty.cache when a new cache item is chosen. | ||
455 | */ | ||
456 | struct brw_winsys_buffer *last_bo[BRW_MAX_CACHE]; | ||
457 | }; | ||
458 | |||
459 | |||
460 | struct brw_tracked_state { | ||
461 | struct brw_state_flags dirty; | ||
462 | int (*prepare)( struct brw_context *brw ); | ||
463 | int (*emit)( struct brw_context *brw ); | ||
464 | }; | ||
465 | |||
466 | /* Flags for brw->state.cache. | ||
467 | */ | ||
468 | #define CACHE_NEW_CC_VP (1<<BRW_CC_VP) | ||
469 | #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT) | ||
470 | #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG) | ||
471 | #define CACHE_NEW_SAMPLER_DEFAULT_COLOR (1<<BRW_SAMPLER_DEFAULT_COLOR) | ||
472 | #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER) | ||
473 | #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT) | ||
474 | #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG) | ||
475 | #define CACHE_NEW_SF_VP (1<<BRW_SF_VP) | ||
476 | #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT) | ||
477 | #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT) | ||
478 | #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG) | ||
479 | #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT) | ||
480 | #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG) | ||
481 | #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP) | ||
482 | #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT) | ||
483 | #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG) | ||
484 | #define CACHE_NEW_SURFACE (1<<BRW_SS_SURFACE) | ||
485 | #define CACHE_NEW_SURF_BIND (1<<BRW_SS_SURF_BIND) | ||
486 | |||
487 | struct brw_cached_batch_item { | ||
488 | struct header *header; | ||
489 | GLuint sz; | ||
490 | struct brw_cached_batch_item *next; | ||
491 | }; | ||
492 | |||
493 | |||
494 | |||
495 | /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life | ||
496 | * be easier if C allowed arrays of packed elements? | ||
497 | */ | ||
498 | #define VS_INPUT_BITMASK_DWORDS ((PIPE_MAX_SHADER_INPUTS+31)/32) | ||
499 | |||
500 | |||
501 | |||
502 | |||
503 | struct brw_vertex_info { | ||
504 | GLuint sizes[VS_INPUT_BITMASK_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */ | ||
505 | }; | ||
506 | |||
507 | |||
508 | struct brw_query_object { | ||
509 | /** Doubly linked list of active query objects in the context. */ | ||
510 | struct brw_query_object *prev, *next; | ||
511 | |||
512 | /** Last query BO associated with this query. */ | ||
513 | struct brw_winsys_buffer *bo; | ||
514 | /** First index in bo with query data for this object. */ | ||
515 | int first_index; | ||
516 | /** Last index in bo with query data for this object. */ | ||
517 | int last_index; | ||
518 | |||
519 | /* Total count of pixels from previous BOs */ | ||
520 | uint64_t result; | ||
521 | }; | ||
522 | |||
523 | #define CC_RELOC_VP 0 | ||
524 | |||
525 | |||
526 | /** | ||
527 | * brw_context is derived from pipe_context | ||
528 | */ | ||
529 | struct brw_context | ||
530 | { | ||
531 | struct pipe_context base; | ||
532 | int gen; | ||
533 | boolean has_negative_rhw_bug; | ||
534 | boolean needs_ff_sync; | ||
535 | boolean is_g4x; | ||
536 | |||
537 | int urb_size; | ||
538 | int vs_max_threads; | ||
539 | int wm_max_threads; | ||
540 | |||
541 | struct brw_winsys_screen *sws; | ||
542 | |||
543 | struct brw_batchbuffer *batch; | ||
544 | |||
545 | GLuint primitive; | ||
546 | GLuint reduced_primitive; | ||
547 | |||
548 | /* Active state from the state tracker: | ||
549 | */ | ||
550 | struct { | ||
551 | struct brw_vertex_shader *vertex_shader; | ||
552 | struct brw_fragment_shader *fragment_shader; | ||
553 | const struct brw_blend_state *blend; | ||
554 | const struct brw_rasterizer_state *rast; | ||
555 | const struct brw_depth_stencil_state *zstencil; | ||
556 | const struct brw_vertex_element_packet *velems; | ||
557 | |||
558 | const struct brw_sampler *sampler[PIPE_MAX_SAMPLERS]; | ||
559 | unsigned num_samplers; | ||
560 | |||
561 | struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS]; | ||
562 | struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; | ||
563 | unsigned num_fragment_sampler_views; | ||
564 | unsigned num_vertex_buffers; | ||
565 | |||
566 | struct pipe_scissor_state scissor; | ||
567 | struct pipe_viewport_state viewport; | ||
568 | struct pipe_stencil_ref stencil_ref; | ||
569 | struct pipe_framebuffer_state fb; | ||
570 | struct pipe_clip_state ucp; | ||
571 | struct pipe_resource *vertex_constants; | ||
572 | struct pipe_resource *fragment_constants; | ||
573 | |||
574 | struct brw_blend_constant_color bcc; | ||
575 | struct brw_cc1 cc1_stencil_ref; | ||
576 | struct brw_polygon_stipple bps; | ||
577 | struct brw_cc_viewport ccv; | ||
578 | |||
579 | /** | ||
580 | * Index buffer for this draw_prims call. | ||
581 | * | ||
582 | * Updates are signaled by PIPE_NEW_INDEX_BUFFER. | ||
583 | */ | ||
584 | struct pipe_resource *index_buffer; | ||
585 | unsigned index_size; | ||
586 | unsigned index_offset; | ||
587 | |||
588 | /* Updates are signalled by PIPE_NEW_INDEX_RANGE: | ||
589 | */ | ||
590 | unsigned min_index; | ||
591 | unsigned max_index; | ||
592 | |||
593 | } curr; | ||
594 | |||
595 | struct { | ||
596 | struct brw_state_flags dirty; | ||
597 | |||
598 | /** | ||
599 | * List of buffers accumulated in brw_validate_state to receive | ||
600 | * dri_bo_check_aperture treatment before exec, so we can know if we | ||
601 | * should flush the batch and try again before emitting primitives. | ||
602 | * | ||
603 | * This can be a fixed number as we only have a limited number of | ||
604 | * objects referenced from the batchbuffer in a primitive emit, | ||
605 | * consisting of the vertex buffers, pipelined state pointers, | ||
606 | * the CURBE, the depth buffer, and a query BO. | ||
607 | */ | ||
608 | struct brw_winsys_buffer *validated_bos[PIPE_MAX_SHADER_INPUTS + 16]; | ||
609 | int validated_bo_count; | ||
610 | } state; | ||
611 | |||
612 | struct brw_cache cache; /** non-surface items */ | ||
613 | struct brw_cache surface_cache; /* surface items */ | ||
614 | struct brw_cached_batch_item *cached_batch_items; | ||
615 | |||
616 | struct { | ||
617 | struct u_upload_mgr *upload_vertex; | ||
618 | struct u_upload_mgr *upload_index; | ||
619 | |||
620 | /* Information on uploaded vertex buffers: | ||
621 | */ | ||
622 | struct { | ||
623 | unsigned stride; /* in bytes between successive vertices */ | ||
624 | unsigned offset; /* in bytes, of first vertex in bo */ | ||
625 | unsigned vertex_count; /* count of valid vertices which may be accessed */ | ||
626 | struct brw_winsys_buffer *bo; | ||
627 | } vb[PIPE_MAX_ATTRIBS]; | ||
628 | |||
629 | unsigned nr_vb; /* currently the same as curr.num_vertex_buffers */ | ||
630 | } vb; | ||
631 | |||
632 | struct { | ||
633 | /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */ | ||
634 | struct brw_winsys_buffer *bo; | ||
635 | unsigned int offset; | ||
636 | unsigned int size; | ||
637 | /* Offset to index buffer index to use in CMD_3D_PRIM so that we can | ||
638 | * avoid re-uploading the IB packet over and over if we're actually | ||
639 | * referencing the same index buffer. | ||
640 | */ | ||
641 | unsigned int start_vertex_offset; | ||
642 | } ib; | ||
643 | |||
644 | |||
645 | /* BRW_NEW_URB_ALLOCATIONS: | ||
646 | */ | ||
647 | struct { | ||
648 | GLuint vsize; /* vertex size plus header in urb registers */ | ||
649 | GLuint csize; /* constant buffer size in urb registers */ | ||
650 | GLuint sfsize; /* setup data size in urb registers */ | ||
651 | |||
652 | GLboolean constrained; | ||
653 | |||
654 | GLuint nr_vs_entries; | ||
655 | GLuint nr_gs_entries; | ||
656 | GLuint nr_clip_entries; | ||
657 | GLuint nr_sf_entries; | ||
658 | GLuint nr_cs_entries; | ||
659 | |||
660 | GLuint vs_start; | ||
661 | GLuint gs_start; | ||
662 | GLuint clip_start; | ||
663 | GLuint sf_start; | ||
664 | GLuint cs_start; | ||
665 | } urb; | ||
666 | |||
667 | |||
668 | /* BRW_NEW_CURBE_OFFSETS: | ||
669 | */ | ||
670 | struct { | ||
671 | GLuint wm_start; /**< pos of first wm const in CURBE buffer */ | ||
672 | GLuint wm_size; /**< number of float[4] consts, multiple of 16 */ | ||
673 | GLuint clip_start; | ||
674 | GLuint clip_size; | ||
675 | GLuint vs_start; | ||
676 | GLuint vs_size; | ||
677 | GLuint total_size; | ||
678 | |||
679 | struct brw_winsys_buffer *curbe_bo; | ||
680 | /** Offset within curbe_bo of space for current curbe entry */ | ||
681 | GLuint curbe_offset; | ||
682 | /** Offset within curbe_bo of space for next curbe entry */ | ||
683 | GLuint curbe_next_offset; | ||
684 | |||
685 | GLfloat *last_buf; | ||
686 | GLuint last_bufsz; | ||
687 | /** | ||
688 | * Whether we should create a new bo instead of reusing the old one | ||
689 | * (if we just dispatch the batch pointing at the old one. | ||
690 | */ | ||
691 | GLboolean need_new_bo; | ||
692 | } curbe; | ||
693 | |||
694 | struct { | ||
695 | struct brw_vs_prog_data *prog_data; | ||
696 | |||
697 | struct brw_winsys_buffer *prog_bo; | ||
698 | struct brw_winsys_buffer *state_bo; | ||
699 | |||
700 | /** Binding table of pointers to surf_bo entries */ | ||
701 | struct brw_winsys_buffer *bind_bo; | ||
702 | struct brw_winsys_buffer *surf_bo[BRW_VS_MAX_SURF]; | ||
703 | GLuint nr_surfaces; | ||
704 | } vs; | ||
705 | |||
706 | struct { | ||
707 | struct brw_gs_prog_data *prog_data; | ||
708 | |||
709 | GLboolean prog_active; | ||
710 | struct brw_winsys_buffer *prog_bo; | ||
711 | struct brw_winsys_buffer *state_bo; | ||
712 | } gs; | ||
713 | |||
714 | struct { | ||
715 | struct brw_clip_prog_data *prog_data; | ||
716 | |||
717 | struct brw_winsys_buffer *prog_bo; | ||
718 | struct brw_winsys_buffer *state_bo; | ||
719 | struct brw_winsys_buffer *vp_bo; | ||
720 | } clip; | ||
721 | |||
722 | |||
723 | struct { | ||
724 | struct brw_sf_prog_data *prog_data; | ||
725 | |||
726 | struct brw_winsys_buffer *prog_bo; | ||
727 | struct brw_winsys_buffer *state_bo; | ||
728 | struct brw_winsys_buffer *vp_bo; | ||
729 | } sf; | ||
730 | |||
731 | struct { | ||
732 | struct brw_wm_prog_data *prog_data; | ||
733 | struct brw_wm_compile *compile_data; | ||
734 | |||
735 | /** Input sizes, calculated from active vertex program. | ||
736 | * One bit per fragment program input attribute. | ||
737 | */ | ||
738 | /*GLbitfield input_size_masks[4];*/ | ||
739 | |||
740 | /** Array of surface default colors (texture border color) */ | ||
741 | struct brw_winsys_buffer *sdc_bo[BRW_MAX_TEX_UNIT]; | ||
742 | |||
743 | GLuint render_surf; | ||
744 | GLuint nr_surfaces; | ||
745 | |||
746 | GLuint max_threads; | ||
747 | struct brw_winsys_buffer *scratch_bo; | ||
748 | |||
749 | GLuint sampler_count; | ||
750 | struct brw_winsys_buffer *sampler_bo; | ||
751 | |||
752 | /** Binding table of pointers to surf_bo entries */ | ||
753 | struct brw_winsys_buffer *bind_bo; | ||
754 | struct brw_winsys_buffer *surf_bo[BRW_WM_MAX_SURF]; | ||
755 | |||
756 | struct brw_winsys_buffer *prog_bo; | ||
757 | struct brw_winsys_buffer *state_bo; | ||
758 | } wm; | ||
759 | |||
760 | |||
761 | struct { | ||
762 | struct brw_winsys_buffer *state_bo; | ||
763 | |||
764 | struct brw_cc_unit_state cc; | ||
765 | struct brw_winsys_reloc reloc[1]; | ||
766 | } cc; | ||
767 | |||
768 | struct { | ||
769 | struct brw_query_object active_head; | ||
770 | struct brw_winsys_buffer *bo; | ||
771 | int index; | ||
772 | GLboolean active; | ||
773 | int stats_wm; | ||
774 | } query; | ||
775 | |||
776 | struct { | ||
777 | unsigned always_emit_state:1; | ||
778 | unsigned always_flush_batch:1; | ||
779 | unsigned force_swtnl:1; | ||
780 | unsigned no_swtnl:1; | ||
781 | } flags; | ||
782 | |||
783 | /* Used to give every program string a unique id | ||
784 | */ | ||
785 | GLuint program_id; | ||
786 | }; | ||
787 | |||
788 | |||
789 | |||
790 | /*====================================================================== | ||
791 | * brw_queryobj.c | ||
792 | */ | ||
793 | void brw_init_query(struct brw_context *brw); | ||
794 | enum pipe_error brw_prepare_query_begin(struct brw_context *brw); | ||
795 | void brw_emit_query_begin(struct brw_context *brw); | ||
796 | void brw_emit_query_end(struct brw_context *brw); | ||
797 | |||
798 | /*====================================================================== | ||
799 | * brw_state_dump.c | ||
800 | */ | ||
801 | void brw_debug_batch(struct brw_context *intel); | ||
802 | |||
803 | |||
804 | /*====================================================================== | ||
805 | * brw_pipe_*.c | ||
806 | */ | ||
807 | void brw_pipe_blend_init( struct brw_context *brw ); | ||
808 | void brw_pipe_depth_stencil_init( struct brw_context *brw ); | ||
809 | void brw_pipe_framebuffer_init( struct brw_context *brw ); | ||
810 | void brw_pipe_flush_init( struct brw_context *brw ); | ||
811 | void brw_pipe_misc_init( struct brw_context *brw ); | ||
812 | void brw_pipe_query_init( struct brw_context *brw ); | ||
813 | void brw_pipe_rast_init( struct brw_context *brw ); | ||
814 | void brw_pipe_sampler_init( struct brw_context *brw ); | ||
815 | void brw_pipe_shader_init( struct brw_context *brw ); | ||
816 | void brw_pipe_vertex_init( struct brw_context *brw ); | ||
817 | void brw_pipe_clear_init( struct brw_context *brw ); | ||
818 | |||
819 | |||
820 | void brw_pipe_blend_cleanup( struct brw_context *brw ); | ||
821 | void brw_pipe_depth_stencil_cleanup( struct brw_context *brw ); | ||
822 | void brw_pipe_framebuffer_cleanup( struct brw_context *brw ); | ||
823 | void brw_pipe_flush_cleanup( struct brw_context *brw ); | ||
824 | void brw_pipe_misc_cleanup( struct brw_context *brw ); | ||
825 | void brw_pipe_query_cleanup( struct brw_context *brw ); | ||
826 | void brw_pipe_rast_cleanup( struct brw_context *brw ); | ||
827 | void brw_pipe_sampler_cleanup( struct brw_context *brw ); | ||
828 | void brw_pipe_shader_cleanup( struct brw_context *brw ); | ||
829 | void brw_pipe_vertex_cleanup( struct brw_context *brw ); | ||
830 | void brw_pipe_clear_cleanup( struct brw_context *brw ); | ||
831 | void brw_pipe_surface_init( struct brw_context *brw ); | ||
832 | |||
833 | void brw_hw_cc_init( struct brw_context *brw ); | ||
834 | void brw_hw_cc_cleanup( struct brw_context *brw ); | ||
835 | |||
836 | |||
837 | |||
838 | void brw_context_flush( struct brw_context *brw ); | ||
839 | |||
840 | |||
841 | /* brw_urb.c | ||
842 | */ | ||
843 | int brw_upload_urb_fence(struct brw_context *brw); | ||
844 | |||
845 | /* brw_curbe.c | ||
846 | */ | ||
847 | int brw_upload_cs_urb_state(struct brw_context *brw); | ||
848 | |||
849 | /* brw_context.c | ||
850 | */ | ||
851 | struct pipe_context *brw_create_context(struct pipe_screen *screen, | ||
852 | void *priv); | ||
853 | |||
854 | /*====================================================================== | ||
855 | * Inline conversion functions. These are better-typed than the | ||
856 | * macros used previously: | ||
857 | */ | ||
858 | static INLINE struct brw_context * | ||
859 | brw_context( struct pipe_context *ctx ) | ||
860 | { | ||
861 | return (struct brw_context *)ctx; | ||
862 | } | ||
863 | |||
864 | #endif | ||
865 | |||
diff --git a/src/gallium/drivers/i965/brw_curbe.c b/src/gallium/drivers/i965/brw_curbe.c deleted file mode 100644 index a701de33f5d..00000000000 --- a/src/gallium/drivers/i965/brw_curbe.c +++ /dev/null | |||
@@ -1,382 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_memory.h" | ||
33 | #include "util/u_math.h" | ||
34 | |||
35 | #include "brw_batchbuffer.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_defines.h" | ||
38 | #include "brw_state.h" | ||
39 | #include "brw_debug.h" | ||
40 | |||
41 | |||
42 | /** | ||
43 | * Partition the CURBE between the various users of constant values: | ||
44 | * Note that vertex and fragment shaders can now fetch constants out | ||
45 | * of constant buffers. We no longer allocatea block of the GRF for | ||
46 | * constants. That greatly reduces the demand for space in the CURBE. | ||
47 | * Some of the comments within are dated... | ||
48 | */ | ||
49 | static int calculate_curbe_offsets( struct brw_context *brw ) | ||
50 | { | ||
51 | /* CACHE_NEW_WM_PROG */ | ||
52 | const GLuint nr_fp_regs = brw->wm.prog_data->curb_read_length; | ||
53 | |||
54 | /* BRW_NEW_VERTEX_PROGRAM */ | ||
55 | const GLuint nr_vp_regs = brw->vs.prog_data->curb_read_length; | ||
56 | GLuint nr_clip_regs = 0; | ||
57 | GLuint total_regs; | ||
58 | |||
59 | /* PIPE_NEW_CLIP */ | ||
60 | if (brw->curr.ucp.nr) { | ||
61 | GLuint nr_planes = 6 + brw->curr.ucp.nr; | ||
62 | nr_clip_regs = (nr_planes * 4 + 15) / 16; | ||
63 | } | ||
64 | |||
65 | |||
66 | total_regs = nr_fp_regs + nr_vp_regs + nr_clip_regs; | ||
67 | |||
68 | /* When this is > 32, want to use a true constant buffer to hold | ||
69 | * the extra constants. | ||
70 | */ | ||
71 | assert(total_regs <= 32); | ||
72 | |||
73 | /* Lazy resize: | ||
74 | */ | ||
75 | if (nr_fp_regs > brw->curbe.wm_size || | ||
76 | nr_vp_regs > brw->curbe.vs_size || | ||
77 | nr_clip_regs != brw->curbe.clip_size || | ||
78 | (total_regs < brw->curbe.total_size / 4 && | ||
79 | brw->curbe.total_size > 16)) { | ||
80 | |||
81 | GLuint reg = 0; | ||
82 | |||
83 | /* Calculate a new layout: | ||
84 | */ | ||
85 | reg = 0; | ||
86 | brw->curbe.wm_start = reg; | ||
87 | brw->curbe.wm_size = nr_fp_regs; reg += nr_fp_regs; | ||
88 | brw->curbe.clip_start = reg; | ||
89 | brw->curbe.clip_size = nr_clip_regs; reg += nr_clip_regs; | ||
90 | brw->curbe.vs_start = reg; | ||
91 | brw->curbe.vs_size = nr_vp_regs; reg += nr_vp_regs; | ||
92 | brw->curbe.total_size = reg; | ||
93 | |||
94 | if (BRW_DEBUG & DEBUG_CURBE) | ||
95 | debug_printf("curbe wm %d+%d clip %d+%d vs %d+%d\n", | ||
96 | brw->curbe.wm_start, | ||
97 | brw->curbe.wm_size, | ||
98 | brw->curbe.clip_start, | ||
99 | brw->curbe.clip_size, | ||
100 | brw->curbe.vs_start, | ||
101 | brw->curbe.vs_size ); | ||
102 | |||
103 | brw->state.dirty.brw |= BRW_NEW_CURBE_OFFSETS; | ||
104 | } | ||
105 | |||
106 | return 0; | ||
107 | } | ||
108 | |||
109 | |||
110 | const struct brw_tracked_state brw_curbe_offsets = { | ||
111 | .dirty = { | ||
112 | .mesa = PIPE_NEW_CLIP, | ||
113 | .brw = BRW_NEW_VERTEX_PROGRAM, | ||
114 | .cache = CACHE_NEW_WM_PROG | ||
115 | }, | ||
116 | .prepare = calculate_curbe_offsets | ||
117 | }; | ||
118 | |||
119 | |||
120 | |||
121 | |||
122 | /* Define the number of curbes within CS's urb allocation. Multiple | ||
123 | * urb entries -> multiple curbes. These will be used by | ||
124 | * fixed-function hardware in a double-buffering scheme to avoid a | ||
125 | * pipeline stall each time the contents of the curbe is changed. | ||
126 | */ | ||
127 | int brw_upload_cs_urb_state(struct brw_context *brw) | ||
128 | { | ||
129 | struct brw_cs_urb_state cs_urb; | ||
130 | memset(&cs_urb, 0, sizeof(cs_urb)); | ||
131 | |||
132 | /* It appears that this is the state packet for the CS unit, ie. the | ||
133 | * urb entries detailed here are housed in the CS range from the | ||
134 | * URB_FENCE command. | ||
135 | */ | ||
136 | cs_urb.header.opcode = CMD_CS_URB_STATE; | ||
137 | cs_urb.header.length = sizeof(cs_urb)/4 - 2; | ||
138 | |||
139 | /* BRW_NEW_URB_FENCE */ | ||
140 | cs_urb.bits0.nr_urb_entries = brw->urb.nr_cs_entries; | ||
141 | cs_urb.bits0.urb_entry_size = brw->urb.csize - 1; | ||
142 | |||
143 | assert(brw->urb.nr_cs_entries); | ||
144 | BRW_CACHED_BATCH_STRUCT(brw, &cs_urb); | ||
145 | return 0; | ||
146 | } | ||
147 | |||
148 | static GLfloat fixed_plane[6][4] = { | ||
149 | { 0, 0, -1, 1 }, | ||
150 | { 0, 0, 1, 1 }, | ||
151 | { 0, -1, 0, 1 }, | ||
152 | { 0, 1, 0, 1 }, | ||
153 | {-1, 0, 0, 1 }, | ||
154 | { 1, 0, 0, 1 } | ||
155 | }; | ||
156 | |||
157 | /* Upload a new set of constants. Too much variability to go into the | ||
158 | * cache mechanism, but maybe would benefit from a comparison against | ||
159 | * the current uploaded set of constants. | ||
160 | */ | ||
161 | static enum pipe_error prepare_curbe_buffer(struct brw_context *brw) | ||
162 | { | ||
163 | const GLuint sz = brw->curbe.total_size; | ||
164 | const GLuint bufsz = sz * 16 * sizeof(GLfloat); | ||
165 | enum pipe_error ret; | ||
166 | GLfloat *buf; | ||
167 | GLuint i; | ||
168 | |||
169 | if (sz == 0) { | ||
170 | if (brw->curbe.last_buf) { | ||
171 | FREE(brw->curbe.last_buf); | ||
172 | brw->curbe.last_buf = NULL; | ||
173 | brw->curbe.last_bufsz = 0; | ||
174 | } | ||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | buf = (GLfloat *) CALLOC(bufsz, 1); | ||
179 | |||
180 | /* fragment shader constants */ | ||
181 | if (brw->curbe.wm_size) { | ||
182 | const struct brw_fragment_shader *fs = brw->curr.fragment_shader; | ||
183 | GLuint offset = brw->curbe.wm_start * 16; | ||
184 | GLuint nr_immediate, nr_const; | ||
185 | |||
186 | nr_immediate = fs->immediates.nr; | ||
187 | if (nr_immediate) { | ||
188 | memcpy(&buf[offset], | ||
189 | fs->immediates.data, | ||
190 | nr_immediate * 4 * sizeof(float)); | ||
191 | |||
192 | offset += nr_immediate * 4; | ||
193 | } | ||
194 | |||
195 | nr_const = fs->info.file_max[TGSI_FILE_CONSTANT] + 1; | ||
196 | /* nr_const = brw->wm.prog_data->nr_params; */ | ||
197 | if (nr_const) { | ||
198 | pipe_buffer_read( &brw->base, | ||
199 | brw->curr.fragment_constants, | ||
200 | 0, | ||
201 | nr_const * 4 * sizeof(float), | ||
202 | &buf[offset]); | ||
203 | } | ||
204 | } | ||
205 | |||
206 | |||
207 | /* The clipplanes are actually delivered to both CLIP and VS units. | ||
208 | * VS uses them to calculate the outcode bitmasks. | ||
209 | */ | ||
210 | if (brw->curbe.clip_size) { | ||
211 | GLuint offset = brw->curbe.clip_start * 16; | ||
212 | GLuint j; | ||
213 | |||
214 | /* If any planes are going this way, send them all this way: | ||
215 | */ | ||
216 | for (i = 0; i < 6; i++) { | ||
217 | buf[offset + i * 4 + 0] = fixed_plane[i][0]; | ||
218 | buf[offset + i * 4 + 1] = fixed_plane[i][1]; | ||
219 | buf[offset + i * 4 + 2] = fixed_plane[i][2]; | ||
220 | buf[offset + i * 4 + 3] = fixed_plane[i][3]; | ||
221 | } | ||
222 | |||
223 | /* Clip planes: | ||
224 | */ | ||
225 | assert(brw->curr.ucp.nr <= 6); | ||
226 | for (j = 0; j < brw->curr.ucp.nr; j++) { | ||
227 | buf[offset + i * 4 + 0] = brw->curr.ucp.ucp[j][0]; | ||
228 | buf[offset + i * 4 + 1] = brw->curr.ucp.ucp[j][1]; | ||
229 | buf[offset + i * 4 + 2] = brw->curr.ucp.ucp[j][2]; | ||
230 | buf[offset + i * 4 + 3] = brw->curr.ucp.ucp[j][3]; | ||
231 | i++; | ||
232 | } | ||
233 | } | ||
234 | |||
235 | /* vertex shader constants */ | ||
236 | if (brw->curbe.vs_size) { | ||
237 | GLuint offset = brw->curbe.vs_start * 16; | ||
238 | const struct brw_vertex_shader *vs = brw->curr.vertex_shader; | ||
239 | GLuint nr_immediate, nr_const; | ||
240 | |||
241 | nr_immediate = vs->immediates.nr; | ||
242 | if (nr_immediate) { | ||
243 | memcpy(&buf[offset], | ||
244 | vs->immediates.data, | ||
245 | nr_immediate * 4 * sizeof(float)); | ||
246 | |||
247 | offset += nr_immediate * 4; | ||
248 | } | ||
249 | |||
250 | nr_const = vs->info.file_max[TGSI_FILE_CONSTANT] + 1; | ||
251 | if (nr_const) { | ||
252 | /* XXX: note that constant buffers are currently *already* in | ||
253 | * buffer objects. If we want to keep on putting them into the | ||
254 | * curbe, makes sense to treat constbuf's specially with malloc. | ||
255 | */ | ||
256 | |||
257 | /* XXX: what if user's constant buffer is too small? | ||
258 | */ | ||
259 | pipe_buffer_read(&brw->base, | ||
260 | brw->curr.vertex_constants, | ||
261 | 0, | ||
262 | nr_const * 4 * sizeof(float), | ||
263 | &buf[offset]); | ||
264 | } | ||
265 | } | ||
266 | |||
267 | if (BRW_DEBUG & DEBUG_CURBE) { | ||
268 | for (i = 0; i < sz*16; i+=4) | ||
269 | debug_printf("curbe %d.%d: %f %f %f %f\n", i/8, i&4, | ||
270 | buf[i+0], buf[i+1], buf[i+2], buf[i+3]); | ||
271 | |||
272 | debug_printf("last_buf %p buf %p sz %d/%d cmp %d\n", | ||
273 | (void *)brw->curbe.last_buf, (void *)buf, | ||
274 | bufsz, brw->curbe.last_bufsz, | ||
275 | brw->curbe.last_buf ? memcmp(buf, brw->curbe.last_buf, bufsz) : -1); | ||
276 | } | ||
277 | |||
278 | if (brw->curbe.curbe_bo != NULL && | ||
279 | brw->curbe.last_buf && | ||
280 | bufsz == brw->curbe.last_bufsz && | ||
281 | memcmp(buf, brw->curbe.last_buf, bufsz) == 0) { | ||
282 | /* constants have not changed */ | ||
283 | FREE(buf); | ||
284 | } | ||
285 | else { | ||
286 | /* constants have changed */ | ||
287 | FREE(brw->curbe.last_buf); | ||
288 | |||
289 | brw->curbe.last_buf = buf; | ||
290 | brw->curbe.last_bufsz = bufsz; | ||
291 | |||
292 | if (brw->curbe.curbe_bo != NULL && | ||
293 | (brw->curbe.need_new_bo || | ||
294 | brw->curbe.curbe_next_offset + bufsz > brw->curbe.curbe_bo->size)) | ||
295 | { | ||
296 | bo_reference(&brw->curbe.curbe_bo, NULL); | ||
297 | } | ||
298 | |||
299 | if (brw->curbe.curbe_bo == NULL) { | ||
300 | /* Allocate a single page for CURBE entries for this | ||
301 | * batchbuffer. They're generally around 64b. We will | ||
302 | * discard the curbe buffer after the batch is flushed to | ||
303 | * avoid synchronous updates. | ||
304 | */ | ||
305 | ret = brw->sws->bo_alloc(brw->sws, | ||
306 | BRW_BUFFER_TYPE_CURBE, | ||
307 | 4096, 1 << 6, | ||
308 | &brw->curbe.curbe_bo); | ||
309 | if (ret) | ||
310 | return ret; | ||
311 | |||
312 | brw->curbe.curbe_next_offset = 0; | ||
313 | } | ||
314 | |||
315 | brw->curbe.curbe_offset = brw->curbe.curbe_next_offset; | ||
316 | brw->curbe.curbe_next_offset += bufsz; | ||
317 | brw->curbe.curbe_next_offset = align(brw->curbe.curbe_next_offset, 64); | ||
318 | |||
319 | /* Copy data to the buffer: | ||
320 | */ | ||
321 | brw->sws->bo_subdata(brw->curbe.curbe_bo, | ||
322 | BRW_DATA_CONSTANT_BUFFER, | ||
323 | brw->curbe.curbe_offset, | ||
324 | bufsz, | ||
325 | buf, | ||
326 | NULL, 0); | ||
327 | } | ||
328 | |||
329 | brw_add_validated_bo(brw, brw->curbe.curbe_bo); | ||
330 | |||
331 | /* Because this provokes an action (ie copy the constants into the | ||
332 | * URB), it shouldn't be shortcircuited if identical to the | ||
333 | * previous time - because eg. the urb destination may have | ||
334 | * changed, or the urb contents different to last time. | ||
335 | * | ||
336 | * Note that the data referred to is actually copied internally, | ||
337 | * not just used in place according to passed pointer. | ||
338 | * | ||
339 | * It appears that the CS unit takes care of using each available | ||
340 | * URB entry (Const URB Entry == CURBE) in turn, and issuing | ||
341 | * flushes as necessary when doublebuffering of CURBEs isn't | ||
342 | * possible. | ||
343 | */ | ||
344 | |||
345 | return 0; | ||
346 | } | ||
347 | |||
348 | static enum pipe_error emit_curbe_buffer(struct brw_context *brw) | ||
349 | { | ||
350 | GLuint sz = brw->curbe.total_size; | ||
351 | |||
352 | BEGIN_BATCH(2, IGNORE_CLIPRECTS); | ||
353 | if (sz == 0) { | ||
354 | OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); | ||
355 | OUT_BATCH(0); | ||
356 | } else { | ||
357 | OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2)); | ||
358 | OUT_RELOC(brw->curbe.curbe_bo, | ||
359 | BRW_USAGE_STATE, | ||
360 | (sz - 1) + brw->curbe.curbe_offset); | ||
361 | } | ||
362 | ADVANCE_BATCH(); | ||
363 | return 0; | ||
364 | } | ||
365 | |||
366 | const struct brw_tracked_state brw_curbe_buffer = { | ||
367 | .dirty = { | ||
368 | .mesa = (PIPE_NEW_FRAGMENT_CONSTANTS | | ||
369 | PIPE_NEW_VERTEX_CONSTANTS | | ||
370 | PIPE_NEW_CLIP), | ||
371 | .brw = (BRW_NEW_FRAGMENT_PROGRAM | | ||
372 | BRW_NEW_VERTEX_PROGRAM | | ||
373 | BRW_NEW_URB_FENCE | /* Implicit - hardware requires this, not used above */ | ||
374 | BRW_NEW_PSP | /* Implicit - hardware requires this, not used above */ | ||
375 | BRW_NEW_CURBE_OFFSETS | | ||
376 | BRW_NEW_BATCH), | ||
377 | .cache = (CACHE_NEW_WM_PROG) | ||
378 | }, | ||
379 | .prepare = prepare_curbe_buffer, | ||
380 | .emit = emit_curbe_buffer, | ||
381 | }; | ||
382 | |||
diff --git a/src/gallium/drivers/i965/brw_debug.h b/src/gallium/drivers/i965/brw_debug.h deleted file mode 100644 index ae8e9254a68..00000000000 --- a/src/gallium/drivers/i965/brw_debug.h +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | #ifndef BRW_DEBUG_H | ||
2 | #define BRW_DEBUG_H | ||
3 | |||
4 | /* ================================================================ | ||
5 | * Debugging: | ||
6 | */ | ||
7 | |||
8 | #define DEBUG_TEXTURE 0x1 | ||
9 | #define DEBUG_STATE 0x2 | ||
10 | #define DEBUG_IOCTL 0x4 | ||
11 | #define DEBUG_BLIT 0x8 | ||
12 | #define DEBUG_CURBE 0x10 | ||
13 | #define DEBUG_FALLBACKS 0x20 | ||
14 | #define DEBUG_VERBOSE 0x40 | ||
15 | #define DEBUG_BATCH 0x80 | ||
16 | #define DEBUG_PIXEL 0x100 | ||
17 | #define DEBUG_WINSYS 0x200 | ||
18 | #define DEBUG_MIN_URB 0x400 | ||
19 | #define DEBUG_DISASSEM 0x800 | ||
20 | #define DEBUG_unused3 0x1000 | ||
21 | #define DEBUG_SYNC 0x2000 | ||
22 | #define DEBUG_PRIMS 0x4000 | ||
23 | #define DEBUG_VERTS 0x8000 | ||
24 | #define DEBUG_unused4 0x10000 | ||
25 | #define DEBUG_DMA 0x20000 | ||
26 | #define DEBUG_SANITY 0x40000 | ||
27 | #define DEBUG_SLEEP 0x80000 | ||
28 | #define DEBUG_STATS 0x100000 | ||
29 | #define DEBUG_unused5 0x200000 | ||
30 | #define DEBUG_SINGLE_THREAD 0x400000 | ||
31 | #define DEBUG_WM 0x800000 | ||
32 | #define DEBUG_URB 0x1000000 | ||
33 | #define DEBUG_VS 0x2000000 | ||
34 | |||
35 | #ifdef DEBUG | ||
36 | extern int BRW_DEBUG; | ||
37 | #else | ||
38 | #define BRW_DEBUG 0 | ||
39 | #endif | ||
40 | |||
41 | |||
42 | |||
43 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_defines.h b/src/gallium/drivers/i965/brw_defines.h deleted file mode 100644 index 7547eae97c7..00000000000 --- a/src/gallium/drivers/i965/brw_defines.h +++ /dev/null | |||
@@ -1,1166 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_DEFINES_H | ||
34 | #define BRW_DEFINES_H | ||
35 | |||
36 | /* 3D state: | ||
37 | */ | ||
38 | #define _3DOP_3DSTATE_PIPELINED 0x0 | ||
39 | #define _3DOP_3DSTATE_NONPIPELINED 0x1 | ||
40 | #define _3DOP_3DCONTROL 0x2 | ||
41 | #define _3DOP_3DPRIMITIVE 0x3 | ||
42 | |||
43 | #define _3DSTATE_PIPELINED_POINTERS 0x00 | ||
44 | #define _3DSTATE_BINDING_TABLE_POINTERS 0x01 | ||
45 | #define _3DSTATE_VERTEX_BUFFERS 0x08 | ||
46 | #define _3DSTATE_VERTEX_ELEMENTS 0x09 | ||
47 | #define _3DSTATE_INDEX_BUFFER 0x0A | ||
48 | #define _3DSTATE_VF_STATISTICS 0x0B | ||
49 | #define _3DSTATE_DRAWING_RECTANGLE 0x00 | ||
50 | #define _3DSTATE_CONSTANT_COLOR 0x01 | ||
51 | #define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 | ||
52 | #define _3DSTATE_CHROMA_KEY 0x04 | ||
53 | #define _3DSTATE_DEPTH_BUFFER 0x05 | ||
54 | #define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 | ||
55 | #define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 | ||
56 | #define _3DSTATE_LINE_STIPPLE 0x08 | ||
57 | #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 | ||
58 | #define _3DCONTROL 0x00 | ||
59 | |||
60 | #define PIPE_CONTROL_NOWRITE 0x00 | ||
61 | #define PIPE_CONTROL_WRITEIMMEDIATE 0x01 | ||
62 | #define PIPE_CONTROL_WRITEDEPTH 0x02 | ||
63 | #define PIPE_CONTROL_WRITETIMESTAMP 0x03 | ||
64 | |||
65 | #define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 | ||
66 | #define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 | ||
67 | |||
68 | #define _3DPRIM_POINTLIST 0x01 | ||
69 | #define _3DPRIM_LINELIST 0x02 | ||
70 | #define _3DPRIM_LINESTRIP 0x03 | ||
71 | #define _3DPRIM_TRILIST 0x04 | ||
72 | #define _3DPRIM_TRISTRIP 0x05 | ||
73 | #define _3DPRIM_TRIFAN 0x06 | ||
74 | #define _3DPRIM_QUADLIST 0x07 | ||
75 | #define _3DPRIM_QUADSTRIP 0x08 | ||
76 | #define _3DPRIM_LINELIST_ADJ 0x09 | ||
77 | #define _3DPRIM_LINESTRIP_ADJ 0x0A | ||
78 | #define _3DPRIM_TRILIST_ADJ 0x0B | ||
79 | #define _3DPRIM_TRISTRIP_ADJ 0x0C | ||
80 | #define _3DPRIM_TRISTRIP_REVERSE 0x0D | ||
81 | #define _3DPRIM_POLYGON 0x0E | ||
82 | #define _3DPRIM_RECTLIST 0x0F | ||
83 | #define _3DPRIM_LINELOOP 0x10 | ||
84 | #define _3DPRIM_POINTLIST_BF 0x11 | ||
85 | #define _3DPRIM_LINESTRIP_CONT 0x12 | ||
86 | #define _3DPRIM_LINESTRIP_BF 0x13 | ||
87 | #define _3DPRIM_LINESTRIP_CONT_BF 0x14 | ||
88 | #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 | ||
89 | |||
90 | #define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 | ||
91 | #define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 | ||
92 | |||
93 | #define BRW_ANISORATIO_2 0 | ||
94 | #define BRW_ANISORATIO_4 1 | ||
95 | #define BRW_ANISORATIO_6 2 | ||
96 | #define BRW_ANISORATIO_8 3 | ||
97 | #define BRW_ANISORATIO_10 4 | ||
98 | #define BRW_ANISORATIO_12 5 | ||
99 | #define BRW_ANISORATIO_14 6 | ||
100 | #define BRW_ANISORATIO_16 7 | ||
101 | |||
102 | #define BRW_BLENDFACTOR_ONE 0x1 | ||
103 | #define BRW_BLENDFACTOR_SRC_COLOR 0x2 | ||
104 | #define BRW_BLENDFACTOR_SRC_ALPHA 0x3 | ||
105 | #define BRW_BLENDFACTOR_DST_ALPHA 0x4 | ||
106 | #define BRW_BLENDFACTOR_DST_COLOR 0x5 | ||
107 | #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 | ||
108 | #define BRW_BLENDFACTOR_CONST_COLOR 0x7 | ||
109 | #define BRW_BLENDFACTOR_CONST_ALPHA 0x8 | ||
110 | #define BRW_BLENDFACTOR_SRC1_COLOR 0x9 | ||
111 | #define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A | ||
112 | #define BRW_BLENDFACTOR_ZERO 0x11 | ||
113 | #define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 | ||
114 | #define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 | ||
115 | #define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 | ||
116 | #define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 | ||
117 | #define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 | ||
118 | #define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 | ||
119 | #define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 | ||
120 | #define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A | ||
121 | |||
122 | #define BRW_BLENDFUNCTION_ADD 0 | ||
123 | #define BRW_BLENDFUNCTION_SUBTRACT 1 | ||
124 | #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 | ||
125 | #define BRW_BLENDFUNCTION_MIN 3 | ||
126 | #define BRW_BLENDFUNCTION_MAX 4 | ||
127 | |||
128 | #define BRW_ALPHATEST_FORMAT_UNORM8 0 | ||
129 | #define BRW_ALPHATEST_FORMAT_FLOAT32 1 | ||
130 | |||
131 | #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 | ||
132 | #define BRW_CHROMAKEY_REPLACE_BLACK 1 | ||
133 | |||
134 | #define BRW_CLIP_API_OGL 0 | ||
135 | #define BRW_CLIP_API_DX 1 | ||
136 | |||
137 | #define BRW_CLIPMODE_NORMAL 0 | ||
138 | #define BRW_CLIPMODE_CLIP_ALL 1 | ||
139 | #define BRW_CLIPMODE_CLIP_NON_REJECTED 2 | ||
140 | #define BRW_CLIPMODE_REJECT_ALL 3 | ||
141 | #define BRW_CLIPMODE_ACCEPT_ALL 4 | ||
142 | #define BRW_CLIPMODE_KERNEL_CLIP 5 | ||
143 | |||
144 | #define BRW_CLIP_NDCSPACE 0 | ||
145 | #define BRW_CLIP_SCREENSPACE 1 | ||
146 | |||
147 | #define BRW_COMPAREFUNCTION_ALWAYS 0 | ||
148 | #define BRW_COMPAREFUNCTION_NEVER 1 | ||
149 | #define BRW_COMPAREFUNCTION_LESS 2 | ||
150 | #define BRW_COMPAREFUNCTION_EQUAL 3 | ||
151 | #define BRW_COMPAREFUNCTION_LEQUAL 4 | ||
152 | #define BRW_COMPAREFUNCTION_GREATER 5 | ||
153 | #define BRW_COMPAREFUNCTION_NOTEQUAL 6 | ||
154 | #define BRW_COMPAREFUNCTION_GEQUAL 7 | ||
155 | |||
156 | #define BRW_COVERAGE_PIXELS_HALF 0 | ||
157 | #define BRW_COVERAGE_PIXELS_1 1 | ||
158 | #define BRW_COVERAGE_PIXELS_2 2 | ||
159 | #define BRW_COVERAGE_PIXELS_4 3 | ||
160 | |||
161 | #define BRW_CULLMODE_BOTH 0 | ||
162 | #define BRW_CULLMODE_NONE 1 | ||
163 | #define BRW_CULLMODE_FRONT 2 | ||
164 | #define BRW_CULLMODE_BACK 3 | ||
165 | |||
166 | #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 | ||
167 | #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 | ||
168 | |||
169 | #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 | ||
170 | #define BRW_DEPTHFORMAT_D32_FLOAT 1 | ||
171 | #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 | ||
172 | #define BRW_DEPTHFORMAT_D16_UNORM 5 | ||
173 | |||
174 | #define BRW_FLOATING_POINT_IEEE_754 0 | ||
175 | #define BRW_FLOATING_POINT_NON_IEEE_754 1 | ||
176 | |||
177 | #define BRW_FRONTWINDING_CW 0 | ||
178 | #define BRW_FRONTWINDING_CCW 1 | ||
179 | |||
180 | #define BRW_SPRITE_POINT_ENABLE 16 | ||
181 | |||
182 | #define BRW_INDEX_BYTE 0 | ||
183 | #define BRW_INDEX_WORD 1 | ||
184 | #define BRW_INDEX_DWORD 2 | ||
185 | |||
186 | #define BRW_LOGICOPFUNCTION_CLEAR 0 | ||
187 | #define BRW_LOGICOPFUNCTION_NOR 1 | ||
188 | #define BRW_LOGICOPFUNCTION_AND_INVERTED 2 | ||
189 | #define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 | ||
190 | #define BRW_LOGICOPFUNCTION_AND_REVERSE 4 | ||
191 | #define BRW_LOGICOPFUNCTION_INVERT 5 | ||
192 | #define BRW_LOGICOPFUNCTION_XOR 6 | ||
193 | #define BRW_LOGICOPFUNCTION_NAND 7 | ||
194 | #define BRW_LOGICOPFUNCTION_AND 8 | ||
195 | #define BRW_LOGICOPFUNCTION_EQUIV 9 | ||
196 | #define BRW_LOGICOPFUNCTION_NOOP 10 | ||
197 | #define BRW_LOGICOPFUNCTION_OR_INVERTED 11 | ||
198 | #define BRW_LOGICOPFUNCTION_COPY 12 | ||
199 | #define BRW_LOGICOPFUNCTION_OR_REVERSE 13 | ||
200 | #define BRW_LOGICOPFUNCTION_OR 14 | ||
201 | #define BRW_LOGICOPFUNCTION_SET 15 | ||
202 | |||
203 | #define BRW_MAPFILTER_NEAREST 0x0 | ||
204 | #define BRW_MAPFILTER_LINEAR 0x1 | ||
205 | #define BRW_MAPFILTER_ANISOTROPIC 0x2 | ||
206 | |||
207 | #define BRW_MIPFILTER_NONE 0 | ||
208 | #define BRW_MIPFILTER_NEAREST 1 | ||
209 | #define BRW_MIPFILTER_LINEAR 3 | ||
210 | |||
211 | #define BRW_POLYGON_FRONT_FACING 0 | ||
212 | #define BRW_POLYGON_BACK_FACING 1 | ||
213 | |||
214 | #define BRW_PREFILTER_ALWAYS 0x0 | ||
215 | #define BRW_PREFILTER_NEVER 0x1 | ||
216 | #define BRW_PREFILTER_LESS 0x2 | ||
217 | #define BRW_PREFILTER_EQUAL 0x3 | ||
218 | #define BRW_PREFILTER_LEQUAL 0x4 | ||
219 | #define BRW_PREFILTER_GREATER 0x5 | ||
220 | #define BRW_PREFILTER_NOTEQUAL 0x6 | ||
221 | #define BRW_PREFILTER_GEQUAL 0x7 | ||
222 | |||
223 | #define BRW_PROVOKING_VERTEX_0 0 | ||
224 | #define BRW_PROVOKING_VERTEX_1 1 | ||
225 | #define BRW_PROVOKING_VERTEX_2 2 | ||
226 | |||
227 | #define BRW_RASTRULE_UPPER_LEFT 0 | ||
228 | #define BRW_RASTRULE_UPPER_RIGHT 1 | ||
229 | /* These are listed as "Reserved, but not seen as useful" | ||
230 | * in Intel documentation (page 212, "Point Rasterization Rule", | ||
231 | * section 7.4 "SF Pipeline State Summary", of document | ||
232 | * "Intel® 965 Express Chipset Family and Intel® G35 Express | ||
233 | * Chipset Graphics Controller Programmer's Reference Manual, | ||
234 | * Volume 2: 3D/Media", Revision 1.0b as of January 2008, | ||
235 | * available at | ||
236 | * http://intellinuxgraphics.org/documentation.html | ||
237 | * at the time of this writing). | ||
238 | * | ||
239 | * These appear to be supported on at least some | ||
240 | * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT | ||
241 | * is useful when using OpenGL to render to a FBO | ||
242 | * (which has the pixel coordinate Y orientation inverted | ||
243 | * with respect to the normal OpenGL pixel coordinate system). | ||
244 | */ | ||
245 | #define BRW_RASTRULE_LOWER_LEFT 2 | ||
246 | #define BRW_RASTRULE_LOWER_RIGHT 3 | ||
247 | |||
248 | #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 | ||
249 | #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 | ||
250 | #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 | ||
251 | |||
252 | #define BRW_STENCILOP_KEEP 0 | ||
253 | #define BRW_STENCILOP_ZERO 1 | ||
254 | #define BRW_STENCILOP_REPLACE 2 | ||
255 | #define BRW_STENCILOP_INCRSAT 3 | ||
256 | #define BRW_STENCILOP_DECRSAT 4 | ||
257 | #define BRW_STENCILOP_INCR 5 | ||
258 | #define BRW_STENCILOP_DECR 6 | ||
259 | #define BRW_STENCILOP_INVERT 7 | ||
260 | |||
261 | #define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 | ||
262 | #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 | ||
263 | |||
264 | #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 | ||
265 | #define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 | ||
266 | #define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 | ||
267 | #define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 | ||
268 | #define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 | ||
269 | #define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 | ||
270 | #define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 | ||
271 | #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 | ||
272 | #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 | ||
273 | #define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 | ||
274 | #define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 | ||
275 | #define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 | ||
276 | #define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 | ||
277 | #define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 | ||
278 | #define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 | ||
279 | #define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 | ||
280 | #define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 | ||
281 | #define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 | ||
282 | #define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 | ||
283 | #define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 | ||
284 | #define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 | ||
285 | #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 | ||
286 | #define BRW_SURFACEFORMAT_R32G32_SINT 0x086 | ||
287 | #define BRW_SURFACEFORMAT_R32G32_UINT 0x087 | ||
288 | #define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 | ||
289 | #define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 | ||
290 | #define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A | ||
291 | #define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B | ||
292 | #define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C | ||
293 | #define BRW_SURFACEFORMAT_R64_FLOAT 0x08D | ||
294 | #define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E | ||
295 | #define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F | ||
296 | #define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 | ||
297 | #define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 | ||
298 | #define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 | ||
299 | #define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 | ||
300 | #define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 | ||
301 | #define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 | ||
302 | #define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 | ||
303 | #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 | ||
304 | #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 | ||
305 | #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 | ||
306 | #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 | ||
307 | #define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 | ||
308 | #define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 | ||
309 | #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 | ||
310 | #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 | ||
311 | #define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 | ||
312 | #define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA | ||
313 | #define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB | ||
314 | #define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC | ||
315 | #define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD | ||
316 | #define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE | ||
317 | #define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF | ||
318 | #define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 | ||
319 | #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 | ||
320 | #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 | ||
321 | #define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 | ||
322 | #define BRW_SURFACEFORMAT_R32_SINT 0x0D6 | ||
323 | #define BRW_SURFACEFORMAT_R32_UINT 0x0D7 | ||
324 | #define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 | ||
325 | #define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 | ||
326 | #define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA | ||
327 | #define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF | ||
328 | #define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 | ||
329 | #define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 | ||
330 | #define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 | ||
331 | #define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 | ||
332 | #define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 | ||
333 | #define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 | ||
334 | #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 | ||
335 | #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA | ||
336 | #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB | ||
337 | #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC | ||
338 | #define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED | ||
339 | #define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE | ||
340 | #define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 | ||
341 | #define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 | ||
342 | #define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 | ||
343 | #define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 | ||
344 | #define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 | ||
345 | #define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 | ||
346 | #define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 | ||
347 | #define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 | ||
348 | #define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 | ||
349 | #define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 | ||
350 | #define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 | ||
351 | #define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 | ||
352 | #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 | ||
353 | #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 | ||
354 | #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 | ||
355 | #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 | ||
356 | #define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 | ||
357 | #define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 | ||
358 | #define BRW_SURFACEFORMAT_R8G8_SINT 0x108 | ||
359 | #define BRW_SURFACEFORMAT_R8G8_UINT 0x109 | ||
360 | #define BRW_SURFACEFORMAT_R16_UNORM 0x10A | ||
361 | #define BRW_SURFACEFORMAT_R16_SNORM 0x10B | ||
362 | #define BRW_SURFACEFORMAT_R16_SINT 0x10C | ||
363 | #define BRW_SURFACEFORMAT_R16_UINT 0x10D | ||
364 | #define BRW_SURFACEFORMAT_R16_FLOAT 0x10E | ||
365 | #define BRW_SURFACEFORMAT_I16_UNORM 0x111 | ||
366 | #define BRW_SURFACEFORMAT_L16_UNORM 0x112 | ||
367 | #define BRW_SURFACEFORMAT_A16_UNORM 0x113 | ||
368 | #define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 | ||
369 | #define BRW_SURFACEFORMAT_I16_FLOAT 0x115 | ||
370 | #define BRW_SURFACEFORMAT_L16_FLOAT 0x116 | ||
371 | #define BRW_SURFACEFORMAT_A16_FLOAT 0x117 | ||
372 | #define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118 | ||
373 | #define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 | ||
374 | #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A | ||
375 | #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B | ||
376 | #define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C | ||
377 | #define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D | ||
378 | #define BRW_SURFACEFORMAT_R16_SSCALED 0x11E | ||
379 | #define BRW_SURFACEFORMAT_R16_USCALED 0x11F | ||
380 | #define BRW_SURFACEFORMAT_R8_UNORM 0x140 | ||
381 | #define BRW_SURFACEFORMAT_R8_SNORM 0x141 | ||
382 | #define BRW_SURFACEFORMAT_R8_SINT 0x142 | ||
383 | #define BRW_SURFACEFORMAT_R8_UINT 0x143 | ||
384 | #define BRW_SURFACEFORMAT_A8_UNORM 0x144 | ||
385 | #define BRW_SURFACEFORMAT_I8_UNORM 0x145 | ||
386 | #define BRW_SURFACEFORMAT_L8_UNORM 0x146 | ||
387 | #define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 | ||
388 | #define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 | ||
389 | #define BRW_SURFACEFORMAT_R8_SSCALED 0x149 | ||
390 | #define BRW_SURFACEFORMAT_R8_USCALED 0x14A | ||
391 | #define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C | ||
392 | #define BRW_SURFACEFORMAT_R1_UINT 0x181 | ||
393 | #define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 | ||
394 | #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 | ||
395 | #define BRW_SURFACEFORMAT_BC1_UNORM 0x186 | ||
396 | #define BRW_SURFACEFORMAT_BC2_UNORM 0x187 | ||
397 | #define BRW_SURFACEFORMAT_BC3_UNORM 0x188 | ||
398 | #define BRW_SURFACEFORMAT_BC4_UNORM 0x189 | ||
399 | #define BRW_SURFACEFORMAT_BC5_UNORM 0x18A | ||
400 | #define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B | ||
401 | #define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C | ||
402 | #define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D | ||
403 | #define BRW_SURFACEFORMAT_MONO8 0x18E | ||
404 | #define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F | ||
405 | #define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 | ||
406 | #define BRW_SURFACEFORMAT_DXT1_RGB 0x191 | ||
407 | #define BRW_SURFACEFORMAT_FXT1 0x192 | ||
408 | #define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 | ||
409 | #define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 | ||
410 | #define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 | ||
411 | #define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 | ||
412 | #define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 | ||
413 | #define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 | ||
414 | #define BRW_SURFACEFORMAT_BC4_SNORM 0x199 | ||
415 | #define BRW_SURFACEFORMAT_BC5_SNORM 0x19A | ||
416 | #define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C | ||
417 | #define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D | ||
418 | #define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E | ||
419 | #define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F | ||
420 | #define BRW_SURFACEFORMAT_INVALID 0xFFF | ||
421 | |||
422 | #define BRW_SURFACERETURNFORMAT_FLOAT32 0 | ||
423 | #define BRW_SURFACERETURNFORMAT_S1 1 | ||
424 | |||
425 | #define BRW_SURFACE_1D 0 | ||
426 | #define BRW_SURFACE_2D 1 | ||
427 | #define BRW_SURFACE_3D 2 | ||
428 | #define BRW_SURFACE_CUBE 3 | ||
429 | #define BRW_SURFACE_BUFFER 4 | ||
430 | #define BRW_SURFACE_NULL 7 | ||
431 | |||
432 | #define BRW_TEXCOORDMODE_WRAP 0 | ||
433 | #define BRW_TEXCOORDMODE_MIRROR 1 | ||
434 | #define BRW_TEXCOORDMODE_CLAMP 2 | ||
435 | #define BRW_TEXCOORDMODE_CUBE 3 | ||
436 | #define BRW_TEXCOORDMODE_CLAMP_BORDER 4 | ||
437 | #define BRW_TEXCOORDMODE_MIRROR_ONCE 5 | ||
438 | |||
439 | #define BRW_THREAD_PRIORITY_NORMAL 0 | ||
440 | #define BRW_THREAD_PRIORITY_HIGH 1 | ||
441 | |||
442 | #define BRW_TILEWALK_XMAJOR 0 | ||
443 | #define BRW_TILEWALK_YMAJOR 1 | ||
444 | |||
445 | #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 | ||
446 | #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 | ||
447 | |||
448 | /* Execution Unit (EU) defines | ||
449 | */ | ||
450 | |||
451 | #define BRW_ALIGN_1 0 | ||
452 | #define BRW_ALIGN_16 1 | ||
453 | |||
454 | #define BRW_ADDRESS_DIRECT 0 | ||
455 | #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 | ||
456 | |||
457 | #define BRW_CHANNEL_X 0 | ||
458 | #define BRW_CHANNEL_Y 1 | ||
459 | #define BRW_CHANNEL_Z 2 | ||
460 | #define BRW_CHANNEL_W 3 | ||
461 | |||
462 | #define BRW_COMPRESSION_NONE 0 | ||
463 | #define BRW_COMPRESSION_2NDHALF 1 | ||
464 | #define BRW_COMPRESSION_COMPRESSED 2 | ||
465 | |||
466 | #define GEN6_COMPRESSION_1Q 0 | ||
467 | #define GEN6_COMPRESSION_2Q 1 | ||
468 | #define GEN6_COMPRESSION_3Q 2 | ||
469 | #define GEN6_COMPRESSION_4Q 3 | ||
470 | #define GEN6_COMPRESSION_1H 0 | ||
471 | #define GEN6_COMPRESSION_2H 2 | ||
472 | |||
473 | #define BRW_CONDITIONAL_NONE 0 | ||
474 | #define BRW_CONDITIONAL_Z 1 | ||
475 | #define BRW_CONDITIONAL_NZ 2 | ||
476 | #define BRW_CONDITIONAL_EQ 1 /* Z */ | ||
477 | #define BRW_CONDITIONAL_NEQ 2 /* NZ */ | ||
478 | #define BRW_CONDITIONAL_G 3 | ||
479 | #define BRW_CONDITIONAL_GE 4 | ||
480 | #define BRW_CONDITIONAL_L 5 | ||
481 | #define BRW_CONDITIONAL_LE 6 | ||
482 | #define BRW_CONDITIONAL_R 7 | ||
483 | #define BRW_CONDITIONAL_O 8 | ||
484 | #define BRW_CONDITIONAL_U 9 | ||
485 | |||
486 | #define BRW_DEBUG_NONE 0 | ||
487 | #define BRW_DEBUG_BREAKPOINT 1 | ||
488 | |||
489 | #define BRW_DEPENDENCY_NORMAL 0 | ||
490 | #define BRW_DEPENDENCY_NOTCLEARED 1 | ||
491 | #define BRW_DEPENDENCY_NOTCHECKED 2 | ||
492 | #define BRW_DEPENDENCY_DISABLE 3 | ||
493 | |||
494 | #define BRW_EXECUTE_1 0 | ||
495 | #define BRW_EXECUTE_2 1 | ||
496 | #define BRW_EXECUTE_4 2 | ||
497 | #define BRW_EXECUTE_8 3 | ||
498 | #define BRW_EXECUTE_16 4 | ||
499 | #define BRW_EXECUTE_32 5 | ||
500 | |||
501 | #define BRW_HORIZONTAL_STRIDE_0 0 | ||
502 | #define BRW_HORIZONTAL_STRIDE_1 1 | ||
503 | #define BRW_HORIZONTAL_STRIDE_2 2 | ||
504 | #define BRW_HORIZONTAL_STRIDE_4 3 | ||
505 | |||
506 | #define BRW_INSTRUCTION_NORMAL 0 | ||
507 | #define BRW_INSTRUCTION_SATURATE 1 | ||
508 | |||
509 | #define BRW_MASK_ENABLE 0 | ||
510 | #define BRW_MASK_DISABLE 1 | ||
511 | |||
512 | /** @{ | ||
513 | * | ||
514 | * Gen6 has replaced "mask enable/disable" with WECtrl, which is | ||
515 | * effectively the same but much simpler to think about. Now, there | ||
516 | * are two contributors ANDed together to whether channels are | ||
517 | * executed: The predication on the instruction, and the channel write | ||
518 | * enable. | ||
519 | */ | ||
520 | /** | ||
521 | * This is the default value. It means that a channel's write enable is set | ||
522 | * if the per-channel IP is pointing at this instruction. | ||
523 | */ | ||
524 | #define BRW_WE_NORMAL 0 | ||
525 | /** | ||
526 | * This is used like BRW_MASK_DISABLE, and causes all channels to have | ||
527 | * their write enable set. Note that predication still contributes to | ||
528 | * whether the channel actually gets written. | ||
529 | */ | ||
530 | #define BRW_WE_ALL 1 | ||
531 | /** @} */ | ||
532 | |||
533 | #define BRW_OPCODE_MOV 1 | ||
534 | #define BRW_OPCODE_SEL 2 | ||
535 | #define BRW_OPCODE_NOT 4 | ||
536 | #define BRW_OPCODE_AND 5 | ||
537 | #define BRW_OPCODE_OR 6 | ||
538 | #define BRW_OPCODE_XOR 7 | ||
539 | #define BRW_OPCODE_SHR 8 | ||
540 | #define BRW_OPCODE_SHL 9 | ||
541 | #define BRW_OPCODE_RSR 10 | ||
542 | #define BRW_OPCODE_RSL 11 | ||
543 | #define BRW_OPCODE_ASR 12 | ||
544 | #define BRW_OPCODE_CMP 16 | ||
545 | #define BRW_OPCODE_CMPN 17 | ||
546 | #define BRW_OPCODE_JMPI 32 | ||
547 | #define BRW_OPCODE_IF 34 | ||
548 | #define BRW_OPCODE_IFF 35 | ||
549 | #define BRW_OPCODE_ELSE 36 | ||
550 | #define BRW_OPCODE_ENDIF 37 | ||
551 | #define BRW_OPCODE_DO 38 | ||
552 | #define BRW_OPCODE_WHILE 39 | ||
553 | #define BRW_OPCODE_BREAK 40 | ||
554 | #define BRW_OPCODE_CONTINUE 41 | ||
555 | #define BRW_OPCODE_HALT 42 | ||
556 | #define BRW_OPCODE_MSAVE 44 | ||
557 | #define BRW_OPCODE_MRESTORE 45 | ||
558 | #define BRW_OPCODE_PUSH 46 | ||
559 | #define BRW_OPCODE_POP 47 | ||
560 | #define BRW_OPCODE_WAIT 48 | ||
561 | #define BRW_OPCODE_SEND 49 | ||
562 | #define BRW_OPCODE_SENDC 50 | ||
563 | #define BRW_OPCODE_MATH 56 | ||
564 | #define BRW_OPCODE_ADD 64 | ||
565 | #define BRW_OPCODE_MUL 65 | ||
566 | #define BRW_OPCODE_AVG 66 | ||
567 | #define BRW_OPCODE_FRC 67 | ||
568 | #define BRW_OPCODE_RNDU 68 | ||
569 | #define BRW_OPCODE_RNDD 69 | ||
570 | #define BRW_OPCODE_RNDE 70 | ||
571 | #define BRW_OPCODE_RNDZ 71 | ||
572 | #define BRW_OPCODE_MAC 72 | ||
573 | #define BRW_OPCODE_MACH 73 | ||
574 | #define BRW_OPCODE_LZD 74 | ||
575 | #define BRW_OPCODE_SAD2 80 | ||
576 | #define BRW_OPCODE_SADA2 81 | ||
577 | #define BRW_OPCODE_DP4 84 | ||
578 | #define BRW_OPCODE_DPH 85 | ||
579 | #define BRW_OPCODE_DP3 86 | ||
580 | #define BRW_OPCODE_DP2 87 | ||
581 | #define BRW_OPCODE_DPA2 88 | ||
582 | #define BRW_OPCODE_LINE 89 | ||
583 | #define BRW_OPCODE_PLN 90 | ||
584 | #define BRW_OPCODE_NOP 126 | ||
585 | |||
586 | #define BRW_PREDICATE_NONE 0 | ||
587 | #define BRW_PREDICATE_NORMAL 1 | ||
588 | #define BRW_PREDICATE_ALIGN1_ANYV 2 | ||
589 | #define BRW_PREDICATE_ALIGN1_ALLV 3 | ||
590 | #define BRW_PREDICATE_ALIGN1_ANY2H 4 | ||
591 | #define BRW_PREDICATE_ALIGN1_ALL2H 5 | ||
592 | #define BRW_PREDICATE_ALIGN1_ANY4H 6 | ||
593 | #define BRW_PREDICATE_ALIGN1_ALL4H 7 | ||
594 | #define BRW_PREDICATE_ALIGN1_ANY8H 8 | ||
595 | #define BRW_PREDICATE_ALIGN1_ALL8H 9 | ||
596 | #define BRW_PREDICATE_ALIGN1_ANY16H 10 | ||
597 | #define BRW_PREDICATE_ALIGN1_ALL16H 11 | ||
598 | #define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 | ||
599 | #define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 | ||
600 | #define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 | ||
601 | #define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 | ||
602 | #define BRW_PREDICATE_ALIGN16_ANY4H 6 | ||
603 | #define BRW_PREDICATE_ALIGN16_ALL4H 7 | ||
604 | |||
605 | #define BRW_ARCHITECTURE_REGISTER_FILE 0 | ||
606 | #define BRW_GENERAL_REGISTER_FILE 1 | ||
607 | #define BRW_MESSAGE_REGISTER_FILE 2 | ||
608 | #define BRW_IMMEDIATE_VALUE 3 | ||
609 | |||
610 | #define BRW_REGISTER_TYPE_UD 0 | ||
611 | #define BRW_REGISTER_TYPE_D 1 | ||
612 | #define BRW_REGISTER_TYPE_UW 2 | ||
613 | #define BRW_REGISTER_TYPE_W 3 | ||
614 | #define BRW_REGISTER_TYPE_UB 4 | ||
615 | #define BRW_REGISTER_TYPE_B 5 | ||
616 | #define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ | ||
617 | #define BRW_REGISTER_TYPE_HF 6 | ||
618 | #define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ | ||
619 | #define BRW_REGISTER_TYPE_F 7 | ||
620 | |||
621 | #define BRW_ARF_NULL 0x00 | ||
622 | #define BRW_ARF_ADDRESS 0x10 | ||
623 | #define BRW_ARF_ACCUMULATOR 0x20 | ||
624 | #define BRW_ARF_FLAG 0x30 | ||
625 | #define BRW_ARF_MASK 0x40 | ||
626 | #define BRW_ARF_MASK_STACK 0x50 | ||
627 | #define BRW_ARF_MASK_STACK_DEPTH 0x60 | ||
628 | #define BRW_ARF_STATE 0x70 | ||
629 | #define BRW_ARF_CONTROL 0x80 | ||
630 | #define BRW_ARF_NOTIFICATION_COUNT 0x90 | ||
631 | #define BRW_ARF_IP 0xA0 | ||
632 | |||
633 | #define BRW_MRF_COMPR4 (1 << 7) | ||
634 | |||
635 | #define BRW_AMASK 0 | ||
636 | #define BRW_IMASK 1 | ||
637 | #define BRW_LMASK 2 | ||
638 | #define BRW_CMASK 3 | ||
639 | |||
640 | |||
641 | |||
642 | #define BRW_THREAD_NORMAL 0 | ||
643 | #define BRW_THREAD_ATOMIC 1 | ||
644 | #define BRW_THREAD_SWITCH 2 | ||
645 | |||
646 | #define BRW_VERTICAL_STRIDE_0 0 | ||
647 | #define BRW_VERTICAL_STRIDE_1 1 | ||
648 | #define BRW_VERTICAL_STRIDE_2 2 | ||
649 | #define BRW_VERTICAL_STRIDE_4 3 | ||
650 | #define BRW_VERTICAL_STRIDE_8 4 | ||
651 | #define BRW_VERTICAL_STRIDE_16 5 | ||
652 | #define BRW_VERTICAL_STRIDE_32 6 | ||
653 | #define BRW_VERTICAL_STRIDE_64 7 | ||
654 | #define BRW_VERTICAL_STRIDE_128 8 | ||
655 | #define BRW_VERTICAL_STRIDE_256 9 | ||
656 | #define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF | ||
657 | |||
658 | #define BRW_WIDTH_1 0 | ||
659 | #define BRW_WIDTH_2 1 | ||
660 | #define BRW_WIDTH_4 2 | ||
661 | #define BRW_WIDTH_8 3 | ||
662 | #define BRW_WIDTH_16 4 | ||
663 | |||
664 | #define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 | ||
665 | #define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 | ||
666 | #define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 | ||
667 | #define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 | ||
668 | #define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 | ||
669 | #define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 | ||
670 | #define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 | ||
671 | #define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 | ||
672 | #define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 | ||
673 | #define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 | ||
674 | #define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 | ||
675 | #define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 | ||
676 | |||
677 | #define BRW_POLYGON_FACING_FRONT 0 | ||
678 | #define BRW_POLYGON_FACING_BACK 1 | ||
679 | |||
680 | #define BRW_MESSAGE_TARGET_NULL 0 | ||
681 | #define BRW_MESSAGE_TARGET_MATH 1 /* reserved on GEN6 */ | ||
682 | #define BRW_MESSAGE_TARGET_SAMPLER 2 | ||
683 | #define BRW_MESSAGE_TARGET_GATEWAY 3 | ||
684 | #define BRW_MESSAGE_TARGET_DATAPORT_READ 4 /* sampler cache on GEN6 */ | ||
685 | #define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 /* render cache on Gen6 */ | ||
686 | #define BRW_MESSAGE_TARGET_URB 6 | ||
687 | #define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 | ||
688 | #define BRW_MESSAGE_TARGET_CONST_CACHE 9 /* GEN6 */ | ||
689 | |||
690 | #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 | ||
691 | #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 | ||
692 | #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 | ||
693 | |||
694 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 | ||
695 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 | ||
696 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 | ||
697 | #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 | ||
698 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 | ||
699 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 | ||
700 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 | ||
701 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 | ||
702 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 | ||
703 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 | ||
704 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 | ||
705 | #define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 | ||
706 | #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 | ||
707 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 | ||
708 | #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 | ||
709 | #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 | ||
710 | |||
711 | #define BRW_SAMPLER_MESSAGE_SAMPLE_GEN5 0 | ||
712 | #define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5 1 | ||
713 | #define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5 2 | ||
714 | #define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5 3 | ||
715 | #define BRW_SAMPLER_MESSAGE_SAMPLE_DERIVS_GEN5 4 | ||
716 | #define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5 5 | ||
717 | #define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE_GEN5 6 | ||
718 | |||
719 | /* for GEN5 only */ | ||
720 | #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 | ||
721 | #define BRW_SAMPLER_SIMD_MODE_SIMD8 1 | ||
722 | #define BRW_SAMPLER_SIMD_MODE_SIMD16 2 | ||
723 | #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 | ||
724 | |||
725 | #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 | ||
726 | #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 | ||
727 | #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 | ||
728 | #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 | ||
729 | #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 | ||
730 | |||
731 | #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 | ||
732 | #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 | ||
733 | |||
734 | #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 | ||
735 | #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 | ||
736 | |||
737 | /* This one stays the same across generations. */ | ||
738 | #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 | ||
739 | /* GEN4 */ | ||
740 | #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 | ||
741 | #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 | ||
742 | #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 | ||
743 | /* G45, GEN5 */ | ||
744 | #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 | ||
745 | #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 | ||
746 | #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 | ||
747 | #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 | ||
748 | #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 | ||
749 | /* GEN6 */ | ||
750 | #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 | ||
751 | #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 | ||
752 | #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 | ||
753 | #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 | ||
754 | #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 | ||
755 | |||
756 | #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 | ||
757 | #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 | ||
758 | #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 | ||
759 | |||
760 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 | ||
761 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 | ||
762 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 | ||
763 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 | ||
764 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 | ||
765 | |||
766 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 | ||
767 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 | ||
768 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 | ||
769 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 | ||
770 | #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 | ||
771 | #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 | ||
772 | #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 | ||
773 | |||
774 | /* GEN6 */ | ||
775 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE_GEN6 7 | ||
776 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE_GEN6 8 | ||
777 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE_GEN6 9 | ||
778 | #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE_GEN6 10 | ||
779 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE_GEN6 11 | ||
780 | #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6 12 | ||
781 | #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE_GEN6 13 | ||
782 | #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE_GEN6 14 | ||
783 | |||
784 | #define BRW_MATH_FUNCTION_INV 1 | ||
785 | #define BRW_MATH_FUNCTION_LOG 2 | ||
786 | #define BRW_MATH_FUNCTION_EXP 3 | ||
787 | #define BRW_MATH_FUNCTION_SQRT 4 | ||
788 | #define BRW_MATH_FUNCTION_RSQ 5 | ||
789 | #define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ | ||
790 | #define BRW_MATH_FUNCTION_COS 7 /* was 8 */ | ||
791 | #define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ | ||
792 | #define BRW_MATH_FUNCTION_TAN 9 /* gen4 */ | ||
793 | #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */ | ||
794 | #define BRW_MATH_FUNCTION_POW 10 | ||
795 | #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 | ||
796 | #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 | ||
797 | #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 | ||
798 | |||
799 | #define BRW_MATH_INTEGER_UNSIGNED 0 | ||
800 | #define BRW_MATH_INTEGER_SIGNED 1 | ||
801 | |||
802 | #define BRW_MATH_PRECISION_FULL 0 | ||
803 | #define BRW_MATH_PRECISION_PARTIAL 1 | ||
804 | |||
805 | #define BRW_MATH_SATURATE_NONE 0 | ||
806 | #define BRW_MATH_SATURATE_SATURATE 1 | ||
807 | |||
808 | #define BRW_MATH_DATA_VECTOR 0 | ||
809 | #define BRW_MATH_DATA_SCALAR 1 | ||
810 | |||
811 | #define BRW_URB_OPCODE_WRITE 0 | ||
812 | |||
813 | #define BRW_URB_SWIZZLE_NONE 0 | ||
814 | #define BRW_URB_SWIZZLE_INTERLEAVE 1 | ||
815 | #define BRW_URB_SWIZZLE_TRANSPOSE 2 | ||
816 | |||
817 | #define BRW_SCRATCH_SPACE_SIZE_1K 0 | ||
818 | #define BRW_SCRATCH_SPACE_SIZE_2K 1 | ||
819 | #define BRW_SCRATCH_SPACE_SIZE_4K 2 | ||
820 | #define BRW_SCRATCH_SPACE_SIZE_8K 3 | ||
821 | #define BRW_SCRATCH_SPACE_SIZE_16K 4 | ||
822 | #define BRW_SCRATCH_SPACE_SIZE_32K 5 | ||
823 | #define BRW_SCRATCH_SPACE_SIZE_64K 6 | ||
824 | #define BRW_SCRATCH_SPACE_SIZE_128K 7 | ||
825 | #define BRW_SCRATCH_SPACE_SIZE_256K 8 | ||
826 | #define BRW_SCRATCH_SPACE_SIZE_512K 9 | ||
827 | #define BRW_SCRATCH_SPACE_SIZE_1M 10 | ||
828 | #define BRW_SCRATCH_SPACE_SIZE_2M 11 | ||
829 | |||
830 | |||
831 | |||
832 | |||
833 | #define CMD_URB_FENCE 0x6000 | ||
834 | #define CMD_CS_URB_STATE 0x6001 | ||
835 | #define CMD_CONST_BUFFER 0x6002 | ||
836 | |||
837 | #define CMD_STATE_BASE_ADDRESS 0x6101 | ||
838 | #define CMD_STATE_INSN_POINTER 0x6102 | ||
839 | #define CMD_PIPELINE_SELECT_965 0x6104 | ||
840 | #define CMD_PIPELINE_SELECT_GM45 0x6904 | ||
841 | |||
842 | #define CMD_PIPELINED_STATE_POINTERS 0x7800 | ||
843 | #define CMD_BINDING_TABLE_PTRS 0x7801 | ||
844 | # define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8) | ||
845 | # define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9) | ||
846 | # define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12) | ||
847 | |||
848 | #define CMD_3D_SAMPLER_STATE_POINTERS 0x7802 /* SNB+ */ | ||
849 | # define PS_SAMPLER_STATE_CHANGE (1 << 12) | ||
850 | # define GS_SAMPLER_STATE_CHANGE (1 << 9) | ||
851 | # define VS_SAMPLER_STATE_CHANGE (1 << 8) | ||
852 | /* DW1: VS */ | ||
853 | /* DW2: GS */ | ||
854 | /* DW3: PS */ | ||
855 | |||
856 | #define CMD_VERTEX_BUFFER 0x7808 | ||
857 | # define BRW_VB0_INDEX_SHIFT 27 | ||
858 | # define GEN6_VB0_INDEX_SHIFT 26 | ||
859 | # define BRW_VB0_ACCESS_VERTEXDATA (0 << 26) | ||
860 | # define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26) | ||
861 | # define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20) | ||
862 | # define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20) | ||
863 | # define BRW_VB0_PITCH_SHIFT 0 | ||
864 | |||
865 | #define CMD_VERTEX_ELEMENT 0x7809 | ||
866 | # define BRW_VE0_INDEX_SHIFT 27 | ||
867 | # define GEN6_VE0_INDEX_SHIFT 26 | ||
868 | # define BRW_VE0_FORMAT_SHIFT 16 | ||
869 | # define BRW_VE0_VALID (1 << 26) | ||
870 | # define GEN6_VE0_VALID (1 << 25) | ||
871 | # define BRW_VE0_SRC_OFFSET_SHIFT 0 | ||
872 | # define BRW_VE1_COMPONENT_NOSTORE 0 | ||
873 | # define BRW_VE1_COMPONENT_STORE_SRC 1 | ||
874 | # define BRW_VE1_COMPONENT_STORE_0 2 | ||
875 | # define BRW_VE1_COMPONENT_STORE_1_FLT 3 | ||
876 | # define BRW_VE1_COMPONENT_STORE_1_INT 4 | ||
877 | # define BRW_VE1_COMPONENT_STORE_VID 5 | ||
878 | # define BRW_VE1_COMPONENT_STORE_IID 6 | ||
879 | # define BRW_VE1_COMPONENT_STORE_PID 7 | ||
880 | # define BRW_VE1_COMPONENT_0_SHIFT 28 | ||
881 | # define BRW_VE1_COMPONENT_1_SHIFT 24 | ||
882 | # define BRW_VE1_COMPONENT_2_SHIFT 20 | ||
883 | # define BRW_VE1_COMPONENT_3_SHIFT 16 | ||
884 | # define BRW_VE1_DST_OFFSET_SHIFT 0 | ||
885 | |||
886 | #define CMD_INDEX_BUFFER 0x780a | ||
887 | #define CMD_VF_STATISTICS_965 0x780b | ||
888 | #define CMD_VF_STATISTICS_GM45 0x680b | ||
889 | #define CMD_3D_CC_STATE_POINTERS 0x780e /* GEN6+ */ | ||
890 | |||
891 | #define CMD_URB 0x7805 /* GEN6+ */ | ||
892 | # define GEN6_URB_VS_SIZE_SHIFT 16 | ||
893 | # define GEN6_URB_VS_ENTRIES_SHIFT 0 | ||
894 | # define GEN6_URB_GS_ENTRIES_SHIFT 8 | ||
895 | # define GEN6_URB_GS_SIZE_SHIFT 0 | ||
896 | |||
897 | #define CMD_VIEWPORT_STATE_POINTERS 0x780d /* GEN6+ */ | ||
898 | # define GEN6_CC_VIEWPORT_MODIFY (1 << 12) | ||
899 | # define GEN6_SF_VIEWPORT_MODIFY (1 << 11) | ||
900 | # define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10) | ||
901 | |||
902 | #define CMD_3D_SCISSOR_STATE_POINTERS 0x780f /* GEN6+ */ | ||
903 | |||
904 | #define CMD_3D_VS_STATE 0x7810 /* GEN6+ */ | ||
905 | /* DW2 */ | ||
906 | # define GEN6_VS_SPF_MODE (1 << 31) | ||
907 | # define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30) | ||
908 | # define GEN6_VS_SAMPLER_COUNT_SHIFT 27 | ||
909 | # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 | ||
910 | # define GEN6_VS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) | ||
911 | # define GEN6_VS_FLOATING_POINT_MODE_ALT (1 << 16) | ||
912 | /* DW4 */ | ||
913 | # define GEN6_VS_DISPATCH_START_GRF_SHIFT 20 | ||
914 | # define GEN6_VS_URB_READ_LENGTH_SHIFT 11 | ||
915 | # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4 | ||
916 | /* DW5 */ | ||
917 | # define GEN6_VS_MAX_THREADS_SHIFT 25 | ||
918 | # define GEN6_VS_STATISTICS_ENABLE (1 << 10) | ||
919 | # define GEN6_VS_CACHE_DISABLE (1 << 1) | ||
920 | # define GEN6_VS_ENABLE (1 << 0) | ||
921 | |||
922 | #define CMD_3D_GS_STATE 0x7811 /* GEN6+ */ | ||
923 | /* DW2 */ | ||
924 | # define GEN6_GS_SPF_MODE (1 << 31) | ||
925 | # define GEN6_GS_VECTOR_MASK_ENABLE (1 << 30) | ||
926 | # define GEN6_GS_SAMPLER_COUNT_SHIFT 27 | ||
927 | # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 | ||
928 | /* DW4 */ | ||
929 | # define GEN6_GS_URB_READ_LENGTH_SHIFT 11 | ||
930 | # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4 | ||
931 | # define GEN6_GS_DISPATCH_START_GRF_SHIFT 0 | ||
932 | /* DW5 */ | ||
933 | # define GEN6_GS_MAX_THREADS_SHIFT 25 | ||
934 | # define GEN6_GS_STATISTICS_ENABLE (1 << 10) | ||
935 | # define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9) | ||
936 | # define GEN6_GS_RENDERING_ENABLE (1 << 8) | ||
937 | /* DW6 */ | ||
938 | # define GEN6_GS_ENABLE (1 << 15) | ||
939 | |||
940 | #define CMD_3D_CLIP_STATE 0x7812 /* GEN6+ */ | ||
941 | /* DW1 */ | ||
942 | # define GEN6_CLIP_STATISTICS_ENABLE (1 << 10) | ||
943 | /** | ||
944 | * Just does cheap culling based on the clip distance. Bits must be | ||
945 | * disjoint with USER_CLIP_CLIP_DISTANCE bits. | ||
946 | */ | ||
947 | # define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT 0 | ||
948 | /* DW2 */ | ||
949 | # define GEN6_CLIP_ENABLE (1 << 31) | ||
950 | # define GEN6_CLIP_API_OGL (0 << 30) | ||
951 | # define GEN6_CLIP_API_D3D (1 << 30) | ||
952 | # define GEN6_CLIP_XY_TEST (1 << 28) | ||
953 | # define GEN6_CLIP_Z_TEST (1 << 27) | ||
954 | # define GEN6_CLIP_GB_TEST (1 << 26) | ||
955 | /** 8-bit field of which user clip distances to clip aganist. */ | ||
956 | # define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT 16 | ||
957 | # define GEN6_CLIP_MODE_NORMAL (0 << 13) | ||
958 | # define GEN6_CLIP_MODE_REJECT_ALL (3 << 13) | ||
959 | # define GEN6_CLIP_MODE_ACCEPT_ALL (4 << 13) | ||
960 | # define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE (1 << 9) | ||
961 | # define GEN6_CLIP_BARYCENTRIC_ENABLE (1 << 8) | ||
962 | # define GEN6_CLIP_TRI_PROVOKE_SHIFT 4 | ||
963 | # define GEN6_CLIP_LINE_PROVOKE_SHIFT 2 | ||
964 | # define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT 0 | ||
965 | /* DW3 */ | ||
966 | # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17 | ||
967 | # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6 | ||
968 | # define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5) | ||
969 | |||
970 | #define CMD_3D_SF_STATE 0x7813 /* GEN6+ */ | ||
971 | /* DW1 */ | ||
972 | # define GEN6_SF_NUM_OUTPUTS_SHIFT 22 | ||
973 | # define GEN6_SF_SWIZZLE_ENABLE (1 << 21) | ||
974 | # define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20) | ||
975 | # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 | ||
976 | # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 | ||
977 | /* DW2 */ | ||
978 | # define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS (1 << 11) | ||
979 | # define GEN6_SF_STATISTICS_ENABLE (1 << 10) | ||
980 | # define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID (1 << 9) | ||
981 | # define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME (1 << 8) | ||
982 | # define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT (1 << 7) | ||
983 | # define GEN6_SF_FRONT_SOLID (0 << 5) | ||
984 | # define GEN6_SF_FRONT_WIREFRAME (1 << 5) | ||
985 | # define GEN6_SF_FRONT_POINT (2 << 5) | ||
986 | # define GEN6_SF_BACK_SOLID (0 << 3) | ||
987 | # define GEN6_SF_BACK_WIREFRAME (1 << 3) | ||
988 | # define GEN6_SF_BACK_POINT (2 << 3) | ||
989 | # define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE (1 << 1) | ||
990 | # define GEN6_SF_WINDING_CCW (1 << 0) | ||
991 | /* DW3 */ | ||
992 | # define GEN6_SF_LINE_AA_ENABLE (1 << 31) | ||
993 | # define GEN6_SF_CULL_BOTH (0 << 29) | ||
994 | # define GEN6_SF_CULL_NONE (1 << 29) | ||
995 | # define GEN6_SF_CULL_FRONT (2 << 29) | ||
996 | # define GEN6_SF_CULL_BACK (3 << 29) | ||
997 | # define GEN6_SF_LINE_WIDTH_SHIFT 18 /* U3.7 */ | ||
998 | # define GEN6_SF_LINE_END_CAP_WIDTH_0_5 (0 << 16) | ||
999 | # define GEN6_SF_LINE_END_CAP_WIDTH_1_0 (1 << 16) | ||
1000 | # define GEN6_SF_LINE_END_CAP_WIDTH_2_0 (2 << 16) | ||
1001 | # define GEN6_SF_LINE_END_CAP_WIDTH_4_0 (3 << 16) | ||
1002 | # define GEN6_SF_SCISSOR_ENABLE (1 << 11) | ||
1003 | # define GEN6_SF_MSRAST_OFF_PIXEL (0 << 8) | ||
1004 | # define GEN6_SF_MSRAST_OFF_PATTERN (1 << 8) | ||
1005 | # define GEN6_SF_MSRAST_ON_PIXEL (2 << 8) | ||
1006 | # define GEN6_SF_MSRAST_ON_PATTERN (3 << 8) | ||
1007 | /* DW4 */ | ||
1008 | # define GEN6_SF_TRI_PROVOKE_SHIFT 29 | ||
1009 | # define GEN6_SF_LINE_PROVOKE_SHIFT 27 | ||
1010 | # define GEN6_SF_TRIFAN_PROVOKE_SHIFT 25 | ||
1011 | # define GEN6_SF_LINE_AA_MODE_MANHATTAN (0 << 14) | ||
1012 | # define GEN6_SF_LINE_AA_MODE_TRUE (1 << 14) | ||
1013 | # define GEN6_SF_VERTEX_SUBPIXEL_8BITS (0 << 12) | ||
1014 | # define GEN6_SF_VERTEX_SUBPIXEL_4BITS (1 << 12) | ||
1015 | # define GEN6_SF_USE_STATE_POINT_WIDTH (1 << 11) | ||
1016 | # define GEN6_SF_POINT_WIDTH_SHIFT 0 /* U8.3 */ | ||
1017 | /* DW5: depth offset constant */ | ||
1018 | /* DW6: depth offset scale */ | ||
1019 | /* DW7: depth offset clamp */ | ||
1020 | /* DW8 */ | ||
1021 | # define ATTRIBUTE_1_OVERRIDE_W (1 << 31) | ||
1022 | # define ATTRIBUTE_1_OVERRIDE_Z (1 << 30) | ||
1023 | # define ATTRIBUTE_1_OVERRIDE_Y (1 << 29) | ||
1024 | # define ATTRIBUTE_1_OVERRIDE_X (1 << 28) | ||
1025 | # define ATTRIBUTE_1_CONST_SOURCE_SHIFT 25 | ||
1026 | # define ATTRIBUTE_1_SWIZZLE_SHIFT 22 | ||
1027 | # define ATTRIBUTE_1_SOURCE_SHIFT 16 | ||
1028 | # define ATTRIBUTE_0_OVERRIDE_W (1 << 15) | ||
1029 | # define ATTRIBUTE_0_OVERRIDE_Z (1 << 14) | ||
1030 | # define ATTRIBUTE_0_OVERRIDE_Y (1 << 13) | ||
1031 | # define ATTRIBUTE_0_OVERRIDE_X (1 << 12) | ||
1032 | # define ATTRIBUTE_0_CONST_SOURCE_SHIFT 9 | ||
1033 | # define ATTRIBUTE_0_SWIZZLE_SHIFT 6 | ||
1034 | # define ATTRIBUTE_0_SOURCE_SHIFT 0 | ||
1035 | |||
1036 | # define ATTRIBUTE_SWIZZLE_INPUTATTR 0 | ||
1037 | # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1 | ||
1038 | # define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2 | ||
1039 | # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3 | ||
1040 | # define ATTRIBUTE_SWIZZLE_SHIFT 6 | ||
1041 | |||
1042 | /* DW16: Point sprite texture coordinate enables */ | ||
1043 | /* DW17: Constant interpolation enables */ | ||
1044 | /* DW18: attr 0-7 wrap shortest enables */ | ||
1045 | /* DW19: attr 8-16 wrap shortest enables */ | ||
1046 | |||
1047 | #define CMD_3D_WM_STATE 0x7814 /* GEN6+ */ | ||
1048 | /* DW1: kernel pointer */ | ||
1049 | /* DW2 */ | ||
1050 | # define GEN6_WM_SPF_MODE (1 << 31) | ||
1051 | # define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30) | ||
1052 | # define GEN6_WM_SAMPLER_COUNT_SHIFT 27 | ||
1053 | # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 | ||
1054 | # define GEN6_WM_FLOATING_POINT_MODE_IEEE_754 (0 << 16) | ||
1055 | # define GEN6_WM_FLOATING_POINT_MODE_ALT (1 << 16) | ||
1056 | /* DW3: scratch space */ | ||
1057 | /* DW4 */ | ||
1058 | # define GEN6_WM_STATISTICS_ENABLE (1 << 31) | ||
1059 | # define GEN6_WM_DEPTH_CLEAR (1 << 30) | ||
1060 | # define GEN6_WM_DEPTH_RESOLVE (1 << 28) | ||
1061 | # define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) | ||
1062 | # define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16 | ||
1063 | # define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8 | ||
1064 | # define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0 | ||
1065 | /* DW5 */ | ||
1066 | # define GEN6_WM_MAX_THREADS_SHIFT 25 | ||
1067 | # define GEN6_WM_KILL_ENABLE (1 << 22) | ||
1068 | # define GEN6_WM_COMPUTED_DEPTH (1 << 21) | ||
1069 | # define GEN6_WM_USES_SOURCE_DEPTH (1 << 20) | ||
1070 | # define GEN6_WM_DISPATCH_ENABLE (1 << 19) | ||
1071 | # define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16) | ||
1072 | # define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16) | ||
1073 | # define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16) | ||
1074 | # define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16) | ||
1075 | # define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14) | ||
1076 | # define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14) | ||
1077 | # define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14) | ||
1078 | # define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14) | ||
1079 | # define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13) | ||
1080 | # define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 11) | ||
1081 | # define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9) | ||
1082 | # define GEN6_WM_USES_SOURCE_W (1 << 8) | ||
1083 | # define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7) | ||
1084 | # define GEN6_WM_32_DISPATCH_ENABLE (1 << 2) | ||
1085 | # define GEN6_WM_16_DISPATCH_ENABLE (1 << 1) | ||
1086 | # define GEN6_WM_8_DISPATCH_ENABLE (1 << 0) | ||
1087 | /* DW6 */ | ||
1088 | # define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20 | ||
1089 | # define GEN6_WM_POSOFFSET_NONE (0 << 18) | ||
1090 | # define GEN6_WM_POSOFFSET_CENTROID (2 << 18) | ||
1091 | # define GEN6_WM_POSOFFSET_SAMPLE (3 << 18) | ||
1092 | # define GEN6_WM_POSITION_ZW_PIXEL (0 << 16) | ||
1093 | # define GEN6_WM_POSITION_ZW_CENTROID (2 << 16) | ||
1094 | # define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16) | ||
1095 | # define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) | ||
1096 | # define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) | ||
1097 | # define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) | ||
1098 | # define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) | ||
1099 | # define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) | ||
1100 | # define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) | ||
1101 | # define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9) | ||
1102 | # define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1) | ||
1103 | # define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1) | ||
1104 | # define GEN6_WM_MSRAST_ON_PIXEL (2 << 1) | ||
1105 | # define GEN6_WM_MSRAST_ON_PATTERN (3 << 1) | ||
1106 | # define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0) | ||
1107 | /* DW7: kernel 1 pointer */ | ||
1108 | /* DW8: kernel 2 pointer */ | ||
1109 | |||
1110 | #define CMD_3D_CONSTANT_VS_STATE 0x7815 /* GEN6+ */ | ||
1111 | #define CMD_3D_CONSTANT_GS_STATE 0x7816 /* GEN6+ */ | ||
1112 | #define CMD_3D_CONSTANT_PS_STATE 0x7817 /* GEN6+ */ | ||
1113 | # define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15) | ||
1114 | # define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14) | ||
1115 | # define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13) | ||
1116 | # define GEN6_CONSTANT_BUFFER_0_ENABLE (1 << 12) | ||
1117 | |||
1118 | #define CMD_3D_SAMPLE_MASK 0x7818 /* GEN6+ */ | ||
1119 | |||
1120 | #define CMD_DRAW_RECT 0x7900 | ||
1121 | #define CMD_BLEND_CONSTANT_COLOR 0x7901 | ||
1122 | #define CMD_CHROMA_KEY 0x7904 | ||
1123 | #define CMD_DEPTH_BUFFER 0x7905 | ||
1124 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 | ||
1125 | #define CMD_POLY_STIPPLE_PATTERN 0x7907 | ||
1126 | #define CMD_LINE_STIPPLE_PATTERN 0x7908 | ||
1127 | #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909 | ||
1128 | #define CMD_AA_LINE_PARAMETERS 0x790a | ||
1129 | |||
1130 | #define CMD_GS_SVB_INDEX 0x790b /* CTG+ */ | ||
1131 | /* DW1 */ | ||
1132 | # define SVB_INDEX_SHIFT 29 | ||
1133 | # define SVB_LOAD_INTERNAL_VERTEX_COUNT (1 << 0) /* SNB+ */ | ||
1134 | /* DW2: SVB index */ | ||
1135 | /* DW3: SVB maximum index */ | ||
1136 | |||
1137 | #define CMD_3D_MULTISAMPLE 0x790d /* SNB+ */ | ||
1138 | /* DW1 */ | ||
1139 | # define MS_PIXEL_LOCATION_CENTER (0 << 4) | ||
1140 | # define MS_PIXEL_LOCATION_UPPER_LEFT (1 << 4) | ||
1141 | # define MS_NUMSAMPLES_1 (0 << 1) | ||
1142 | # define MS_NUMSAMPLES_4 (2 << 1) | ||
1143 | # define MS_NUMSAMPLES_8 (3 << 1) | ||
1144 | |||
1145 | #define CMD_3D_CLEAR_PARAMS 0x7910 /* ILK+ */ | ||
1146 | # define DEPTH_CLEAR_VALID (1 << 15) | ||
1147 | /* DW1: depth clear value */ | ||
1148 | |||
1149 | #define CMD_PIPE_CONTROL 0x7a00 | ||
1150 | |||
1151 | #define CMD_3D_PRIM 0x7b00 | ||
1152 | |||
1153 | #define CMD_MI_FLUSH 0x0200 | ||
1154 | |||
1155 | |||
1156 | /* Various values from the R0 vertex header: | ||
1157 | */ | ||
1158 | #define R02_PRIM_END 0x1 | ||
1159 | #define R02_PRIM_START 0x2 | ||
1160 | |||
1161 | #define URB_SIZES(brw) (brw->gen == 5 ? 1024 : \ | ||
1162 | (brw->is_g4x ? 384 : 256)) /* 512 bit units */ | ||
1163 | |||
1164 | |||
1165 | |||
1166 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_disasm.c b/src/gallium/drivers/i965/brw_disasm.c deleted file mode 100644 index b093569f0cf..00000000000 --- a/src/gallium/drivers/i965/brw_disasm.c +++ /dev/null | |||
@@ -1,1023 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright © 2008 Keith Packard | ||
3 | * | ||
4 | * Permission to use, copy, modify, distribute, and sell this software and its | ||
5 | * documentation for any purpose is hereby granted without fee, provided that | ||
6 | * the above copyright notice appear in all copies and that both that copyright | ||
7 | * notice and this permission notice appear in supporting documentation, and | ||
8 | * that the name of the copyright holders not be used in advertising or | ||
9 | * publicity pertaining to distribution of the software without specific, | ||
10 | * written prior permission. The copyright holders make no representations | ||
11 | * about the suitability of this software for any purpose. It is provided "as | ||
12 | * is" without express or implied warranty. | ||
13 | * | ||
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | ||
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | ||
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | ||
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | ||
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | ||
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | ||
20 | * OF THIS SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <stdio.h> | ||
24 | #include <stdlib.h> | ||
25 | #include <string.h> | ||
26 | #include <unistd.h> | ||
27 | #include <stdarg.h> | ||
28 | |||
29 | #include "brw_disasm.h" | ||
30 | #include "brw_structs.h" | ||
31 | #include "brw_reg.h" | ||
32 | #include "brw_defines.h" | ||
33 | |||
34 | struct { | ||
35 | char *name; | ||
36 | int nsrc; | ||
37 | int ndst; | ||
38 | } opcode[128] = { | ||
39 | [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 }, | ||
40 | [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 }, | ||
41 | [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 }, | ||
42 | [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 }, | ||
43 | [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 }, | ||
44 | [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, | ||
45 | [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, | ||
46 | [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, | ||
47 | |||
48 | [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, | ||
49 | [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, | ||
50 | [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 }, | ||
51 | [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 }, | ||
52 | [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 }, | ||
53 | [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 }, | ||
54 | [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 }, | ||
55 | [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 }, | ||
56 | [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 }, | ||
57 | [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 }, | ||
58 | [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 }, | ||
59 | [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 }, | ||
60 | |||
61 | [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 }, | ||
62 | [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 }, | ||
63 | [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 }, | ||
64 | [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 }, | ||
65 | [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 }, | ||
66 | [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 }, | ||
67 | [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 }, | ||
68 | [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 }, | ||
69 | [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, | ||
70 | [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, | ||
71 | [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, | ||
72 | |||
73 | [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, | ||
74 | [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, | ||
75 | [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 }, | ||
76 | [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 }, | ||
77 | [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 }, | ||
78 | [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 }, | ||
79 | [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 }, | ||
80 | [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 }, | ||
81 | [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 }, | ||
82 | [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 }, | ||
83 | [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 }, | ||
84 | [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 }, | ||
85 | [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 }, | ||
86 | [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 }, | ||
87 | [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 }, | ||
88 | [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 }, | ||
89 | [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 }, | ||
90 | [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 }, | ||
91 | }; | ||
92 | |||
93 | char *conditional_modifier[16] = { | ||
94 | [BRW_CONDITIONAL_NONE] = "", | ||
95 | [BRW_CONDITIONAL_Z] = ".e", | ||
96 | [BRW_CONDITIONAL_NZ] = ".ne", | ||
97 | [BRW_CONDITIONAL_G] = ".g", | ||
98 | [BRW_CONDITIONAL_GE] = ".ge", | ||
99 | [BRW_CONDITIONAL_L] = ".l", | ||
100 | [BRW_CONDITIONAL_LE] = ".le", | ||
101 | [BRW_CONDITIONAL_R] = ".r", | ||
102 | [BRW_CONDITIONAL_O] = ".o", | ||
103 | [BRW_CONDITIONAL_U] = ".u", | ||
104 | }; | ||
105 | |||
106 | char *negate[2] = { | ||
107 | [0] = "", | ||
108 | [1] = "-", | ||
109 | }; | ||
110 | |||
111 | char *_abs[2] = { | ||
112 | [0] = "", | ||
113 | [1] = "(abs)", | ||
114 | }; | ||
115 | |||
116 | char *vert_stride[16] = { | ||
117 | [0] = "0", | ||
118 | [1] = "1", | ||
119 | [2] = "2", | ||
120 | [3] = "4", | ||
121 | [4] = "8", | ||
122 | [5] = "16", | ||
123 | [6] = "32", | ||
124 | [15] = "VxH", | ||
125 | }; | ||
126 | |||
127 | char *width[8] = { | ||
128 | [0] = "1", | ||
129 | [1] = "2", | ||
130 | [2] = "4", | ||
131 | [3] = "8", | ||
132 | [4] = "16", | ||
133 | }; | ||
134 | |||
135 | char *horiz_stride[4] = { | ||
136 | [0] = "0", | ||
137 | [1] = "1", | ||
138 | [2] = "2", | ||
139 | [3] = "4" | ||
140 | }; | ||
141 | |||
142 | char *chan_sel[4] = { | ||
143 | [0] = "x", | ||
144 | [1] = "y", | ||
145 | [2] = "z", | ||
146 | [3] = "w", | ||
147 | }; | ||
148 | |||
149 | char *dest_condmod[16] = { | ||
150 | }; | ||
151 | |||
152 | char *debug_ctrl[2] = { | ||
153 | [0] = "", | ||
154 | [1] = ".breakpoint" | ||
155 | }; | ||
156 | |||
157 | char *saturate[2] = { | ||
158 | [0] = "", | ||
159 | [1] = ".sat" | ||
160 | }; | ||
161 | |||
162 | char *accwr[2] = { | ||
163 | [0] = "", | ||
164 | [1] = "AccWrEnable" | ||
165 | }; | ||
166 | |||
167 | char *wectrl[2] = { | ||
168 | [0] = "WE_normal", | ||
169 | [1] = "WE_all" | ||
170 | }; | ||
171 | |||
172 | char *exec_size[8] = { | ||
173 | [0] = "1", | ||
174 | [1] = "2", | ||
175 | [2] = "4", | ||
176 | [3] = "8", | ||
177 | [4] = "16", | ||
178 | [5] = "32" | ||
179 | }; | ||
180 | |||
181 | char *pred_inv[2] = { | ||
182 | [0] = "+", | ||
183 | [1] = "-" | ||
184 | }; | ||
185 | |||
186 | char *pred_ctrl_align16[16] = { | ||
187 | [1] = "", | ||
188 | [2] = ".x", | ||
189 | [3] = ".y", | ||
190 | [4] = ".z", | ||
191 | [5] = ".w", | ||
192 | [6] = ".any4h", | ||
193 | [7] = ".all4h", | ||
194 | }; | ||
195 | |||
196 | char *pred_ctrl_align1[16] = { | ||
197 | [1] = "", | ||
198 | [2] = ".anyv", | ||
199 | [3] = ".allv", | ||
200 | [4] = ".any2h", | ||
201 | [5] = ".all2h", | ||
202 | [6] = ".any4h", | ||
203 | [7] = ".all4h", | ||
204 | [8] = ".any8h", | ||
205 | [9] = ".all8h", | ||
206 | [10] = ".any16h", | ||
207 | [11] = ".all16h", | ||
208 | }; | ||
209 | |||
210 | char *thread_ctrl[4] = { | ||
211 | [0] = "", | ||
212 | [2] = "switch" | ||
213 | }; | ||
214 | |||
215 | char *compr_ctrl[4] = { | ||
216 | [0] = "", | ||
217 | [1] = "sechalf", | ||
218 | [2] = "compr", | ||
219 | [3] = "compr4", | ||
220 | }; | ||
221 | |||
222 | char *dep_ctrl[4] = { | ||
223 | [0] = "", | ||
224 | [1] = "NoDDClr", | ||
225 | [2] = "NoDDChk", | ||
226 | [3] = "NoDDClr,NoDDChk", | ||
227 | }; | ||
228 | |||
229 | char *mask_ctrl[4] = { | ||
230 | [0] = "", | ||
231 | [1] = "nomask", | ||
232 | }; | ||
233 | |||
234 | char *access_mode[2] = { | ||
235 | [0] = "align1", | ||
236 | [1] = "align16", | ||
237 | }; | ||
238 | |||
239 | char *reg_encoding[8] = { | ||
240 | [0] = "UD", | ||
241 | [1] = "D", | ||
242 | [2] = "UW", | ||
243 | [3] = "W", | ||
244 | [4] = "UB", | ||
245 | [5] = "B", | ||
246 | [7] = "F" | ||
247 | }; | ||
248 | |||
249 | int reg_type_size[8] = { | ||
250 | [0] = 4, | ||
251 | [1] = 4, | ||
252 | [2] = 2, | ||
253 | [3] = 2, | ||
254 | [4] = 1, | ||
255 | [5] = 1, | ||
256 | [7] = 4 | ||
257 | }; | ||
258 | |||
259 | char *imm_encoding[8] = { | ||
260 | [0] = "UD", | ||
261 | [1] = "D", | ||
262 | [2] = "UW", | ||
263 | [3] = "W", | ||
264 | [5] = "VF", | ||
265 | [6] = "V", | ||
266 | [7] = "F" | ||
267 | }; | ||
268 | |||
269 | char *reg_file[4] = { | ||
270 | [0] = "A", | ||
271 | [1] = "g", | ||
272 | [2] = "m", | ||
273 | [3] = "imm", | ||
274 | }; | ||
275 | |||
276 | char *writemask[16] = { | ||
277 | [0x0] = ".", | ||
278 | [0x1] = ".x", | ||
279 | [0x2] = ".y", | ||
280 | [0x3] = ".xy", | ||
281 | [0x4] = ".z", | ||
282 | [0x5] = ".xz", | ||
283 | [0x6] = ".yz", | ||
284 | [0x7] = ".xyz", | ||
285 | [0x8] = ".w", | ||
286 | [0x9] = ".xw", | ||
287 | [0xa] = ".yw", | ||
288 | [0xb] = ".xyw", | ||
289 | [0xc] = ".zw", | ||
290 | [0xd] = ".xzw", | ||
291 | [0xe] = ".yzw", | ||
292 | [0xf] = "", | ||
293 | }; | ||
294 | |||
295 | char *end_of_thread[2] = { | ||
296 | [0] = "", | ||
297 | [1] = "EOT" | ||
298 | }; | ||
299 | |||
300 | char *target_function[16] = { | ||
301 | [BRW_MESSAGE_TARGET_NULL] = "null", | ||
302 | [BRW_MESSAGE_TARGET_MATH] = "math", | ||
303 | [BRW_MESSAGE_TARGET_SAMPLER] = "sampler", | ||
304 | [BRW_MESSAGE_TARGET_GATEWAY] = "gateway", | ||
305 | [BRW_MESSAGE_TARGET_DATAPORT_READ] = "read", | ||
306 | [BRW_MESSAGE_TARGET_DATAPORT_WRITE] = "write", | ||
307 | [BRW_MESSAGE_TARGET_URB] = "urb", | ||
308 | [BRW_MESSAGE_TARGET_THREAD_SPAWNER] = "thread_spawner" | ||
309 | }; | ||
310 | |||
311 | char *math_function[16] = { | ||
312 | [BRW_MATH_FUNCTION_INV] = "inv", | ||
313 | [BRW_MATH_FUNCTION_LOG] = "log", | ||
314 | [BRW_MATH_FUNCTION_EXP] = "exp", | ||
315 | [BRW_MATH_FUNCTION_SQRT] = "sqrt", | ||
316 | [BRW_MATH_FUNCTION_RSQ] = "rsq", | ||
317 | [BRW_MATH_FUNCTION_SIN] = "sin", | ||
318 | [BRW_MATH_FUNCTION_COS] = "cos", | ||
319 | [BRW_MATH_FUNCTION_SINCOS] = "sincos", | ||
320 | [BRW_MATH_FUNCTION_TAN] = "tan", | ||
321 | [BRW_MATH_FUNCTION_POW] = "pow", | ||
322 | [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", | ||
323 | [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intmod", | ||
324 | [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intdiv", | ||
325 | }; | ||
326 | |||
327 | char *math_saturate[2] = { | ||
328 | [0] = "", | ||
329 | [1] = "sat" | ||
330 | }; | ||
331 | |||
332 | char *math_signed[2] = { | ||
333 | [0] = "", | ||
334 | [1] = "signed" | ||
335 | }; | ||
336 | |||
337 | char *math_scalar[2] = { | ||
338 | [0] = "", | ||
339 | [1] = "scalar" | ||
340 | }; | ||
341 | |||
342 | char *math_precision[2] = { | ||
343 | [0] = "", | ||
344 | [1] = "partial_precision" | ||
345 | }; | ||
346 | |||
347 | char *urb_opcode[2] = { | ||
348 | [0] = "urb_write", | ||
349 | [1] = "ff_sync", | ||
350 | }; | ||
351 | |||
352 | char *urb_swizzle[4] = { | ||
353 | [BRW_URB_SWIZZLE_NONE] = "", | ||
354 | [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave", | ||
355 | [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose", | ||
356 | }; | ||
357 | |||
358 | char *urb_allocate[2] = { | ||
359 | [0] = "", | ||
360 | [1] = "allocate" | ||
361 | }; | ||
362 | |||
363 | char *urb_used[2] = { | ||
364 | [0] = "", | ||
365 | [1] = "used" | ||
366 | }; | ||
367 | |||
368 | char *urb_complete[2] = { | ||
369 | [0] = "", | ||
370 | [1] = "complete" | ||
371 | }; | ||
372 | |||
373 | char *sampler_target_format[4] = { | ||
374 | [0] = "F", | ||
375 | [2] = "UD", | ||
376 | [3] = "D" | ||
377 | }; | ||
378 | |||
379 | |||
380 | static int column; | ||
381 | |||
382 | static int string (FILE *file, char *string) | ||
383 | { | ||
384 | fputs (string, file); | ||
385 | column += strlen (string); | ||
386 | return 0; | ||
387 | } | ||
388 | |||
389 | static int format (FILE *f, char *format, ...) | ||
390 | { | ||
391 | char buf[1024]; | ||
392 | va_list args; | ||
393 | va_start (args, format); | ||
394 | |||
395 | vsnprintf (buf, sizeof (buf) - 1, format, args); | ||
396 | va_end (args); | ||
397 | string (f, buf); | ||
398 | return 0; | ||
399 | } | ||
400 | |||
401 | static int newline (FILE *f) | ||
402 | { | ||
403 | putc ('\n', f); | ||
404 | column = 0; | ||
405 | return 0; | ||
406 | } | ||
407 | |||
408 | static int pad (FILE *f, int c) | ||
409 | { | ||
410 | do | ||
411 | string (f, " "); | ||
412 | while (column < c); | ||
413 | return 0; | ||
414 | } | ||
415 | |||
416 | static int control (FILE *file, char *name, char *ctrl[], GLuint id, int *space) | ||
417 | { | ||
418 | if (!ctrl[id]) { | ||
419 | fprintf (file, "*** invalid %s value %d ", | ||
420 | name, id); | ||
421 | return 1; | ||
422 | } | ||
423 | if (ctrl[id][0]) | ||
424 | { | ||
425 | if (space && *space) | ||
426 | string (file, " "); | ||
427 | string (file, ctrl[id]); | ||
428 | if (space) | ||
429 | *space = 1; | ||
430 | } | ||
431 | return 0; | ||
432 | } | ||
433 | |||
434 | static int print_opcode (FILE *file, int id) | ||
435 | { | ||
436 | if (!opcode[id].name) { | ||
437 | format (file, "*** invalid opcode value %d ", id); | ||
438 | return 1; | ||
439 | } | ||
440 | string (file, opcode[id].name); | ||
441 | return 0; | ||
442 | } | ||
443 | |||
444 | static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr) | ||
445 | { | ||
446 | int err = 0; | ||
447 | |||
448 | /* Clear the Compr4 instruction compression bit. */ | ||
449 | if (_reg_file == BRW_MESSAGE_REGISTER_FILE) | ||
450 | _reg_nr &= ~(1 << 7); | ||
451 | |||
452 | if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { | ||
453 | switch (_reg_nr & 0xf0) { | ||
454 | case BRW_ARF_NULL: | ||
455 | string (file, "null"); | ||
456 | return -1; | ||
457 | case BRW_ARF_ADDRESS: | ||
458 | format (file, "a%d", _reg_nr & 0x0f); | ||
459 | break; | ||
460 | case BRW_ARF_ACCUMULATOR: | ||
461 | format (file, "acc%d", _reg_nr & 0x0f); | ||
462 | break; | ||
463 | case BRW_ARF_FLAG: | ||
464 | format (file, "f%d", _reg_nr & 0x0f); | ||
465 | break; | ||
466 | case BRW_ARF_MASK: | ||
467 | format (file, "mask%d", _reg_nr & 0x0f); | ||
468 | break; | ||
469 | case BRW_ARF_MASK_STACK: | ||
470 | format (file, "msd%d", _reg_nr & 0x0f); | ||
471 | break; | ||
472 | case BRW_ARF_STATE: | ||
473 | format (file, "sr%d", _reg_nr & 0x0f); | ||
474 | break; | ||
475 | case BRW_ARF_CONTROL: | ||
476 | format (file, "cr%d", _reg_nr & 0x0f); | ||
477 | break; | ||
478 | case BRW_ARF_NOTIFICATION_COUNT: | ||
479 | format (file, "n%d", _reg_nr & 0x0f); | ||
480 | break; | ||
481 | case BRW_ARF_IP: | ||
482 | string (file, "ip"); | ||
483 | return -1; | ||
484 | break; | ||
485 | default: | ||
486 | format (file, "ARF%d", _reg_nr); | ||
487 | break; | ||
488 | } | ||
489 | } else { | ||
490 | err |= control (file, "src reg file", reg_file, _reg_file, NULL); | ||
491 | format (file, "%d", _reg_nr); | ||
492 | } | ||
493 | return err; | ||
494 | } | ||
495 | |||
496 | static int dest (FILE *file, struct brw_instruction *inst) | ||
497 | { | ||
498 | int err = 0; | ||
499 | |||
500 | if (inst->header.access_mode == BRW_ALIGN_1) | ||
501 | { | ||
502 | if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT) | ||
503 | { | ||
504 | err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr); | ||
505 | if (err == -1) | ||
506 | return 0; | ||
507 | if (inst->bits1.da1.dest_subreg_nr) | ||
508 | format (file, ".%d", inst->bits1.da1.dest_subreg_nr / | ||
509 | reg_type_size[inst->bits1.da1.dest_reg_type]); | ||
510 | format (file, "<%d>", inst->bits1.da1.dest_horiz_stride); | ||
511 | err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL); | ||
512 | } | ||
513 | else | ||
514 | { | ||
515 | string (file, "g[a0"); | ||
516 | if (inst->bits1.ia1.dest_subreg_nr) | ||
517 | format (file, ".%d", inst->bits1.ia1.dest_subreg_nr / | ||
518 | reg_type_size[inst->bits1.ia1.dest_reg_type]); | ||
519 | if (inst->bits1.ia1.dest_indirect_offset) | ||
520 | format (file, " %d", inst->bits1.ia1.dest_indirect_offset); | ||
521 | string (file, "]"); | ||
522 | format (file, "<%d>", inst->bits1.ia1.dest_horiz_stride); | ||
523 | err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL); | ||
524 | } | ||
525 | } | ||
526 | else | ||
527 | { | ||
528 | if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) | ||
529 | { | ||
530 | err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr); | ||
531 | if (err == -1) | ||
532 | return 0; | ||
533 | if (inst->bits1.da16.dest_subreg_nr) | ||
534 | format (file, ".%d", inst->bits1.da16.dest_subreg_nr / | ||
535 | reg_type_size[inst->bits1.da16.dest_reg_type]); | ||
536 | string (file, "<1>"); | ||
537 | err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL); | ||
538 | err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL); | ||
539 | } | ||
540 | else | ||
541 | { | ||
542 | err = 1; | ||
543 | string (file, "Indirect align16 address mode not supported"); | ||
544 | } | ||
545 | } | ||
546 | |||
547 | return 0; | ||
548 | } | ||
549 | |||
550 | static int src_align1_region (FILE *file, | ||
551 | GLuint _vert_stride, GLuint _width, GLuint _horiz_stride) | ||
552 | { | ||
553 | int err = 0; | ||
554 | string (file, "<"); | ||
555 | err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); | ||
556 | string (file, ","); | ||
557 | err |= control (file, "width", width, _width, NULL); | ||
558 | string (file, ","); | ||
559 | err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL); | ||
560 | string (file, ">"); | ||
561 | return err; | ||
562 | } | ||
563 | |||
564 | static int src_da1 (FILE *file, GLuint type, GLuint _reg_file, | ||
565 | GLuint _vert_stride, GLuint _width, GLuint _horiz_stride, | ||
566 | GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate) | ||
567 | { | ||
568 | int err = 0; | ||
569 | err |= control (file, "negate", negate, _negate, NULL); | ||
570 | err |= control (file, "abs", _abs, __abs, NULL); | ||
571 | |||
572 | err |= reg (file, _reg_file, reg_num); | ||
573 | if (err == -1) | ||
574 | return 0; | ||
575 | if (sub_reg_num) | ||
576 | format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */ | ||
577 | src_align1_region (file, _vert_stride, _width, _horiz_stride); | ||
578 | err |= control (file, "src reg encoding", reg_encoding, type, NULL); | ||
579 | return err; | ||
580 | } | ||
581 | |||
582 | static int src_ia1 (FILE *file, | ||
583 | GLuint type, | ||
584 | GLuint _reg_file, | ||
585 | GLint _addr_imm, | ||
586 | GLuint _addr_subreg_nr, | ||
587 | GLuint _negate, | ||
588 | GLuint __abs, | ||
589 | GLuint _addr_mode, | ||
590 | GLuint _horiz_stride, | ||
591 | GLuint _width, | ||
592 | GLuint _vert_stride) | ||
593 | { | ||
594 | int err = 0; | ||
595 | err |= control (file, "negate", negate, _negate, NULL); | ||
596 | err |= control (file, "abs", _abs, __abs, NULL); | ||
597 | |||
598 | string (file, "g[a0"); | ||
599 | if (_addr_subreg_nr) | ||
600 | format (file, ".%d", _addr_subreg_nr); | ||
601 | if (_addr_imm) | ||
602 | format (file, " %d", _addr_imm); | ||
603 | string (file, "]"); | ||
604 | src_align1_region (file, _vert_stride, _width, _horiz_stride); | ||
605 | err |= control (file, "src reg encoding", reg_encoding, type, NULL); | ||
606 | return err; | ||
607 | } | ||
608 | |||
609 | static int src_da16 (FILE *file, | ||
610 | GLuint _reg_type, | ||
611 | GLuint _reg_file, | ||
612 | GLuint _vert_stride, | ||
613 | GLuint _reg_nr, | ||
614 | GLuint _subreg_nr, | ||
615 | GLuint __abs, | ||
616 | GLuint _negate, | ||
617 | GLuint swz_x, | ||
618 | GLuint swz_y, | ||
619 | GLuint swz_z, | ||
620 | GLuint swz_w) | ||
621 | { | ||
622 | int err = 0; | ||
623 | err |= control (file, "negate", negate, _negate, NULL); | ||
624 | err |= control (file, "abs", _abs, __abs, NULL); | ||
625 | |||
626 | err |= reg (file, _reg_file, _reg_nr); | ||
627 | if (err == -1) | ||
628 | return 0; | ||
629 | if (_subreg_nr) | ||
630 | /* bit4 for subreg number byte addressing. Make this same meaning as | ||
631 | in da1 case, so output looks consistent. */ | ||
632 | format (file, ".%d", 16 / reg_type_size[_reg_type]); | ||
633 | string (file, "<"); | ||
634 | err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); | ||
635 | string (file, ",4,1>"); | ||
636 | /* | ||
637 | * Three kinds of swizzle display: | ||
638 | * identity - nothing printed | ||
639 | * 1->all - print the single channel | ||
640 | * 1->1 - print the mapping | ||
641 | */ | ||
642 | if (swz_x == BRW_CHANNEL_X && | ||
643 | swz_y == BRW_CHANNEL_Y && | ||
644 | swz_z == BRW_CHANNEL_Z && | ||
645 | swz_w == BRW_CHANNEL_W) | ||
646 | { | ||
647 | ; | ||
648 | } | ||
649 | else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) | ||
650 | { | ||
651 | string (file, "."); | ||
652 | err |= control (file, "channel select", chan_sel, swz_x, NULL); | ||
653 | } | ||
654 | else | ||
655 | { | ||
656 | string (file, "."); | ||
657 | err |= control (file, "channel select", chan_sel, swz_x, NULL); | ||
658 | err |= control (file, "channel select", chan_sel, swz_y, NULL); | ||
659 | err |= control (file, "channel select", chan_sel, swz_z, NULL); | ||
660 | err |= control (file, "channel select", chan_sel, swz_w, NULL); | ||
661 | } | ||
662 | err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL); | ||
663 | return err; | ||
664 | } | ||
665 | |||
666 | |||
667 | static int imm (FILE *file, GLuint type, struct brw_instruction *inst) { | ||
668 | switch (type) { | ||
669 | case BRW_REGISTER_TYPE_UD: | ||
670 | format (file, "0x%08xUD", inst->bits3.ud); | ||
671 | break; | ||
672 | case BRW_REGISTER_TYPE_D: | ||
673 | format (file, "%dD", inst->bits3.d); | ||
674 | break; | ||
675 | case BRW_REGISTER_TYPE_UW: | ||
676 | format (file, "0x%04xUW", (uint16_t) inst->bits3.ud); | ||
677 | break; | ||
678 | case BRW_REGISTER_TYPE_W: | ||
679 | format (file, "%dW", (int16_t) inst->bits3.d); | ||
680 | break; | ||
681 | case BRW_REGISTER_TYPE_UB: | ||
682 | format (file, "0x%02xUB", (int8_t) inst->bits3.ud); | ||
683 | break; | ||
684 | case BRW_REGISTER_TYPE_VF: | ||
685 | format (file, "Vector Float"); | ||
686 | break; | ||
687 | case BRW_REGISTER_TYPE_V: | ||
688 | format (file, "0x%08xV", inst->bits3.ud); | ||
689 | break; | ||
690 | case BRW_REGISTER_TYPE_F: | ||
691 | format (file, "%-gF", inst->bits3.f); | ||
692 | } | ||
693 | return 0; | ||
694 | } | ||
695 | |||
696 | static int src0 (FILE *file, struct brw_instruction *inst) | ||
697 | { | ||
698 | if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) | ||
699 | return imm (file, inst->bits1.da1.src0_reg_type, | ||
700 | inst); | ||
701 | else if (inst->header.access_mode == BRW_ALIGN_1) | ||
702 | { | ||
703 | if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT) | ||
704 | { | ||
705 | return src_da1 (file, | ||
706 | inst->bits1.da1.src0_reg_type, | ||
707 | inst->bits1.da1.src0_reg_file, | ||
708 | inst->bits2.da1.src0_vert_stride, | ||
709 | inst->bits2.da1.src0_width, | ||
710 | inst->bits2.da1.src0_horiz_stride, | ||
711 | inst->bits2.da1.src0_reg_nr, | ||
712 | inst->bits2.da1.src0_subreg_nr, | ||
713 | inst->bits2.da1.src0_abs, | ||
714 | inst->bits2.da1.src0_negate); | ||
715 | } | ||
716 | else | ||
717 | { | ||
718 | return src_ia1 (file, | ||
719 | inst->bits1.ia1.src0_reg_type, | ||
720 | inst->bits1.ia1.src0_reg_file, | ||
721 | inst->bits2.ia1.src0_indirect_offset, | ||
722 | inst->bits2.ia1.src0_subreg_nr, | ||
723 | inst->bits2.ia1.src0_negate, | ||
724 | inst->bits2.ia1.src0_abs, | ||
725 | inst->bits2.ia1.src0_address_mode, | ||
726 | inst->bits2.ia1.src0_horiz_stride, | ||
727 | inst->bits2.ia1.src0_width, | ||
728 | inst->bits2.ia1.src0_vert_stride); | ||
729 | } | ||
730 | } | ||
731 | else | ||
732 | { | ||
733 | if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT) | ||
734 | { | ||
735 | return src_da16 (file, | ||
736 | inst->bits1.da16.src0_reg_type, | ||
737 | inst->bits1.da16.src0_reg_file, | ||
738 | inst->bits2.da16.src0_vert_stride, | ||
739 | inst->bits2.da16.src0_reg_nr, | ||
740 | inst->bits2.da16.src0_subreg_nr, | ||
741 | inst->bits2.da16.src0_abs, | ||
742 | inst->bits2.da16.src0_negate, | ||
743 | inst->bits2.da16.src0_swz_x, | ||
744 | inst->bits2.da16.src0_swz_y, | ||
745 | inst->bits2.da16.src0_swz_z, | ||
746 | inst->bits2.da16.src0_swz_w); | ||
747 | } | ||
748 | else | ||
749 | { | ||
750 | string (file, "Indirect align16 address mode not supported"); | ||
751 | return 1; | ||
752 | } | ||
753 | } | ||
754 | } | ||
755 | |||
756 | static int src1 (FILE *file, struct brw_instruction *inst) | ||
757 | { | ||
758 | if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE) | ||
759 | return imm (file, inst->bits1.da1.src1_reg_type, | ||
760 | inst); | ||
761 | else if (inst->header.access_mode == BRW_ALIGN_1) | ||
762 | { | ||
763 | if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) | ||
764 | { | ||
765 | return src_da1 (file, | ||
766 | inst->bits1.da1.src1_reg_type, | ||
767 | inst->bits1.da1.src1_reg_file, | ||
768 | inst->bits3.da1.src1_vert_stride, | ||
769 | inst->bits3.da1.src1_width, | ||
770 | inst->bits3.da1.src1_horiz_stride, | ||
771 | inst->bits3.da1.src1_reg_nr, | ||
772 | inst->bits3.da1.src1_subreg_nr, | ||
773 | inst->bits3.da1.src1_abs, | ||
774 | inst->bits3.da1.src1_negate); | ||
775 | } | ||
776 | else | ||
777 | { | ||
778 | return src_ia1 (file, | ||
779 | inst->bits1.ia1.src1_reg_type, | ||
780 | inst->bits1.ia1.src1_reg_file, | ||
781 | inst->bits3.ia1.src1_indirect_offset, | ||
782 | inst->bits3.ia1.src1_subreg_nr, | ||
783 | inst->bits3.ia1.src1_negate, | ||
784 | inst->bits3.ia1.src1_abs, | ||
785 | inst->bits3.ia1.src1_address_mode, | ||
786 | inst->bits3.ia1.src1_horiz_stride, | ||
787 | inst->bits3.ia1.src1_width, | ||
788 | inst->bits3.ia1.src1_vert_stride); | ||
789 | } | ||
790 | } | ||
791 | else | ||
792 | { | ||
793 | if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT) | ||
794 | { | ||
795 | return src_da16 (file, | ||
796 | inst->bits1.da16.src1_reg_type, | ||
797 | inst->bits1.da16.src1_reg_file, | ||
798 | inst->bits3.da16.src1_vert_stride, | ||
799 | inst->bits3.da16.src1_reg_nr, | ||
800 | inst->bits3.da16.src1_subreg_nr, | ||
801 | inst->bits3.da16.src1_abs, | ||
802 | inst->bits3.da16.src1_negate, | ||
803 | inst->bits3.da16.src1_swz_x, | ||
804 | inst->bits3.da16.src1_swz_y, | ||
805 | inst->bits3.da16.src1_swz_z, | ||
806 | inst->bits3.da16.src1_swz_w); | ||
807 | } | ||
808 | else | ||
809 | { | ||
810 | string (file, "Indirect align16 address mode not supported"); | ||
811 | return 1; | ||
812 | } | ||
813 | } | ||
814 | } | ||
815 | |||
816 | int brw_disasm_insn (FILE *file, struct brw_instruction *inst, int gen) | ||
817 | { | ||
818 | int err = 0; | ||
819 | int space = 0; | ||
820 | |||
821 | if (inst->header.predicate_control) { | ||
822 | string (file, "("); | ||
823 | err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); | ||
824 | string (file, "f0"); | ||
825 | if (inst->bits2.da1.flag_reg_nr) | ||
826 | format (file, ".%d", inst->bits2.da1.flag_reg_nr); | ||
827 | if (inst->header.access_mode == BRW_ALIGN_1) | ||
828 | err |= control (file, "predicate control align1", pred_ctrl_align1, | ||
829 | inst->header.predicate_control, NULL); | ||
830 | else | ||
831 | err |= control (file, "predicate control align16", pred_ctrl_align16, | ||
832 | inst->header.predicate_control, NULL); | ||
833 | string (file, ") "); | ||
834 | } | ||
835 | |||
836 | err |= print_opcode (file, inst->header.opcode); | ||
837 | err |= control (file, "saturate", saturate, inst->header.saturate, NULL); | ||
838 | err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL); | ||
839 | |||
840 | if (inst->header.opcode != BRW_OPCODE_SEND) | ||
841 | err |= control (file, "conditional modifier", conditional_modifier, | ||
842 | inst->header.destreg__conditionalmod, NULL); | ||
843 | |||
844 | if (inst->header.opcode != BRW_OPCODE_NOP) { | ||
845 | string (file, "("); | ||
846 | err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL); | ||
847 | string (file, ")"); | ||
848 | } | ||
849 | |||
850 | if (inst->header.opcode == BRW_OPCODE_SEND) | ||
851 | format (file, " %d", inst->header.destreg__conditionalmod); | ||
852 | |||
853 | if (opcode[inst->header.opcode].ndst > 0) { | ||
854 | pad (file, 16); | ||
855 | err |= dest (file, inst); | ||
856 | } | ||
857 | if (opcode[inst->header.opcode].nsrc > 0) { | ||
858 | pad (file, 32); | ||
859 | err |= src0 (file, inst); | ||
860 | } | ||
861 | if (opcode[inst->header.opcode].nsrc > 1) { | ||
862 | pad (file, 48); | ||
863 | err |= src1 (file, inst); | ||
864 | } | ||
865 | |||
866 | if (inst->header.opcode == BRW_OPCODE_SEND || | ||
867 | inst->header.opcode == BRW_OPCODE_SENDC) { | ||
868 | newline (file); | ||
869 | pad (file, 16); | ||
870 | space = 0; | ||
871 | err |= control (file, "target function", target_function, | ||
872 | inst->bits3.generic.msg_target, &space); | ||
873 | switch (inst->bits3.generic.msg_target) { | ||
874 | case BRW_MESSAGE_TARGET_MATH: | ||
875 | err |= control (file, "math function", math_function, | ||
876 | inst->bits3.math.function, &space); | ||
877 | err |= control (file, "math saturate", math_saturate, | ||
878 | inst->bits3.math.saturate, &space); | ||
879 | err |= control (file, "math signed", math_signed, | ||
880 | inst->bits3.math.int_type, &space); | ||
881 | err |= control (file, "math scalar", math_scalar, | ||
882 | inst->bits3.math.data_type, &space); | ||
883 | err |= control (file, "math precision", math_precision, | ||
884 | inst->bits3.math.precision, &space); | ||
885 | break; | ||
886 | case BRW_MESSAGE_TARGET_SAMPLER: | ||
887 | if (gen >= 5) { | ||
888 | format (file, " (%d, %d, %d, %d)", | ||
889 | inst->bits3.sampler_gen5.binding_table_index, | ||
890 | inst->bits3.sampler_gen5.sampler, | ||
891 | inst->bits3.sampler_gen5.msg_type, | ||
892 | inst->bits3.sampler_gen5.simd_mode); | ||
893 | } else if (0 /* FINISHME: is_g4x */) { | ||
894 | format (file, " (%d, %d)", | ||
895 | inst->bits3.sampler_g4x.binding_table_index, | ||
896 | inst->bits3.sampler_g4x.sampler); | ||
897 | } else { | ||
898 | format (file, " (%d, %d, ", | ||
899 | inst->bits3.sampler.binding_table_index, | ||
900 | inst->bits3.sampler.sampler); | ||
901 | err |= control (file, "sampler target format", sampler_target_format, | ||
902 | inst->bits3.sampler.return_format, NULL); | ||
903 | string (file, ")"); | ||
904 | } | ||
905 | break; | ||
906 | case BRW_MESSAGE_TARGET_DATAPORT_READ: | ||
907 | if (gen >= 6) { | ||
908 | format (file, " (%d, %d, %d, %d, %d, %d)", | ||
909 | inst->bits3.dp_render_cache.binding_table_index, | ||
910 | inst->bits3.dp_render_cache.msg_control, | ||
911 | inst->bits3.dp_render_cache.msg_type, | ||
912 | inst->bits3.dp_render_cache.send_commit_msg, | ||
913 | inst->bits3.dp_render_cache.msg_length, | ||
914 | inst->bits3.dp_render_cache.response_length); | ||
915 | } else if (gen >= 5 /* FINISHME: || is_g4x */) { | ||
916 | format (file, " (%d, %d, %d)", | ||
917 | inst->bits3.dp_read_gen5.binding_table_index, | ||
918 | inst->bits3.dp_read_gen5.msg_control, | ||
919 | inst->bits3.dp_read_gen5.msg_type); | ||
920 | } else { | ||
921 | format (file, " (%d, %d, %d)", | ||
922 | inst->bits3.dp_read.binding_table_index, | ||
923 | inst->bits3.dp_read.msg_control, | ||
924 | inst->bits3.dp_read.msg_type); | ||
925 | } | ||
926 | break; | ||
927 | case BRW_MESSAGE_TARGET_DATAPORT_WRITE: | ||
928 | if (gen >= 6) { | ||
929 | format (file, " (%d, %d, %d, %d, %d, %d)", | ||
930 | inst->bits3.dp_render_cache.binding_table_index, | ||
931 | inst->bits3.dp_render_cache.msg_control, | ||
932 | inst->bits3.dp_render_cache.msg_type, | ||
933 | inst->bits3.dp_render_cache.send_commit_msg, | ||
934 | inst->bits3.dp_render_cache.msg_length, | ||
935 | inst->bits3.dp_render_cache.response_length); | ||
936 | } else { | ||
937 | format (file, " (%d, %d, %d, %d)", | ||
938 | inst->bits3.dp_write.binding_table_index, | ||
939 | (inst->bits3.dp_write.pixel_scoreboard_clear << 3) | | ||
940 | inst->bits3.dp_write.msg_control, | ||
941 | inst->bits3.dp_write.msg_type, | ||
942 | inst->bits3.dp_write.send_commit_msg); | ||
943 | } | ||
944 | break; | ||
945 | case BRW_MESSAGE_TARGET_URB: | ||
946 | if (gen >= 5) { | ||
947 | format (file, " %d", inst->bits3.urb_gen5.offset); | ||
948 | } else { | ||
949 | format (file, " %d", inst->bits3.urb.offset); | ||
950 | } | ||
951 | err |= control (file, "urb swizzle", urb_swizzle, | ||
952 | inst->bits3.urb.swizzle_control, &space); | ||
953 | err |= control (file, "urb allocate", urb_allocate, | ||
954 | inst->bits3.urb.allocate, &space); | ||
955 | err |= control (file, "urb used", urb_used, | ||
956 | inst->bits3.urb.used, &space); | ||
957 | err |= control (file, "urb complete", urb_complete, | ||
958 | inst->bits3.urb.complete, &space); | ||
959 | if (gen >= 5) { | ||
960 | format (file, " mlen %d, rlen %d\n", | ||
961 | inst->bits3.urb_gen5.msg_length, | ||
962 | inst->bits3.urb_gen5.response_length); | ||
963 | } | ||
964 | break; | ||
965 | case BRW_MESSAGE_TARGET_THREAD_SPAWNER: | ||
966 | break; | ||
967 | default: | ||
968 | format (file, "unsupported target %d", inst->bits3.generic.msg_target); | ||
969 | break; | ||
970 | } | ||
971 | if (space) | ||
972 | string (file, " "); | ||
973 | if (gen >= 5) { | ||
974 | format (file, "mlen %d", | ||
975 | inst->bits3.generic_gen5.msg_length); | ||
976 | format (file, " rlen %d", | ||
977 | inst->bits3.generic_gen5.response_length); | ||
978 | } else { | ||
979 | format (file, "mlen %d", | ||
980 | inst->bits3.generic.msg_length); | ||
981 | format (file, " rlen %d", | ||
982 | inst->bits3.generic.response_length); | ||
983 | } | ||
984 | } | ||
985 | pad (file, 64); | ||
986 | if (inst->header.opcode != BRW_OPCODE_NOP) { | ||
987 | string (file, "{"); | ||
988 | space = 1; | ||
989 | err |= control(file, "access mode", access_mode, inst->header.access_mode, &space); | ||
990 | err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space); | ||
991 | err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space); | ||
992 | err |= control (file, "compression control", compr_ctrl, inst->header.compression_control, &space); | ||
993 | err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space); | ||
994 | if (inst->header.opcode == BRW_OPCODE_SEND || | ||
995 | inst->header.opcode == BRW_OPCODE_SENDC) | ||
996 | err |= control (file, "end of thread", end_of_thread, | ||
997 | inst->bits3.generic.end_of_thread, &space); | ||
998 | if (space) | ||
999 | string (file, " "); | ||
1000 | string (file, "}"); | ||
1001 | } | ||
1002 | string (file, ";"); | ||
1003 | newline (file); | ||
1004 | return err; | ||
1005 | } | ||
1006 | |||
1007 | |||
1008 | int brw_disasm (FILE *file, | ||
1009 | struct brw_instruction *inst, | ||
1010 | unsigned count, int gen) | ||
1011 | { | ||
1012 | int i, err; | ||
1013 | |||
1014 | for (i = 0; i < count; i++) { | ||
1015 | err = brw_disasm_insn(stderr, &inst[i], gen); | ||
1016 | if (err) | ||
1017 | return err; | ||
1018 | } | ||
1019 | |||
1020 | fprintf(file, "\n"); | ||
1021 | return 0; | ||
1022 | } | ||
1023 | |||
diff --git a/src/gallium/drivers/i965/brw_disasm.h b/src/gallium/drivers/i965/brw_disasm.h deleted file mode 100644 index ce451ed5a06..00000000000 --- a/src/gallium/drivers/i965/brw_disasm.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright © 2008 Keith Packard | ||
3 | * | ||
4 | * Permission to use, copy, modify, distribute, and sell this software and its | ||
5 | * documentation for any purpose is hereby granted without fee, provided that | ||
6 | * the above copyright notice appear in all copies and that both that copyright | ||
7 | * notice and this permission notice appear in supporting documentation, and | ||
8 | * that the name of the copyright holders not be used in advertising or | ||
9 | * publicity pertaining to distribution of the software without specific, | ||
10 | * written prior permission. The copyright holders make no representations | ||
11 | * about the suitability of this software for any purpose. It is provided "as | ||
12 | * is" without express or implied warranty. | ||
13 | * | ||
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | ||
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | ||
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | ||
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | ||
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | ||
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | ||
20 | * OF THIS SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef BRW_DISASM_H | ||
24 | #define BRW_DISASM_H | ||
25 | |||
26 | #include <stdio.h> | ||
27 | |||
28 | struct brw_instruction; | ||
29 | |||
30 | int brw_disasm_insn (FILE *file, struct brw_instruction *inst, int gen); | ||
31 | int brw_disasm (FILE *file, | ||
32 | struct brw_instruction *inst, | ||
33 | unsigned count, int gen); | ||
34 | |||
35 | #endif | ||
36 | |||
diff --git a/src/gallium/drivers/i965/brw_draw.c b/src/gallium/drivers/i965/brw_draw.c deleted file mode 100644 index 3ab9024c31e..00000000000 --- a/src/gallium/drivers/i965/brw_draw.c +++ /dev/null | |||
@@ -1,254 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | |||
29 | #include "util/u_inlines.h" | ||
30 | #include "util/u_prim.h" | ||
31 | #include "util/u_upload_mgr.h" | ||
32 | |||
33 | #include "brw_draw.h" | ||
34 | #include "brw_defines.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_debug.h" | ||
38 | |||
39 | #include "brw_batchbuffer.h" | ||
40 | |||
41 | |||
42 | static uint32_t prim_to_hw_prim[PIPE_PRIM_POLYGON+1] = { | ||
43 | _3DPRIM_POINTLIST, | ||
44 | _3DPRIM_LINELIST, | ||
45 | _3DPRIM_LINELOOP, | ||
46 | _3DPRIM_LINESTRIP, | ||
47 | _3DPRIM_TRILIST, | ||
48 | _3DPRIM_TRISTRIP, | ||
49 | _3DPRIM_TRIFAN, | ||
50 | _3DPRIM_QUADLIST, | ||
51 | _3DPRIM_QUADSTRIP, | ||
52 | _3DPRIM_POLYGON | ||
53 | }; | ||
54 | |||
55 | |||
56 | |||
57 | /* When the primitive changes, set a state bit and re-validate. Not | ||
58 | * the nicest and would rather deal with this by having all the | ||
59 | * programs be immune to the active primitive (ie. cope with all | ||
60 | * possibilities). That may not be realistic however. | ||
61 | */ | ||
62 | static int brw_set_prim(struct brw_context *brw, unsigned prim ) | ||
63 | { | ||
64 | |||
65 | if (BRW_DEBUG & DEBUG_PRIMS) | ||
66 | debug_printf("PRIM: %s\n", u_prim_name(prim)); | ||
67 | |||
68 | if (prim != brw->primitive) { | ||
69 | unsigned reduced_prim; | ||
70 | |||
71 | brw->primitive = prim; | ||
72 | brw->state.dirty.brw |= BRW_NEW_PRIMITIVE; | ||
73 | |||
74 | reduced_prim = u_reduced_prim(prim); | ||
75 | if (reduced_prim != brw->reduced_primitive) { | ||
76 | brw->reduced_primitive = reduced_prim; | ||
77 | brw->state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE; | ||
78 | } | ||
79 | } | ||
80 | |||
81 | return prim_to_hw_prim[prim]; | ||
82 | } | ||
83 | |||
84 | |||
85 | |||
86 | static int brw_emit_prim(struct brw_context *brw, | ||
87 | unsigned start, | ||
88 | unsigned count, | ||
89 | boolean indexed, | ||
90 | uint32_t hw_prim) | ||
91 | { | ||
92 | struct brw_3d_primitive prim_packet; | ||
93 | int ret; | ||
94 | |||
95 | if (BRW_DEBUG & DEBUG_PRIMS) | ||
96 | debug_printf("%s start %d count %d indexed %d hw_prim %d\n", | ||
97 | __FUNCTION__, start, count, indexed, hw_prim); | ||
98 | |||
99 | prim_packet.header.opcode = CMD_3D_PRIM; | ||
100 | prim_packet.header.length = sizeof(prim_packet)/4 - 2; | ||
101 | prim_packet.header.pad = 0; | ||
102 | prim_packet.header.topology = hw_prim; | ||
103 | prim_packet.header.indexed = indexed; | ||
104 | |||
105 | prim_packet.verts_per_instance = count; | ||
106 | prim_packet.start_vert_location = start; | ||
107 | if (indexed) | ||
108 | prim_packet.start_vert_location += brw->ib.start_vertex_offset; | ||
109 | prim_packet.instance_count = 1; | ||
110 | prim_packet.start_instance_location = 0; | ||
111 | prim_packet.base_vert_location = 0; /* prim->basevertex; XXX: add this to gallium */ | ||
112 | |||
113 | |||
114 | /* If we're set to always flush, do it before and after the primitive emit. | ||
115 | * We want to catch both missed flushes that hurt instruction/state cache | ||
116 | * and missed flushes of the render cache as it heads to other parts of | ||
117 | * the besides the draw code. | ||
118 | */ | ||
119 | if (0) { | ||
120 | BEGIN_BATCH(1, IGNORE_CLIPRECTS); | ||
121 | OUT_BATCH((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE); | ||
122 | ADVANCE_BATCH(); | ||
123 | } | ||
124 | if (prim_packet.verts_per_instance) { | ||
125 | ret = brw_batchbuffer_data( brw->batch, &prim_packet, | ||
126 | sizeof(prim_packet), LOOP_CLIPRECTS); | ||
127 | if (ret) | ||
128 | return ret; | ||
129 | } | ||
130 | if (0) { | ||
131 | BEGIN_BATCH(1, IGNORE_CLIPRECTS); | ||
132 | OUT_BATCH((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE); | ||
133 | ADVANCE_BATCH(); | ||
134 | } | ||
135 | |||
136 | return 0; | ||
137 | } | ||
138 | |||
139 | |||
140 | /* May fail if out of video memory for texture or vbo upload, or on | ||
141 | * fallback conditions. | ||
142 | */ | ||
143 | static int | ||
144 | try_draw_range_elements(struct brw_context *brw, | ||
145 | boolean indexed, | ||
146 | unsigned hw_prim, | ||
147 | unsigned start, unsigned count) | ||
148 | { | ||
149 | int ret; | ||
150 | |||
151 | ret = brw_validate_state(brw); | ||
152 | if (ret) | ||
153 | return ret; | ||
154 | |||
155 | /* Check that we can fit our state in with our existing batchbuffer, or | ||
156 | * flush otherwise. | ||
157 | */ | ||
158 | ret = brw->sws->check_aperture_space(brw->sws, | ||
159 | brw->state.validated_bos, | ||
160 | brw->state.validated_bo_count); | ||
161 | if (ret) | ||
162 | return ret; | ||
163 | |||
164 | ret = brw_upload_state(brw); | ||
165 | if (ret) | ||
166 | return ret; | ||
167 | |||
168 | ret = brw_emit_prim(brw, start, count, indexed, hw_prim); | ||
169 | if (ret) | ||
170 | return ret; | ||
171 | |||
172 | if (brw->flags.always_flush_batch) | ||
173 | brw_context_flush( brw ); | ||
174 | |||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | |||
179 | static void | ||
180 | brw_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) | ||
181 | { | ||
182 | struct brw_context *brw = brw_context(pipe); | ||
183 | int ret; | ||
184 | uint32_t hw_prim; | ||
185 | |||
186 | hw_prim = brw_set_prim(brw, info->mode); | ||
187 | |||
188 | if (BRW_DEBUG & DEBUG_PRIMS) | ||
189 | debug_printf("PRIM: %s start %d count %d index_buffer %p\n", | ||
190 | u_prim_name(info->mode), info->start, info->count, | ||
191 | (void *) brw->curr.index_buffer); | ||
192 | |||
193 | assert(info->index_bias == 0); | ||
194 | |||
195 | /* Potentially trigger upload of new index buffer range. | ||
196 | * XXX: do we really care? | ||
197 | */ | ||
198 | if (brw->curr.min_index != info->min_index || | ||
199 | brw->curr.max_index != info->max_index) | ||
200 | { | ||
201 | brw->curr.min_index = info->min_index; | ||
202 | brw->curr.max_index = info->max_index; | ||
203 | brw->state.dirty.mesa |= PIPE_NEW_INDEX_RANGE; | ||
204 | } | ||
205 | |||
206 | |||
207 | /* Make a first attempt at drawing: | ||
208 | */ | ||
209 | ret = try_draw_range_elements(brw, info->indexed, | ||
210 | hw_prim, info->start, info->count); | ||
211 | |||
212 | /* Otherwise, flush and retry: | ||
213 | */ | ||
214 | if (ret != 0) { | ||
215 | brw_context_flush( brw ); | ||
216 | ret = try_draw_range_elements(brw, info->indexed, | ||
217 | hw_prim, info->start, info->count); | ||
218 | assert(ret == 0); | ||
219 | } | ||
220 | } | ||
221 | |||
222 | |||
223 | boolean brw_draw_init( struct brw_context *brw ) | ||
224 | { | ||
225 | /* Register our drawing function: | ||
226 | */ | ||
227 | brw->base.draw_vbo = brw_draw_vbo; | ||
228 | |||
229 | /* Create helpers for uploading data in user buffers: | ||
230 | */ | ||
231 | brw->vb.upload_vertex = u_upload_create( &brw->base, | ||
232 | 128 * 1024, | ||
233 | 64, | ||
234 | PIPE_BIND_VERTEX_BUFFER ); | ||
235 | if (brw->vb.upload_vertex == NULL) | ||
236 | return FALSE; | ||
237 | |||
238 | brw->vb.upload_index = u_upload_create( &brw->base, | ||
239 | 32 * 1024, | ||
240 | 64, | ||
241 | PIPE_BIND_INDEX_BUFFER ); | ||
242 | if (brw->vb.upload_index == NULL) | ||
243 | return FALSE; | ||
244 | |||
245 | return TRUE; | ||
246 | } | ||
247 | |||
248 | void brw_draw_cleanup( struct brw_context *brw ) | ||
249 | { | ||
250 | u_upload_destroy( brw->vb.upload_vertex ); | ||
251 | u_upload_destroy( brw->vb.upload_index ); | ||
252 | |||
253 | bo_reference(&brw->ib.bo, NULL); | ||
254 | } | ||
diff --git a/src/gallium/drivers/i965/brw_draw.h b/src/gallium/drivers/i965/brw_draw.h deleted file mode 100644 index 8dc5dbce622..00000000000 --- a/src/gallium/drivers/i965/brw_draw.h +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #ifndef BRW_DRAW_H | ||
29 | #define BRW_DRAW_H | ||
30 | |||
31 | #include "brw_types.h" | ||
32 | |||
33 | struct brw_context; | ||
34 | |||
35 | boolean brw_draw_init( struct brw_context *brw ); | ||
36 | void brw_draw_cleanup( struct brw_context *brw ); | ||
37 | |||
38 | |||
39 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_draw_upload.c b/src/gallium/drivers/i965/brw_draw_upload.c deleted file mode 100644 index 04ec5c81a6b..00000000000 --- a/src/gallium/drivers/i965/brw_draw_upload.c +++ /dev/null | |||
@@ -1,359 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #include "pipe/p_context.h" | ||
29 | #include "util/u_inlines.h" | ||
30 | |||
31 | #include "util/u_upload_mgr.h" | ||
32 | #include "util/u_math.h" | ||
33 | |||
34 | #include "brw_draw.h" | ||
35 | #include "brw_defines.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_state.h" | ||
38 | #include "brw_screen.h" | ||
39 | #include "brw_batchbuffer.h" | ||
40 | #include "brw_debug.h" | ||
41 | #include "brw_resource.h" | ||
42 | |||
43 | |||
44 | |||
45 | |||
46 | static unsigned get_index_type(int type) | ||
47 | { | ||
48 | switch (type) { | ||
49 | case 1: return BRW_INDEX_BYTE; | ||
50 | case 2: return BRW_INDEX_WORD; | ||
51 | case 4: return BRW_INDEX_DWORD; | ||
52 | default: assert(0); return 0; | ||
53 | } | ||
54 | } | ||
55 | |||
56 | |||
57 | static int brw_prepare_vertices(struct brw_context *brw) | ||
58 | { | ||
59 | unsigned int min_index = brw->curr.min_index; | ||
60 | unsigned int max_index = brw->curr.max_index; | ||
61 | GLuint i; | ||
62 | int ret; | ||
63 | |||
64 | if (BRW_DEBUG & DEBUG_VERTS) | ||
65 | debug_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index); | ||
66 | |||
67 | |||
68 | for (i = 0; i < brw->curr.num_vertex_buffers; i++) { | ||
69 | struct pipe_vertex_buffer *vb = &brw->curr.vertex_buffer[i]; | ||
70 | struct brw_winsys_buffer *bo; | ||
71 | struct pipe_resource *upload_buf = NULL; | ||
72 | unsigned offset; | ||
73 | |||
74 | if (BRW_DEBUG & DEBUG_VERTS) | ||
75 | debug_printf("%s vb[%d] user:%d offset:0x%x sz:0x%x stride:0x%x\n", | ||
76 | __FUNCTION__, i, | ||
77 | brw_buffer_is_user_buffer(vb->buffer), | ||
78 | vb->buffer_offset, | ||
79 | vb->buffer->width0, | ||
80 | vb->stride); | ||
81 | |||
82 | if (brw_buffer_is_user_buffer(vb->buffer)) { | ||
83 | |||
84 | /* XXX: simplify this. Stop the state trackers from generating | ||
85 | * zero-stride buffers & have them use additional constants (or | ||
86 | * add support for >1 constant buffer) instead. | ||
87 | */ | ||
88 | unsigned size = (vb->stride == 0 ? | ||
89 | vb->buffer->width0 - vb->buffer_offset : | ||
90 | MAX2(vb->buffer->width0 - vb->buffer_offset, | ||
91 | vb->stride * (max_index + 1 - min_index))); | ||
92 | boolean flushed; | ||
93 | |||
94 | ret = u_upload_buffer( brw->vb.upload_vertex, | ||
95 | 0, | ||
96 | vb->buffer_offset + min_index * vb->stride, | ||
97 | size, | ||
98 | vb->buffer, | ||
99 | &offset, | ||
100 | &upload_buf, | ||
101 | &flushed ); | ||
102 | if (ret) | ||
103 | return ret; | ||
104 | |||
105 | bo = brw_buffer(upload_buf)->bo; | ||
106 | |||
107 | assert(offset + size <= bo->size); | ||
108 | } | ||
109 | else | ||
110 | { | ||
111 | offset = vb->buffer_offset; | ||
112 | bo = brw_buffer(vb->buffer)->bo; | ||
113 | } | ||
114 | |||
115 | assert(offset < bo->size); | ||
116 | |||
117 | /* Set up post-upload info about this vertex buffer: | ||
118 | */ | ||
119 | brw->vb.vb[i].offset = offset; | ||
120 | brw->vb.vb[i].stride = vb->stride; | ||
121 | brw->vb.vb[i].vertex_count = (vb->stride == 0 ? | ||
122 | 1 : | ||
123 | (bo->size - offset) / vb->stride); | ||
124 | |||
125 | bo_reference( &brw->vb.vb[i].bo, bo ); | ||
126 | |||
127 | /* Don't need to retain this reference. We have a reference on | ||
128 | * the underlying winsys buffer: | ||
129 | */ | ||
130 | pipe_resource_reference( &upload_buf, NULL ); | ||
131 | } | ||
132 | |||
133 | brw->vb.nr_vb = i; | ||
134 | brw_prepare_query_begin(brw); | ||
135 | |||
136 | for (i = 0; i < brw->vb.nr_vb; i++) { | ||
137 | brw_add_validated_bo(brw, brw->vb.vb[i].bo); | ||
138 | } | ||
139 | |||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | static int brw_emit_vertex_buffers( struct brw_context *brw ) | ||
144 | { | ||
145 | int i; | ||
146 | |||
147 | /* If the VS doesn't read any inputs (calculating vertex position from | ||
148 | * a state variable for some reason, for example), just bail. | ||
149 | * | ||
150 | * The stale VB state stays in place, but they don't do anything unless | ||
151 | * a VE loads from them. | ||
152 | */ | ||
153 | if (brw->vb.nr_vb == 0) { | ||
154 | if (BRW_DEBUG & DEBUG_VERTS) | ||
155 | debug_printf("%s: no active vertex buffers\n", __FUNCTION__); | ||
156 | |||
157 | return 0; | ||
158 | } | ||
159 | |||
160 | /* Emit VB state packets. | ||
161 | */ | ||
162 | BEGIN_BATCH(1 + brw->vb.nr_vb * 4, IGNORE_CLIPRECTS); | ||
163 | OUT_BATCH((CMD_VERTEX_BUFFER << 16) | | ||
164 | ((1 + brw->vb.nr_vb * 4) - 2)); | ||
165 | |||
166 | for (i = 0; i < brw->vb.nr_vb; i++) { | ||
167 | OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) | | ||
168 | BRW_VB0_ACCESS_VERTEXDATA | | ||
169 | (brw->vb.vb[i].stride << BRW_VB0_PITCH_SHIFT)); | ||
170 | OUT_RELOC(brw->vb.vb[i].bo, | ||
171 | BRW_USAGE_VERTEX, | ||
172 | brw->vb.vb[i].offset); | ||
173 | if (brw->gen == 5) { | ||
174 | OUT_RELOC(brw->vb.vb[i].bo, | ||
175 | BRW_USAGE_VERTEX, | ||
176 | brw->vb.vb[i].bo->size - 1); | ||
177 | } else | ||
178 | OUT_BATCH(brw->vb.vb[i].stride ? brw->vb.vb[i].vertex_count : 0); | ||
179 | OUT_BATCH(0); /* Instance data step rate */ | ||
180 | } | ||
181 | ADVANCE_BATCH(); | ||
182 | return 0; | ||
183 | } | ||
184 | |||
185 | |||
186 | |||
187 | static int brw_emit_vertex_elements(struct brw_context *brw) | ||
188 | { | ||
189 | const struct brw_vertex_element_packet *brw_velems = brw->curr.velems; | ||
190 | unsigned size = brw_velems->header.length + 2; | ||
191 | |||
192 | /* why is this here */ | ||
193 | brw_emit_query_begin(brw); | ||
194 | |||
195 | brw_batchbuffer_data(brw->batch, brw_velems, size * 4, IGNORE_CLIPRECTS); | ||
196 | |||
197 | return 0; | ||
198 | } | ||
199 | |||
200 | |||
201 | static int brw_emit_vertices( struct brw_context *brw ) | ||
202 | { | ||
203 | int ret; | ||
204 | |||
205 | ret = brw_emit_vertex_buffers( brw ); | ||
206 | if (ret) | ||
207 | return ret; | ||
208 | |||
209 | /* XXX should separate this? */ | ||
210 | ret = brw_emit_vertex_elements( brw ); | ||
211 | if (ret) | ||
212 | return ret; | ||
213 | |||
214 | return 0; | ||
215 | } | ||
216 | |||
217 | |||
218 | const struct brw_tracked_state brw_vertices = { | ||
219 | .dirty = { | ||
220 | .mesa = (PIPE_NEW_INDEX_RANGE | | ||
221 | PIPE_NEW_VERTEX_BUFFER | | ||
222 | PIPE_NEW_VERTEX_ELEMENT), | ||
223 | .brw = BRW_NEW_BATCH, | ||
224 | .cache = 0, | ||
225 | }, | ||
226 | .prepare = brw_prepare_vertices, | ||
227 | .emit = brw_emit_vertices, | ||
228 | }; | ||
229 | |||
230 | |||
231 | static int brw_prepare_indices(struct brw_context *brw) | ||
232 | { | ||
233 | struct pipe_resource *index_buffer = brw->curr.index_buffer; | ||
234 | struct pipe_resource *upload_buf = NULL; | ||
235 | struct brw_winsys_buffer *bo = NULL; | ||
236 | GLuint offset; | ||
237 | GLuint index_size, index_offset; | ||
238 | GLuint ib_size; | ||
239 | int ret; | ||
240 | |||
241 | if (index_buffer == NULL) | ||
242 | return 0; | ||
243 | |||
244 | if (BRW_DEBUG & DEBUG_VERTS) | ||
245 | debug_printf("%s: index_size:%d index_buffer->size:%d\n", | ||
246 | __FUNCTION__, | ||
247 | brw->curr.index_size, | ||
248 | brw->curr.index_buffer->width0); | ||
249 | |||
250 | ib_size = index_buffer->width0; | ||
251 | index_size = brw->curr.index_size; | ||
252 | index_offset = brw->curr.index_offset; | ||
253 | |||
254 | /* Turn userbuffer into a proper hardware buffer? | ||
255 | */ | ||
256 | if (brw_buffer_is_user_buffer(index_buffer)) { | ||
257 | boolean flushed; | ||
258 | |||
259 | ret = u_upload_buffer( brw->vb.upload_index, | ||
260 | 0, | ||
261 | index_offset, | ||
262 | ib_size, | ||
263 | index_buffer, | ||
264 | &offset, | ||
265 | &upload_buf, | ||
266 | &flushed ); | ||
267 | if (ret) | ||
268 | return ret; | ||
269 | |||
270 | bo = brw_buffer(upload_buf)->bo; | ||
271 | |||
272 | /* XXX: annotate the userbuffer with the upload information so | ||
273 | * that successive calls don't get re-uploaded. | ||
274 | */ | ||
275 | } | ||
276 | else { | ||
277 | bo = brw_buffer(index_buffer)->bo; | ||
278 | ib_size = bo->size; | ||
279 | offset = index_offset; | ||
280 | } | ||
281 | |||
282 | /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading the | ||
283 | * index buffer state when we're just moving the start index of our | ||
284 | * drawing. | ||
285 | * | ||
286 | * In gallium this will happen in the case where successive draw | ||
287 | * calls are made with (distinct?) userbuffers, but the upload_mgr | ||
288 | * places the data into a single winsys buffer. | ||
289 | * | ||
290 | * This statechange doesn't raise any state flags and is always | ||
291 | * just merged into the final draw packet: | ||
292 | */ | ||
293 | if (1) { | ||
294 | assert((offset & (index_size - 1)) == 0); | ||
295 | brw->ib.start_vertex_offset = offset / index_size; | ||
296 | } | ||
297 | |||
298 | /* These statechanges trigger a new CMD_INDEX_BUFFER packet: | ||
299 | */ | ||
300 | if (brw->ib.bo != bo || | ||
301 | brw->ib.size != ib_size) | ||
302 | { | ||
303 | bo_reference(&brw->ib.bo, bo); | ||
304 | brw->ib.size = ib_size; | ||
305 | brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER; | ||
306 | } | ||
307 | |||
308 | pipe_resource_reference( &upload_buf, NULL ); | ||
309 | brw_add_validated_bo(brw, brw->ib.bo); | ||
310 | return 0; | ||
311 | } | ||
312 | |||
313 | const struct brw_tracked_state brw_indices = { | ||
314 | .dirty = { | ||
315 | .mesa = PIPE_NEW_INDEX_BUFFER, | ||
316 | .brw = 0, | ||
317 | .cache = 0, | ||
318 | }, | ||
319 | .prepare = brw_prepare_indices, | ||
320 | }; | ||
321 | |||
322 | static int brw_emit_index_buffer(struct brw_context *brw) | ||
323 | { | ||
324 | /* Emit the indexbuffer packet: | ||
325 | */ | ||
326 | if (brw->ib.bo) | ||
327 | { | ||
328 | struct brw_indexbuffer ib; | ||
329 | |||
330 | memset(&ib, 0, sizeof(ib)); | ||
331 | |||
332 | ib.header.bits.opcode = CMD_INDEX_BUFFER; | ||
333 | ib.header.bits.length = sizeof(ib)/4 - 2; | ||
334 | ib.header.bits.index_format = get_index_type(brw->ib.size); | ||
335 | ib.header.bits.cut_index_enable = 0; | ||
336 | |||
337 | BEGIN_BATCH(4, IGNORE_CLIPRECTS); | ||
338 | OUT_BATCH( ib.header.dword ); | ||
339 | OUT_RELOC(brw->ib.bo, | ||
340 | BRW_USAGE_VERTEX, | ||
341 | brw->ib.offset); | ||
342 | OUT_RELOC(brw->ib.bo, | ||
343 | BRW_USAGE_VERTEX, | ||
344 | brw->ib.offset + brw->ib.size - 1); | ||
345 | OUT_BATCH( 0 ); | ||
346 | ADVANCE_BATCH(); | ||
347 | } | ||
348 | |||
349 | return 0; | ||
350 | } | ||
351 | |||
352 | const struct brw_tracked_state brw_index_buffer = { | ||
353 | .dirty = { | ||
354 | .mesa = 0, | ||
355 | .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER, | ||
356 | .cache = 0, | ||
357 | }, | ||
358 | .emit = brw_emit_index_buffer, | ||
359 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_eu.c b/src/gallium/drivers/i965/brw_eu.c deleted file mode 100644 index a8fcb5f97eb..00000000000 --- a/src/gallium/drivers/i965/brw_eu.c +++ /dev/null | |||
@@ -1,262 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_memory.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_defines.h" | ||
36 | #include "brw_eu.h" | ||
37 | |||
38 | |||
39 | |||
40 | /* How does predicate control work when execution_size != 8? Do I | ||
41 | * need to test/set for 0xffff when execution_size is 16? | ||
42 | */ | ||
43 | void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ) | ||
44 | { | ||
45 | p->current->header.predicate_control = BRW_PREDICATE_NONE; | ||
46 | |||
47 | if (value != 0xff) { | ||
48 | if (value != p->flag_value) { | ||
49 | brw_push_insn_state(p); | ||
50 | brw_MOV(p, brw_flag_reg(), brw_imm_uw(value)); | ||
51 | p->flag_value = value; | ||
52 | brw_pop_insn_state(p); | ||
53 | } | ||
54 | |||
55 | p->current->header.predicate_control = BRW_PREDICATE_NORMAL; | ||
56 | } | ||
57 | } | ||
58 | |||
59 | void brw_set_predicate_control( struct brw_compile *p, GLuint pc ) | ||
60 | { | ||
61 | p->current->header.predicate_control = pc; | ||
62 | } | ||
63 | |||
64 | void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ) | ||
65 | { | ||
66 | p->current->header.destreg__conditionalmod = conditional; | ||
67 | } | ||
68 | |||
69 | void brw_set_access_mode( struct brw_compile *p, GLuint access_mode ) | ||
70 | { | ||
71 | p->current->header.access_mode = access_mode; | ||
72 | } | ||
73 | |||
74 | void brw_set_compression_control( struct brw_compile *p, GLboolean compression_control ) | ||
75 | { | ||
76 | p->current->header.compression_control = compression_control; | ||
77 | } | ||
78 | |||
79 | void brw_set_mask_control( struct brw_compile *p, GLuint value ) | ||
80 | { | ||
81 | p->current->header.mask_control = value; | ||
82 | } | ||
83 | |||
84 | void brw_set_saturate( struct brw_compile *p, GLuint value ) | ||
85 | { | ||
86 | p->current->header.saturate = value; | ||
87 | } | ||
88 | |||
89 | void brw_push_insn_state( struct brw_compile *p ) | ||
90 | { | ||
91 | assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); | ||
92 | memcpy(p->current+1, p->current, sizeof(struct brw_instruction)); | ||
93 | p->current++; | ||
94 | } | ||
95 | |||
96 | void brw_pop_insn_state( struct brw_compile *p ) | ||
97 | { | ||
98 | assert(p->current != p->stack); | ||
99 | p->current--; | ||
100 | } | ||
101 | |||
102 | |||
103 | /*********************************************************************** | ||
104 | */ | ||
105 | void brw_init_compile( struct brw_context *brw, struct brw_compile *p ) | ||
106 | { | ||
107 | p->brw = brw; | ||
108 | p->nr_insn = 0; | ||
109 | p->current = p->stack; | ||
110 | memset(p->current, 0, sizeof(p->current[0])); | ||
111 | |||
112 | /* Some defaults? | ||
113 | */ | ||
114 | brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */ | ||
115 | brw_set_saturate(p, 0); | ||
116 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
117 | brw_set_predicate_control_flag_value(p, 0xff); | ||
118 | } | ||
119 | |||
120 | |||
121 | enum pipe_error brw_get_program( struct brw_compile *p, | ||
122 | const GLuint **data, | ||
123 | GLuint *sz ) | ||
124 | { | ||
125 | GLuint i; | ||
126 | |||
127 | for (i = 0; i < 8; i++) | ||
128 | brw_NOP(p); | ||
129 | |||
130 | /* Is the generated program malformed for some reason? | ||
131 | */ | ||
132 | if (p->error) | ||
133 | return PIPE_ERROR_BAD_INPUT; | ||
134 | |||
135 | *sz = p->nr_insn * sizeof(struct brw_instruction); | ||
136 | *data = (const GLuint *)p->store; | ||
137 | return PIPE_OK; | ||
138 | } | ||
139 | |||
140 | |||
141 | |||
142 | /** | ||
143 | * Subroutine calls require special attention. | ||
144 | * Mesa instructions may be expanded into multiple hardware instructions | ||
145 | * so the prog_instruction::BranchTarget field can't be used as an index | ||
146 | * into the hardware instructions. | ||
147 | * | ||
148 | * The BranchTarget field isn't needed, however. Mesa's GLSL compiler | ||
149 | * emits CAL and BGNSUB instructions with labels that can be used to map | ||
150 | * subroutine calls to actual subroutine code blocks. | ||
151 | * | ||
152 | * The structures and function here implement patching of CAL instructions | ||
153 | * so they jump to the right subroutine code... | ||
154 | */ | ||
155 | |||
156 | |||
157 | /** | ||
158 | * For each OPCODE_BGNSUB we create one of these. | ||
159 | */ | ||
160 | struct brw_eu_label | ||
161 | { | ||
162 | GLuint label; /**< the label number */ | ||
163 | GLuint position; /**< the position of the brw instruction for this label */ | ||
164 | struct brw_eu_label *next; /**< next in linked list */ | ||
165 | }; | ||
166 | |||
167 | |||
168 | /** | ||
169 | * For each OPCODE_CAL we create one of these. | ||
170 | */ | ||
171 | struct brw_eu_call | ||
172 | { | ||
173 | GLuint call_inst_pos; /**< location of the CAL instruction */ | ||
174 | GLuint label; | ||
175 | struct brw_eu_call *next; /**< next in linked list */ | ||
176 | }; | ||
177 | |||
178 | |||
179 | /** | ||
180 | * Called for each OPCODE_BGNSUB. | ||
181 | */ | ||
182 | void | ||
183 | brw_save_label(struct brw_compile *c, unsigned l, GLuint position) | ||
184 | { | ||
185 | struct brw_eu_label *label = CALLOC_STRUCT(brw_eu_label); | ||
186 | label->label = l; | ||
187 | label->position = position; | ||
188 | label->next = c->first_label; | ||
189 | c->first_label = label; | ||
190 | } | ||
191 | |||
192 | |||
193 | /** | ||
194 | * Called for each OPCODE_CAL. | ||
195 | */ | ||
196 | void | ||
197 | brw_save_call(struct brw_compile *c, GLuint label, GLuint call_pos) | ||
198 | { | ||
199 | struct brw_eu_call *call = CALLOC_STRUCT(brw_eu_call); | ||
200 | call->call_inst_pos = call_pos; | ||
201 | call->label = label; | ||
202 | call->next = c->first_call; | ||
203 | c->first_call = call; | ||
204 | } | ||
205 | |||
206 | |||
207 | /** | ||
208 | * Lookup a label, return label's position/offset. | ||
209 | */ | ||
210 | static GLuint | ||
211 | brw_lookup_label(struct brw_compile *c, unsigned l) | ||
212 | { | ||
213 | const struct brw_eu_label *label; | ||
214 | for (label = c->first_label; label; label = label->next) { | ||
215 | if (l == label->label) { | ||
216 | return label->position; | ||
217 | } | ||
218 | } | ||
219 | abort(); /* should never happen */ | ||
220 | return ~0; | ||
221 | } | ||
222 | |||
223 | |||
224 | /** | ||
225 | * When we're done generating code, this function is called to resolve | ||
226 | * subroutine calls. | ||
227 | */ | ||
228 | void | ||
229 | brw_resolve_cals(struct brw_compile *c) | ||
230 | { | ||
231 | const struct brw_eu_call *call; | ||
232 | |||
233 | for (call = c->first_call; call; call = call->next) { | ||
234 | const GLuint sub_loc = brw_lookup_label(c, call->label); | ||
235 | struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos]; | ||
236 | struct brw_instruction *brw_sub_inst = &c->store[sub_loc]; | ||
237 | GLint offset = brw_sub_inst - brw_call_inst; | ||
238 | |||
239 | /* patch brw_inst1 to point to brw_inst2 */ | ||
240 | brw_set_src1(brw_call_inst, brw_imm_d(offset * 16)); | ||
241 | } | ||
242 | |||
243 | /* free linked list of calls */ | ||
244 | { | ||
245 | struct brw_eu_call *call, *next; | ||
246 | for (call = c->first_call; call; call = next) { | ||
247 | next = call->next; | ||
248 | FREE(call); | ||
249 | } | ||
250 | c->first_call = NULL; | ||
251 | } | ||
252 | |||
253 | /* free linked list of labels */ | ||
254 | { | ||
255 | struct brw_eu_label *label, *next; | ||
256 | for (label = c->first_label; label; label = next) { | ||
257 | next = label->next; | ||
258 | FREE(label); | ||
259 | } | ||
260 | c->first_label = NULL; | ||
261 | } | ||
262 | } | ||
diff --git a/src/gallium/drivers/i965/brw_eu.h b/src/gallium/drivers/i965/brw_eu.h deleted file mode 100644 index af509b2e5f4..00000000000 --- a/src/gallium/drivers/i965/brw_eu.h +++ /dev/null | |||
@@ -1,992 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_EU_H | ||
34 | #define BRW_EU_H | ||
35 | |||
36 | #include "util/u_debug.h" | ||
37 | #include "pipe/p_defines.h" | ||
38 | |||
39 | #include "brw_structs.h" | ||
40 | #include "brw_defines.h" | ||
41 | |||
42 | #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6)) | ||
43 | #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3) | ||
44 | |||
45 | #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3) | ||
46 | #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) | ||
47 | #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0) | ||
48 | #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1) | ||
49 | |||
50 | #define BRW_WRITEMASK_NONE 0x00 | ||
51 | #define BRW_WRITEMASK_X 0x01 | ||
52 | #define BRW_WRITEMASK_Y 0x02 | ||
53 | #define BRW_WRITEMASK_XY 0x03 | ||
54 | #define BRW_WRITEMASK_Z 0x04 | ||
55 | #define BRW_WRITEMASK_XZ 0x05 | ||
56 | #define BRW_WRITEMASK_YZ 0x06 | ||
57 | #define BRW_WRITEMASK_XYZ 0x07 | ||
58 | #define BRW_WRITEMASK_W 0x08 | ||
59 | #define BRW_WRITEMASK_XW 0x09 | ||
60 | #define BRW_WRITEMASK_YW 0x0A | ||
61 | #define BRW_WRITEMASK_XYW 0x0B | ||
62 | #define BRW_WRITEMASK_ZW 0x0C | ||
63 | #define BRW_WRITEMASK_XZW 0x0D | ||
64 | #define BRW_WRITEMASK_YZW 0x0E | ||
65 | #define BRW_WRITEMASK_XYZW 0x0F | ||
66 | |||
67 | |||
68 | #define REG_SIZE (8*4) | ||
69 | |||
70 | |||
71 | /* These aren't hardware structs, just something useful for us to pass around: | ||
72 | * | ||
73 | * Align1 operation has a lot of control over input ranges. Used in | ||
74 | * WM programs to implement shaders decomposed into "channel serial" | ||
75 | * or "structure of array" form: | ||
76 | */ | ||
77 | struct brw_reg | ||
78 | { | ||
79 | GLuint type:4; | ||
80 | GLuint file:2; | ||
81 | GLuint nr:8; | ||
82 | GLuint subnr:5; /* :1 in align16 */ | ||
83 | GLuint negate:1; /* source only */ | ||
84 | GLuint abs:1; /* source only */ | ||
85 | GLuint vstride:4; /* source only */ | ||
86 | GLuint width:3; /* src only, align1 only */ | ||
87 | GLuint hstride:2; /* align1 only */ | ||
88 | GLuint address_mode:1; /* relative addressing, hopefully! */ | ||
89 | GLuint pad0:1; | ||
90 | |||
91 | union { | ||
92 | struct { | ||
93 | GLuint swizzle:8; /* src only, align16 only */ | ||
94 | GLuint writemask:4; /* dest only, align16 only */ | ||
95 | GLint indirect_offset:10; /* relative addressing offset */ | ||
96 | GLuint pad1:10; /* two dwords total */ | ||
97 | } bits; | ||
98 | |||
99 | GLfloat f; | ||
100 | GLint d; | ||
101 | GLuint ud; | ||
102 | } dw1; | ||
103 | }; | ||
104 | |||
105 | |||
106 | struct brw_indirect { | ||
107 | GLuint addr_subnr:4; | ||
108 | GLint addr_offset:10; | ||
109 | GLuint pad:18; | ||
110 | }; | ||
111 | |||
112 | |||
113 | struct brw_eu_label; | ||
114 | struct brw_eu_call; | ||
115 | |||
116 | |||
117 | |||
118 | #define BRW_EU_MAX_INSN_STACK 5 | ||
119 | #define BRW_EU_MAX_INSN 10000 | ||
120 | |||
121 | struct brw_compile { | ||
122 | struct brw_instruction store[BRW_EU_MAX_INSN]; | ||
123 | GLuint nr_insn; | ||
124 | |||
125 | /* Allow clients to push/pop instruction state: | ||
126 | */ | ||
127 | struct brw_instruction stack[BRW_EU_MAX_INSN_STACK]; | ||
128 | struct brw_instruction *current; | ||
129 | |||
130 | GLuint flag_value; | ||
131 | GLboolean single_program_flow; | ||
132 | struct brw_context *brw; | ||
133 | |||
134 | struct brw_eu_label *first_label; /**< linked list of labels */ | ||
135 | struct brw_eu_call *first_call; /**< linked list of CALs */ | ||
136 | |||
137 | boolean error; | ||
138 | }; | ||
139 | |||
140 | |||
141 | void | ||
142 | brw_save_label(struct brw_compile *c, unsigned label, GLuint position); | ||
143 | |||
144 | void | ||
145 | brw_save_call(struct brw_compile *c, unsigned label, GLuint call_pos); | ||
146 | |||
147 | void | ||
148 | brw_resolve_cals(struct brw_compile *c); | ||
149 | |||
150 | |||
151 | |||
152 | static INLINE int type_sz( GLuint type ) | ||
153 | { | ||
154 | switch( type ) { | ||
155 | case BRW_REGISTER_TYPE_UD: | ||
156 | case BRW_REGISTER_TYPE_D: | ||
157 | case BRW_REGISTER_TYPE_F: | ||
158 | return 4; | ||
159 | case BRW_REGISTER_TYPE_HF: | ||
160 | case BRW_REGISTER_TYPE_UW: | ||
161 | case BRW_REGISTER_TYPE_W: | ||
162 | return 2; | ||
163 | case BRW_REGISTER_TYPE_UB: | ||
164 | case BRW_REGISTER_TYPE_B: | ||
165 | return 1; | ||
166 | default: | ||
167 | return 0; | ||
168 | } | ||
169 | } | ||
170 | |||
171 | /** | ||
172 | * Construct a brw_reg. | ||
173 | * \param file one of the BRW_x_REGISTER_FILE values | ||
174 | * \param nr register number/index | ||
175 | * \param subnr register sub number | ||
176 | * \param type one of BRW_REGISTER_TYPE_x | ||
177 | * \param vstride one of BRW_VERTICAL_STRIDE_x | ||
178 | * \param width one of BRW_WIDTH_x | ||
179 | * \param hstride one of BRW_HORIZONTAL_STRIDE_x | ||
180 | * \param swizzle one of BRW_SWIZZLE_x | ||
181 | * \param writemask BRW_WRITEMASK_X/Y/Z/W bitfield | ||
182 | */ | ||
183 | static INLINE struct brw_reg brw_reg( GLuint file, | ||
184 | GLuint nr, | ||
185 | GLuint subnr, | ||
186 | GLuint type, | ||
187 | GLuint vstride, | ||
188 | GLuint width, | ||
189 | GLuint hstride, | ||
190 | GLuint swizzle, | ||
191 | GLuint writemask ) | ||
192 | { | ||
193 | struct brw_reg reg; | ||
194 | if (type == BRW_GENERAL_REGISTER_FILE) | ||
195 | assert(nr < BRW_MAX_GRF); | ||
196 | else if (type == BRW_MESSAGE_REGISTER_FILE) | ||
197 | assert(nr < BRW_MAX_MRF); | ||
198 | else if (type == BRW_ARCHITECTURE_REGISTER_FILE) | ||
199 | assert(nr <= BRW_ARF_IP); | ||
200 | |||
201 | reg.type = type; | ||
202 | reg.file = file; | ||
203 | reg.nr = nr; | ||
204 | reg.subnr = subnr * type_sz(type); | ||
205 | reg.negate = 0; | ||
206 | reg.abs = 0; | ||
207 | reg.vstride = vstride; | ||
208 | reg.width = width; | ||
209 | reg.hstride = hstride; | ||
210 | reg.address_mode = BRW_ADDRESS_DIRECT; | ||
211 | reg.pad0 = 0; | ||
212 | |||
213 | /* Could do better: If the reg is r5.3<0;1,0>, we probably want to | ||
214 | * set swizzle and writemask to W, as the lower bits of subnr will | ||
215 | * be lost when converted to align16. This is probably too much to | ||
216 | * keep track of as you'd want it adjusted by suboffset(), etc. | ||
217 | * Perhaps fix up when converting to align16? | ||
218 | */ | ||
219 | reg.dw1.bits.swizzle = swizzle; | ||
220 | reg.dw1.bits.writemask = writemask; | ||
221 | reg.dw1.bits.indirect_offset = 0; | ||
222 | reg.dw1.bits.pad1 = 0; | ||
223 | return reg; | ||
224 | } | ||
225 | |||
226 | /** Construct float[16] register */ | ||
227 | static INLINE struct brw_reg brw_vec16_reg( GLuint file, | ||
228 | GLuint nr, | ||
229 | GLuint subnr ) | ||
230 | { | ||
231 | return brw_reg(file, | ||
232 | nr, | ||
233 | subnr, | ||
234 | BRW_REGISTER_TYPE_F, | ||
235 | BRW_VERTICAL_STRIDE_16, | ||
236 | BRW_WIDTH_16, | ||
237 | BRW_HORIZONTAL_STRIDE_1, | ||
238 | BRW_SWIZZLE_XYZW, | ||
239 | BRW_WRITEMASK_XYZW); | ||
240 | } | ||
241 | |||
242 | /** Construct float[8] register */ | ||
243 | static INLINE struct brw_reg brw_vec8_reg( GLuint file, | ||
244 | GLuint nr, | ||
245 | GLuint subnr ) | ||
246 | { | ||
247 | return brw_reg(file, | ||
248 | nr, | ||
249 | subnr, | ||
250 | BRW_REGISTER_TYPE_F, | ||
251 | BRW_VERTICAL_STRIDE_8, | ||
252 | BRW_WIDTH_8, | ||
253 | BRW_HORIZONTAL_STRIDE_1, | ||
254 | BRW_SWIZZLE_XYZW, | ||
255 | BRW_WRITEMASK_XYZW); | ||
256 | } | ||
257 | |||
258 | /** Construct float[4] register */ | ||
259 | static INLINE struct brw_reg brw_vec4_reg( GLuint file, | ||
260 | GLuint nr, | ||
261 | GLuint subnr ) | ||
262 | { | ||
263 | return brw_reg(file, | ||
264 | nr, | ||
265 | subnr, | ||
266 | BRW_REGISTER_TYPE_F, | ||
267 | BRW_VERTICAL_STRIDE_4, | ||
268 | BRW_WIDTH_4, | ||
269 | BRW_HORIZONTAL_STRIDE_1, | ||
270 | BRW_SWIZZLE_XYZW, | ||
271 | BRW_WRITEMASK_XYZW); | ||
272 | } | ||
273 | |||
274 | /** Construct float[2] register */ | ||
275 | static INLINE struct brw_reg brw_vec2_reg( GLuint file, | ||
276 | GLuint nr, | ||
277 | GLuint subnr ) | ||
278 | { | ||
279 | return brw_reg(file, | ||
280 | nr, | ||
281 | subnr, | ||
282 | BRW_REGISTER_TYPE_F, | ||
283 | BRW_VERTICAL_STRIDE_2, | ||
284 | BRW_WIDTH_2, | ||
285 | BRW_HORIZONTAL_STRIDE_1, | ||
286 | BRW_SWIZZLE_XYXY, | ||
287 | BRW_WRITEMASK_XY); | ||
288 | } | ||
289 | |||
290 | /** Construct float[1] register */ | ||
291 | static INLINE struct brw_reg brw_vec1_reg( GLuint file, | ||
292 | GLuint nr, | ||
293 | GLuint subnr ) | ||
294 | { | ||
295 | return brw_reg(file, | ||
296 | nr, | ||
297 | subnr, | ||
298 | BRW_REGISTER_TYPE_F, | ||
299 | BRW_VERTICAL_STRIDE_0, | ||
300 | BRW_WIDTH_1, | ||
301 | BRW_HORIZONTAL_STRIDE_0, | ||
302 | BRW_SWIZZLE_XXXX, | ||
303 | BRW_WRITEMASK_X); | ||
304 | } | ||
305 | |||
306 | |||
307 | static INLINE struct brw_reg retype( struct brw_reg reg, | ||
308 | GLuint type ) | ||
309 | { | ||
310 | reg.type = type; | ||
311 | return reg; | ||
312 | } | ||
313 | |||
314 | static INLINE struct brw_reg suboffset( struct brw_reg reg, | ||
315 | GLuint delta ) | ||
316 | { | ||
317 | reg.subnr += delta * type_sz(reg.type); | ||
318 | return reg; | ||
319 | } | ||
320 | |||
321 | |||
322 | static INLINE struct brw_reg offset( struct brw_reg reg, | ||
323 | GLuint delta ) | ||
324 | { | ||
325 | reg.nr += delta; | ||
326 | return reg; | ||
327 | } | ||
328 | |||
329 | |||
330 | static INLINE struct brw_reg byte_offset( struct brw_reg reg, | ||
331 | GLuint bytes ) | ||
332 | { | ||
333 | GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes; | ||
334 | reg.nr = newoffset / REG_SIZE; | ||
335 | reg.subnr = newoffset % REG_SIZE; | ||
336 | return reg; | ||
337 | } | ||
338 | |||
339 | |||
340 | /** Construct unsigned word[16] register */ | ||
341 | static INLINE struct brw_reg brw_uw16_reg( GLuint file, | ||
342 | GLuint nr, | ||
343 | GLuint subnr ) | ||
344 | { | ||
345 | return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); | ||
346 | } | ||
347 | |||
348 | /** Construct unsigned word[8] register */ | ||
349 | static INLINE struct brw_reg brw_uw8_reg( GLuint file, | ||
350 | GLuint nr, | ||
351 | GLuint subnr ) | ||
352 | { | ||
353 | return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); | ||
354 | } | ||
355 | |||
356 | /** Construct unsigned word[1] register */ | ||
357 | static INLINE struct brw_reg brw_uw1_reg( GLuint file, | ||
358 | GLuint nr, | ||
359 | GLuint subnr ) | ||
360 | { | ||
361 | return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr); | ||
362 | } | ||
363 | |||
364 | static INLINE struct brw_reg brw_imm_reg( GLuint type ) | ||
365 | { | ||
366 | return brw_reg( BRW_IMMEDIATE_VALUE, | ||
367 | 0, | ||
368 | 0, | ||
369 | type, | ||
370 | BRW_VERTICAL_STRIDE_0, | ||
371 | BRW_WIDTH_1, | ||
372 | BRW_HORIZONTAL_STRIDE_0, | ||
373 | 0, | ||
374 | 0); | ||
375 | } | ||
376 | |||
377 | /** Construct float immediate register */ | ||
378 | static INLINE struct brw_reg brw_imm_f( GLfloat f ) | ||
379 | { | ||
380 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); | ||
381 | imm.dw1.f = f; | ||
382 | return imm; | ||
383 | } | ||
384 | |||
385 | /** Construct integer immediate register */ | ||
386 | static INLINE struct brw_reg brw_imm_d( GLint d ) | ||
387 | { | ||
388 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); | ||
389 | imm.dw1.d = d; | ||
390 | return imm; | ||
391 | } | ||
392 | |||
393 | /** Construct uint immediate register */ | ||
394 | static INLINE struct brw_reg brw_imm_ud( GLuint ud ) | ||
395 | { | ||
396 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); | ||
397 | imm.dw1.ud = ud; | ||
398 | return imm; | ||
399 | } | ||
400 | |||
401 | /** Construct ushort immediate register */ | ||
402 | static INLINE struct brw_reg brw_imm_uw( GLushort uw ) | ||
403 | { | ||
404 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); | ||
405 | imm.dw1.ud = uw | (uw << 16); | ||
406 | return imm; | ||
407 | } | ||
408 | |||
409 | /** Construct short immediate register */ | ||
410 | static INLINE struct brw_reg brw_imm_w( GLshort w ) | ||
411 | { | ||
412 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); | ||
413 | imm.dw1.d = w | (w << 16); | ||
414 | return imm; | ||
415 | } | ||
416 | |||
417 | /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type | ||
418 | * numbers alias with _V and _VF below: | ||
419 | */ | ||
420 | |||
421 | /** Construct vector of eight signed half-byte values */ | ||
422 | static INLINE struct brw_reg brw_imm_v( GLuint v ) | ||
423 | { | ||
424 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V); | ||
425 | imm.vstride = BRW_VERTICAL_STRIDE_0; | ||
426 | imm.width = BRW_WIDTH_8; | ||
427 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; | ||
428 | imm.dw1.ud = v; | ||
429 | return imm; | ||
430 | } | ||
431 | |||
432 | /** Construct vector of four 8-bit float values */ | ||
433 | static INLINE struct brw_reg brw_imm_vf( GLuint v ) | ||
434 | { | ||
435 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); | ||
436 | imm.vstride = BRW_VERTICAL_STRIDE_0; | ||
437 | imm.width = BRW_WIDTH_4; | ||
438 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; | ||
439 | imm.dw1.ud = v; | ||
440 | return imm; | ||
441 | } | ||
442 | |||
443 | #define VF_ZERO 0x0 | ||
444 | #define VF_ONE 0x30 | ||
445 | #define VF_NEG (1<<7) | ||
446 | |||
447 | static INLINE struct brw_reg brw_imm_vf4( GLuint v0, | ||
448 | GLuint v1, | ||
449 | GLuint v2, | ||
450 | GLuint v3) | ||
451 | { | ||
452 | struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF); | ||
453 | imm.vstride = BRW_VERTICAL_STRIDE_0; | ||
454 | imm.width = BRW_WIDTH_4; | ||
455 | imm.hstride = BRW_HORIZONTAL_STRIDE_1; | ||
456 | imm.dw1.ud = ((v0 << 0) | | ||
457 | (v1 << 8) | | ||
458 | (v2 << 16) | | ||
459 | (v3 << 24)); | ||
460 | return imm; | ||
461 | } | ||
462 | |||
463 | |||
464 | static INLINE struct brw_reg brw_address( struct brw_reg reg ) | ||
465 | { | ||
466 | return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr); | ||
467 | } | ||
468 | |||
469 | /** Construct float[1] general-purpose register */ | ||
470 | static INLINE struct brw_reg brw_vec1_grf( GLuint nr, GLuint subnr ) | ||
471 | { | ||
472 | return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
473 | } | ||
474 | |||
475 | /** Construct float[2] general-purpose register */ | ||
476 | static INLINE struct brw_reg brw_vec2_grf( GLuint nr, GLuint subnr ) | ||
477 | { | ||
478 | return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
479 | } | ||
480 | |||
481 | /** Construct float[4] general-purpose register */ | ||
482 | static INLINE struct brw_reg brw_vec4_grf( GLuint nr, GLuint subnr ) | ||
483 | { | ||
484 | return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
485 | } | ||
486 | |||
487 | /** Construct float[8] general-purpose register */ | ||
488 | static INLINE struct brw_reg brw_vec8_grf( GLuint nr, GLuint subnr ) | ||
489 | { | ||
490 | return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
491 | } | ||
492 | |||
493 | |||
494 | static INLINE struct brw_reg brw_uw8_grf( GLuint nr, GLuint subnr ) | ||
495 | { | ||
496 | return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
497 | } | ||
498 | |||
499 | static INLINE struct brw_reg brw_uw16_grf( GLuint nr, GLuint subnr ) | ||
500 | { | ||
501 | return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr); | ||
502 | } | ||
503 | |||
504 | |||
505 | /** Construct null register (usually used for setting condition codes) */ | ||
506 | static INLINE struct brw_reg brw_null_reg( void ) | ||
507 | { | ||
508 | return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
509 | BRW_ARF_NULL, | ||
510 | 0); | ||
511 | } | ||
512 | |||
513 | static INLINE struct brw_reg brw_address_reg( GLuint subnr ) | ||
514 | { | ||
515 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
516 | BRW_ARF_ADDRESS, | ||
517 | subnr); | ||
518 | } | ||
519 | |||
520 | /* If/else instructions break in align16 mode if writemask & swizzle | ||
521 | * aren't xyzw. This goes against the convention for other scalar | ||
522 | * regs: | ||
523 | */ | ||
524 | static INLINE struct brw_reg brw_ip_reg( void ) | ||
525 | { | ||
526 | return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
527 | BRW_ARF_IP, | ||
528 | 0, | ||
529 | BRW_REGISTER_TYPE_UD, | ||
530 | BRW_VERTICAL_STRIDE_4, /* ? */ | ||
531 | BRW_WIDTH_1, | ||
532 | BRW_HORIZONTAL_STRIDE_0, | ||
533 | BRW_SWIZZLE_XYZW, /* NOTE! */ | ||
534 | BRW_WRITEMASK_XYZW); /* NOTE! */ | ||
535 | } | ||
536 | |||
537 | static INLINE struct brw_reg brw_acc_reg( void ) | ||
538 | { | ||
539 | return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
540 | BRW_ARF_ACCUMULATOR, | ||
541 | 0); | ||
542 | } | ||
543 | |||
544 | |||
545 | static INLINE struct brw_reg brw_flag_reg( void ) | ||
546 | { | ||
547 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
548 | BRW_ARF_FLAG, | ||
549 | 0); | ||
550 | } | ||
551 | |||
552 | |||
553 | static INLINE struct brw_reg brw_mask_reg( GLuint subnr ) | ||
554 | { | ||
555 | return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
556 | BRW_ARF_MASK, | ||
557 | subnr); | ||
558 | } | ||
559 | |||
560 | static INLINE struct brw_reg brw_message_reg( GLuint nr ) | ||
561 | { | ||
562 | assert(nr < BRW_MAX_MRF); | ||
563 | return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, | ||
564 | nr, | ||
565 | 0); | ||
566 | } | ||
567 | |||
568 | |||
569 | |||
570 | |||
571 | /* This is almost always called with a numeric constant argument, so | ||
572 | * make things easy to evaluate at compile time: | ||
573 | */ | ||
574 | static INLINE GLuint cvt( GLuint val ) | ||
575 | { | ||
576 | switch (val) { | ||
577 | case 0: return 0; | ||
578 | case 1: return 1; | ||
579 | case 2: return 2; | ||
580 | case 4: return 3; | ||
581 | case 8: return 4; | ||
582 | case 16: return 5; | ||
583 | case 32: return 6; | ||
584 | } | ||
585 | return 0; | ||
586 | } | ||
587 | |||
588 | static INLINE struct brw_reg stride( struct brw_reg reg, | ||
589 | GLuint vstride, | ||
590 | GLuint width, | ||
591 | GLuint hstride ) | ||
592 | { | ||
593 | reg.vstride = cvt(vstride); | ||
594 | reg.width = cvt(width) - 1; | ||
595 | reg.hstride = cvt(hstride); | ||
596 | return reg; | ||
597 | } | ||
598 | |||
599 | |||
600 | static INLINE struct brw_reg vec16( struct brw_reg reg ) | ||
601 | { | ||
602 | return stride(reg, 16,16,1); | ||
603 | } | ||
604 | |||
605 | static INLINE struct brw_reg vec8( struct brw_reg reg ) | ||
606 | { | ||
607 | return stride(reg, 8,8,1); | ||
608 | } | ||
609 | |||
610 | static INLINE struct brw_reg vec4( struct brw_reg reg ) | ||
611 | { | ||
612 | return stride(reg, 4,4,1); | ||
613 | } | ||
614 | |||
615 | static INLINE struct brw_reg vec2( struct brw_reg reg ) | ||
616 | { | ||
617 | return stride(reg, 2,2,1); | ||
618 | } | ||
619 | |||
620 | static INLINE struct brw_reg vec1( struct brw_reg reg ) | ||
621 | { | ||
622 | return stride(reg, 0,1,0); | ||
623 | } | ||
624 | |||
625 | |||
626 | static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt ) | ||
627 | { | ||
628 | return vec1(suboffset(reg, elt)); | ||
629 | } | ||
630 | |||
631 | static INLINE struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt ) | ||
632 | { | ||
633 | return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt)); | ||
634 | } | ||
635 | |||
636 | |||
637 | static INLINE struct brw_reg brw_swizzle( struct brw_reg reg, | ||
638 | GLuint x, | ||
639 | GLuint y, | ||
640 | GLuint z, | ||
641 | GLuint w) | ||
642 | { | ||
643 | reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x), | ||
644 | BRW_GET_SWZ(reg.dw1.bits.swizzle, y), | ||
645 | BRW_GET_SWZ(reg.dw1.bits.swizzle, z), | ||
646 | BRW_GET_SWZ(reg.dw1.bits.swizzle, w)); | ||
647 | return reg; | ||
648 | } | ||
649 | |||
650 | |||
651 | static INLINE struct brw_reg brw_swizzle1( struct brw_reg reg, | ||
652 | GLuint x ) | ||
653 | { | ||
654 | return brw_swizzle(reg, x, x, x, x); | ||
655 | } | ||
656 | |||
657 | static INLINE struct brw_reg brw_writemask( struct brw_reg reg, | ||
658 | GLuint mask ) | ||
659 | { | ||
660 | reg.dw1.bits.writemask &= mask; | ||
661 | return reg; | ||
662 | } | ||
663 | |||
664 | static INLINE struct brw_reg brw_set_writemask( struct brw_reg reg, | ||
665 | GLuint mask ) | ||
666 | { | ||
667 | reg.dw1.bits.writemask = mask; | ||
668 | return reg; | ||
669 | } | ||
670 | |||
671 | static INLINE struct brw_reg negate( struct brw_reg reg ) | ||
672 | { | ||
673 | reg.negate ^= 1; | ||
674 | return reg; | ||
675 | } | ||
676 | |||
677 | static INLINE struct brw_reg brw_abs( struct brw_reg reg ) | ||
678 | { | ||
679 | reg.abs = 1; | ||
680 | return reg; | ||
681 | } | ||
682 | |||
683 | /*********************************************************************** | ||
684 | */ | ||
685 | static INLINE struct brw_reg brw_vec4_indirect( GLuint subnr, | ||
686 | GLint offset ) | ||
687 | { | ||
688 | struct brw_reg reg = brw_vec4_grf(0, 0); | ||
689 | reg.subnr = subnr; | ||
690 | reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; | ||
691 | reg.dw1.bits.indirect_offset = offset; | ||
692 | return reg; | ||
693 | } | ||
694 | |||
695 | static INLINE struct brw_reg brw_vec1_indirect( GLuint subnr, | ||
696 | GLint offset ) | ||
697 | { | ||
698 | struct brw_reg reg = brw_vec1_grf(0, 0); | ||
699 | reg.subnr = subnr; | ||
700 | reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; | ||
701 | reg.dw1.bits.indirect_offset = offset; | ||
702 | return reg; | ||
703 | } | ||
704 | |||
705 | static INLINE struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset) | ||
706 | { | ||
707 | return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset); | ||
708 | } | ||
709 | |||
710 | static INLINE struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset) | ||
711 | { | ||
712 | return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset); | ||
713 | } | ||
714 | |||
715 | static INLINE struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset) | ||
716 | { | ||
717 | return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B); | ||
718 | } | ||
719 | |||
720 | static INLINE struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset) | ||
721 | { | ||
722 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW); | ||
723 | } | ||
724 | |||
725 | static INLINE struct brw_reg deref_1d(struct brw_indirect ptr, GLint offset) | ||
726 | { | ||
727 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D); | ||
728 | } | ||
729 | |||
730 | static INLINE struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset) | ||
731 | { | ||
732 | return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD); | ||
733 | } | ||
734 | |||
735 | static INLINE struct brw_reg get_addr_reg(struct brw_indirect ptr) | ||
736 | { | ||
737 | return brw_address_reg(ptr.addr_subnr); | ||
738 | } | ||
739 | |||
740 | static INLINE struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset ) | ||
741 | { | ||
742 | ptr.addr_offset += offset; | ||
743 | return ptr; | ||
744 | } | ||
745 | |||
746 | static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset ) | ||
747 | { | ||
748 | struct brw_indirect ptr; | ||
749 | ptr.addr_subnr = addr_subnr; | ||
750 | ptr.addr_offset = offset; | ||
751 | ptr.pad = 0; | ||
752 | return ptr; | ||
753 | } | ||
754 | |||
755 | /** Do two brw_regs refer to the same register? */ | ||
756 | static INLINE GLboolean | ||
757 | brw_same_reg(struct brw_reg r1, struct brw_reg r2) | ||
758 | { | ||
759 | return r1.file == r2.file && r1.nr == r2.nr; | ||
760 | } | ||
761 | |||
762 | static INLINE struct brw_instruction *current_insn( struct brw_compile *p) | ||
763 | { | ||
764 | return &p->store[p->nr_insn]; | ||
765 | } | ||
766 | |||
767 | void brw_pop_insn_state( struct brw_compile *p ); | ||
768 | void brw_push_insn_state( struct brw_compile *p ); | ||
769 | void brw_set_mask_control( struct brw_compile *p, GLuint value ); | ||
770 | void brw_set_saturate( struct brw_compile *p, GLuint value ); | ||
771 | void brw_set_access_mode( struct brw_compile *p, GLuint access_mode ); | ||
772 | void brw_set_compression_control( struct brw_compile *p, GLboolean control ); | ||
773 | void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ); | ||
774 | void brw_set_predicate_control( struct brw_compile *p, GLuint pc ); | ||
775 | void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ); | ||
776 | |||
777 | void brw_init_compile( struct brw_context *, struct brw_compile *p ); | ||
778 | |||
779 | enum pipe_error brw_get_program( struct brw_compile *p, | ||
780 | const GLuint **program, | ||
781 | GLuint *sz ); | ||
782 | |||
783 | |||
784 | /* Helpers for regular instructions: | ||
785 | */ | ||
786 | #define ALU1(OP) \ | ||
787 | struct brw_instruction *brw_##OP(struct brw_compile *p, \ | ||
788 | struct brw_reg dest, \ | ||
789 | struct brw_reg src0); | ||
790 | |||
791 | #define ALU2(OP) \ | ||
792 | struct brw_instruction *brw_##OP(struct brw_compile *p, \ | ||
793 | struct brw_reg dest, \ | ||
794 | struct brw_reg src0, \ | ||
795 | struct brw_reg src1); | ||
796 | |||
797 | ALU1(MOV) | ||
798 | ALU2(SEL) | ||
799 | ALU1(NOT) | ||
800 | ALU2(AND) | ||
801 | ALU2(OR) | ||
802 | ALU2(XOR) | ||
803 | ALU2(SHR) | ||
804 | ALU2(SHL) | ||
805 | ALU2(RSR) | ||
806 | ALU2(RSL) | ||
807 | ALU2(ASR) | ||
808 | ALU2(JMPI) | ||
809 | ALU2(ADD) | ||
810 | ALU2(MUL) | ||
811 | ALU1(FRC) | ||
812 | ALU1(RNDD) | ||
813 | ALU1(RNDZ) | ||
814 | ALU2(MAC) | ||
815 | ALU2(MACH) | ||
816 | ALU1(LZD) | ||
817 | ALU2(DP4) | ||
818 | ALU2(DPH) | ||
819 | ALU2(DP3) | ||
820 | ALU2(DP2) | ||
821 | ALU2(LINE) | ||
822 | |||
823 | #undef ALU1 | ||
824 | #undef ALU2 | ||
825 | |||
826 | |||
827 | |||
828 | /* Helpers for SEND instruction: | ||
829 | */ | ||
830 | void brw_urb_WRITE(struct brw_compile *p, | ||
831 | struct brw_reg dest, | ||
832 | GLuint msg_reg_nr, | ||
833 | struct brw_reg src0, | ||
834 | GLboolean allocate, | ||
835 | GLboolean used, | ||
836 | GLuint msg_length, | ||
837 | GLuint response_length, | ||
838 | GLboolean eot, | ||
839 | GLboolean writes_complete, | ||
840 | GLuint offset, | ||
841 | GLuint swizzle); | ||
842 | |||
843 | void brw_ff_sync(struct brw_compile *p, | ||
844 | struct brw_reg dest, | ||
845 | GLuint msg_reg_nr, | ||
846 | struct brw_reg src0, | ||
847 | GLboolean allocate, | ||
848 | GLboolean used, | ||
849 | GLuint msg_length, | ||
850 | GLuint response_length, | ||
851 | GLboolean eot, | ||
852 | GLboolean writes_complete, | ||
853 | GLuint offset, | ||
854 | GLuint swizzle); | ||
855 | |||
856 | void brw_fb_WRITE(struct brw_compile *p, | ||
857 | struct brw_reg dest, | ||
858 | GLuint msg_reg_nr, | ||
859 | struct brw_reg src0, | ||
860 | GLuint binding_table_index, | ||
861 | GLuint msg_length, | ||
862 | GLuint response_length, | ||
863 | GLboolean eot); | ||
864 | |||
865 | void brw_SAMPLE(struct brw_compile *p, | ||
866 | struct brw_reg dest, | ||
867 | GLuint msg_reg_nr, | ||
868 | struct brw_reg src0, | ||
869 | GLuint binding_table_index, | ||
870 | GLuint sampler, | ||
871 | GLuint writemask, | ||
872 | GLuint msg_type, | ||
873 | GLuint response_length, | ||
874 | GLuint msg_length, | ||
875 | GLboolean eot, | ||
876 | GLuint header_present, | ||
877 | GLuint simd_mode); | ||
878 | |||
879 | void brw_math_16( struct brw_compile *p, | ||
880 | struct brw_reg dest, | ||
881 | GLuint function, | ||
882 | GLuint saturate, | ||
883 | GLuint msg_reg_nr, | ||
884 | struct brw_reg src, | ||
885 | GLuint precision ); | ||
886 | |||
887 | void brw_math( struct brw_compile *p, | ||
888 | struct brw_reg dest, | ||
889 | GLuint function, | ||
890 | GLuint saturate, | ||
891 | GLuint msg_reg_nr, | ||
892 | struct brw_reg src, | ||
893 | GLuint data_type, | ||
894 | GLuint precision ); | ||
895 | |||
896 | void brw_dp_READ_16( struct brw_compile *p, | ||
897 | struct brw_reg dest, | ||
898 | GLuint scratch_offset ); | ||
899 | |||
900 | void brw_dp_READ_4( struct brw_compile *p, | ||
901 | struct brw_reg dest, | ||
902 | GLboolean relAddr, | ||
903 | GLuint location, | ||
904 | GLuint bind_table_index ); | ||
905 | |||
906 | void brw_dp_READ_4_vs( struct brw_compile *p, | ||
907 | struct brw_reg dest, | ||
908 | GLuint oword, | ||
909 | GLboolean relAddr, | ||
910 | struct brw_reg addrReg, | ||
911 | GLuint location, | ||
912 | GLuint bind_table_index ); | ||
913 | |||
914 | void brw_dp_WRITE_16( struct brw_compile *p, | ||
915 | struct brw_reg src, | ||
916 | GLuint scratch_offset ); | ||
917 | |||
918 | /* If/else/endif. Works by manipulating the execution flags on each | ||
919 | * channel. | ||
920 | */ | ||
921 | struct brw_instruction *brw_IF(struct brw_compile *p, | ||
922 | GLuint execute_size); | ||
923 | |||
924 | struct brw_instruction *brw_ELSE(struct brw_compile *p, | ||
925 | struct brw_instruction *if_insn); | ||
926 | |||
927 | void brw_ENDIF(struct brw_compile *p, | ||
928 | struct brw_instruction *if_or_else_insn); | ||
929 | |||
930 | |||
931 | /* DO/WHILE loops: | ||
932 | */ | ||
933 | struct brw_instruction *brw_DO(struct brw_compile *p, | ||
934 | GLuint execute_size); | ||
935 | |||
936 | struct brw_instruction *brw_WHILE(struct brw_compile *p, | ||
937 | struct brw_instruction *patch_insn); | ||
938 | |||
939 | struct brw_instruction *brw_BREAK(struct brw_compile *p); | ||
940 | struct brw_instruction *brw_CONT(struct brw_compile *p); | ||
941 | /* Forward jumps: | ||
942 | */ | ||
943 | void brw_land_fwd_jump(struct brw_compile *p, | ||
944 | struct brw_instruction *jmp_insn); | ||
945 | |||
946 | |||
947 | |||
948 | void brw_NOP(struct brw_compile *p); | ||
949 | |||
950 | /* Special case: there is never a destination, execution size will be | ||
951 | * taken from src0: | ||
952 | */ | ||
953 | void brw_CMP(struct brw_compile *p, | ||
954 | struct brw_reg dest, | ||
955 | GLuint conditional, | ||
956 | struct brw_reg src0, | ||
957 | struct brw_reg src1); | ||
958 | |||
959 | void brw_print_reg( struct brw_reg reg ); | ||
960 | |||
961 | |||
962 | /*********************************************************************** | ||
963 | * brw_eu_util.c: | ||
964 | */ | ||
965 | |||
966 | void brw_copy_indirect_to_indirect(struct brw_compile *p, | ||
967 | struct brw_indirect dst_ptr, | ||
968 | struct brw_indirect src_ptr, | ||
969 | GLuint count); | ||
970 | |||
971 | void brw_copy_from_indirect(struct brw_compile *p, | ||
972 | struct brw_reg dst, | ||
973 | struct brw_indirect ptr, | ||
974 | GLuint count); | ||
975 | |||
976 | void brw_copy4(struct brw_compile *p, | ||
977 | struct brw_reg dst, | ||
978 | struct brw_reg src, | ||
979 | GLuint count); | ||
980 | |||
981 | void brw_copy8(struct brw_compile *p, | ||
982 | struct brw_reg dst, | ||
983 | struct brw_reg src, | ||
984 | GLuint count); | ||
985 | |||
986 | void brw_math_invert( struct brw_compile *p, | ||
987 | struct brw_reg dst, | ||
988 | struct brw_reg src); | ||
989 | |||
990 | void brw_set_src1( struct brw_instruction *insn, | ||
991 | struct brw_reg reg ); | ||
992 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_eu_debug.c b/src/gallium/drivers/i965/brw_eu_debug.c deleted file mode 100644 index 5989f5a04ee..00000000000 --- a/src/gallium/drivers/i965/brw_eu_debug.c +++ /dev/null | |||
@@ -1,94 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_debug.h" | ||
33 | |||
34 | #include "brw_eu.h" | ||
35 | |||
36 | void brw_print_reg( struct brw_reg hwreg ) | ||
37 | { | ||
38 | static const char *file[] = { | ||
39 | "arf", | ||
40 | "grf", | ||
41 | "msg", | ||
42 | "imm" | ||
43 | }; | ||
44 | |||
45 | static const char *type[] = { | ||
46 | "ud", | ||
47 | "d", | ||
48 | "uw", | ||
49 | "w", | ||
50 | "ub", | ||
51 | "vf", | ||
52 | "hf", | ||
53 | "f" | ||
54 | }; | ||
55 | |||
56 | debug_printf("%s%s", | ||
57 | hwreg.abs ? "abs/" : "", | ||
58 | hwreg.negate ? "-" : ""); | ||
59 | |||
60 | if (hwreg.file == BRW_GENERAL_REGISTER_FILE && | ||
61 | hwreg.nr % 2 == 0 && | ||
62 | hwreg.subnr == 0 && | ||
63 | hwreg.vstride == BRW_VERTICAL_STRIDE_8 && | ||
64 | hwreg.width == BRW_WIDTH_8 && | ||
65 | hwreg.hstride == BRW_HORIZONTAL_STRIDE_1 && | ||
66 | hwreg.type == BRW_REGISTER_TYPE_F) { | ||
67 | /* vector register */ | ||
68 | debug_printf("vec%d", hwreg.nr); | ||
69 | } | ||
70 | else if (hwreg.file == BRW_GENERAL_REGISTER_FILE && | ||
71 | hwreg.vstride == BRW_VERTICAL_STRIDE_0 && | ||
72 | hwreg.width == BRW_WIDTH_1 && | ||
73 | hwreg.hstride == BRW_HORIZONTAL_STRIDE_0 && | ||
74 | hwreg.type == BRW_REGISTER_TYPE_F) { | ||
75 | /* "scalar" register */ | ||
76 | debug_printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4); | ||
77 | } | ||
78 | else if (hwreg.file == BRW_IMMEDIATE_VALUE) { | ||
79 | debug_printf("imm %f", hwreg.dw1.f); | ||
80 | } | ||
81 | else { | ||
82 | debug_printf("%s%d.%d<%d;%d,%d>:%s", | ||
83 | file[hwreg.file], | ||
84 | hwreg.nr, | ||
85 | hwreg.subnr / type_sz(hwreg.type), | ||
86 | hwreg.vstride ? (1<<(hwreg.vstride-1)) : 0, | ||
87 | 1<<hwreg.width, | ||
88 | hwreg.hstride ? (1<<(hwreg.hstride-1)) : 0, | ||
89 | type[hwreg.type]); | ||
90 | } | ||
91 | } | ||
92 | |||
93 | |||
94 | |||
diff --git a/src/gallium/drivers/i965/brw_eu_emit.c b/src/gallium/drivers/i965/brw_eu_emit.c deleted file mode 100644 index ba1159e4c32..00000000000 --- a/src/gallium/drivers/i965/brw_eu_emit.c +++ /dev/null | |||
@@ -1,1433 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_context.h" | ||
34 | #include "brw_defines.h" | ||
35 | #include "brw_eu.h" | ||
36 | #include "brw_debug.h" | ||
37 | #include "brw_disasm.h" | ||
38 | |||
39 | |||
40 | |||
41 | |||
42 | /*********************************************************************** | ||
43 | * Internal helper for constructing instructions | ||
44 | */ | ||
45 | |||
46 | static void guess_execution_size( struct brw_instruction *insn, | ||
47 | struct brw_reg reg ) | ||
48 | { | ||
49 | if (reg.width == BRW_WIDTH_8 && | ||
50 | insn->header.compression_control == BRW_COMPRESSION_COMPRESSED) | ||
51 | insn->header.execution_size = BRW_EXECUTE_16; | ||
52 | else | ||
53 | insn->header.execution_size = reg.width; /* note - definitions are compatible */ | ||
54 | } | ||
55 | |||
56 | |||
57 | static void brw_set_dest( struct brw_instruction *insn, | ||
58 | struct brw_reg dest ) | ||
59 | { | ||
60 | if (dest.type != BRW_ARCHITECTURE_REGISTER_FILE) | ||
61 | assert(dest.nr < 128); | ||
62 | |||
63 | insn->bits1.da1.dest_reg_file = dest.file; | ||
64 | insn->bits1.da1.dest_reg_type = dest.type; | ||
65 | insn->bits1.da1.dest_address_mode = dest.address_mode; | ||
66 | |||
67 | if (dest.address_mode == BRW_ADDRESS_DIRECT) { | ||
68 | insn->bits1.da1.dest_reg_nr = dest.nr; | ||
69 | |||
70 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
71 | insn->bits1.da1.dest_subreg_nr = dest.subnr; | ||
72 | if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) | ||
73 | dest.hstride = BRW_HORIZONTAL_STRIDE_1; | ||
74 | insn->bits1.da1.dest_horiz_stride = dest.hstride; | ||
75 | } | ||
76 | else { | ||
77 | insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; | ||
78 | insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask; | ||
79 | } | ||
80 | } | ||
81 | else { | ||
82 | insn->bits1.ia1.dest_subreg_nr = dest.subnr; | ||
83 | |||
84 | /* These are different sizes in align1 vs align16: | ||
85 | */ | ||
86 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
87 | insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset; | ||
88 | if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) | ||
89 | dest.hstride = BRW_HORIZONTAL_STRIDE_1; | ||
90 | insn->bits1.ia1.dest_horiz_stride = dest.hstride; | ||
91 | } | ||
92 | else { | ||
93 | insn->bits1.ia16.dest_indirect_offset = dest.dw1.bits.indirect_offset; | ||
94 | } | ||
95 | } | ||
96 | |||
97 | /* NEW: Set the execution size based on dest.width and | ||
98 | * insn->compression_control: | ||
99 | */ | ||
100 | guess_execution_size(insn, dest); | ||
101 | } | ||
102 | |||
103 | static void brw_set_src0( struct brw_instruction *insn, | ||
104 | struct brw_reg reg ) | ||
105 | { | ||
106 | assert(reg.file != BRW_MESSAGE_REGISTER_FILE); | ||
107 | |||
108 | if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE) | ||
109 | assert(reg.nr < 128); | ||
110 | |||
111 | insn->bits1.da1.src0_reg_file = reg.file; | ||
112 | insn->bits1.da1.src0_reg_type = reg.type; | ||
113 | insn->bits2.da1.src0_abs = reg.abs; | ||
114 | insn->bits2.da1.src0_negate = reg.negate; | ||
115 | insn->bits2.da1.src0_address_mode = reg.address_mode; | ||
116 | |||
117 | if (reg.file == BRW_IMMEDIATE_VALUE) { | ||
118 | insn->bits3.ud = reg.dw1.ud; | ||
119 | |||
120 | /* Required to set some fields in src1 as well: | ||
121 | */ | ||
122 | insn->bits1.da1.src1_reg_file = 0; /* arf */ | ||
123 | insn->bits1.da1.src1_reg_type = reg.type; | ||
124 | } | ||
125 | else | ||
126 | { | ||
127 | if (reg.address_mode == BRW_ADDRESS_DIRECT) { | ||
128 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
129 | insn->bits2.da1.src0_subreg_nr = reg.subnr; | ||
130 | insn->bits2.da1.src0_reg_nr = reg.nr; | ||
131 | } | ||
132 | else { | ||
133 | insn->bits2.da16.src0_subreg_nr = reg.subnr / 16; | ||
134 | insn->bits2.da16.src0_reg_nr = reg.nr; | ||
135 | } | ||
136 | } | ||
137 | else { | ||
138 | insn->bits2.ia1.src0_subreg_nr = reg.subnr; | ||
139 | |||
140 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
141 | insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset; | ||
142 | } | ||
143 | else { | ||
144 | insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset; | ||
145 | } | ||
146 | } | ||
147 | |||
148 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
149 | if (reg.width == BRW_WIDTH_1 && | ||
150 | insn->header.execution_size == BRW_EXECUTE_1) { | ||
151 | insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0; | ||
152 | insn->bits2.da1.src0_width = BRW_WIDTH_1; | ||
153 | insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0; | ||
154 | } | ||
155 | else { | ||
156 | insn->bits2.da1.src0_horiz_stride = reg.hstride; | ||
157 | insn->bits2.da1.src0_width = reg.width; | ||
158 | insn->bits2.da1.src0_vert_stride = reg.vstride; | ||
159 | } | ||
160 | } | ||
161 | else { | ||
162 | insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X); | ||
163 | insn->bits2.da16.src0_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y); | ||
164 | insn->bits2.da16.src0_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z); | ||
165 | insn->bits2.da16.src0_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W); | ||
166 | |||
167 | /* This is an oddity of the fact we're using the same | ||
168 | * descriptions for registers in align_16 as align_1: | ||
169 | */ | ||
170 | if (reg.vstride == BRW_VERTICAL_STRIDE_8) | ||
171 | insn->bits2.da16.src0_vert_stride = BRW_VERTICAL_STRIDE_4; | ||
172 | else | ||
173 | insn->bits2.da16.src0_vert_stride = reg.vstride; | ||
174 | } | ||
175 | } | ||
176 | } | ||
177 | |||
178 | |||
179 | void brw_set_src1( struct brw_instruction *insn, | ||
180 | struct brw_reg reg ) | ||
181 | { | ||
182 | assert(reg.file != BRW_MESSAGE_REGISTER_FILE); | ||
183 | |||
184 | assert(reg.nr < 128); | ||
185 | |||
186 | insn->bits1.da1.src1_reg_file = reg.file; | ||
187 | insn->bits1.da1.src1_reg_type = reg.type; | ||
188 | insn->bits3.da1.src1_abs = reg.abs; | ||
189 | insn->bits3.da1.src1_negate = reg.negate; | ||
190 | |||
191 | /* Only src1 can be immediate in two-argument instructions. | ||
192 | */ | ||
193 | assert(insn->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE); | ||
194 | |||
195 | if (reg.file == BRW_IMMEDIATE_VALUE) { | ||
196 | insn->bits3.ud = reg.dw1.ud; | ||
197 | } | ||
198 | else { | ||
199 | /* This is a hardware restriction, which may or may not be lifted | ||
200 | * in the future: | ||
201 | */ | ||
202 | assert (reg.address_mode == BRW_ADDRESS_DIRECT); | ||
203 | /*assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ | ||
204 | |||
205 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
206 | insn->bits3.da1.src1_subreg_nr = reg.subnr; | ||
207 | insn->bits3.da1.src1_reg_nr = reg.nr; | ||
208 | } | ||
209 | else { | ||
210 | insn->bits3.da16.src1_subreg_nr = reg.subnr / 16; | ||
211 | insn->bits3.da16.src1_reg_nr = reg.nr; | ||
212 | } | ||
213 | |||
214 | if (insn->header.access_mode == BRW_ALIGN_1) { | ||
215 | if (reg.width == BRW_WIDTH_1 && | ||
216 | insn->header.execution_size == BRW_EXECUTE_1) { | ||
217 | insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0; | ||
218 | insn->bits3.da1.src1_width = BRW_WIDTH_1; | ||
219 | insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0; | ||
220 | } | ||
221 | else { | ||
222 | insn->bits3.da1.src1_horiz_stride = reg.hstride; | ||
223 | insn->bits3.da1.src1_width = reg.width; | ||
224 | insn->bits3.da1.src1_vert_stride = reg.vstride; | ||
225 | } | ||
226 | } | ||
227 | else { | ||
228 | insn->bits3.da16.src1_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X); | ||
229 | insn->bits3.da16.src1_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y); | ||
230 | insn->bits3.da16.src1_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z); | ||
231 | insn->bits3.da16.src1_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W); | ||
232 | |||
233 | /* This is an oddity of the fact we're using the same | ||
234 | * descriptions for registers in align_16 as align_1: | ||
235 | */ | ||
236 | if (reg.vstride == BRW_VERTICAL_STRIDE_8) | ||
237 | insn->bits3.da16.src1_vert_stride = BRW_VERTICAL_STRIDE_4; | ||
238 | else | ||
239 | insn->bits3.da16.src1_vert_stride = reg.vstride; | ||
240 | } | ||
241 | } | ||
242 | } | ||
243 | |||
244 | |||
245 | |||
246 | static void brw_set_math_message( struct brw_context *brw, | ||
247 | struct brw_instruction *insn, | ||
248 | GLuint msg_length, | ||
249 | GLuint response_length, | ||
250 | GLuint function, | ||
251 | GLuint integer_type, | ||
252 | GLboolean low_precision, | ||
253 | GLboolean saturate, | ||
254 | GLuint dataType ) | ||
255 | { | ||
256 | brw_set_src1(insn, brw_imm_d(0)); | ||
257 | |||
258 | if (brw->gen == 5) { | ||
259 | insn->bits3.math_gen5.function = function; | ||
260 | insn->bits3.math_gen5.int_type = integer_type; | ||
261 | insn->bits3.math_gen5.precision = low_precision; | ||
262 | insn->bits3.math_gen5.saturate = saturate; | ||
263 | insn->bits3.math_gen5.data_type = dataType; | ||
264 | insn->bits3.math_gen5.snapshot = 0; | ||
265 | insn->bits3.math_gen5.header_present = 0; | ||
266 | insn->bits3.math_gen5.response_length = response_length; | ||
267 | insn->bits3.math_gen5.msg_length = msg_length; | ||
268 | insn->bits3.math_gen5.end_of_thread = 0; | ||
269 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH; | ||
270 | insn->bits2.send_gen5.end_of_thread = 0; | ||
271 | } else { | ||
272 | insn->bits3.math.function = function; | ||
273 | insn->bits3.math.int_type = integer_type; | ||
274 | insn->bits3.math.precision = low_precision; | ||
275 | insn->bits3.math.saturate = saturate; | ||
276 | insn->bits3.math.data_type = dataType; | ||
277 | insn->bits3.math.response_length = response_length; | ||
278 | insn->bits3.math.msg_length = msg_length; | ||
279 | insn->bits3.math.msg_target = BRW_MESSAGE_TARGET_MATH; | ||
280 | insn->bits3.math.end_of_thread = 0; | ||
281 | } | ||
282 | } | ||
283 | |||
284 | |||
285 | static void brw_set_ff_sync_message( struct brw_context *brw, | ||
286 | struct brw_instruction *insn, | ||
287 | GLboolean allocate, | ||
288 | GLboolean used, | ||
289 | GLuint msg_length, | ||
290 | GLuint response_length, | ||
291 | GLboolean end_of_thread, | ||
292 | GLboolean complete, | ||
293 | GLuint offset, | ||
294 | GLuint swizzle_control ) | ||
295 | { | ||
296 | brw_set_src1(insn, brw_imm_d(0)); | ||
297 | |||
298 | insn->bits3.urb_gen5.opcode = 1; | ||
299 | insn->bits3.urb_gen5.offset = offset; | ||
300 | insn->bits3.urb_gen5.swizzle_control = swizzle_control; | ||
301 | insn->bits3.urb_gen5.allocate = allocate; | ||
302 | insn->bits3.urb_gen5.used = used; | ||
303 | insn->bits3.urb_gen5.complete = complete; | ||
304 | insn->bits3.urb_gen5.header_present = 1; | ||
305 | insn->bits3.urb_gen5.response_length = response_length; | ||
306 | insn->bits3.urb_gen5.msg_length = msg_length; | ||
307 | insn->bits3.urb_gen5.end_of_thread = end_of_thread; | ||
308 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB; | ||
309 | insn->bits2.send_gen5.end_of_thread = end_of_thread; | ||
310 | } | ||
311 | |||
312 | static void brw_set_urb_message( struct brw_context *brw, | ||
313 | struct brw_instruction *insn, | ||
314 | GLboolean allocate, | ||
315 | GLboolean used, | ||
316 | GLuint msg_length, | ||
317 | GLuint response_length, | ||
318 | GLboolean end_of_thread, | ||
319 | GLboolean complete, | ||
320 | GLuint offset, | ||
321 | GLuint swizzle_control ) | ||
322 | { | ||
323 | brw_set_src1(insn, brw_imm_d(0)); | ||
324 | |||
325 | if (brw->gen == 5) { | ||
326 | insn->bits3.urb_gen5.opcode = 0; /* ? */ | ||
327 | insn->bits3.urb_gen5.offset = offset; | ||
328 | insn->bits3.urb_gen5.swizzle_control = swizzle_control; | ||
329 | insn->bits3.urb_gen5.allocate = allocate; | ||
330 | insn->bits3.urb_gen5.used = used; /* ? */ | ||
331 | insn->bits3.urb_gen5.complete = complete; | ||
332 | insn->bits3.urb_gen5.header_present = 1; | ||
333 | insn->bits3.urb_gen5.response_length = response_length; | ||
334 | insn->bits3.urb_gen5.msg_length = msg_length; | ||
335 | insn->bits3.urb_gen5.end_of_thread = end_of_thread; | ||
336 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB; | ||
337 | insn->bits2.send_gen5.end_of_thread = end_of_thread; | ||
338 | } else { | ||
339 | insn->bits3.urb.opcode = 0; /* ? */ | ||
340 | insn->bits3.urb.offset = offset; | ||
341 | insn->bits3.urb.swizzle_control = swizzle_control; | ||
342 | insn->bits3.urb.allocate = allocate; | ||
343 | insn->bits3.urb.used = used; /* ? */ | ||
344 | insn->bits3.urb.complete = complete; | ||
345 | insn->bits3.urb.response_length = response_length; | ||
346 | insn->bits3.urb.msg_length = msg_length; | ||
347 | insn->bits3.urb.msg_target = BRW_MESSAGE_TARGET_URB; | ||
348 | insn->bits3.urb.end_of_thread = end_of_thread; | ||
349 | } | ||
350 | } | ||
351 | |||
352 | static void brw_set_dp_write_message( struct brw_context *brw, | ||
353 | struct brw_instruction *insn, | ||
354 | GLuint binding_table_index, | ||
355 | GLuint msg_control, | ||
356 | GLuint msg_type, | ||
357 | GLuint msg_length, | ||
358 | GLuint pixel_scoreboard_clear, | ||
359 | GLuint response_length, | ||
360 | GLuint end_of_thread ) | ||
361 | { | ||
362 | brw_set_src1(insn, brw_imm_d(0)); | ||
363 | |||
364 | if (brw->gen == 5) { | ||
365 | insn->bits3.dp_write_gen5.binding_table_index = binding_table_index; | ||
366 | insn->bits3.dp_write_gen5.msg_control = msg_control; | ||
367 | insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear; | ||
368 | insn->bits3.dp_write_gen5.msg_type = msg_type; | ||
369 | insn->bits3.dp_write_gen5.send_commit_msg = 0; | ||
370 | insn->bits3.dp_write_gen5.header_present = 1; | ||
371 | insn->bits3.dp_write_gen5.response_length = response_length; | ||
372 | insn->bits3.dp_write_gen5.msg_length = msg_length; | ||
373 | insn->bits3.dp_write_gen5.end_of_thread = end_of_thread; | ||
374 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE; | ||
375 | insn->bits2.send_gen5.end_of_thread = end_of_thread; | ||
376 | } else { | ||
377 | insn->bits3.dp_write.binding_table_index = binding_table_index; | ||
378 | insn->bits3.dp_write.msg_control = msg_control; | ||
379 | insn->bits3.dp_write.pixel_scoreboard_clear = pixel_scoreboard_clear; | ||
380 | insn->bits3.dp_write.msg_type = msg_type; | ||
381 | insn->bits3.dp_write.send_commit_msg = 0; | ||
382 | insn->bits3.dp_write.response_length = response_length; | ||
383 | insn->bits3.dp_write.msg_length = msg_length; | ||
384 | insn->bits3.dp_write.msg_target = BRW_MESSAGE_TARGET_DATAPORT_WRITE; | ||
385 | insn->bits3.dp_write.end_of_thread = end_of_thread; | ||
386 | } | ||
387 | } | ||
388 | |||
389 | static void brw_set_dp_read_message( struct brw_context *brw, | ||
390 | struct brw_instruction *insn, | ||
391 | GLuint binding_table_index, | ||
392 | GLuint msg_control, | ||
393 | GLuint msg_type, | ||
394 | GLuint target_cache, | ||
395 | GLuint msg_length, | ||
396 | GLuint response_length, | ||
397 | GLuint end_of_thread ) | ||
398 | { | ||
399 | brw_set_src1(insn, brw_imm_d(0)); | ||
400 | |||
401 | if (brw->gen == 5) { | ||
402 | insn->bits3.dp_read_gen5.binding_table_index = binding_table_index; | ||
403 | insn->bits3.dp_read_gen5.msg_control = msg_control; | ||
404 | insn->bits3.dp_read_gen5.msg_type = msg_type; | ||
405 | insn->bits3.dp_read_gen5.target_cache = target_cache; | ||
406 | insn->bits3.dp_read_gen5.header_present = 1; | ||
407 | insn->bits3.dp_read_gen5.response_length = response_length; | ||
408 | insn->bits3.dp_read_gen5.msg_length = msg_length; | ||
409 | insn->bits3.dp_read_gen5.pad1 = 0; | ||
410 | insn->bits3.dp_read_gen5.end_of_thread = end_of_thread; | ||
411 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ; | ||
412 | insn->bits2.send_gen5.end_of_thread = end_of_thread; | ||
413 | } else { | ||
414 | insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/ | ||
415 | insn->bits3.dp_read.msg_control = msg_control; /*8:11*/ | ||
416 | insn->bits3.dp_read.msg_type = msg_type; /*12:13*/ | ||
417 | insn->bits3.dp_read.target_cache = target_cache; /*14:15*/ | ||
418 | insn->bits3.dp_read.response_length = response_length; /*16:19*/ | ||
419 | insn->bits3.dp_read.msg_length = msg_length; /*20:23*/ | ||
420 | insn->bits3.dp_read.msg_target = BRW_MESSAGE_TARGET_DATAPORT_READ; /*24:27*/ | ||
421 | insn->bits3.dp_read.pad1 = 0; /*28:30*/ | ||
422 | insn->bits3.dp_read.end_of_thread = end_of_thread; /*31*/ | ||
423 | } | ||
424 | } | ||
425 | |||
426 | static void brw_set_sampler_message(struct brw_context *brw, | ||
427 | struct brw_instruction *insn, | ||
428 | GLuint binding_table_index, | ||
429 | GLuint sampler, | ||
430 | GLuint msg_type, | ||
431 | GLuint response_length, | ||
432 | GLuint msg_length, | ||
433 | GLboolean eot, | ||
434 | GLuint header_present, | ||
435 | GLuint simd_mode) | ||
436 | { | ||
437 | assert(eot == 0); | ||
438 | brw_set_src1(insn, brw_imm_d(0)); | ||
439 | |||
440 | if (brw->gen == 5) { | ||
441 | insn->bits3.sampler_gen5.binding_table_index = binding_table_index; | ||
442 | insn->bits3.sampler_gen5.sampler = sampler; | ||
443 | insn->bits3.sampler_gen5.msg_type = msg_type; | ||
444 | insn->bits3.sampler_gen5.simd_mode = simd_mode; | ||
445 | insn->bits3.sampler_gen5.header_present = header_present; | ||
446 | insn->bits3.sampler_gen5.response_length = response_length; | ||
447 | insn->bits3.sampler_gen5.msg_length = msg_length; | ||
448 | insn->bits3.sampler_gen5.end_of_thread = eot; | ||
449 | insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER; | ||
450 | insn->bits2.send_gen5.end_of_thread = eot; | ||
451 | } else if (brw->is_g4x) { | ||
452 | insn->bits3.sampler_g4x.binding_table_index = binding_table_index; | ||
453 | insn->bits3.sampler_g4x.sampler = sampler; | ||
454 | insn->bits3.sampler_g4x.msg_type = msg_type; | ||
455 | insn->bits3.sampler_g4x.response_length = response_length; | ||
456 | insn->bits3.sampler_g4x.msg_length = msg_length; | ||
457 | insn->bits3.sampler_g4x.end_of_thread = eot; | ||
458 | insn->bits3.sampler_g4x.msg_target = BRW_MESSAGE_TARGET_SAMPLER; | ||
459 | } else { | ||
460 | insn->bits3.sampler.binding_table_index = binding_table_index; | ||
461 | insn->bits3.sampler.sampler = sampler; | ||
462 | insn->bits3.sampler.msg_type = msg_type; | ||
463 | insn->bits3.sampler.return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; | ||
464 | insn->bits3.sampler.response_length = response_length; | ||
465 | insn->bits3.sampler.msg_length = msg_length; | ||
466 | insn->bits3.sampler.end_of_thread = eot; | ||
467 | insn->bits3.sampler.msg_target = BRW_MESSAGE_TARGET_SAMPLER; | ||
468 | } | ||
469 | } | ||
470 | |||
471 | |||
472 | |||
473 | static struct brw_instruction *next_insn( struct brw_compile *p, | ||
474 | GLuint opcode ) | ||
475 | { | ||
476 | struct brw_instruction *insn; | ||
477 | |||
478 | if (0 && (BRW_DEBUG & DEBUG_DISASSEM)) | ||
479 | { | ||
480 | if (p->nr_insn) | ||
481 | brw_disasm_insn(stderr, &p->store[p->nr_insn-1], p->brw->gen); | ||
482 | } | ||
483 | |||
484 | assert(p->nr_insn + 1 < BRW_EU_MAX_INSN); | ||
485 | |||
486 | insn = &p->store[p->nr_insn++]; | ||
487 | memcpy(insn, p->current, sizeof(*insn)); | ||
488 | |||
489 | /* Reset this one-shot flag: | ||
490 | */ | ||
491 | |||
492 | if (p->current->header.destreg__conditionalmod) { | ||
493 | p->current->header.destreg__conditionalmod = 0; | ||
494 | p->current->header.predicate_control = BRW_PREDICATE_NORMAL; | ||
495 | } | ||
496 | |||
497 | insn->header.opcode = opcode; | ||
498 | return insn; | ||
499 | } | ||
500 | |||
501 | |||
502 | static struct brw_instruction *brw_alu1( struct brw_compile *p, | ||
503 | GLuint opcode, | ||
504 | struct brw_reg dest, | ||
505 | struct brw_reg src ) | ||
506 | { | ||
507 | struct brw_instruction *insn = next_insn(p, opcode); | ||
508 | brw_set_dest(insn, dest); | ||
509 | brw_set_src0(insn, src); | ||
510 | return insn; | ||
511 | } | ||
512 | |||
513 | static struct brw_instruction *brw_alu2(struct brw_compile *p, | ||
514 | GLuint opcode, | ||
515 | struct brw_reg dest, | ||
516 | struct brw_reg src0, | ||
517 | struct brw_reg src1 ) | ||
518 | { | ||
519 | struct brw_instruction *insn = next_insn(p, opcode); | ||
520 | brw_set_dest(insn, dest); | ||
521 | brw_set_src0(insn, src0); | ||
522 | brw_set_src1(insn, src1); | ||
523 | return insn; | ||
524 | } | ||
525 | |||
526 | |||
527 | /*********************************************************************** | ||
528 | * Convenience routines. | ||
529 | */ | ||
530 | #define ALU1(OP) \ | ||
531 | struct brw_instruction *brw_##OP(struct brw_compile *p, \ | ||
532 | struct brw_reg dest, \ | ||
533 | struct brw_reg src0) \ | ||
534 | { \ | ||
535 | return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \ | ||
536 | } | ||
537 | |||
538 | #define ALU2(OP) \ | ||
539 | struct brw_instruction *brw_##OP(struct brw_compile *p, \ | ||
540 | struct brw_reg dest, \ | ||
541 | struct brw_reg src0, \ | ||
542 | struct brw_reg src1) \ | ||
543 | { \ | ||
544 | return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \ | ||
545 | } | ||
546 | |||
547 | |||
548 | ALU1(MOV) | ||
549 | ALU2(SEL) | ||
550 | ALU1(NOT) | ||
551 | ALU2(AND) | ||
552 | ALU2(OR) | ||
553 | ALU2(XOR) | ||
554 | ALU2(SHR) | ||
555 | ALU2(SHL) | ||
556 | ALU2(RSR) | ||
557 | ALU2(RSL) | ||
558 | ALU2(ASR) | ||
559 | ALU2(ADD) | ||
560 | ALU2(MUL) | ||
561 | ALU1(FRC) | ||
562 | ALU1(RNDD) | ||
563 | ALU1(RNDZ) | ||
564 | ALU2(MAC) | ||
565 | ALU2(MACH) | ||
566 | ALU1(LZD) | ||
567 | ALU2(DP4) | ||
568 | ALU2(DPH) | ||
569 | ALU2(DP3) | ||
570 | ALU2(DP2) | ||
571 | ALU2(LINE) | ||
572 | |||
573 | |||
574 | |||
575 | |||
576 | void brw_NOP(struct brw_compile *p) | ||
577 | { | ||
578 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP); | ||
579 | brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); | ||
580 | brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); | ||
581 | brw_set_src1(insn, brw_imm_ud(0x0)); | ||
582 | } | ||
583 | |||
584 | |||
585 | |||
586 | |||
587 | |||
588 | /*********************************************************************** | ||
589 | * Comparisons, if/else/endif | ||
590 | */ | ||
591 | |||
592 | struct brw_instruction *brw_JMPI(struct brw_compile *p, | ||
593 | struct brw_reg dest, | ||
594 | struct brw_reg src0, | ||
595 | struct brw_reg src1) | ||
596 | { | ||
597 | struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1); | ||
598 | |||
599 | insn->header.execution_size = 1; | ||
600 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
601 | insn->header.mask_control = BRW_MASK_DISABLE; | ||
602 | |||
603 | p->current->header.predicate_control = BRW_PREDICATE_NONE; | ||
604 | |||
605 | return insn; | ||
606 | } | ||
607 | |||
608 | /* EU takes the value from the flag register and pushes it onto some | ||
609 | * sort of a stack (presumably merging with any flag value already on | ||
610 | * the stack). Within an if block, the flags at the top of the stack | ||
611 | * control execution on each channel of the unit, eg. on each of the | ||
612 | * 16 pixel values in our wm programs. | ||
613 | * | ||
614 | * When the matching 'else' instruction is reached (presumably by | ||
615 | * countdown of the instruction count patched in by our ELSE/ENDIF | ||
616 | * functions), the relevent flags are inverted. | ||
617 | * | ||
618 | * When the matching 'endif' instruction is reached, the flags are | ||
619 | * popped off. If the stack is now empty, normal execution resumes. | ||
620 | * | ||
621 | * No attempt is made to deal with stack overflow (14 elements?). | ||
622 | */ | ||
623 | struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) | ||
624 | { | ||
625 | struct brw_instruction *insn; | ||
626 | |||
627 | if (p->single_program_flow) { | ||
628 | assert(execute_size == BRW_EXECUTE_1); | ||
629 | |||
630 | insn = next_insn(p, BRW_OPCODE_ADD); | ||
631 | insn->header.predicate_inverse = 1; | ||
632 | } else { | ||
633 | insn = next_insn(p, BRW_OPCODE_IF); | ||
634 | } | ||
635 | |||
636 | /* Override the defaults for this instruction: | ||
637 | */ | ||
638 | brw_set_dest(insn, brw_ip_reg()); | ||
639 | brw_set_src0(insn, brw_ip_reg()); | ||
640 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
641 | |||
642 | insn->header.execution_size = execute_size; | ||
643 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
644 | insn->header.predicate_control = BRW_PREDICATE_NORMAL; | ||
645 | insn->header.mask_control = BRW_MASK_ENABLE; | ||
646 | if (!p->single_program_flow) | ||
647 | insn->header.thread_control = BRW_THREAD_SWITCH; | ||
648 | |||
649 | p->current->header.predicate_control = BRW_PREDICATE_NONE; | ||
650 | |||
651 | return insn; | ||
652 | } | ||
653 | |||
654 | |||
655 | struct brw_instruction *brw_ELSE(struct brw_compile *p, | ||
656 | struct brw_instruction *if_insn) | ||
657 | { | ||
658 | struct brw_instruction *insn; | ||
659 | GLuint br = 1; | ||
660 | |||
661 | if (p->brw->gen == 5) | ||
662 | br = 2; | ||
663 | |||
664 | if (p->single_program_flow) { | ||
665 | insn = next_insn(p, BRW_OPCODE_ADD); | ||
666 | } else { | ||
667 | insn = next_insn(p, BRW_OPCODE_ELSE); | ||
668 | } | ||
669 | |||
670 | brw_set_dest(insn, brw_ip_reg()); | ||
671 | brw_set_src0(insn, brw_ip_reg()); | ||
672 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
673 | |||
674 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
675 | insn->header.execution_size = if_insn->header.execution_size; | ||
676 | insn->header.mask_control = BRW_MASK_ENABLE; | ||
677 | if (!p->single_program_flow) | ||
678 | insn->header.thread_control = BRW_THREAD_SWITCH; | ||
679 | |||
680 | /* Patch the if instruction to point at this instruction. | ||
681 | */ | ||
682 | if (p->single_program_flow) { | ||
683 | assert(if_insn->header.opcode == BRW_OPCODE_ADD); | ||
684 | |||
685 | if_insn->bits3.ud = (insn - if_insn + 1) * 16; | ||
686 | } else { | ||
687 | assert(if_insn->header.opcode == BRW_OPCODE_IF); | ||
688 | |||
689 | if_insn->bits3.if_else.jump_count = br * (insn - if_insn); | ||
690 | if_insn->bits3.if_else.pop_count = 0; | ||
691 | if_insn->bits3.if_else.pad0 = 0; | ||
692 | } | ||
693 | |||
694 | return insn; | ||
695 | } | ||
696 | |||
697 | void brw_ENDIF(struct brw_compile *p, | ||
698 | struct brw_instruction *patch_insn) | ||
699 | { | ||
700 | GLuint br = 1; | ||
701 | |||
702 | if (p->brw->gen == 5) | ||
703 | br = 2; | ||
704 | |||
705 | if (p->single_program_flow) { | ||
706 | /* In single program flow mode, there's no need to execute an ENDIF, | ||
707 | * since we don't need to do any stack operations, and if we're executing | ||
708 | * currently, we want to just continue executing. | ||
709 | */ | ||
710 | struct brw_instruction *next = &p->store[p->nr_insn]; | ||
711 | |||
712 | assert(patch_insn->header.opcode == BRW_OPCODE_ADD); | ||
713 | |||
714 | patch_insn->bits3.ud = (next - patch_insn) * 16; | ||
715 | } else { | ||
716 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF); | ||
717 | |||
718 | brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); | ||
719 | brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); | ||
720 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
721 | |||
722 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
723 | insn->header.execution_size = patch_insn->header.execution_size; | ||
724 | insn->header.mask_control = BRW_MASK_ENABLE; | ||
725 | insn->header.thread_control = BRW_THREAD_SWITCH; | ||
726 | |||
727 | assert(patch_insn->bits3.if_else.jump_count == 0); | ||
728 | |||
729 | /* Patch the if or else instructions to point at this or the next | ||
730 | * instruction respectively. | ||
731 | */ | ||
732 | if (patch_insn->header.opcode == BRW_OPCODE_IF) { | ||
733 | /* Automagically turn it into an IFF: | ||
734 | */ | ||
735 | patch_insn->header.opcode = BRW_OPCODE_IFF; | ||
736 | patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); | ||
737 | patch_insn->bits3.if_else.pop_count = 0; | ||
738 | patch_insn->bits3.if_else.pad0 = 0; | ||
739 | } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) { | ||
740 | patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); | ||
741 | patch_insn->bits3.if_else.pop_count = 1; | ||
742 | patch_insn->bits3.if_else.pad0 = 0; | ||
743 | } else { | ||
744 | assert(0); | ||
745 | } | ||
746 | |||
747 | /* Also pop item off the stack in the endif instruction: | ||
748 | */ | ||
749 | insn->bits3.if_else.jump_count = 0; | ||
750 | insn->bits3.if_else.pop_count = 1; | ||
751 | insn->bits3.if_else.pad0 = 0; | ||
752 | } | ||
753 | } | ||
754 | |||
755 | struct brw_instruction *brw_BREAK(struct brw_compile *p) | ||
756 | { | ||
757 | struct brw_instruction *insn; | ||
758 | insn = next_insn(p, BRW_OPCODE_BREAK); | ||
759 | brw_set_dest(insn, brw_ip_reg()); | ||
760 | brw_set_src0(insn, brw_ip_reg()); | ||
761 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
762 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
763 | insn->header.execution_size = BRW_EXECUTE_8; | ||
764 | /* insn->header.mask_control = BRW_MASK_DISABLE; */ | ||
765 | insn->bits3.if_else.pad0 = 0; | ||
766 | return insn; | ||
767 | } | ||
768 | |||
769 | struct brw_instruction *brw_CONT(struct brw_compile *p) | ||
770 | { | ||
771 | struct brw_instruction *insn; | ||
772 | insn = next_insn(p, BRW_OPCODE_CONTINUE); | ||
773 | brw_set_dest(insn, brw_ip_reg()); | ||
774 | brw_set_src0(insn, brw_ip_reg()); | ||
775 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
776 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
777 | insn->header.execution_size = BRW_EXECUTE_8; | ||
778 | /* insn->header.mask_control = BRW_MASK_DISABLE; */ | ||
779 | insn->bits3.if_else.pad0 = 0; | ||
780 | return insn; | ||
781 | } | ||
782 | |||
783 | /* DO/WHILE loop: | ||
784 | */ | ||
785 | struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) | ||
786 | { | ||
787 | if (p->single_program_flow) { | ||
788 | return &p->store[p->nr_insn]; | ||
789 | } else { | ||
790 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); | ||
791 | |||
792 | /* Override the defaults for this instruction: | ||
793 | */ | ||
794 | brw_set_dest(insn, brw_null_reg()); | ||
795 | brw_set_src0(insn, brw_null_reg()); | ||
796 | brw_set_src1(insn, brw_null_reg()); | ||
797 | |||
798 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
799 | insn->header.execution_size = execute_size; | ||
800 | insn->header.predicate_control = BRW_PREDICATE_NONE; | ||
801 | /* insn->header.mask_control = BRW_MASK_ENABLE; */ | ||
802 | /* insn->header.mask_control = BRW_MASK_DISABLE; */ | ||
803 | |||
804 | return insn; | ||
805 | } | ||
806 | } | ||
807 | |||
808 | |||
809 | |||
810 | struct brw_instruction *brw_WHILE(struct brw_compile *p, | ||
811 | struct brw_instruction *do_insn) | ||
812 | { | ||
813 | struct brw_instruction *insn; | ||
814 | GLuint br = 1; | ||
815 | |||
816 | if (p->brw->gen == 5) | ||
817 | br = 2; | ||
818 | |||
819 | if (p->single_program_flow) | ||
820 | insn = next_insn(p, BRW_OPCODE_ADD); | ||
821 | else | ||
822 | insn = next_insn(p, BRW_OPCODE_WHILE); | ||
823 | |||
824 | brw_set_dest(insn, brw_ip_reg()); | ||
825 | brw_set_src0(insn, brw_ip_reg()); | ||
826 | brw_set_src1(insn, brw_imm_d(0x0)); | ||
827 | |||
828 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
829 | |||
830 | if (p->single_program_flow) { | ||
831 | insn->header.execution_size = BRW_EXECUTE_1; | ||
832 | |||
833 | insn->bits3.d = (do_insn - insn) * 16; | ||
834 | } else { | ||
835 | insn->header.execution_size = do_insn->header.execution_size; | ||
836 | |||
837 | assert(do_insn->header.opcode == BRW_OPCODE_DO); | ||
838 | insn->bits3.if_else.jump_count = br * (do_insn - insn + 1); | ||
839 | insn->bits3.if_else.pop_count = 0; | ||
840 | insn->bits3.if_else.pad0 = 0; | ||
841 | } | ||
842 | |||
843 | /* insn->header.mask_control = BRW_MASK_ENABLE; */ | ||
844 | |||
845 | /* insn->header.mask_control = BRW_MASK_DISABLE; */ | ||
846 | p->current->header.predicate_control = BRW_PREDICATE_NONE; | ||
847 | return insn; | ||
848 | } | ||
849 | |||
850 | |||
851 | /* FORWARD JUMPS: | ||
852 | */ | ||
853 | void brw_land_fwd_jump(struct brw_compile *p, | ||
854 | struct brw_instruction *jmp_insn) | ||
855 | { | ||
856 | struct brw_instruction *landing = &p->store[p->nr_insn]; | ||
857 | GLuint jmpi = 1; | ||
858 | |||
859 | if (p->brw->gen == 5) | ||
860 | jmpi = 2; | ||
861 | |||
862 | assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI); | ||
863 | assert(jmp_insn->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE); | ||
864 | |||
865 | jmp_insn->bits3.ud = jmpi * ((landing - jmp_insn) - 1); | ||
866 | } | ||
867 | |||
868 | |||
869 | |||
870 | /* To integrate with the above, it makes sense that the comparison | ||
871 | * instruction should populate the flag register. It might be simpler | ||
872 | * just to use the flag reg for most WM tasks? | ||
873 | */ | ||
874 | void brw_CMP(struct brw_compile *p, | ||
875 | struct brw_reg dest, | ||
876 | GLuint conditional, | ||
877 | struct brw_reg src0, | ||
878 | struct brw_reg src1) | ||
879 | { | ||
880 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP); | ||
881 | |||
882 | insn->header.destreg__conditionalmod = conditional; | ||
883 | brw_set_dest(insn, dest); | ||
884 | brw_set_src0(insn, src0); | ||
885 | brw_set_src1(insn, src1); | ||
886 | |||
887 | /* guess_execution_size(insn, src0); */ | ||
888 | |||
889 | |||
890 | /* Make it so that future instructions will use the computed flag | ||
891 | * value until brw_set_predicate_control_flag_value() is called | ||
892 | * again. | ||
893 | */ | ||
894 | if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && | ||
895 | dest.nr == 0) { | ||
896 | p->current->header.predicate_control = BRW_PREDICATE_NORMAL; | ||
897 | p->flag_value = 0xff; | ||
898 | } | ||
899 | } | ||
900 | |||
901 | |||
902 | |||
903 | /*********************************************************************** | ||
904 | * Helpers for the various SEND message types: | ||
905 | */ | ||
906 | |||
907 | /** Extended math function, float[8]. | ||
908 | */ | ||
909 | void brw_math( struct brw_compile *p, | ||
910 | struct brw_reg dest, | ||
911 | GLuint function, | ||
912 | GLuint saturate, | ||
913 | GLuint msg_reg_nr, | ||
914 | struct brw_reg src, | ||
915 | GLuint data_type, | ||
916 | GLuint precision ) | ||
917 | { | ||
918 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
919 | GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1; | ||
920 | GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1; | ||
921 | |||
922 | /* Example code doesn't set predicate_control for send | ||
923 | * instructions. | ||
924 | */ | ||
925 | insn->header.predicate_control = 0; | ||
926 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
927 | |||
928 | brw_set_dest(insn, dest); | ||
929 | brw_set_src0(insn, src); | ||
930 | brw_set_math_message(p->brw, | ||
931 | insn, | ||
932 | msg_length, response_length, | ||
933 | function, | ||
934 | BRW_MATH_INTEGER_UNSIGNED, | ||
935 | precision, | ||
936 | saturate, | ||
937 | data_type); | ||
938 | } | ||
939 | |||
940 | /** | ||
941 | * Extended math function, float[16]. | ||
942 | * Use 2 send instructions. | ||
943 | */ | ||
944 | void brw_math_16( struct brw_compile *p, | ||
945 | struct brw_reg dest, | ||
946 | GLuint function, | ||
947 | GLuint saturate, | ||
948 | GLuint msg_reg_nr, | ||
949 | struct brw_reg src, | ||
950 | GLuint precision ) | ||
951 | { | ||
952 | struct brw_instruction *insn; | ||
953 | GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1; | ||
954 | GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1; | ||
955 | |||
956 | /* First instruction: | ||
957 | */ | ||
958 | brw_push_insn_state(p); | ||
959 | brw_set_predicate_control_flag_value(p, 0xff); | ||
960 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
961 | |||
962 | insn = next_insn(p, BRW_OPCODE_SEND); | ||
963 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
964 | |||
965 | brw_set_dest(insn, dest); | ||
966 | brw_set_src0(insn, src); | ||
967 | brw_set_math_message(p->brw, | ||
968 | insn, | ||
969 | msg_length, response_length, | ||
970 | function, | ||
971 | BRW_MATH_INTEGER_UNSIGNED, | ||
972 | precision, | ||
973 | saturate, | ||
974 | BRW_MATH_DATA_VECTOR); | ||
975 | |||
976 | /* Second instruction: | ||
977 | */ | ||
978 | insn = next_insn(p, BRW_OPCODE_SEND); | ||
979 | insn->header.compression_control = BRW_COMPRESSION_2NDHALF; | ||
980 | insn->header.destreg__conditionalmod = msg_reg_nr+1; | ||
981 | |||
982 | brw_set_dest(insn, offset(dest,1)); | ||
983 | brw_set_src0(insn, src); | ||
984 | brw_set_math_message(p->brw, | ||
985 | insn, | ||
986 | msg_length, response_length, | ||
987 | function, | ||
988 | BRW_MATH_INTEGER_UNSIGNED, | ||
989 | precision, | ||
990 | saturate, | ||
991 | BRW_MATH_DATA_VECTOR); | ||
992 | |||
993 | brw_pop_insn_state(p); | ||
994 | } | ||
995 | |||
996 | |||
997 | /** | ||
998 | * Write block of 16 dwords/floats to the data port Render Cache scratch buffer. | ||
999 | * Scratch offset should be a multiple of 64. | ||
1000 | * Used for register spilling. | ||
1001 | */ | ||
1002 | void brw_dp_WRITE_16( struct brw_compile *p, | ||
1003 | struct brw_reg src, | ||
1004 | GLuint scratch_offset ) | ||
1005 | { | ||
1006 | GLuint msg_reg_nr = 1; | ||
1007 | { | ||
1008 | brw_push_insn_state(p); | ||
1009 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1010 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1011 | |||
1012 | /* set message header global offset field (reg 0, element 2) */ | ||
1013 | brw_MOV(p, | ||
1014 | retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D), | ||
1015 | brw_imm_d(scratch_offset)); | ||
1016 | |||
1017 | brw_pop_insn_state(p); | ||
1018 | } | ||
1019 | |||
1020 | { | ||
1021 | GLuint msg_length = 3; | ||
1022 | struct brw_reg dest = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); | ||
1023 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1024 | |||
1025 | insn->header.predicate_control = 0; /* XXX */ | ||
1026 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1027 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1028 | |||
1029 | brw_set_dest(insn, dest); | ||
1030 | brw_set_src0(insn, src); | ||
1031 | |||
1032 | brw_set_dp_write_message(p->brw, | ||
1033 | insn, | ||
1034 | 255, /* binding table index (255=stateless) */ | ||
1035 | BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, /* msg_control */ | ||
1036 | BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */ | ||
1037 | msg_length, | ||
1038 | 0, /* pixel scoreboard */ | ||
1039 | 0, /* response_length */ | ||
1040 | 0); /* eot */ | ||
1041 | } | ||
1042 | } | ||
1043 | |||
1044 | |||
1045 | /** | ||
1046 | * Read block of 16 dwords/floats from the data port Render Cache scratch buffer. | ||
1047 | * Scratch offset should be a multiple of 64. | ||
1048 | * Used for register spilling. | ||
1049 | */ | ||
1050 | void brw_dp_READ_16( struct brw_compile *p, | ||
1051 | struct brw_reg dest, | ||
1052 | GLuint scratch_offset ) | ||
1053 | { | ||
1054 | GLuint msg_reg_nr = 1; | ||
1055 | { | ||
1056 | brw_push_insn_state(p); | ||
1057 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1058 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1059 | |||
1060 | /* set message header global offset field (reg 0, element 2) */ | ||
1061 | brw_MOV(p, | ||
1062 | retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D), | ||
1063 | brw_imm_d(scratch_offset)); | ||
1064 | |||
1065 | brw_pop_insn_state(p); | ||
1066 | } | ||
1067 | |||
1068 | { | ||
1069 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1070 | |||
1071 | insn->header.predicate_control = 0; /* XXX */ | ||
1072 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1073 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1074 | |||
1075 | brw_set_dest(insn, dest); /* UW? */ | ||
1076 | brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); | ||
1077 | |||
1078 | brw_set_dp_read_message(p->brw, | ||
1079 | insn, | ||
1080 | 255, /* binding table index (255=stateless) */ | ||
1081 | 3, /* msg_control (3 means 4 Owords) */ | ||
1082 | BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ | ||
1083 | 1, /* target cache (render/scratch) */ | ||
1084 | 1, /* msg_length */ | ||
1085 | 2, /* response_length */ | ||
1086 | 0); /* eot */ | ||
1087 | } | ||
1088 | } | ||
1089 | |||
1090 | |||
1091 | /** | ||
1092 | * Read a float[4] vector from the data port Data Cache (const buffer). | ||
1093 | * Location (in buffer) should be a multiple of 16. | ||
1094 | * Used for fetching shader constants. | ||
1095 | * If relAddr is true, we'll do an indirect fetch using the address register. | ||
1096 | */ | ||
1097 | void brw_dp_READ_4( struct brw_compile *p, | ||
1098 | struct brw_reg dest, | ||
1099 | GLboolean relAddr, | ||
1100 | GLuint location, | ||
1101 | GLuint bind_table_index ) | ||
1102 | { | ||
1103 | /* XXX: relAddr not implemented */ | ||
1104 | GLuint msg_reg_nr = 1; | ||
1105 | { | ||
1106 | struct brw_reg b; | ||
1107 | brw_push_insn_state(p); | ||
1108 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1109 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1110 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1111 | |||
1112 | /* Setup MRF[1] with location/offset into const buffer */ | ||
1113 | b = brw_message_reg(msg_reg_nr); | ||
1114 | b = retype(b, BRW_REGISTER_TYPE_UD); | ||
1115 | /* XXX I think we're setting all the dwords of MRF[1] to 'location'. | ||
1116 | * when the docs say only dword[2] should be set. Hmmm. But it works. | ||
1117 | */ | ||
1118 | brw_MOV(p, b, brw_imm_ud(location)); | ||
1119 | brw_pop_insn_state(p); | ||
1120 | } | ||
1121 | |||
1122 | { | ||
1123 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1124 | |||
1125 | insn->header.predicate_control = BRW_PREDICATE_NONE; | ||
1126 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1127 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1128 | insn->header.mask_control = BRW_MASK_DISABLE; | ||
1129 | |||
1130 | /* cast dest to a uword[8] vector */ | ||
1131 | dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW); | ||
1132 | |||
1133 | brw_set_dest(insn, dest); | ||
1134 | brw_set_src0(insn, brw_null_reg()); | ||
1135 | |||
1136 | brw_set_dp_read_message(p->brw, | ||
1137 | insn, | ||
1138 | bind_table_index, | ||
1139 | 0, /* msg_control (0 means 1 Oword) */ | ||
1140 | BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ | ||
1141 | 0, /* source cache = data cache */ | ||
1142 | 1, /* msg_length */ | ||
1143 | 1, /* response_length (1 Oword) */ | ||
1144 | 0); /* eot */ | ||
1145 | } | ||
1146 | } | ||
1147 | |||
1148 | |||
1149 | /** | ||
1150 | * Read float[4] constant(s) from VS constant buffer. | ||
1151 | * For relative addressing, two float[4] constants will be read into 'dest'. | ||
1152 | * Otherwise, one float[4] constant will be read into the lower half of 'dest'. | ||
1153 | */ | ||
1154 | void brw_dp_READ_4_vs(struct brw_compile *p, | ||
1155 | struct brw_reg dest, | ||
1156 | GLuint oword, | ||
1157 | GLboolean relAddr, | ||
1158 | struct brw_reg addrReg, | ||
1159 | GLuint location, | ||
1160 | GLuint bind_table_index) | ||
1161 | { | ||
1162 | GLuint msg_reg_nr = 1; | ||
1163 | |||
1164 | assert(oword < 2); | ||
1165 | /* | ||
1166 | printf("vs const read msg, location %u, msg_reg_nr %d\n", | ||
1167 | location, msg_reg_nr); | ||
1168 | */ | ||
1169 | |||
1170 | /* Setup MRF[1] with location/offset into const buffer */ | ||
1171 | { | ||
1172 | struct brw_reg b; | ||
1173 | |||
1174 | brw_push_insn_state(p); | ||
1175 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1176 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1177 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1178 | /*brw_set_access_mode(p, BRW_ALIGN_16);*/ | ||
1179 | |||
1180 | /* XXX I think we're setting all the dwords of MRF[1] to 'location'. | ||
1181 | * when the docs say only dword[2] should be set. Hmmm. But it works. | ||
1182 | */ | ||
1183 | b = brw_message_reg(msg_reg_nr); | ||
1184 | b = retype(b, BRW_REGISTER_TYPE_UD); | ||
1185 | /*b = get_element_ud(b, 2);*/ | ||
1186 | if (relAddr) { | ||
1187 | brw_ADD(p, b, addrReg, brw_imm_ud(location)); | ||
1188 | } | ||
1189 | else { | ||
1190 | brw_MOV(p, b, brw_imm_ud(location)); | ||
1191 | } | ||
1192 | |||
1193 | brw_pop_insn_state(p); | ||
1194 | } | ||
1195 | |||
1196 | { | ||
1197 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1198 | |||
1199 | insn->header.predicate_control = BRW_PREDICATE_NONE; | ||
1200 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1201 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1202 | insn->header.mask_control = BRW_MASK_DISABLE; | ||
1203 | /*insn->header.access_mode = BRW_ALIGN_16;*/ | ||
1204 | |||
1205 | brw_set_dest(insn, dest); | ||
1206 | brw_set_src0(insn, brw_null_reg()); | ||
1207 | |||
1208 | brw_set_dp_read_message(p->brw, | ||
1209 | insn, | ||
1210 | bind_table_index, | ||
1211 | oword, /* 0 = lower Oword, 1 = upper Oword */ | ||
1212 | BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ | ||
1213 | 0, /* source cache = data cache */ | ||
1214 | 1, /* msg_length */ | ||
1215 | 1, /* response_length (1 Oword) */ | ||
1216 | 0); /* eot */ | ||
1217 | } | ||
1218 | } | ||
1219 | |||
1220 | |||
1221 | |||
1222 | void brw_fb_WRITE(struct brw_compile *p, | ||
1223 | struct brw_reg dest, | ||
1224 | GLuint msg_reg_nr, | ||
1225 | struct brw_reg src0, | ||
1226 | GLuint binding_table_index, | ||
1227 | GLuint msg_length, | ||
1228 | GLuint response_length, | ||
1229 | GLboolean eot) | ||
1230 | { | ||
1231 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1232 | |||
1233 | insn->header.predicate_control = 0; /* XXX */ | ||
1234 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1235 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1236 | |||
1237 | brw_set_dest(insn, dest); | ||
1238 | brw_set_src0(insn, src0); | ||
1239 | brw_set_dp_write_message(p->brw, | ||
1240 | insn, | ||
1241 | binding_table_index, | ||
1242 | BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, /* msg_control */ | ||
1243 | BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, /* msg_type */ | ||
1244 | msg_length, | ||
1245 | 1, /* pixel scoreboard */ | ||
1246 | response_length, | ||
1247 | eot); | ||
1248 | } | ||
1249 | |||
1250 | |||
1251 | /** | ||
1252 | * Texture sample instruction. | ||
1253 | * Note: the msg_type plus msg_length values determine exactly what kind | ||
1254 | * of sampling operation is performed. See volume 4, page 161 of docs. | ||
1255 | */ | ||
1256 | void brw_SAMPLE(struct brw_compile *p, | ||
1257 | struct brw_reg dest, | ||
1258 | GLuint msg_reg_nr, | ||
1259 | struct brw_reg src0, | ||
1260 | GLuint binding_table_index, | ||
1261 | GLuint sampler, | ||
1262 | GLuint writemask, | ||
1263 | GLuint msg_type, | ||
1264 | GLuint response_length, | ||
1265 | GLuint msg_length, | ||
1266 | GLboolean eot, | ||
1267 | GLuint header_present, | ||
1268 | GLuint simd_mode) | ||
1269 | { | ||
1270 | GLboolean need_stall = 0; | ||
1271 | |||
1272 | if (writemask == 0) { | ||
1273 | /*debug_printf("%s: zero writemask??\n", __FUNCTION__); */ | ||
1274 | return; | ||
1275 | } | ||
1276 | |||
1277 | /* Hardware doesn't do destination dependency checking on send | ||
1278 | * instructions properly. Add a workaround which generates the | ||
1279 | * dependency by other means. In practice it seems like this bug | ||
1280 | * only crops up for texture samples, and only where registers are | ||
1281 | * written by the send and then written again later without being | ||
1282 | * read in between. Luckily for us, we already track that | ||
1283 | * information and use it to modify the writemask for the | ||
1284 | * instruction, so that is a guide for whether a workaround is | ||
1285 | * needed. | ||
1286 | */ | ||
1287 | if (writemask != BRW_WRITEMASK_XYZW) { | ||
1288 | GLuint dst_offset = 0; | ||
1289 | GLuint i, newmask = 0, len = 0; | ||
1290 | |||
1291 | for (i = 0; i < 4; i++) { | ||
1292 | if (writemask & (1<<i)) | ||
1293 | break; | ||
1294 | dst_offset += 2; | ||
1295 | } | ||
1296 | for (; i < 4; i++) { | ||
1297 | if (!(writemask & (1<<i))) | ||
1298 | break; | ||
1299 | newmask |= 1<<i; | ||
1300 | len++; | ||
1301 | } | ||
1302 | |||
1303 | if (newmask != writemask) { | ||
1304 | need_stall = 1; | ||
1305 | /* debug_printf("need stall %x %x\n", newmask , writemask); */ | ||
1306 | } | ||
1307 | else { | ||
1308 | struct brw_reg m1 = brw_message_reg(msg_reg_nr); | ||
1309 | |||
1310 | newmask = ~newmask & BRW_WRITEMASK_XYZW; | ||
1311 | |||
1312 | brw_push_insn_state(p); | ||
1313 | |||
1314 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1315 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1316 | |||
1317 | brw_MOV(p, m1, brw_vec8_grf(0,0)); | ||
1318 | brw_MOV(p, get_element_ud(m1, 2), brw_imm_ud(newmask << 12)); | ||
1319 | |||
1320 | brw_pop_insn_state(p); | ||
1321 | |||
1322 | src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); | ||
1323 | dest = offset(dest, dst_offset); | ||
1324 | response_length = len * 2; | ||
1325 | } | ||
1326 | } | ||
1327 | |||
1328 | { | ||
1329 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1330 | |||
1331 | insn->header.predicate_control = 0; /* XXX */ | ||
1332 | insn->header.compression_control = BRW_COMPRESSION_NONE; | ||
1333 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1334 | |||
1335 | brw_set_dest(insn, dest); | ||
1336 | brw_set_src0(insn, src0); | ||
1337 | brw_set_sampler_message(p->brw, insn, | ||
1338 | binding_table_index, | ||
1339 | sampler, | ||
1340 | msg_type, | ||
1341 | response_length, | ||
1342 | msg_length, | ||
1343 | eot, | ||
1344 | header_present, | ||
1345 | simd_mode); | ||
1346 | } | ||
1347 | |||
1348 | if (need_stall) { | ||
1349 | struct brw_reg reg = vec8(offset(dest, response_length-1)); | ||
1350 | |||
1351 | /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 } | ||
1352 | */ | ||
1353 | brw_push_insn_state(p); | ||
1354 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1355 | brw_MOV(p, reg, reg); | ||
1356 | brw_pop_insn_state(p); | ||
1357 | } | ||
1358 | |||
1359 | } | ||
1360 | |||
1361 | /* All these variables are pretty confusing - we might be better off | ||
1362 | * using bitmasks and macros for this, in the old style. Or perhaps | ||
1363 | * just having the caller instantiate the fields in dword3 itself. | ||
1364 | */ | ||
1365 | void brw_urb_WRITE(struct brw_compile *p, | ||
1366 | struct brw_reg dest, | ||
1367 | GLuint msg_reg_nr, | ||
1368 | struct brw_reg src0, | ||
1369 | GLboolean allocate, | ||
1370 | GLboolean used, | ||
1371 | GLuint msg_length, | ||
1372 | GLuint response_length, | ||
1373 | GLboolean eot, | ||
1374 | GLboolean writes_complete, | ||
1375 | GLuint offset, | ||
1376 | GLuint swizzle) | ||
1377 | { | ||
1378 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1379 | |||
1380 | assert(msg_length < BRW_MAX_MRF); | ||
1381 | |||
1382 | brw_set_dest(insn, dest); | ||
1383 | brw_set_src0(insn, src0); | ||
1384 | brw_set_src1(insn, brw_imm_d(0)); | ||
1385 | |||
1386 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1387 | |||
1388 | brw_set_urb_message(p->brw, | ||
1389 | insn, | ||
1390 | allocate, | ||
1391 | used, | ||
1392 | msg_length, | ||
1393 | response_length, | ||
1394 | eot, | ||
1395 | writes_complete, | ||
1396 | offset, | ||
1397 | swizzle); | ||
1398 | } | ||
1399 | |||
1400 | void brw_ff_sync(struct brw_compile *p, | ||
1401 | struct brw_reg dest, | ||
1402 | GLuint msg_reg_nr, | ||
1403 | struct brw_reg src0, | ||
1404 | GLboolean allocate, | ||
1405 | GLboolean used, | ||
1406 | GLuint msg_length, | ||
1407 | GLuint response_length, | ||
1408 | GLboolean eot, | ||
1409 | GLboolean writes_complete, | ||
1410 | GLuint offset, | ||
1411 | GLuint swizzle) | ||
1412 | { | ||
1413 | struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); | ||
1414 | |||
1415 | assert(msg_length < 16); | ||
1416 | |||
1417 | brw_set_dest(insn, dest); | ||
1418 | brw_set_src0(insn, src0); | ||
1419 | brw_set_src1(insn, brw_imm_d(0)); | ||
1420 | |||
1421 | insn->header.destreg__conditionalmod = msg_reg_nr; | ||
1422 | |||
1423 | brw_set_ff_sync_message(p->brw, | ||
1424 | insn, | ||
1425 | allocate, | ||
1426 | used, | ||
1427 | msg_length, | ||
1428 | response_length, | ||
1429 | eot, | ||
1430 | writes_complete, | ||
1431 | offset, | ||
1432 | swizzle); | ||
1433 | } | ||
diff --git a/src/gallium/drivers/i965/brw_eu_util.c b/src/gallium/drivers/i965/brw_eu_util.c deleted file mode 100644 index 5405cf17a4e..00000000000 --- a/src/gallium/drivers/i965/brw_eu_util.c +++ /dev/null | |||
@@ -1,126 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_context.h" | ||
34 | #include "brw_defines.h" | ||
35 | #include "brw_eu.h" | ||
36 | |||
37 | |||
38 | void brw_math_invert( struct brw_compile *p, | ||
39 | struct brw_reg dst, | ||
40 | struct brw_reg src) | ||
41 | { | ||
42 | brw_math( p, | ||
43 | dst, | ||
44 | BRW_MATH_FUNCTION_INV, | ||
45 | BRW_MATH_SATURATE_NONE, | ||
46 | 0, | ||
47 | src, | ||
48 | BRW_MATH_PRECISION_FULL, | ||
49 | BRW_MATH_DATA_VECTOR ); | ||
50 | } | ||
51 | |||
52 | |||
53 | |||
54 | void brw_copy4(struct brw_compile *p, | ||
55 | struct brw_reg dst, | ||
56 | struct brw_reg src, | ||
57 | GLuint count) | ||
58 | { | ||
59 | GLuint i; | ||
60 | |||
61 | dst = vec4(dst); | ||
62 | src = vec4(src); | ||
63 | |||
64 | for (i = 0; i < count; i++) | ||
65 | { | ||
66 | GLuint delta = i*32; | ||
67 | brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); | ||
68 | brw_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16)); | ||
69 | } | ||
70 | } | ||
71 | |||
72 | |||
73 | void brw_copy8(struct brw_compile *p, | ||
74 | struct brw_reg dst, | ||
75 | struct brw_reg src, | ||
76 | GLuint count) | ||
77 | { | ||
78 | GLuint i; | ||
79 | |||
80 | dst = vec8(dst); | ||
81 | src = vec8(src); | ||
82 | |||
83 | for (i = 0; i < count; i++) | ||
84 | { | ||
85 | GLuint delta = i*32; | ||
86 | brw_MOV(p, byte_offset(dst, delta), byte_offset(src, delta)); | ||
87 | } | ||
88 | } | ||
89 | |||
90 | |||
91 | void brw_copy_indirect_to_indirect(struct brw_compile *p, | ||
92 | struct brw_indirect dst_ptr, | ||
93 | struct brw_indirect src_ptr, | ||
94 | GLuint count) | ||
95 | { | ||
96 | GLuint i; | ||
97 | |||
98 | for (i = 0; i < count; i++) | ||
99 | { | ||
100 | GLuint delta = i*32; | ||
101 | brw_MOV(p, deref_4f(dst_ptr, delta), deref_4f(src_ptr, delta)); | ||
102 | brw_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16)); | ||
103 | } | ||
104 | } | ||
105 | |||
106 | |||
107 | void brw_copy_from_indirect(struct brw_compile *p, | ||
108 | struct brw_reg dst, | ||
109 | struct brw_indirect ptr, | ||
110 | GLuint count) | ||
111 | { | ||
112 | GLuint i; | ||
113 | |||
114 | dst = vec4(dst); | ||
115 | |||
116 | for (i = 0; i < count; i++) | ||
117 | { | ||
118 | GLuint delta = i*32; | ||
119 | brw_MOV(p, byte_offset(dst, delta), deref_4f(ptr, delta)); | ||
120 | brw_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16)); | ||
121 | } | ||
122 | } | ||
123 | |||
124 | |||
125 | |||
126 | |||
diff --git a/src/gallium/drivers/i965/brw_gs.c b/src/gallium/drivers/i965/brw_gs.c deleted file mode 100644 index 2a8165b83ee..00000000000 --- a/src/gallium/drivers/i965/brw_gs.c +++ /dev/null | |||
@@ -1,215 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "brw_batchbuffer.h" | ||
33 | |||
34 | #include "brw_defines.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_eu.h" | ||
37 | #include "brw_state.h" | ||
38 | #include "brw_gs.h" | ||
39 | |||
40 | |||
41 | |||
42 | static enum pipe_error compile_gs_prog( struct brw_context *brw, | ||
43 | struct brw_gs_prog_key *key, | ||
44 | struct brw_winsys_buffer **bo_out ) | ||
45 | { | ||
46 | struct brw_gs_compile c; | ||
47 | enum pipe_error ret; | ||
48 | const GLuint *program; | ||
49 | GLuint program_size; | ||
50 | |||
51 | memset(&c, 0, sizeof(c)); | ||
52 | |||
53 | c.key = *key; | ||
54 | c.need_ff_sync = brw->gen == 5; | ||
55 | /* Need to locate the two positions present in vertex + header. | ||
56 | * These are currently hardcoded: | ||
57 | */ | ||
58 | c.nr_attrs = c.key.nr_attrs; | ||
59 | |||
60 | if (brw->gen == 5) | ||
61 | c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ | ||
62 | else | ||
63 | c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ | ||
64 | |||
65 | c.nr_bytes = c.nr_regs * REG_SIZE; | ||
66 | |||
67 | |||
68 | /* Begin the compilation: | ||
69 | */ | ||
70 | brw_init_compile(brw, &c.func); | ||
71 | |||
72 | c.func.single_program_flow = 1; | ||
73 | |||
74 | /* For some reason the thread is spawned with only 4 channels | ||
75 | * unmasked. | ||
76 | */ | ||
77 | brw_set_mask_control(&c.func, BRW_MASK_DISABLE); | ||
78 | |||
79 | |||
80 | /* Note that primitives which don't require a GS program have | ||
81 | * already been weeded out by this stage: | ||
82 | */ | ||
83 | switch (key->primitive) { | ||
84 | case PIPE_PRIM_QUADS: | ||
85 | brw_gs_quads( &c ); | ||
86 | break; | ||
87 | case PIPE_PRIM_QUAD_STRIP: | ||
88 | brw_gs_quad_strip( &c ); | ||
89 | break; | ||
90 | case PIPE_PRIM_LINE_LOOP: | ||
91 | brw_gs_lines( &c ); | ||
92 | break; | ||
93 | case PIPE_PRIM_LINES: | ||
94 | if (key->hint_gs_always) | ||
95 | brw_gs_lines( &c ); | ||
96 | else { | ||
97 | return PIPE_OK; | ||
98 | } | ||
99 | break; | ||
100 | case PIPE_PRIM_TRIANGLES: | ||
101 | if (key->hint_gs_always) | ||
102 | brw_gs_tris( &c ); | ||
103 | else { | ||
104 | return PIPE_OK; | ||
105 | } | ||
106 | break; | ||
107 | case PIPE_PRIM_POINTS: | ||
108 | if (key->hint_gs_always) | ||
109 | brw_gs_points( &c ); | ||
110 | else { | ||
111 | return PIPE_OK; | ||
112 | } | ||
113 | break; | ||
114 | default: | ||
115 | assert(0); | ||
116 | return PIPE_ERROR_BAD_INPUT; | ||
117 | } | ||
118 | |||
119 | /* get the program | ||
120 | */ | ||
121 | ret = brw_get_program(&c.func, &program, &program_size); | ||
122 | if (ret) | ||
123 | return ret; | ||
124 | |||
125 | /* Upload | ||
126 | */ | ||
127 | ret = brw_upload_cache( &brw->cache, BRW_GS_PROG, | ||
128 | &c.key, sizeof(c.key), | ||
129 | NULL, 0, | ||
130 | program, program_size, | ||
131 | &c.prog_data, | ||
132 | &brw->gs.prog_data, | ||
133 | bo_out ); | ||
134 | if (ret) | ||
135 | return ret; | ||
136 | |||
137 | return PIPE_OK; | ||
138 | } | ||
139 | |||
140 | static const unsigned gs_prim[PIPE_PRIM_MAX] = { | ||
141 | PIPE_PRIM_POINTS, | ||
142 | PIPE_PRIM_LINES, | ||
143 | PIPE_PRIM_LINE_LOOP, | ||
144 | PIPE_PRIM_LINES, | ||
145 | PIPE_PRIM_TRIANGLES, | ||
146 | PIPE_PRIM_TRIANGLES, | ||
147 | PIPE_PRIM_TRIANGLES, | ||
148 | PIPE_PRIM_QUADS, | ||
149 | PIPE_PRIM_QUAD_STRIP, | ||
150 | PIPE_PRIM_TRIANGLES | ||
151 | }; | ||
152 | |||
153 | static void populate_key( struct brw_context *brw, | ||
154 | struct brw_gs_prog_key *key ) | ||
155 | { | ||
156 | const struct brw_fs_signature *sig = &brw->curr.fragment_shader->signature; | ||
157 | |||
158 | memset(key, 0, sizeof(*key)); | ||
159 | |||
160 | /* PIPE_NEW_FRAGMENT_SIGNATURE */ | ||
161 | key->nr_attrs = sig->nr_inputs + 1; | ||
162 | |||
163 | /* BRW_NEW_PRIMITIVE */ | ||
164 | key->primitive = gs_prim[brw->primitive]; | ||
165 | |||
166 | key->hint_gs_always = 0; /* debug code? */ | ||
167 | |||
168 | key->need_gs_prog = (key->hint_gs_always || | ||
169 | brw->primitive == PIPE_PRIM_QUADS || | ||
170 | brw->primitive == PIPE_PRIM_QUAD_STRIP || | ||
171 | brw->primitive == PIPE_PRIM_LINE_LOOP); | ||
172 | } | ||
173 | |||
174 | /* Calculate interpolants for triangle and line rasterization. | ||
175 | */ | ||
176 | static int prepare_gs_prog(struct brw_context *brw) | ||
177 | { | ||
178 | struct brw_gs_prog_key key; | ||
179 | enum pipe_error ret; | ||
180 | |||
181 | /* Populate the key: | ||
182 | */ | ||
183 | populate_key(brw, &key); | ||
184 | |||
185 | if (brw->gs.prog_active != key.need_gs_prog) { | ||
186 | brw->state.dirty.cache |= CACHE_NEW_GS_PROG; | ||
187 | brw->gs.prog_active = key.need_gs_prog; | ||
188 | } | ||
189 | |||
190 | if (!brw->gs.prog_active) | ||
191 | return PIPE_OK; | ||
192 | |||
193 | if (brw_search_cache(&brw->cache, BRW_GS_PROG, | ||
194 | &key, sizeof(key), | ||
195 | NULL, 0, | ||
196 | &brw->gs.prog_data, | ||
197 | &brw->gs.prog_bo)) | ||
198 | return PIPE_OK; | ||
199 | |||
200 | ret = compile_gs_prog( brw, &key, &brw->gs.prog_bo ); | ||
201 | if (ret) | ||
202 | return ret; | ||
203 | |||
204 | return PIPE_OK; | ||
205 | } | ||
206 | |||
207 | |||
208 | const struct brw_tracked_state brw_gs_prog = { | ||
209 | .dirty = { | ||
210 | .mesa = PIPE_NEW_FRAGMENT_SIGNATURE, | ||
211 | .brw = BRW_NEW_PRIMITIVE, | ||
212 | .cache = 0, | ||
213 | }, | ||
214 | .prepare = prepare_gs_prog | ||
215 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_gs.h b/src/gallium/drivers/i965/brw_gs.h deleted file mode 100644 index 6e616dcb875..00000000000 --- a/src/gallium/drivers/i965/brw_gs.h +++ /dev/null | |||
@@ -1,76 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_GS_H | ||
34 | #define BRW_GS_H | ||
35 | |||
36 | |||
37 | #include "brw_context.h" | ||
38 | #include "brw_eu.h" | ||
39 | |||
40 | #define MAX_GS_VERTS (4) | ||
41 | |||
42 | struct brw_gs_prog_key { | ||
43 | GLuint nr_attrs:8; | ||
44 | GLuint primitive:4; | ||
45 | GLuint hint_gs_always:1; | ||
46 | GLuint need_gs_prog:1; | ||
47 | GLuint pad:18; | ||
48 | }; | ||
49 | |||
50 | struct brw_gs_compile { | ||
51 | struct brw_compile func; | ||
52 | struct brw_gs_prog_key key; | ||
53 | struct brw_gs_prog_data prog_data; | ||
54 | |||
55 | struct { | ||
56 | struct brw_reg R0; | ||
57 | struct brw_reg vertex[MAX_GS_VERTS]; | ||
58 | } reg; | ||
59 | |||
60 | /* 3 different ways of expressing vertex size: | ||
61 | */ | ||
62 | GLuint nr_attrs; | ||
63 | GLuint nr_regs; | ||
64 | GLuint nr_bytes; | ||
65 | GLboolean need_ff_sync; | ||
66 | }; | ||
67 | |||
68 | #define ATTR_SIZE (4*4) | ||
69 | |||
70 | void brw_gs_quads( struct brw_gs_compile *c ); | ||
71 | void brw_gs_quad_strip( struct brw_gs_compile *c ); | ||
72 | void brw_gs_tris( struct brw_gs_compile *c ); | ||
73 | void brw_gs_lines( struct brw_gs_compile *c ); | ||
74 | void brw_gs_points( struct brw_gs_compile *c ); | ||
75 | |||
76 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_gs_emit.c b/src/gallium/drivers/i965/brw_gs_emit.c deleted file mode 100644 index 9b58773b3bd..00000000000 --- a/src/gallium/drivers/i965/brw_gs_emit.c +++ /dev/null | |||
@@ -1,180 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_batchbuffer.h" | ||
34 | |||
35 | #include "brw_defines.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_eu.h" | ||
38 | #include "brw_gs.h" | ||
39 | |||
40 | static void brw_gs_alloc_regs( struct brw_gs_compile *c, | ||
41 | GLuint nr_verts ) | ||
42 | { | ||
43 | GLuint i = 0,j; | ||
44 | |||
45 | /* Register usage is static, precompute here: | ||
46 | */ | ||
47 | c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; | ||
48 | |||
49 | /* Payload vertices plus space for more generated vertices: | ||
50 | */ | ||
51 | for (j = 0; j < nr_verts; j++) { | ||
52 | c->reg.vertex[j] = brw_vec4_grf(i, 0); | ||
53 | i += c->nr_regs; | ||
54 | } | ||
55 | |||
56 | c->prog_data.urb_read_length = c->nr_regs; | ||
57 | c->prog_data.total_grf = i; | ||
58 | } | ||
59 | |||
60 | |||
61 | static void brw_gs_emit_vue(struct brw_gs_compile *c, | ||
62 | struct brw_reg vert, | ||
63 | GLboolean last, | ||
64 | GLuint header) | ||
65 | { | ||
66 | struct brw_compile *p = &c->func; | ||
67 | GLboolean allocate = !last; | ||
68 | |||
69 | /* Overwrite PrimType and PrimStart in the message header, for | ||
70 | * each vertex in turn: | ||
71 | */ | ||
72 | brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header)); | ||
73 | |||
74 | /* Copy the vertex from vertn into m1..mN+1: | ||
75 | */ | ||
76 | brw_copy8(p, brw_message_reg(1), vert, c->nr_regs); | ||
77 | |||
78 | /* Send each vertex as a seperate write to the urb. This is | ||
79 | * different to the concept in brw_sf_emit.c, where subsequent | ||
80 | * writes are used to build up a single urb entry. Each of these | ||
81 | * writes instantiates a seperate urb entry, and a new one must be | ||
82 | * allocated each time. | ||
83 | */ | ||
84 | brw_urb_WRITE(p, | ||
85 | allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), | ||
86 | 0, | ||
87 | c->reg.R0, | ||
88 | allocate, | ||
89 | 1, /* used */ | ||
90 | c->nr_regs + 1, /* msg length */ | ||
91 | allocate ? 1 : 0, /* response length */ | ||
92 | allocate ? 0 : 1, /* eot */ | ||
93 | 1, /* writes_complete */ | ||
94 | 0, /* urb offset */ | ||
95 | BRW_URB_SWIZZLE_NONE); | ||
96 | } | ||
97 | |||
98 | static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) | ||
99 | { | ||
100 | struct brw_compile *p = &c->func; | ||
101 | brw_MOV(p, get_element_ud(c->reg.R0, 1), brw_imm_ud(num_prim)); | ||
102 | brw_ff_sync(p, | ||
103 | c->reg.R0, | ||
104 | 0, | ||
105 | c->reg.R0, | ||
106 | 1, | ||
107 | 1, /* used */ | ||
108 | 1, /* msg length */ | ||
109 | 1, /* response length */ | ||
110 | 0, /* eot */ | ||
111 | 1, /* write compelete */ | ||
112 | 0, /* urb offset */ | ||
113 | BRW_URB_SWIZZLE_NONE); | ||
114 | } | ||
115 | |||
116 | |||
117 | void brw_gs_quads( struct brw_gs_compile *c ) | ||
118 | { | ||
119 | brw_gs_alloc_regs(c, 4); | ||
120 | |||
121 | /* Use polygons for correct edgeflag behaviour. Note that vertex 3 | ||
122 | * is the PV for quads, but vertex 0 for polygons: | ||
123 | */ | ||
124 | if (c->need_ff_sync) | ||
125 | brw_gs_ff_sync(c, 1); | ||
126 | brw_gs_emit_vue(c, c->reg.vertex[3], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); | ||
127 | brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); | ||
128 | brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2)); | ||
129 | brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); | ||
130 | } | ||
131 | |||
132 | void brw_gs_quad_strip( struct brw_gs_compile *c ) | ||
133 | { | ||
134 | brw_gs_alloc_regs(c, 4); | ||
135 | |||
136 | if (c->need_ff_sync) | ||
137 | brw_gs_ff_sync(c, 1); | ||
138 | brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); | ||
139 | brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); | ||
140 | brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); | ||
141 | brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); | ||
142 | } | ||
143 | |||
144 | void brw_gs_tris( struct brw_gs_compile *c ) | ||
145 | { | ||
146 | brw_gs_alloc_regs(c, 3); | ||
147 | |||
148 | if (c->need_ff_sync) | ||
149 | brw_gs_ff_sync(c, 1); | ||
150 | brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_TRILIST << 2) | R02_PRIM_START)); | ||
151 | brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_TRILIST << 2)); | ||
152 | brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_TRILIST << 2) | R02_PRIM_END)); | ||
153 | } | ||
154 | |||
155 | void brw_gs_lines( struct brw_gs_compile *c ) | ||
156 | { | ||
157 | brw_gs_alloc_regs(c, 2); | ||
158 | |||
159 | if (c->need_ff_sync) | ||
160 | brw_gs_ff_sync(c, 1); | ||
161 | brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_START)); | ||
162 | brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_END)); | ||
163 | } | ||
164 | |||
165 | void brw_gs_points( struct brw_gs_compile *c ) | ||
166 | { | ||
167 | brw_gs_alloc_regs(c, 1); | ||
168 | |||
169 | if (c->need_ff_sync) | ||
170 | brw_gs_ff_sync(c, 1); | ||
171 | brw_gs_emit_vue(c, c->reg.vertex[0], 1, ((_3DPRIM_POINTLIST << 2) | R02_PRIM_START | R02_PRIM_END)); | ||
172 | } | ||
173 | |||
174 | |||
175 | |||
176 | |||
177 | |||
178 | |||
179 | |||
180 | |||
diff --git a/src/gallium/drivers/i965/brw_gs_state.c b/src/gallium/drivers/i965/brw_gs_state.c deleted file mode 100644 index 6e070f6d756..00000000000 --- a/src/gallium/drivers/i965/brw_gs_state.c +++ /dev/null | |||
@@ -1,169 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_state.h" | ||
36 | #include "brw_defines.h" | ||
37 | #include "brw_debug.h" | ||
38 | |||
39 | struct brw_gs_unit_key { | ||
40 | unsigned int total_grf; | ||
41 | unsigned int urb_entry_read_length; | ||
42 | |||
43 | unsigned int curbe_offset; | ||
44 | |||
45 | unsigned int nr_urb_entries, urb_size; | ||
46 | GLboolean prog_active; | ||
47 | }; | ||
48 | |||
49 | static void | ||
50 | gs_unit_populate_key(struct brw_context *brw, struct brw_gs_unit_key *key) | ||
51 | { | ||
52 | memset(key, 0, sizeof(*key)); | ||
53 | |||
54 | /* CACHE_NEW_GS_PROG */ | ||
55 | key->prog_active = brw->gs.prog_active; | ||
56 | if (key->prog_active) { | ||
57 | key->total_grf = brw->gs.prog_data->total_grf; | ||
58 | key->urb_entry_read_length = brw->gs.prog_data->urb_read_length; | ||
59 | } else { | ||
60 | key->total_grf = 1; | ||
61 | key->urb_entry_read_length = 1; | ||
62 | } | ||
63 | |||
64 | /* BRW_NEW_CURBE_OFFSETS */ | ||
65 | key->curbe_offset = brw->curbe.clip_start; | ||
66 | |||
67 | /* BRW_NEW_URB_FENCE */ | ||
68 | key->nr_urb_entries = brw->urb.nr_gs_entries; | ||
69 | key->urb_size = brw->urb.vsize; | ||
70 | } | ||
71 | |||
72 | static enum pipe_error | ||
73 | gs_unit_create_from_key(struct brw_context *brw, | ||
74 | struct brw_gs_unit_key *key, | ||
75 | struct brw_winsys_reloc *reloc, | ||
76 | unsigned nr_reloc, | ||
77 | struct brw_winsys_buffer **bo_out) | ||
78 | { | ||
79 | struct brw_gs_unit_state gs; | ||
80 | enum pipe_error ret; | ||
81 | |||
82 | |||
83 | memset(&gs, 0, sizeof(gs)); | ||
84 | |||
85 | /* reloc */ | ||
86 | gs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1; | ||
87 | gs.thread0.kernel_start_pointer = 0; | ||
88 | |||
89 | gs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; | ||
90 | gs.thread1.single_program_flow = 1; | ||
91 | |||
92 | gs.thread3.dispatch_grf_start_reg = 1; | ||
93 | gs.thread3.const_urb_entry_read_offset = 0; | ||
94 | gs.thread3.const_urb_entry_read_length = 0; | ||
95 | gs.thread3.urb_entry_read_offset = 0; | ||
96 | gs.thread3.urb_entry_read_length = key->urb_entry_read_length; | ||
97 | |||
98 | gs.thread4.nr_urb_entries = key->nr_urb_entries; | ||
99 | gs.thread4.urb_entry_allocation_size = key->urb_size - 1; | ||
100 | |||
101 | if (key->nr_urb_entries >= 8) | ||
102 | gs.thread4.max_threads = 1; | ||
103 | else | ||
104 | gs.thread4.max_threads = 0; | ||
105 | |||
106 | if (brw->gen == 5) | ||
107 | gs.thread4.rendering_enable = 1; | ||
108 | |||
109 | if (BRW_DEBUG & DEBUG_STATS) | ||
110 | gs.thread4.stats_enable = 1; | ||
111 | |||
112 | ret = brw_upload_cache(&brw->cache, BRW_GS_UNIT, | ||
113 | key, sizeof(*key), | ||
114 | reloc, nr_reloc, | ||
115 | &gs, sizeof(gs), | ||
116 | NULL, NULL, | ||
117 | bo_out); | ||
118 | if (ret) | ||
119 | return ret; | ||
120 | |||
121 | return PIPE_OK; | ||
122 | } | ||
123 | |||
124 | static enum pipe_error prepare_gs_unit(struct brw_context *brw) | ||
125 | { | ||
126 | struct brw_gs_unit_key key; | ||
127 | enum pipe_error ret; | ||
128 | struct brw_winsys_reloc reloc[1]; | ||
129 | unsigned nr_reloc = 0; | ||
130 | unsigned grf_reg_count; | ||
131 | |||
132 | gs_unit_populate_key(brw, &key); | ||
133 | |||
134 | grf_reg_count = (align(key.total_grf, 16) / 16 - 1); | ||
135 | |||
136 | /* GS program relocation */ | ||
137 | if (key.prog_active) { | ||
138 | make_reloc(&reloc[nr_reloc++], | ||
139 | BRW_USAGE_STATE, | ||
140 | grf_reg_count << 1, | ||
141 | offsetof(struct brw_gs_unit_state, thread0), | ||
142 | brw->gs.prog_bo); | ||
143 | } | ||
144 | |||
145 | if (brw_search_cache(&brw->cache, BRW_GS_UNIT, | ||
146 | &key, sizeof(key), | ||
147 | reloc, nr_reloc, | ||
148 | NULL, | ||
149 | &brw->gs.state_bo)) | ||
150 | return PIPE_OK; | ||
151 | |||
152 | ret = gs_unit_create_from_key(brw, &key, | ||
153 | reloc, nr_reloc, | ||
154 | &brw->gs.state_bo); | ||
155 | if (ret) | ||
156 | return ret; | ||
157 | |||
158 | return PIPE_OK; | ||
159 | } | ||
160 | |||
161 | const struct brw_tracked_state brw_gs_unit = { | ||
162 | .dirty = { | ||
163 | .mesa = 0, | ||
164 | .brw = (BRW_NEW_CURBE_OFFSETS | | ||
165 | BRW_NEW_URB_FENCE), | ||
166 | .cache = CACHE_NEW_GS_PROG | ||
167 | }, | ||
168 | .prepare = prepare_gs_unit, | ||
169 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_misc_state.c b/src/gallium/drivers/i965/brw_misc_state.c deleted file mode 100644 index 7d481a78433..00000000000 --- a/src/gallium/drivers/i965/brw_misc_state.c +++ /dev/null | |||
@@ -1,514 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | |||
34 | #include "brw_debug.h" | ||
35 | #include "brw_batchbuffer.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_state.h" | ||
38 | #include "brw_defines.h" | ||
39 | #include "brw_screen.h" | ||
40 | #include "brw_pipe_rast.h" | ||
41 | |||
42 | |||
43 | |||
44 | |||
45 | |||
46 | /*********************************************************************** | ||
47 | * Blend color | ||
48 | */ | ||
49 | |||
50 | static int upload_blend_constant_color(struct brw_context *brw) | ||
51 | { | ||
52 | BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bcc); | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | |||
57 | const struct brw_tracked_state brw_blend_constant_color = { | ||
58 | .dirty = { | ||
59 | .mesa = PIPE_NEW_BLEND_COLOR, | ||
60 | .brw = 0, | ||
61 | .cache = 0 | ||
62 | }, | ||
63 | .emit = upload_blend_constant_color | ||
64 | }; | ||
65 | |||
66 | /*********************************************************************** | ||
67 | * Drawing rectangle - framebuffer dimensions | ||
68 | */ | ||
69 | static int upload_drawing_rect(struct brw_context *brw) | ||
70 | { | ||
71 | BEGIN_BATCH(4, NO_LOOP_CLIPRECTS); | ||
72 | OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); | ||
73 | OUT_BATCH(0); | ||
74 | OUT_BATCH(((brw->curr.fb.width - 1) & 0xffff) | | ||
75 | ((brw->curr.fb.height - 1) << 16)); | ||
76 | OUT_BATCH(0); | ||
77 | ADVANCE_BATCH(); | ||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | const struct brw_tracked_state brw_drawing_rect = { | ||
82 | .dirty = { | ||
83 | .mesa = PIPE_NEW_FRAMEBUFFER_DIMENSIONS, | ||
84 | .brw = 0, | ||
85 | .cache = 0 | ||
86 | }, | ||
87 | .emit = upload_drawing_rect | ||
88 | }; | ||
89 | |||
90 | |||
91 | /*********************************************************************** | ||
92 | * Binding table pointers | ||
93 | */ | ||
94 | |||
95 | static int prepare_binding_table_pointers(struct brw_context *brw) | ||
96 | { | ||
97 | brw_add_validated_bo(brw, brw->vs.bind_bo); | ||
98 | brw_add_validated_bo(brw, brw->wm.bind_bo); | ||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | /** | ||
103 | * Upload the binding table pointers, which point each stage's array of surface | ||
104 | * state pointers. | ||
105 | * | ||
106 | * The binding table pointers are relative to the surface state base address, | ||
107 | * which is 0. | ||
108 | */ | ||
109 | static int upload_binding_table_pointers(struct brw_context *brw) | ||
110 | { | ||
111 | BEGIN_BATCH(6, IGNORE_CLIPRECTS); | ||
112 | OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2)); | ||
113 | if (brw->vs.bind_bo != NULL) | ||
114 | OUT_RELOC(brw->vs.bind_bo, | ||
115 | BRW_USAGE_SAMPLER, | ||
116 | 0); /* vs */ | ||
117 | else | ||
118 | OUT_BATCH(0); | ||
119 | OUT_BATCH(0); /* gs */ | ||
120 | OUT_BATCH(0); /* clip */ | ||
121 | OUT_BATCH(0); /* sf */ | ||
122 | OUT_RELOC(brw->wm.bind_bo, | ||
123 | BRW_USAGE_SAMPLER, | ||
124 | 0); /* wm/ps */ | ||
125 | ADVANCE_BATCH(); | ||
126 | return 0; | ||
127 | } | ||
128 | |||
129 | const struct brw_tracked_state brw_binding_table_pointers = { | ||
130 | .dirty = { | ||
131 | .mesa = 0, | ||
132 | .brw = BRW_NEW_BATCH, | ||
133 | .cache = CACHE_NEW_SURF_BIND, | ||
134 | }, | ||
135 | .prepare = prepare_binding_table_pointers, | ||
136 | .emit = upload_binding_table_pointers, | ||
137 | }; | ||
138 | |||
139 | |||
140 | /********************************************************************** | ||
141 | * Upload pointers to the per-stage state. | ||
142 | * | ||
143 | * The state pointers in this packet are all relative to the general state | ||
144 | * base address set by CMD_STATE_BASE_ADDRESS, which is 0. | ||
145 | */ | ||
146 | static int upload_pipelined_state_pointers(struct brw_context *brw ) | ||
147 | { | ||
148 | BEGIN_BATCH(7, IGNORE_CLIPRECTS); | ||
149 | OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2)); | ||
150 | OUT_RELOC(brw->vs.state_bo, | ||
151 | BRW_USAGE_STATE, | ||
152 | 0); | ||
153 | if (brw->gs.prog_active) | ||
154 | OUT_RELOC(brw->gs.state_bo, | ||
155 | BRW_USAGE_STATE, | ||
156 | 1); | ||
157 | else | ||
158 | OUT_BATCH(0); | ||
159 | OUT_RELOC(brw->clip.state_bo, | ||
160 | BRW_USAGE_STATE, | ||
161 | 1); | ||
162 | OUT_RELOC(brw->sf.state_bo, | ||
163 | BRW_USAGE_STATE, | ||
164 | 0); | ||
165 | OUT_RELOC(brw->wm.state_bo, | ||
166 | BRW_USAGE_STATE, | ||
167 | 0); | ||
168 | OUT_RELOC(brw->cc.state_bo, | ||
169 | BRW_USAGE_STATE, | ||
170 | 0); | ||
171 | ADVANCE_BATCH(); | ||
172 | |||
173 | brw->state.dirty.brw |= BRW_NEW_PSP; | ||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | |||
178 | static int prepare_psp_urb_cbs(struct brw_context *brw) | ||
179 | { | ||
180 | brw_add_validated_bo(brw, brw->vs.state_bo); | ||
181 | brw_add_validated_bo(brw, brw->gs.state_bo); | ||
182 | brw_add_validated_bo(brw, brw->clip.state_bo); | ||
183 | brw_add_validated_bo(brw, brw->sf.state_bo); | ||
184 | brw_add_validated_bo(brw, brw->wm.state_bo); | ||
185 | brw_add_validated_bo(brw, brw->cc.state_bo); | ||
186 | return 0; | ||
187 | } | ||
188 | |||
189 | static int upload_psp_urb_cbs(struct brw_context *brw ) | ||
190 | { | ||
191 | int ret; | ||
192 | |||
193 | ret = upload_pipelined_state_pointers(brw); | ||
194 | if (ret) | ||
195 | return ret; | ||
196 | |||
197 | ret = brw_upload_urb_fence(brw); | ||
198 | if (ret) | ||
199 | return ret; | ||
200 | |||
201 | ret = brw_upload_cs_urb_state(brw); | ||
202 | if (ret) | ||
203 | return ret; | ||
204 | |||
205 | return 0; | ||
206 | } | ||
207 | |||
208 | const struct brw_tracked_state brw_psp_urb_cbs = { | ||
209 | .dirty = { | ||
210 | .mesa = 0, | ||
211 | .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH, | ||
212 | .cache = (CACHE_NEW_VS_UNIT | | ||
213 | CACHE_NEW_GS_UNIT | | ||
214 | CACHE_NEW_GS_PROG | | ||
215 | CACHE_NEW_CLIP_UNIT | | ||
216 | CACHE_NEW_SF_UNIT | | ||
217 | CACHE_NEW_WM_UNIT | | ||
218 | CACHE_NEW_CC_UNIT) | ||
219 | }, | ||
220 | .prepare = prepare_psp_urb_cbs, | ||
221 | .emit = upload_psp_urb_cbs, | ||
222 | }; | ||
223 | |||
224 | |||
225 | /*********************************************************************** | ||
226 | * Depth buffer | ||
227 | */ | ||
228 | |||
229 | static int prepare_depthbuffer(struct brw_context *brw) | ||
230 | { | ||
231 | struct pipe_surface *zsbuf = brw->curr.fb.zsbuf; | ||
232 | |||
233 | if (zsbuf) | ||
234 | brw_add_validated_bo(brw, brw_surface(zsbuf)->bo); | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
239 | static int emit_depthbuffer(struct brw_context *brw) | ||
240 | { | ||
241 | struct pipe_surface *surface = brw->curr.fb.zsbuf; | ||
242 | unsigned int len = (brw->is_g4x || brw->gen == 5) ? 6 : 5; | ||
243 | |||
244 | if (surface == NULL) { | ||
245 | BEGIN_BATCH(len, IGNORE_CLIPRECTS); | ||
246 | OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); | ||
247 | OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | | ||
248 | (BRW_SURFACE_NULL << 29)); | ||
249 | OUT_BATCH(0); | ||
250 | OUT_BATCH(0); | ||
251 | OUT_BATCH(0); | ||
252 | |||
253 | if (brw->is_g4x || brw->gen == 5) | ||
254 | OUT_BATCH(0); | ||
255 | |||
256 | ADVANCE_BATCH(); | ||
257 | } else { | ||
258 | struct brw_winsys_buffer *bo; | ||
259 | unsigned int format; | ||
260 | unsigned int pitch; | ||
261 | unsigned int cpp; | ||
262 | |||
263 | switch (surface->format) { | ||
264 | case PIPE_FORMAT_Z16_UNORM: | ||
265 | format = BRW_DEPTHFORMAT_D16_UNORM; | ||
266 | cpp = 2; | ||
267 | break; | ||
268 | case PIPE_FORMAT_Z24X8_UNORM: | ||
269 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: | ||
270 | format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; | ||
271 | cpp = 4; | ||
272 | break; | ||
273 | case PIPE_FORMAT_Z32_FLOAT: | ||
274 | format = BRW_DEPTHFORMAT_D32_FLOAT; | ||
275 | cpp = 4; | ||
276 | break; | ||
277 | default: | ||
278 | assert(0); | ||
279 | return PIPE_ERROR_BAD_INPUT; | ||
280 | } | ||
281 | |||
282 | bo = brw_surface(surface)->bo; | ||
283 | pitch = brw_surface(surface)->pitch; | ||
284 | |||
285 | BEGIN_BATCH(len, IGNORE_CLIPRECTS); | ||
286 | OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); | ||
287 | OUT_BATCH(((pitch * cpp) - 1) | | ||
288 | (format << 18) | | ||
289 | (BRW_TILEWALK_YMAJOR << 26) | | ||
290 | /* always linear ? | ||
291 | ((surface->layout != PIPE_SURFACE_LAYOUT_LINEAR) << 27) |*/ | ||
292 | (BRW_SURFACE_2D << 29)); | ||
293 | OUT_RELOC(bo, | ||
294 | BRW_USAGE_DEPTH_BUFFER, | ||
295 | brw_surface(surface)->offset); | ||
296 | OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | | ||
297 | ((pitch - 1) << 6) | | ||
298 | ((surface->height - 1) << 19)); | ||
299 | OUT_BATCH(0); | ||
300 | |||
301 | if (brw->is_g4x || brw->gen == 5) | ||
302 | OUT_BATCH(0); | ||
303 | |||
304 | ADVANCE_BATCH(); | ||
305 | } | ||
306 | |||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | const struct brw_tracked_state brw_depthbuffer = { | ||
311 | .dirty = { | ||
312 | .mesa = PIPE_NEW_DEPTH_BUFFER, | ||
313 | .brw = BRW_NEW_BATCH, | ||
314 | .cache = 0, | ||
315 | }, | ||
316 | .prepare = prepare_depthbuffer, | ||
317 | .emit = emit_depthbuffer, | ||
318 | }; | ||
319 | |||
320 | |||
321 | |||
322 | /*********************************************************************** | ||
323 | * Polygon stipple packet | ||
324 | */ | ||
325 | |||
326 | static int upload_polygon_stipple(struct brw_context *brw) | ||
327 | { | ||
328 | BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bps); | ||
329 | return 0; | ||
330 | } | ||
331 | |||
332 | const struct brw_tracked_state brw_polygon_stipple = { | ||
333 | .dirty = { | ||
334 | .mesa = PIPE_NEW_POLYGON_STIPPLE, | ||
335 | .brw = 0, | ||
336 | .cache = 0 | ||
337 | }, | ||
338 | .emit = upload_polygon_stipple | ||
339 | }; | ||
340 | |||
341 | |||
342 | /*********************************************************************** | ||
343 | * Line stipple packet | ||
344 | */ | ||
345 | |||
346 | static int upload_line_stipple(struct brw_context *brw) | ||
347 | { | ||
348 | const struct brw_line_stipple *bls = &brw->curr.rast->bls; | ||
349 | if (bls->header.opcode) { | ||
350 | BRW_CACHED_BATCH_STRUCT(brw, bls); | ||
351 | } | ||
352 | return 0; | ||
353 | } | ||
354 | |||
355 | const struct brw_tracked_state brw_line_stipple = { | ||
356 | .dirty = { | ||
357 | .mesa = PIPE_NEW_RAST, | ||
358 | .brw = 0, | ||
359 | .cache = 0 | ||
360 | }, | ||
361 | .emit = upload_line_stipple | ||
362 | }; | ||
363 | |||
364 | |||
365 | /*********************************************************************** | ||
366 | * Misc invariant state packets | ||
367 | */ | ||
368 | |||
369 | static int upload_invariant_state( struct brw_context *brw ) | ||
370 | { | ||
371 | { | ||
372 | /* 0x61040000 Pipeline Select */ | ||
373 | /* PipelineSelect : 0 */ | ||
374 | struct brw_pipeline_select ps; | ||
375 | |||
376 | memset(&ps, 0, sizeof(ps)); | ||
377 | if (brw->is_g4x || brw->gen == 5) | ||
378 | ps.header.opcode = CMD_PIPELINE_SELECT_GM45; | ||
379 | else | ||
380 | ps.header.opcode = CMD_PIPELINE_SELECT_965; | ||
381 | ps.header.pipeline_select = 0; | ||
382 | BRW_BATCH_STRUCT(brw, &ps); | ||
383 | } | ||
384 | |||
385 | { | ||
386 | struct brw_global_depth_offset_clamp gdo; | ||
387 | memset(&gdo, 0, sizeof(gdo)); | ||
388 | |||
389 | /* Disable depth offset clamping. | ||
390 | */ | ||
391 | gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP; | ||
392 | gdo.header.length = sizeof(gdo)/4 - 2; | ||
393 | gdo.depth_offset_clamp = 0.0; | ||
394 | |||
395 | BRW_BATCH_STRUCT(brw, &gdo); | ||
396 | } | ||
397 | |||
398 | |||
399 | /* 0x61020000 State Instruction Pointer */ | ||
400 | { | ||
401 | struct brw_system_instruction_pointer sip; | ||
402 | memset(&sip, 0, sizeof(sip)); | ||
403 | |||
404 | sip.header.opcode = CMD_STATE_INSN_POINTER; | ||
405 | sip.header.length = 0; | ||
406 | sip.bits0.pad = 0; | ||
407 | sip.bits0.system_instruction_pointer = 0; | ||
408 | BRW_BATCH_STRUCT(brw, &sip); | ||
409 | } | ||
410 | |||
411 | /* VF Statistics */ | ||
412 | { | ||
413 | struct brw_vf_statistics vfs; | ||
414 | memset(&vfs, 0, sizeof(vfs)); | ||
415 | |||
416 | if (brw->is_g4x || brw->gen == 5) | ||
417 | vfs.opcode = CMD_VF_STATISTICS_GM45; | ||
418 | else | ||
419 | vfs.opcode = CMD_VF_STATISTICS_965; | ||
420 | |||
421 | if (BRW_DEBUG & DEBUG_STATS) | ||
422 | vfs.statistics_enable = 1; | ||
423 | |||
424 | BRW_BATCH_STRUCT(brw, &vfs); | ||
425 | } | ||
426 | |||
427 | if (!(brw->gen == 4)) | ||
428 | { | ||
429 | struct brw_aa_line_parameters balp; | ||
430 | |||
431 | /* use legacy aa line coverage computation */ | ||
432 | memset(&balp, 0, sizeof(balp)); | ||
433 | balp.header.opcode = CMD_AA_LINE_PARAMETERS; | ||
434 | balp.header.length = sizeof(balp) / 4 - 2; | ||
435 | |||
436 | BRW_BATCH_STRUCT(brw, &balp); | ||
437 | } | ||
438 | |||
439 | { | ||
440 | struct brw_polygon_stipple_offset bpso; | ||
441 | |||
442 | /* This is invariant state in gallium: | ||
443 | */ | ||
444 | memset(&bpso, 0, sizeof(bpso)); | ||
445 | bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET; | ||
446 | bpso.header.length = sizeof(bpso)/4-2; | ||
447 | bpso.bits0.y_offset = 0; | ||
448 | bpso.bits0.x_offset = 0; | ||
449 | |||
450 | BRW_BATCH_STRUCT(brw, &bpso); | ||
451 | } | ||
452 | |||
453 | return 0; | ||
454 | } | ||
455 | |||
456 | const struct brw_tracked_state brw_invariant_state = { | ||
457 | .dirty = { | ||
458 | .mesa = 0, | ||
459 | .brw = BRW_NEW_CONTEXT, | ||
460 | .cache = 0 | ||
461 | }, | ||
462 | .emit = upload_invariant_state | ||
463 | }; | ||
464 | |||
465 | |||
466 | /*********************************************************************** | ||
467 | * State base address | ||
468 | */ | ||
469 | |||
470 | /** | ||
471 | * Define the base addresses which some state is referenced from. | ||
472 | * | ||
473 | * This allows us to avoid having to emit relocations in many places for | ||
474 | * cached state, and instead emit pointers inside of large, mostly-static | ||
475 | * state pools. This comes at the expense of memory, and more expensive cache | ||
476 | * misses. | ||
477 | */ | ||
478 | static int upload_state_base_address( struct brw_context *brw ) | ||
479 | { | ||
480 | /* Output the structure (brw_state_base_address) directly to the | ||
481 | * batchbuffer, so we can emit relocations inline. | ||
482 | */ | ||
483 | if (brw->gen == 5) { | ||
484 | BEGIN_BATCH(8, IGNORE_CLIPRECTS); | ||
485 | OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); | ||
486 | OUT_BATCH(1); /* General state base address */ | ||
487 | OUT_BATCH(1); /* Surface state base address */ | ||
488 | OUT_BATCH(1); /* Indirect object base address */ | ||
489 | OUT_BATCH(1); /* Instruction base address */ | ||
490 | OUT_BATCH(1); /* General state upper bound */ | ||
491 | OUT_BATCH(1); /* Indirect object upper bound */ | ||
492 | OUT_BATCH(1); /* Instruction access upper bound */ | ||
493 | ADVANCE_BATCH(); | ||
494 | } else { | ||
495 | BEGIN_BATCH(6, IGNORE_CLIPRECTS); | ||
496 | OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); | ||
497 | OUT_BATCH(1); /* General state base address */ | ||
498 | OUT_BATCH(1); /* Surface state base address */ | ||
499 | OUT_BATCH(1); /* Indirect object base address */ | ||
500 | OUT_BATCH(1); /* General state upper bound */ | ||
501 | OUT_BATCH(1); /* Indirect object upper bound */ | ||
502 | ADVANCE_BATCH(); | ||
503 | } | ||
504 | return 0; | ||
505 | } | ||
506 | |||
507 | const struct brw_tracked_state brw_state_base_address = { | ||
508 | .dirty = { | ||
509 | .mesa = 0, | ||
510 | .brw = BRW_NEW_CONTEXT, | ||
511 | .cache = 0, | ||
512 | }, | ||
513 | .emit = upload_state_base_address | ||
514 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_blend.c b/src/gallium/drivers/i965/brw_pipe_blend.c deleted file mode 100644 index 21f786f8715..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_blend.c +++ /dev/null | |||
@@ -1,208 +0,0 @@ | |||
1 | |||
2 | #include "util/u_memory.h" | ||
3 | #include "pipe/p_context.h" | ||
4 | #include "pipe/p_state.h" | ||
5 | |||
6 | #include "brw_context.h" | ||
7 | #include "brw_defines.h" | ||
8 | #include "brw_debug.h" | ||
9 | |||
10 | static int translate_logicop(unsigned logicop) | ||
11 | { | ||
12 | switch (logicop) { | ||
13 | case PIPE_LOGICOP_CLEAR: | ||
14 | return BRW_LOGICOPFUNCTION_CLEAR; | ||
15 | case PIPE_LOGICOP_AND: | ||
16 | return BRW_LOGICOPFUNCTION_AND; | ||
17 | case PIPE_LOGICOP_AND_REVERSE: | ||
18 | return BRW_LOGICOPFUNCTION_AND_REVERSE; | ||
19 | case PIPE_LOGICOP_COPY: | ||
20 | return BRW_LOGICOPFUNCTION_COPY; | ||
21 | case PIPE_LOGICOP_COPY_INVERTED: | ||
22 | return BRW_LOGICOPFUNCTION_COPY_INVERTED; | ||
23 | case PIPE_LOGICOP_AND_INVERTED: | ||
24 | return BRW_LOGICOPFUNCTION_AND_INVERTED; | ||
25 | case PIPE_LOGICOP_NOOP: | ||
26 | return BRW_LOGICOPFUNCTION_NOOP; | ||
27 | case PIPE_LOGICOP_XOR: | ||
28 | return BRW_LOGICOPFUNCTION_XOR; | ||
29 | case PIPE_LOGICOP_OR: | ||
30 | return BRW_LOGICOPFUNCTION_OR; | ||
31 | case PIPE_LOGICOP_OR_INVERTED: | ||
32 | return BRW_LOGICOPFUNCTION_OR_INVERTED; | ||
33 | case PIPE_LOGICOP_NOR: | ||
34 | return BRW_LOGICOPFUNCTION_NOR; | ||
35 | case PIPE_LOGICOP_EQUIV: | ||
36 | return BRW_LOGICOPFUNCTION_EQUIV; | ||
37 | case PIPE_LOGICOP_INVERT: | ||
38 | return BRW_LOGICOPFUNCTION_INVERT; | ||
39 | case PIPE_LOGICOP_OR_REVERSE: | ||
40 | return BRW_LOGICOPFUNCTION_OR_REVERSE; | ||
41 | case PIPE_LOGICOP_NAND: | ||
42 | return BRW_LOGICOPFUNCTION_NAND; | ||
43 | case PIPE_LOGICOP_SET: | ||
44 | return BRW_LOGICOPFUNCTION_SET; | ||
45 | default: | ||
46 | assert(0); | ||
47 | return BRW_LOGICOPFUNCTION_SET; | ||
48 | } | ||
49 | } | ||
50 | |||
51 | |||
52 | static unsigned translate_blend_equation( unsigned mode ) | ||
53 | { | ||
54 | switch (mode) { | ||
55 | case PIPE_BLEND_ADD: | ||
56 | return BRW_BLENDFUNCTION_ADD; | ||
57 | case PIPE_BLEND_MIN: | ||
58 | return BRW_BLENDFUNCTION_MIN; | ||
59 | case PIPE_BLEND_MAX: | ||
60 | return BRW_BLENDFUNCTION_MAX; | ||
61 | case PIPE_BLEND_SUBTRACT: | ||
62 | return BRW_BLENDFUNCTION_SUBTRACT; | ||
63 | case PIPE_BLEND_REVERSE_SUBTRACT: | ||
64 | return BRW_BLENDFUNCTION_REVERSE_SUBTRACT; | ||
65 | default: | ||
66 | assert(0); | ||
67 | return BRW_BLENDFUNCTION_ADD; | ||
68 | } | ||
69 | } | ||
70 | |||
71 | static unsigned translate_blend_factor( unsigned factor ) | ||
72 | { | ||
73 | switch(factor) { | ||
74 | case PIPE_BLENDFACTOR_ZERO: | ||
75 | return BRW_BLENDFACTOR_ZERO; | ||
76 | case PIPE_BLENDFACTOR_SRC_ALPHA: | ||
77 | return BRW_BLENDFACTOR_SRC_ALPHA; | ||
78 | case PIPE_BLENDFACTOR_ONE: | ||
79 | return BRW_BLENDFACTOR_ONE; | ||
80 | case PIPE_BLENDFACTOR_SRC_COLOR: | ||
81 | return BRW_BLENDFACTOR_SRC_COLOR; | ||
82 | case PIPE_BLENDFACTOR_INV_SRC_COLOR: | ||
83 | return BRW_BLENDFACTOR_INV_SRC_COLOR; | ||
84 | case PIPE_BLENDFACTOR_DST_COLOR: | ||
85 | return BRW_BLENDFACTOR_DST_COLOR; | ||
86 | case PIPE_BLENDFACTOR_INV_DST_COLOR: | ||
87 | return BRW_BLENDFACTOR_INV_DST_COLOR; | ||
88 | case PIPE_BLENDFACTOR_INV_SRC_ALPHA: | ||
89 | return BRW_BLENDFACTOR_INV_SRC_ALPHA; | ||
90 | case PIPE_BLENDFACTOR_DST_ALPHA: | ||
91 | return BRW_BLENDFACTOR_DST_ALPHA; | ||
92 | case PIPE_BLENDFACTOR_INV_DST_ALPHA: | ||
93 | return BRW_BLENDFACTOR_INV_DST_ALPHA; | ||
94 | case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: | ||
95 | return BRW_BLENDFACTOR_SRC_ALPHA_SATURATE; | ||
96 | case PIPE_BLENDFACTOR_CONST_COLOR: | ||
97 | return BRW_BLENDFACTOR_CONST_COLOR; | ||
98 | case PIPE_BLENDFACTOR_INV_CONST_COLOR: | ||
99 | return BRW_BLENDFACTOR_INV_CONST_COLOR; | ||
100 | case PIPE_BLENDFACTOR_CONST_ALPHA: | ||
101 | return BRW_BLENDFACTOR_CONST_ALPHA; | ||
102 | case PIPE_BLENDFACTOR_INV_CONST_ALPHA: | ||
103 | return BRW_BLENDFACTOR_INV_CONST_ALPHA; | ||
104 | default: | ||
105 | assert(0); | ||
106 | return BRW_BLENDFACTOR_ZERO; | ||
107 | } | ||
108 | } | ||
109 | |||
110 | static void *brw_create_blend_state( struct pipe_context *pipe, | ||
111 | const struct pipe_blend_state *templ ) | ||
112 | { | ||
113 | struct brw_blend_state *blend = CALLOC_STRUCT(brw_blend_state); | ||
114 | if (blend == NULL) | ||
115 | return NULL; | ||
116 | |||
117 | if (templ->logicop_enable) { | ||
118 | blend->cc2.logicop_enable = 1; | ||
119 | blend->cc5.logicop_func = translate_logicop(templ->logicop_func); | ||
120 | } | ||
121 | else if (templ->rt[0].blend_enable) { | ||
122 | blend->cc6.dest_blend_factor = translate_blend_factor(templ->rt[0].rgb_dst_factor); | ||
123 | blend->cc6.src_blend_factor = translate_blend_factor(templ->rt[0].rgb_src_factor); | ||
124 | blend->cc6.blend_function = translate_blend_equation(templ->rt[0].rgb_func); | ||
125 | |||
126 | blend->cc5.ia_dest_blend_factor = translate_blend_factor(templ->rt[0].alpha_dst_factor); | ||
127 | blend->cc5.ia_src_blend_factor = translate_blend_factor(templ->rt[0].alpha_src_factor); | ||
128 | blend->cc5.ia_blend_function = translate_blend_equation(templ->rt[0].alpha_func); | ||
129 | |||
130 | blend->cc3.blend_enable = 1; | ||
131 | blend->cc3.ia_blend_enable = | ||
132 | (blend->cc6.dest_blend_factor != blend->cc5.ia_dest_blend_factor || | ||
133 | blend->cc6.src_blend_factor != blend->cc5.ia_src_blend_factor || | ||
134 | blend->cc6.blend_function != blend->cc5.ia_blend_function); | ||
135 | |||
136 | /* Per-surface blend enables, currently just follow global | ||
137 | * state: | ||
138 | */ | ||
139 | blend->ss0.color_blend = 1; | ||
140 | } | ||
141 | |||
142 | blend->cc5.dither_enable = templ->dither; | ||
143 | |||
144 | if (BRW_DEBUG & DEBUG_STATS) | ||
145 | blend->cc5.statistics_enable = 1; | ||
146 | |||
147 | /* Per-surface color mask -- just follow global state: | ||
148 | */ | ||
149 | blend->ss0.writedisable_red = (templ->rt[0].colormask & PIPE_MASK_R) ? 0 : 1; | ||
150 | blend->ss0.writedisable_green = (templ->rt[0].colormask & PIPE_MASK_G) ? 0 : 1; | ||
151 | blend->ss0.writedisable_blue = (templ->rt[0].colormask & PIPE_MASK_B) ? 0 : 1; | ||
152 | blend->ss0.writedisable_alpha = (templ->rt[0].colormask & PIPE_MASK_A) ? 0 : 1; | ||
153 | |||
154 | return (void *)blend; | ||
155 | } | ||
156 | |||
157 | static void brw_bind_blend_state(struct pipe_context *pipe, | ||
158 | void *cso) | ||
159 | { | ||
160 | struct brw_context *brw = brw_context(pipe); | ||
161 | brw->curr.blend = (const struct brw_blend_state *)cso; | ||
162 | brw->state.dirty.mesa |= PIPE_NEW_BLEND; | ||
163 | } | ||
164 | |||
165 | static void brw_delete_blend_state(struct pipe_context *pipe, | ||
166 | void *cso) | ||
167 | { | ||
168 | struct brw_context *brw = brw_context(pipe); | ||
169 | assert((const void *)cso != (const void *)brw->curr.blend); | ||
170 | FREE(cso); | ||
171 | } | ||
172 | |||
173 | |||
174 | static void brw_set_blend_color(struct pipe_context *pipe, | ||
175 | const struct pipe_blend_color *blend_color) | ||
176 | { | ||
177 | struct brw_context *brw = brw_context(pipe); | ||
178 | struct brw_blend_constant_color *bcc = &brw->curr.bcc; | ||
179 | |||
180 | bcc->blend_constant_color[0] = blend_color->color[0]; | ||
181 | bcc->blend_constant_color[1] = blend_color->color[1]; | ||
182 | bcc->blend_constant_color[2] = blend_color->color[2]; | ||
183 | bcc->blend_constant_color[3] = blend_color->color[3]; | ||
184 | |||
185 | brw->state.dirty.mesa |= PIPE_NEW_BLEND_COLOR; | ||
186 | } | ||
187 | |||
188 | |||
189 | void brw_pipe_blend_init( struct brw_context *brw ) | ||
190 | { | ||
191 | brw->base.set_blend_color = brw_set_blend_color; | ||
192 | brw->base.create_blend_state = brw_create_blend_state; | ||
193 | brw->base.bind_blend_state = brw_bind_blend_state; | ||
194 | brw->base.delete_blend_state = brw_delete_blend_state; | ||
195 | |||
196 | { | ||
197 | struct brw_blend_constant_color *bcc = &brw->curr.bcc; | ||
198 | |||
199 | memset(bcc, 0, sizeof(*bcc)); | ||
200 | bcc->header.opcode = CMD_BLEND_CONSTANT_COLOR; | ||
201 | bcc->header.length = sizeof(*bcc)/4-2; | ||
202 | } | ||
203 | |||
204 | } | ||
205 | |||
206 | void brw_pipe_blend_cleanup( struct brw_context *brw ) | ||
207 | { | ||
208 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_clear.c b/src/gallium/drivers/i965/brw_pipe_clear.c deleted file mode 100644 index 759ef4c7dd9..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_clear.c +++ /dev/null | |||
@@ -1,270 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #include "util/u_pack_color.h" | ||
29 | #include "util/u_math.h" | ||
30 | |||
31 | #include "pipe/p_state.h" | ||
32 | |||
33 | #include "brw_batchbuffer.h" | ||
34 | #include "brw_screen.h" | ||
35 | #include "brw_context.h" | ||
36 | |||
37 | #define MASK16 0xffff | ||
38 | #define MASK24 0xffffff | ||
39 | |||
40 | |||
41 | /** | ||
42 | * Use blitting to clear the renderbuffers named by 'flags'. | ||
43 | * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field | ||
44 | * since that might include software renderbuffers or renderbuffers | ||
45 | * which we're clearing with triangles. | ||
46 | */ | ||
47 | static enum pipe_error | ||
48 | try_clear( struct brw_context *brw, | ||
49 | struct brw_surface *surface, | ||
50 | unsigned value, | ||
51 | unsigned rgba_mask) | ||
52 | { | ||
53 | uint32_t BR13, CMD; | ||
54 | int x1 = 0; | ||
55 | int y1 = 0; | ||
56 | int x2 = surface->base.width; | ||
57 | int y2 = surface->base.height; | ||
58 | int pitch = surface->pitch; | ||
59 | int cpp = surface->cpp; | ||
60 | |||
61 | if (x2 == 0 || y2 == 0) | ||
62 | return 0; | ||
63 | |||
64 | debug_printf("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", | ||
65 | __FUNCTION__, | ||
66 | (void *)surface->bo, pitch * cpp, | ||
67 | surface->offset, | ||
68 | x1, y1, x2 - x1, y2 - y1); | ||
69 | |||
70 | BR13 = 0xf0 << 16; | ||
71 | CMD = XY_COLOR_BLT_CMD | rgba_mask; | ||
72 | |||
73 | /* Setup the blit command */ | ||
74 | if (cpp == 4) { | ||
75 | BR13 |= BR13_8888; | ||
76 | } | ||
77 | else { | ||
78 | assert(cpp == 2); | ||
79 | BR13 |= BR13_565; | ||
80 | } | ||
81 | |||
82 | /* XXX: nasty hack for clearing depth buffers | ||
83 | */ | ||
84 | if (surface->tiling == BRW_TILING_Y) { | ||
85 | x2 = pitch; | ||
86 | } | ||
87 | |||
88 | if (surface->tiling == BRW_TILING_X) { | ||
89 | CMD |= XY_DST_TILED; | ||
90 | pitch /= 4; | ||
91 | } | ||
92 | |||
93 | BR13 |= (pitch * cpp); | ||
94 | |||
95 | BEGIN_BATCH(6, 0); | ||
96 | OUT_BATCH(CMD); | ||
97 | OUT_BATCH(BR13); | ||
98 | OUT_BATCH((y1 << 16) | x1); | ||
99 | OUT_BATCH((y2 << 16) | x2); | ||
100 | OUT_RELOC(surface->bo, | ||
101 | BRW_USAGE_BLIT_DEST, | ||
102 | surface->offset); | ||
103 | OUT_BATCH(value); | ||
104 | ADVANCE_BATCH(); | ||
105 | |||
106 | return 0; | ||
107 | } | ||
108 | |||
109 | |||
110 | |||
111 | |||
112 | static void color_clear(struct brw_context *brw, | ||
113 | struct brw_surface *bsurface, | ||
114 | const float *rgba ) | ||
115 | { | ||
116 | enum pipe_error ret; | ||
117 | union util_color value; | ||
118 | |||
119 | util_pack_color( rgba, bsurface->base.format, &value ); | ||
120 | |||
121 | if (bsurface->cpp == 2) | ||
122 | value.ui |= value.ui << 16; | ||
123 | |||
124 | ret = try_clear( brw, bsurface, value.ui, | ||
125 | XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA ); | ||
126 | |||
127 | if (ret != 0) { | ||
128 | brw_context_flush( brw ); | ||
129 | ret = try_clear( brw, bsurface, value.ui, | ||
130 | XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA ); | ||
131 | assert( ret == 0 ); | ||
132 | } | ||
133 | } | ||
134 | |||
135 | static void zstencil_clear(struct brw_context *brw, | ||
136 | struct brw_surface *bsurface, | ||
137 | unsigned clear_flags, | ||
138 | double depth, | ||
139 | unsigned stencil ) | ||
140 | { | ||
141 | enum pipe_error ret; | ||
142 | unsigned value; | ||
143 | unsigned mask = 0; | ||
144 | union fi tmp; | ||
145 | |||
146 | if (clear_flags & PIPE_CLEAR_DEPTH) | ||
147 | mask |= XY_BLT_WRITE_RGB; | ||
148 | |||
149 | switch (bsurface->base.format) { | ||
150 | case PIPE_FORMAT_Z32_FLOAT: | ||
151 | tmp.f = (float)depth; | ||
152 | value = tmp.ui; | ||
153 | break; | ||
154 | case PIPE_FORMAT_Z24X8_UNORM: | ||
155 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: | ||
156 | value = ((unsigned)(depth * MASK24) & MASK24); | ||
157 | break; | ||
158 | case PIPE_FORMAT_Z16_UNORM: | ||
159 | value = ((unsigned)(depth * MASK16) & MASK16); | ||
160 | break; | ||
161 | default: | ||
162 | assert(0); | ||
163 | return; | ||
164 | } | ||
165 | |||
166 | switch (bsurface->base.format) { | ||
167 | case PIPE_FORMAT_Z32_FLOAT: | ||
168 | mask |= XY_BLT_WRITE_ALPHA; | ||
169 | break; | ||
170 | case PIPE_FORMAT_Z24X8_UNORM: | ||
171 | value = value | (stencil << 24); | ||
172 | mask |= XY_BLT_WRITE_ALPHA; | ||
173 | break; | ||
174 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: | ||
175 | value = value | (stencil << 24); | ||
176 | if (clear_flags & PIPE_CLEAR_STENCIL) | ||
177 | mask |= XY_BLT_WRITE_ALPHA; | ||
178 | break; | ||
179 | case PIPE_FORMAT_Z16_UNORM: | ||
180 | value = value | (value << 16); | ||
181 | mask |= XY_BLT_WRITE_ALPHA; | ||
182 | break; | ||
183 | default: | ||
184 | break; | ||
185 | } | ||
186 | |||
187 | ret = try_clear( brw, bsurface, value, mask ); | ||
188 | |||
189 | if (ret != 0) { | ||
190 | brw_context_flush( brw ); | ||
191 | ret = try_clear( brw, bsurface, value, mask ); | ||
192 | assert( ret == 0 ); | ||
193 | } | ||
194 | } | ||
195 | |||
196 | |||
197 | |||
198 | /** | ||
199 | * Clear the given surface to the specified value. | ||
200 | * No masking, no scissor (clear entire buffer). | ||
201 | */ | ||
202 | static void brw_clear(struct pipe_context *pipe, | ||
203 | unsigned buffers, | ||
204 | const union pipe_color_union *color, | ||
205 | double depth, | ||
206 | unsigned stencil) | ||
207 | { | ||
208 | struct brw_context *brw = brw_context( pipe ); | ||
209 | int i; | ||
210 | |||
211 | if (buffers & PIPE_CLEAR_COLOR) { | ||
212 | for (i = 0; i < brw->curr.fb.nr_cbufs; i++) { | ||
213 | color_clear( brw, | ||
214 | brw_surface(brw->curr.fb.cbufs[i]), | ||
215 | color->f ); | ||
216 | } | ||
217 | } | ||
218 | |||
219 | if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { | ||
220 | if (brw->curr.fb.zsbuf) { | ||
221 | zstencil_clear( brw, | ||
222 | brw_surface(brw->curr.fb.zsbuf), | ||
223 | buffers & PIPE_CLEAR_DEPTHSTENCIL, | ||
224 | depth, stencil ); | ||
225 | } | ||
226 | } | ||
227 | } | ||
228 | |||
229 | /* XXX should respect region */ | ||
230 | static void brw_clear_render_target(struct pipe_context *pipe, | ||
231 | struct pipe_surface *dst, | ||
232 | const union pipe_color_union *color, | ||
233 | unsigned dstx, unsigned dsty, | ||
234 | unsigned width, unsigned height) | ||
235 | { | ||
236 | struct brw_context *brw = brw_context( pipe ); | ||
237 | |||
238 | color_clear( brw, | ||
239 | brw_surface(dst), | ||
240 | color->f ); | ||
241 | } | ||
242 | |||
243 | /* XXX should respect region */ | ||
244 | static void brw_clear_depth_stencil(struct pipe_context *pipe, | ||
245 | struct pipe_surface *dst, | ||
246 | unsigned clear_flags, | ||
247 | double depth, | ||
248 | unsigned stencil, | ||
249 | unsigned dstx, unsigned dsty, | ||
250 | unsigned width, unsigned height) | ||
251 | { | ||
252 | struct brw_context *brw = brw_context( pipe ); | ||
253 | |||
254 | zstencil_clear( brw, | ||
255 | brw_surface(dst), | ||
256 | clear_flags, | ||
257 | depth, stencil ); | ||
258 | } | ||
259 | |||
260 | void brw_pipe_clear_init( struct brw_context *brw ) | ||
261 | { | ||
262 | brw->base.clear = brw_clear; | ||
263 | brw->base.clear_render_target = brw_clear_render_target; | ||
264 | brw->base.clear_depth_stencil = brw_clear_depth_stencil; | ||
265 | } | ||
266 | |||
267 | |||
268 | void brw_pipe_clear_cleanup( struct brw_context *brw ) | ||
269 | { | ||
270 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_depth.c b/src/gallium/drivers/i965/brw_pipe_depth.c deleted file mode 100644 index 31c2c343d89..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_depth.c +++ /dev/null | |||
@@ -1,187 +0,0 @@ | |||
1 | |||
2 | #include "util/u_math.h" | ||
3 | #include "util/u_memory.h" | ||
4 | |||
5 | #include "brw_context.h" | ||
6 | #include "brw_defines.h" | ||
7 | |||
8 | /* XXX: Fixme - include this to get IZ_ defines | ||
9 | */ | ||
10 | #include "brw_wm.h" | ||
11 | |||
12 | static unsigned brw_translate_compare_func(unsigned func) | ||
13 | { | ||
14 | switch (func) { | ||
15 | case PIPE_FUNC_NEVER: | ||
16 | return BRW_COMPAREFUNCTION_NEVER; | ||
17 | case PIPE_FUNC_LESS: | ||
18 | return BRW_COMPAREFUNCTION_LESS; | ||
19 | case PIPE_FUNC_LEQUAL: | ||
20 | return BRW_COMPAREFUNCTION_LEQUAL; | ||
21 | case PIPE_FUNC_GREATER: | ||
22 | return BRW_COMPAREFUNCTION_GREATER; | ||
23 | case PIPE_FUNC_GEQUAL: | ||
24 | return BRW_COMPAREFUNCTION_GEQUAL; | ||
25 | case PIPE_FUNC_NOTEQUAL: | ||
26 | return BRW_COMPAREFUNCTION_NOTEQUAL; | ||
27 | case PIPE_FUNC_EQUAL: | ||
28 | return BRW_COMPAREFUNCTION_EQUAL; | ||
29 | case PIPE_FUNC_ALWAYS: | ||
30 | return BRW_COMPAREFUNCTION_ALWAYS; | ||
31 | default: | ||
32 | assert(0); | ||
33 | return BRW_COMPAREFUNCTION_ALWAYS; | ||
34 | } | ||
35 | } | ||
36 | |||
37 | static unsigned translate_stencil_op(unsigned op) | ||
38 | { | ||
39 | switch (op) { | ||
40 | case PIPE_STENCIL_OP_KEEP: | ||
41 | return BRW_STENCILOP_KEEP; | ||
42 | case PIPE_STENCIL_OP_ZERO: | ||
43 | return BRW_STENCILOP_ZERO; | ||
44 | case PIPE_STENCIL_OP_REPLACE: | ||
45 | return BRW_STENCILOP_REPLACE; | ||
46 | case PIPE_STENCIL_OP_INCR: | ||
47 | return BRW_STENCILOP_INCRSAT; | ||
48 | case PIPE_STENCIL_OP_DECR: | ||
49 | return BRW_STENCILOP_DECRSAT; | ||
50 | case PIPE_STENCIL_OP_INCR_WRAP: | ||
51 | return BRW_STENCILOP_INCR; | ||
52 | case PIPE_STENCIL_OP_DECR_WRAP: | ||
53 | return BRW_STENCILOP_DECR; | ||
54 | case PIPE_STENCIL_OP_INVERT: | ||
55 | return BRW_STENCILOP_INVERT; | ||
56 | default: | ||
57 | assert(0); | ||
58 | return BRW_STENCILOP_ZERO; | ||
59 | } | ||
60 | } | ||
61 | |||
62 | static void create_bcc_state( struct brw_depth_stencil_state *zstencil, | ||
63 | const struct pipe_depth_stencil_alpha_state *templ ) | ||
64 | { | ||
65 | if (templ->stencil[0].enabled) { | ||
66 | zstencil->cc0.stencil_enable = 1; | ||
67 | zstencil->cc0.stencil_func = | ||
68 | brw_translate_compare_func(templ->stencil[0].func); | ||
69 | zstencil->cc0.stencil_fail_op = | ||
70 | translate_stencil_op(templ->stencil[0].fail_op); | ||
71 | zstencil->cc0.stencil_pass_depth_fail_op = | ||
72 | translate_stencil_op(templ->stencil[0].zfail_op); | ||
73 | zstencil->cc0.stencil_pass_depth_pass_op = | ||
74 | translate_stencil_op(templ->stencil[0].zpass_op); | ||
75 | zstencil->cc1.stencil_write_mask = templ->stencil[0].writemask; | ||
76 | zstencil->cc1.stencil_test_mask = templ->stencil[0].valuemask; | ||
77 | |||
78 | if (templ->stencil[1].enabled) { | ||
79 | zstencil->cc0.bf_stencil_enable = 1; | ||
80 | zstencil->cc0.bf_stencil_func = | ||
81 | brw_translate_compare_func(templ->stencil[1].func); | ||
82 | zstencil->cc0.bf_stencil_fail_op = | ||
83 | translate_stencil_op(templ->stencil[1].fail_op); | ||
84 | zstencil->cc0.bf_stencil_pass_depth_fail_op = | ||
85 | translate_stencil_op(templ->stencil[1].zfail_op); | ||
86 | zstencil->cc0.bf_stencil_pass_depth_pass_op = | ||
87 | translate_stencil_op(templ->stencil[1].zpass_op); | ||
88 | zstencil->cc2.bf_stencil_write_mask = templ->stencil[1].writemask; | ||
89 | zstencil->cc2.bf_stencil_test_mask = templ->stencil[1].valuemask; | ||
90 | } | ||
91 | |||
92 | zstencil->cc0.stencil_write_enable = (zstencil->cc1.stencil_write_mask || | ||
93 | zstencil->cc2.bf_stencil_write_mask); | ||
94 | } | ||
95 | |||
96 | |||
97 | if (templ->alpha.enabled) { | ||
98 | zstencil->cc3.alpha_test = 1; | ||
99 | zstencil->cc3.alpha_test_func = brw_translate_compare_func(templ->alpha.func); | ||
100 | zstencil->cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; | ||
101 | zstencil->cc7.alpha_ref.ub[0] = float_to_ubyte(templ->alpha.ref_value); | ||
102 | } | ||
103 | |||
104 | if (templ->depth.enabled) { | ||
105 | zstencil->cc2.depth_test = 1; | ||
106 | zstencil->cc2.depth_test_function = brw_translate_compare_func(templ->depth.func); | ||
107 | zstencil->cc2.depth_write_enable = templ->depth.writemask; | ||
108 | } | ||
109 | } | ||
110 | |||
111 | static void create_wm_iz_state( struct brw_depth_stencil_state *zstencil ) | ||
112 | { | ||
113 | if (zstencil->cc3.alpha_test) | ||
114 | zstencil->iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT; | ||
115 | |||
116 | if (zstencil->cc2.depth_test) | ||
117 | zstencil->iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT; | ||
118 | |||
119 | if (zstencil->cc2.depth_write_enable) | ||
120 | zstencil->iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT; | ||
121 | |||
122 | if (zstencil->cc0.stencil_enable) | ||
123 | zstencil->iz_lookup |= IZ_STENCIL_TEST_ENABLE_BIT; | ||
124 | |||
125 | if (zstencil->cc0.stencil_write_enable) | ||
126 | zstencil->iz_lookup |= IZ_STENCIL_WRITE_ENABLE_BIT; | ||
127 | |||
128 | } | ||
129 | |||
130 | |||
131 | static void * | ||
132 | brw_create_depth_stencil_state( struct pipe_context *pipe, | ||
133 | const struct pipe_depth_stencil_alpha_state *templ ) | ||
134 | { | ||
135 | struct brw_depth_stencil_state *zstencil = CALLOC_STRUCT(brw_depth_stencil_state); | ||
136 | |||
137 | create_bcc_state( zstencil, templ ); | ||
138 | create_wm_iz_state( zstencil ); | ||
139 | |||
140 | return (void *)zstencil; | ||
141 | } | ||
142 | |||
143 | |||
144 | static void brw_bind_depth_stencil_state(struct pipe_context *pipe, | ||
145 | void *cso) | ||
146 | { | ||
147 | struct brw_context *brw = brw_context(pipe); | ||
148 | brw->curr.zstencil = (const struct brw_depth_stencil_state *)cso; | ||
149 | brw->state.dirty.mesa |= PIPE_NEW_DEPTH_STENCIL_ALPHA; | ||
150 | } | ||
151 | |||
152 | static void brw_delete_depth_stencil_state(struct pipe_context *pipe, | ||
153 | void *cso) | ||
154 | { | ||
155 | struct brw_context *brw = brw_context(pipe); | ||
156 | assert((const void *)cso != (const void *)brw->curr.zstencil); | ||
157 | FREE(cso); | ||
158 | } | ||
159 | |||
160 | static void brw_set_stencil_ref(struct pipe_context *pipe, | ||
161 | const struct pipe_stencil_ref *stencil_ref) | ||
162 | { | ||
163 | struct brw_context *brw = brw_context(pipe); | ||
164 | brw->curr.cc1_stencil_ref.stencil_ref = stencil_ref->ref_value[0]; | ||
165 | brw->curr.cc1_stencil_ref.bf_stencil_ref = stencil_ref->ref_value[1]; | ||
166 | |||
167 | brw->state.dirty.mesa |= PIPE_NEW_DEPTH_STENCIL_ALPHA; | ||
168 | } | ||
169 | |||
170 | static void | ||
171 | brw_set_sample_mask(struct pipe_context *pipe, | ||
172 | unsigned sample_mask) | ||
173 | { | ||
174 | } | ||
175 | |||
176 | void brw_pipe_depth_stencil_init( struct brw_context *brw ) | ||
177 | { | ||
178 | brw->base.set_stencil_ref = brw_set_stencil_ref; | ||
179 | brw->base.create_depth_stencil_alpha_state = brw_create_depth_stencil_state; | ||
180 | brw->base.bind_depth_stencil_alpha_state = brw_bind_depth_stencil_state; | ||
181 | brw->base.delete_depth_stencil_alpha_state = brw_delete_depth_stencil_state; | ||
182 | brw->base.set_sample_mask = brw_set_sample_mask; | ||
183 | } | ||
184 | |||
185 | void brw_pipe_depth_stencil_cleanup( struct brw_context *brw ) | ||
186 | { | ||
187 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_fb.c b/src/gallium/drivers/i965/brw_pipe_fb.c deleted file mode 100644 index a90b7c73f69..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_fb.c +++ /dev/null | |||
@@ -1,84 +0,0 @@ | |||
1 | #include "util/u_math.h" | ||
2 | #include "pipe/p_context.h" | ||
3 | #include "pipe/p_state.h" | ||
4 | #include "util/u_inlines.h" | ||
5 | |||
6 | #include "brw_context.h" | ||
7 | |||
8 | /** | ||
9 | * called from intelDrawBuffer() | ||
10 | */ | ||
11 | static void brw_set_framebuffer_state( struct pipe_context *pipe, | ||
12 | const struct pipe_framebuffer_state *fb ) | ||
13 | { | ||
14 | struct brw_context *brw = brw_context(pipe); | ||
15 | unsigned i; | ||
16 | |||
17 | /* Dimensions: | ||
18 | */ | ||
19 | if (brw->curr.fb.width != fb->width || | ||
20 | brw->curr.fb.height != fb->height) { | ||
21 | brw->curr.fb.width = fb->width; | ||
22 | brw->curr.fb.height = fb->height; | ||
23 | brw->state.dirty.mesa |= PIPE_NEW_FRAMEBUFFER_DIMENSIONS; | ||
24 | } | ||
25 | |||
26 | /* Z/Stencil | ||
27 | */ | ||
28 | if (brw->curr.fb.zsbuf != fb->zsbuf) { | ||
29 | pipe_surface_reference(&brw->curr.fb.zsbuf, fb->zsbuf); | ||
30 | brw->state.dirty.mesa |= PIPE_NEW_DEPTH_BUFFER; | ||
31 | } | ||
32 | |||
33 | /* Color buffers: | ||
34 | */ | ||
35 | for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) { | ||
36 | if (brw->curr.fb.cbufs[i] != fb->cbufs[i]) { | ||
37 | brw->state.dirty.mesa |= PIPE_NEW_COLOR_BUFFERS; | ||
38 | pipe_surface_reference(&brw->curr.fb.cbufs[i], fb->cbufs[i]); | ||
39 | } | ||
40 | } | ||
41 | |||
42 | if (brw->curr.fb.nr_cbufs != fb->nr_cbufs) { | ||
43 | brw->curr.fb.nr_cbufs = MIN2(BRW_MAX_DRAW_BUFFERS, fb->nr_cbufs); | ||
44 | brw->state.dirty.mesa |= PIPE_NEW_NR_CBUFS; | ||
45 | } | ||
46 | } | ||
47 | |||
48 | |||
49 | static void brw_set_viewport_state( struct pipe_context *pipe, | ||
50 | const struct pipe_viewport_state *viewport ) | ||
51 | { | ||
52 | struct brw_context *brw = brw_context(pipe); | ||
53 | |||
54 | brw->curr.viewport = *viewport; | ||
55 | brw->curr.ccv.min_depth = viewport->scale[2] * -1.0 + viewport->translate[2]; | ||
56 | brw->curr.ccv.max_depth = viewport->scale[2] * 1.0 + viewport->translate[2]; | ||
57 | |||
58 | if (0) | ||
59 | debug_printf("%s depth range %f .. %f\n", | ||
60 | __FUNCTION__, | ||
61 | brw->curr.ccv.min_depth, | ||
62 | brw->curr.ccv.max_depth); | ||
63 | |||
64 | brw->state.dirty.mesa |= PIPE_NEW_VIEWPORT; | ||
65 | } | ||
66 | |||
67 | |||
68 | void brw_pipe_framebuffer_init( struct brw_context *brw ) | ||
69 | { | ||
70 | brw->base.set_framebuffer_state = brw_set_framebuffer_state; | ||
71 | brw->base.set_viewport_state = brw_set_viewport_state; | ||
72 | } | ||
73 | |||
74 | void brw_pipe_framebuffer_cleanup( struct brw_context *brw ) | ||
75 | { | ||
76 | struct pipe_framebuffer_state *fb = &brw->curr.fb; | ||
77 | int i; | ||
78 | |||
79 | for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) { | ||
80 | pipe_surface_reference(&fb->cbufs[i], NULL); | ||
81 | } | ||
82 | |||
83 | pipe_surface_reference(&fb->zsbuf, NULL); | ||
84 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_flush.c b/src/gallium/drivers/i965/brw_pipe_flush.c deleted file mode 100644 index 3b4a99beed2..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_flush.c +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | |||
2 | #include "brw_context.h" | ||
3 | #include "brw_batchbuffer.h" | ||
4 | |||
5 | #include "util/u_upload_mgr.h" | ||
6 | |||
7 | |||
8 | |||
9 | |||
10 | /* All batchbuffer flushes must go through this function. | ||
11 | */ | ||
12 | void brw_context_flush( struct brw_context *brw ) | ||
13 | { | ||
14 | /* | ||
15 | * | ||
16 | */ | ||
17 | brw_emit_query_end(brw); | ||
18 | |||
19 | /* Move to the end of the current upload buffer so that we'll force choosing | ||
20 | * a new buffer next time. | ||
21 | */ | ||
22 | u_upload_flush( brw->vb.upload_vertex ); | ||
23 | u_upload_flush( brw->vb.upload_index ); | ||
24 | |||
25 | _brw_batchbuffer_flush( brw->batch, __FILE__, __LINE__ ); | ||
26 | |||
27 | /* Mark all context state as needing to be re-emitted. | ||
28 | * This is probably not as severe as on 915, since almost all of our state | ||
29 | * is just in referenced buffers. | ||
30 | */ | ||
31 | brw->state.dirty.brw |= BRW_NEW_CONTEXT; | ||
32 | brw->state.dirty.mesa |= ~0; | ||
33 | brw->state.dirty.brw |= ~0; | ||
34 | brw->state.dirty.cache |= ~0; | ||
35 | |||
36 | brw->curbe.need_new_bo = GL_TRUE; | ||
37 | } | ||
38 | |||
39 | static void | ||
40 | brw_flush( struct pipe_context *pipe, | ||
41 | struct pipe_fence_handle **fence ) | ||
42 | { | ||
43 | brw_context_flush( brw_context( pipe ) ); | ||
44 | if (fence) | ||
45 | *fence = NULL; | ||
46 | } | ||
47 | |||
48 | void brw_pipe_flush_init( struct brw_context *brw ) | ||
49 | { | ||
50 | brw->base.flush = brw_flush; | ||
51 | } | ||
52 | |||
53 | |||
54 | void brw_pipe_flush_cleanup( struct brw_context *brw ) | ||
55 | { | ||
56 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_misc.c b/src/gallium/drivers/i965/brw_pipe_misc.c deleted file mode 100644 index 30359078079..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_misc.c +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | |||
2 | #include "brw_context.h" | ||
3 | #include "brw_structs.h" | ||
4 | #include "brw_defines.h" | ||
5 | |||
6 | static void brw_set_polygon_stipple( struct pipe_context *pipe, | ||
7 | const struct pipe_poly_stipple *stip ) | ||
8 | { | ||
9 | struct brw_context *brw = brw_context(pipe); | ||
10 | struct brw_polygon_stipple *bps = &brw->curr.bps; | ||
11 | GLuint i; | ||
12 | |||
13 | memset(bps, 0, sizeof *bps); | ||
14 | bps->header.opcode = CMD_POLY_STIPPLE_PATTERN; | ||
15 | bps->header.length = sizeof *bps/4-2; | ||
16 | |||
17 | for (i = 0; i < 32; i++) | ||
18 | bps->stipple[i] = stip->stipple[i]; /* don't invert */ | ||
19 | |||
20 | brw->state.dirty.mesa |= PIPE_NEW_POLYGON_STIPPLE; | ||
21 | } | ||
22 | |||
23 | |||
24 | static void brw_set_scissor_state( struct pipe_context *pipe, | ||
25 | const struct pipe_scissor_state *scissor ) | ||
26 | { | ||
27 | struct brw_context *brw = brw_context(pipe); | ||
28 | |||
29 | brw->curr.scissor = *scissor; | ||
30 | brw->state.dirty.mesa |= PIPE_NEW_SCISSOR; | ||
31 | } | ||
32 | |||
33 | |||
34 | static void brw_set_clip_state( struct pipe_context *pipe, | ||
35 | const struct pipe_clip_state *clip ) | ||
36 | { | ||
37 | struct brw_context *brw = brw_context(pipe); | ||
38 | |||
39 | brw->curr.ucp = *clip; | ||
40 | brw->state.dirty.mesa |= PIPE_NEW_CLIP; | ||
41 | } | ||
42 | |||
43 | |||
44 | void brw_pipe_misc_init( struct brw_context *brw ) | ||
45 | { | ||
46 | brw->base.set_polygon_stipple = brw_set_polygon_stipple; | ||
47 | brw->base.set_scissor_state = brw_set_scissor_state; | ||
48 | brw->base.set_clip_state = brw_set_clip_state; | ||
49 | } | ||
50 | |||
51 | |||
52 | void brw_pipe_misc_cleanup( struct brw_context *brw ) | ||
53 | { | ||
54 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_query.c b/src/gallium/drivers/i965/brw_pipe_query.c deleted file mode 100644 index 0745254c3cc..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_query.c +++ /dev/null | |||
@@ -1,264 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright © 2008 Intel Corporation | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
21 | * IN THE SOFTWARE. | ||
22 | * | ||
23 | * Authors: | ||
24 | * Eric Anholt <eric@anholt.net> | ||
25 | * | ||
26 | */ | ||
27 | |||
28 | /** @file support for ARB_query_object | ||
29 | * | ||
30 | * ARB_query_object is implemented by using the PIPE_CONTROL command to stall | ||
31 | * execution on the completion of previous depth tests, and write the | ||
32 | * current PS_DEPTH_COUNT to a buffer object. | ||
33 | * | ||
34 | * We use before and after counts when drawing during a query so that | ||
35 | * we don't pick up other clients' query data in ours. To reduce overhead, | ||
36 | * a single BO is used to record the query data for all active queries at | ||
37 | * once. This also gives us a simple bound on how much batchbuffer space is | ||
38 | * required for handling queries, so that we can be sure that we won't | ||
39 | * have to emit a batchbuffer without getting the ending PS_DEPTH_COUNT. | ||
40 | */ | ||
41 | #include "util/u_simple_list.h" | ||
42 | |||
43 | #include "brw_context.h" | ||
44 | #include "brw_state.h" | ||
45 | #include "brw_batchbuffer.h" | ||
46 | #include "brw_reg.h" | ||
47 | |||
48 | /** Waits on the query object's BO and totals the results for this query */ | ||
49 | static boolean | ||
50 | brw_query_get_result(struct pipe_context *pipe, | ||
51 | struct pipe_query *q, | ||
52 | boolean wait, | ||
53 | void *vresult) | ||
54 | { | ||
55 | struct brw_context *brw = brw_context(pipe); | ||
56 | struct brw_query_object *query = (struct brw_query_object *)q; | ||
57 | uint64_t *result = (uint64_t*)vresult; | ||
58 | |||
59 | /* Map and count the pixels from the current query BO */ | ||
60 | if (query->bo) { | ||
61 | int i; | ||
62 | uint64_t *map; | ||
63 | |||
64 | if (brw->sws->bo_is_busy(query->bo) && !wait) | ||
65 | return FALSE; | ||
66 | |||
67 | map = bo_map_read(brw->sws, query->bo); | ||
68 | if (map == NULL) | ||
69 | return FALSE; | ||
70 | |||
71 | for (i = query->first_index; i <= query->last_index; i++) { | ||
72 | query->result += map[i * 2 + 1] - map[i * 2]; | ||
73 | } | ||
74 | |||
75 | brw->sws->bo_unmap(query->bo); | ||
76 | bo_reference(&query->bo, NULL); | ||
77 | } | ||
78 | |||
79 | *result = query->result; | ||
80 | return TRUE; | ||
81 | } | ||
82 | |||
83 | static struct pipe_query * | ||
84 | brw_query_create(struct pipe_context *pipe, unsigned type ) | ||
85 | { | ||
86 | struct brw_query_object *query; | ||
87 | |||
88 | switch (type) { | ||
89 | case PIPE_QUERY_OCCLUSION_COUNTER: | ||
90 | query = CALLOC_STRUCT( brw_query_object ); | ||
91 | if (query == NULL) | ||
92 | return NULL; | ||
93 | return (struct pipe_query *)query; | ||
94 | |||
95 | default: | ||
96 | return NULL; | ||
97 | } | ||
98 | } | ||
99 | |||
100 | static void | ||
101 | brw_query_destroy(struct pipe_context *pipe, struct pipe_query *q) | ||
102 | { | ||
103 | struct brw_query_object *query = (struct brw_query_object *)q; | ||
104 | |||
105 | bo_reference(&query->bo, NULL); | ||
106 | FREE(query); | ||
107 | } | ||
108 | |||
109 | static void | ||
110 | brw_query_begin(struct pipe_context *pipe, struct pipe_query *q) | ||
111 | { | ||
112 | struct brw_context *brw = brw_context(pipe); | ||
113 | struct brw_query_object *query = (struct brw_query_object *)q; | ||
114 | |||
115 | /* Reset our driver's tracking of query state. */ | ||
116 | bo_reference(&query->bo, NULL); | ||
117 | query->result = 0; | ||
118 | query->first_index = -1; | ||
119 | query->last_index = -1; | ||
120 | |||
121 | insert_at_head(&brw->query.active_head, query); | ||
122 | brw->query.stats_wm++; | ||
123 | brw->state.dirty.mesa |= PIPE_NEW_QUERY; | ||
124 | } | ||
125 | |||
126 | static void | ||
127 | brw_query_end(struct pipe_context *pipe, struct pipe_query *q) | ||
128 | { | ||
129 | struct brw_context *brw = brw_context(pipe); | ||
130 | struct brw_query_object *query = (struct brw_query_object *)q; | ||
131 | |||
132 | /* Flush the batchbuffer in case it has writes to our query BO. | ||
133 | * Have later queries write to a new query BO so that further rendering | ||
134 | * doesn't delay the collection of our results. | ||
135 | */ | ||
136 | if (query->bo) { | ||
137 | brw_emit_query_end(brw); | ||
138 | brw_context_flush( brw ); | ||
139 | |||
140 | bo_reference(&brw->query.bo, NULL); | ||
141 | } | ||
142 | |||
143 | remove_from_list(query); | ||
144 | brw->query.stats_wm--; | ||
145 | brw->state.dirty.mesa |= PIPE_NEW_QUERY; | ||
146 | } | ||
147 | |||
148 | /*********************************************************************** | ||
149 | * Internal functions and callbacks to implement queries | ||
150 | */ | ||
151 | |||
152 | /** Called to set up the query BO and account for its aperture space */ | ||
153 | enum pipe_error | ||
154 | brw_prepare_query_begin(struct brw_context *brw) | ||
155 | { | ||
156 | enum pipe_error ret; | ||
157 | |||
158 | /* Skip if we're not doing any queries. */ | ||
159 | if (is_empty_list(&brw->query.active_head)) | ||
160 | return PIPE_OK; | ||
161 | |||
162 | /* Get a new query BO if we're going to need it. */ | ||
163 | if (brw->query.bo == NULL || | ||
164 | brw->query.index * 2 + 1 >= 4096 / sizeof(uint64_t)) { | ||
165 | |||
166 | ret = brw->sws->bo_alloc(brw->sws, BRW_BUFFER_TYPE_QUERY, 4096, 1, | ||
167 | &brw->query.bo); | ||
168 | if (ret) | ||
169 | return ret; | ||
170 | |||
171 | brw->query.index = 0; | ||
172 | } | ||
173 | |||
174 | brw_add_validated_bo(brw, brw->query.bo); | ||
175 | |||
176 | return PIPE_OK; | ||
177 | } | ||
178 | |||
179 | /** Called just before primitive drawing to get a beginning PS_DEPTH_COUNT. */ | ||
180 | void | ||
181 | brw_emit_query_begin(struct brw_context *brw) | ||
182 | { | ||
183 | struct brw_query_object *query; | ||
184 | |||
185 | /* Skip if we're not doing any queries, or we've emitted the start. */ | ||
186 | if (brw->query.active || is_empty_list(&brw->query.active_head)) | ||
187 | return; | ||
188 | |||
189 | BEGIN_BATCH(4, IGNORE_CLIPRECTS); | ||
190 | OUT_BATCH(_3DSTATE_PIPE_CONTROL | | ||
191 | PIPE_CONTROL_DEPTH_STALL | | ||
192 | PIPE_CONTROL_WRITE_DEPTH_COUNT); | ||
193 | /* This object could be mapped cacheable, but we don't have an exposed | ||
194 | * mechanism to support that. Since it's going uncached, tell GEM that | ||
195 | * we're writing to it. The usual clflush should be all that's required | ||
196 | * to pick up the results. | ||
197 | */ | ||
198 | OUT_RELOC(brw->query.bo, | ||
199 | BRW_USAGE_QUERY_RESULT, | ||
200 | PIPE_CONTROL_GLOBAL_GTT_WRITE | | ||
201 | ((brw->query.index * 2) * sizeof(uint64_t))); | ||
202 | OUT_BATCH(0); | ||
203 | OUT_BATCH(0); | ||
204 | ADVANCE_BATCH(); | ||
205 | |||
206 | foreach(query, &brw->query.active_head) { | ||
207 | if (query->bo != brw->query.bo) { | ||
208 | uint64_t tmp; | ||
209 | |||
210 | /* Propogate the results from this buffer to all of the | ||
211 | * active queries, as the bo is going away. | ||
212 | */ | ||
213 | if (query->bo != NULL) | ||
214 | brw_query_get_result( &brw->base, | ||
215 | (struct pipe_query *)query, | ||
216 | FALSE, | ||
217 | &tmp ); | ||
218 | |||
219 | bo_reference( &query->bo, brw->query.bo ); | ||
220 | query->first_index = brw->query.index; | ||
221 | } | ||
222 | query->last_index = brw->query.index; | ||
223 | } | ||
224 | brw->query.active = GL_TRUE; | ||
225 | } | ||
226 | |||
227 | /** Called at batchbuffer flush to get an ending PS_DEPTH_COUNT */ | ||
228 | void | ||
229 | brw_emit_query_end(struct brw_context *brw) | ||
230 | { | ||
231 | if (!brw->query.active) | ||
232 | return; | ||
233 | |||
234 | BEGIN_BATCH(4, IGNORE_CLIPRECTS); | ||
235 | OUT_BATCH(_3DSTATE_PIPE_CONTROL | | ||
236 | PIPE_CONTROL_DEPTH_STALL | | ||
237 | PIPE_CONTROL_WRITE_DEPTH_COUNT); | ||
238 | OUT_RELOC(brw->query.bo, | ||
239 | BRW_USAGE_QUERY_RESULT, | ||
240 | PIPE_CONTROL_GLOBAL_GTT_WRITE | | ||
241 | ((brw->query.index * 2 + 1) * sizeof(uint64_t))); | ||
242 | OUT_BATCH(0); | ||
243 | OUT_BATCH(0); | ||
244 | ADVANCE_BATCH(); | ||
245 | |||
246 | brw->query.active = GL_FALSE; | ||
247 | brw->query.index++; | ||
248 | } | ||
249 | |||
250 | void brw_pipe_query_init( struct brw_context *brw ) | ||
251 | { | ||
252 | brw->base.create_query = brw_query_create; | ||
253 | brw->base.destroy_query = brw_query_destroy; | ||
254 | brw->base.begin_query = brw_query_begin; | ||
255 | brw->base.end_query = brw_query_end; | ||
256 | brw->base.get_query_result = brw_query_get_result; | ||
257 | } | ||
258 | |||
259 | |||
260 | void brw_pipe_query_cleanup( struct brw_context *brw ) | ||
261 | { | ||
262 | /* Unreference brw->query.bo ?? | ||
263 | */ | ||
264 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_rast.c b/src/gallium/drivers/i965/brw_pipe_rast.c deleted file mode 100644 index c86681d1495..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_rast.c +++ /dev/null | |||
@@ -1,188 +0,0 @@ | |||
1 | |||
2 | #include "util/u_memory.h" | ||
3 | #include "pipe/p_defines.h" | ||
4 | #include "brw_context.h" | ||
5 | #include "brw_defines.h" | ||
6 | #include "brw_pipe_rast.h" | ||
7 | #include "brw_wm.h" | ||
8 | |||
9 | |||
10 | static unsigned translate_fill( unsigned fill ) | ||
11 | { | ||
12 | switch (fill) { | ||
13 | case PIPE_POLYGON_MODE_FILL: | ||
14 | return CLIP_FILL; | ||
15 | case PIPE_POLYGON_MODE_LINE: | ||
16 | return CLIP_LINE; | ||
17 | case PIPE_POLYGON_MODE_POINT: | ||
18 | return CLIP_POINT; | ||
19 | default: | ||
20 | assert(0); | ||
21 | return CLIP_FILL; | ||
22 | } | ||
23 | } | ||
24 | |||
25 | |||
26 | /* Calculates the key for triangle-mode clipping. Non-triangle | ||
27 | * clipping keys use much less information and are computed on the | ||
28 | * fly. | ||
29 | */ | ||
30 | static void | ||
31 | calculate_clip_key_rast( const struct brw_context *brw, | ||
32 | const struct pipe_rasterizer_state *templ, | ||
33 | const struct brw_rasterizer_state *rast, | ||
34 | struct brw_clip_prog_key *key) | ||
35 | { | ||
36 | memset(key, 0, sizeof *key); | ||
37 | |||
38 | if (brw->gen == 5) | ||
39 | key->clip_mode = BRW_CLIPMODE_KERNEL_CLIP; | ||
40 | else | ||
41 | key->clip_mode = BRW_CLIPMODE_NORMAL; | ||
42 | |||
43 | key->do_flat_shading = templ->flatshade; | ||
44 | |||
45 | if (templ->cull_face == PIPE_FACE_FRONT_AND_BACK) { | ||
46 | key->clip_mode = BRW_CLIPMODE_REJECT_ALL; | ||
47 | return; | ||
48 | } | ||
49 | |||
50 | key->fill_ccw = CLIP_CULL; | ||
51 | key->fill_cw = CLIP_CULL; | ||
52 | |||
53 | if (!(templ->cull_face & PIPE_FACE_FRONT)) { | ||
54 | if (templ->front_ccw) | ||
55 | key->fill_ccw = translate_fill(templ->fill_front); | ||
56 | else | ||
57 | key->fill_cw = translate_fill(templ->fill_front); | ||
58 | } | ||
59 | |||
60 | if (!(templ->cull_face & PIPE_FACE_BACK)) { | ||
61 | if (templ->front_ccw) | ||
62 | key->fill_cw = translate_fill(templ->fill_back); | ||
63 | else | ||
64 | key->fill_ccw = translate_fill(templ->fill_back); | ||
65 | } | ||
66 | |||
67 | if (key->fill_cw == CLIP_LINE || | ||
68 | key->fill_ccw == CLIP_LINE || | ||
69 | key->fill_cw == CLIP_POINT || | ||
70 | key->fill_ccw == CLIP_POINT) { | ||
71 | key->do_unfilled = 1; | ||
72 | key->clip_mode = BRW_CLIPMODE_CLIP_NON_REJECTED; | ||
73 | } | ||
74 | |||
75 | switch (key->fill_cw) { | ||
76 | case CLIP_POINT: | ||
77 | key->offset_cw = templ->offset_point; | ||
78 | break; | ||
79 | case CLIP_LINE: | ||
80 | key->offset_cw = templ->offset_line; | ||
81 | break; | ||
82 | case CLIP_FILL: | ||
83 | key->offset_cw = templ->offset_tri; | ||
84 | break; | ||
85 | } | ||
86 | |||
87 | switch (key->fill_ccw) { | ||
88 | case CLIP_POINT: | ||
89 | key->offset_ccw = templ->offset_point; | ||
90 | break; | ||
91 | case CLIP_LINE: | ||
92 | key->offset_ccw = templ->offset_line; | ||
93 | break; | ||
94 | case CLIP_FILL: | ||
95 | key->offset_ccw = templ->offset_tri; | ||
96 | break; | ||
97 | } | ||
98 | |||
99 | if (templ->light_twoside && key->fill_cw != CLIP_CULL) | ||
100 | key->copy_bfc_cw = 1; | ||
101 | |||
102 | if (templ->light_twoside && key->fill_ccw != CLIP_CULL) | ||
103 | key->copy_bfc_ccw = 1; | ||
104 | } | ||
105 | |||
106 | |||
107 | static void | ||
108 | calculate_line_stipple_rast( const struct pipe_rasterizer_state *templ, | ||
109 | struct brw_line_stipple *bls ) | ||
110 | { | ||
111 | GLfloat tmp = 1.0f / (templ->line_stipple_factor + 1); | ||
112 | GLint tmpi = tmp * (1<<13); | ||
113 | |||
114 | bls->header.opcode = CMD_LINE_STIPPLE_PATTERN; | ||
115 | bls->header.length = sizeof(*bls)/4 - 2; | ||
116 | bls->bits0.pattern = templ->line_stipple_pattern; | ||
117 | bls->bits1.repeat_count = templ->line_stipple_factor + 1; | ||
118 | bls->bits1.inverse_repeat_count = tmpi; | ||
119 | } | ||
120 | |||
121 | static void *brw_create_rasterizer_state( struct pipe_context *pipe, | ||
122 | const struct pipe_rasterizer_state *templ ) | ||
123 | { | ||
124 | struct brw_context *brw = brw_context(pipe); | ||
125 | struct brw_rasterizer_state *rast; | ||
126 | |||
127 | rast = CALLOC_STRUCT(brw_rasterizer_state); | ||
128 | if (rast == NULL) | ||
129 | return NULL; | ||
130 | |||
131 | rast->templ = *templ; | ||
132 | |||
133 | calculate_clip_key_rast( brw, templ, rast, &rast->clip_key ); | ||
134 | |||
135 | if (templ->line_stipple_enable) | ||
136 | calculate_line_stipple_rast( templ, &rast->bls ); | ||
137 | |||
138 | /* Caclculate lookup value for WM IZ table. | ||
139 | */ | ||
140 | if (templ->line_smooth) { | ||
141 | if (templ->fill_front == PIPE_POLYGON_MODE_LINE && | ||
142 | templ->fill_back == PIPE_POLYGON_MODE_LINE) { | ||
143 | rast->unfilled_aa_line = AA_ALWAYS; | ||
144 | } | ||
145 | else if (templ->fill_front == PIPE_POLYGON_MODE_LINE || | ||
146 | templ->fill_back == PIPE_POLYGON_MODE_LINE) { | ||
147 | rast->unfilled_aa_line = AA_SOMETIMES; | ||
148 | } | ||
149 | else { | ||
150 | rast->unfilled_aa_line = AA_NEVER; | ||
151 | } | ||
152 | } | ||
153 | else { | ||
154 | rast->unfilled_aa_line = AA_NEVER; | ||
155 | } | ||
156 | |||
157 | return (void *)rast; | ||
158 | } | ||
159 | |||
160 | |||
161 | static void brw_bind_rasterizer_state(struct pipe_context *pipe, | ||
162 | void *cso) | ||
163 | { | ||
164 | struct brw_context *brw = brw_context(pipe); | ||
165 | brw->curr.rast = (const struct brw_rasterizer_state *)cso; | ||
166 | brw->state.dirty.mesa |= PIPE_NEW_RAST; | ||
167 | } | ||
168 | |||
169 | static void brw_delete_rasterizer_state(struct pipe_context *pipe, | ||
170 | void *cso) | ||
171 | { | ||
172 | struct brw_context *brw = brw_context(pipe); | ||
173 | assert((const void *)cso != (const void *)brw->curr.rast); | ||
174 | FREE(cso); | ||
175 | } | ||
176 | |||
177 | |||
178 | |||
179 | void brw_pipe_rast_init( struct brw_context *brw ) | ||
180 | { | ||
181 | brw->base.create_rasterizer_state = brw_create_rasterizer_state; | ||
182 | brw->base.bind_rasterizer_state = brw_bind_rasterizer_state; | ||
183 | brw->base.delete_rasterizer_state = brw_delete_rasterizer_state; | ||
184 | } | ||
185 | |||
186 | void brw_pipe_rast_cleanup( struct brw_context *brw ) | ||
187 | { | ||
188 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_rast.h b/src/gallium/drivers/i965/brw_pipe_rast.h deleted file mode 100644 index 9354f01e18a..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_rast.h +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | #ifndef BRW_PIPE_RAST_H | ||
2 | #define BRW_PIPE_RAST_H | ||
3 | |||
4 | #include "brw_clip.h" | ||
5 | |||
6 | struct brw_rasterizer_state { | ||
7 | struct pipe_rasterizer_state templ; /* for draw module */ | ||
8 | |||
9 | /* Precalculated hardware state: | ||
10 | */ | ||
11 | struct brw_clip_prog_key clip_key; | ||
12 | struct brw_line_stipple bls; | ||
13 | unsigned unfilled_aa_line; | ||
14 | }; | ||
15 | |||
16 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_sampler.c b/src/gallium/drivers/i965/brw_pipe_sampler.c deleted file mode 100644 index 3fe753ec42c..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_sampler.c +++ /dev/null | |||
@@ -1,259 +0,0 @@ | |||
1 | |||
2 | #include "util/u_memory.h" | ||
3 | #include "util/u_math.h" | ||
4 | |||
5 | #include "pipe/p_context.h" | ||
6 | #include "pipe/p_state.h" | ||
7 | #include "util/u_inlines.h" | ||
8 | |||
9 | #include "brw_context.h" | ||
10 | #include "brw_defines.h" | ||
11 | |||
12 | |||
13 | |||
14 | /* The brw (and related graphics cores) do not support GL_CLAMP. The | ||
15 | * Intel drivers for "other operating systems" implement GL_CLAMP as | ||
16 | * GL_CLAMP_TO_EDGE, so the same is done here. | ||
17 | */ | ||
18 | static GLuint translate_wrap_mode( unsigned wrap ) | ||
19 | { | ||
20 | switch( wrap ) { | ||
21 | case PIPE_TEX_WRAP_REPEAT: | ||
22 | return BRW_TEXCOORDMODE_WRAP; | ||
23 | |||
24 | case PIPE_TEX_WRAP_CLAMP: | ||
25 | case PIPE_TEX_WRAP_CLAMP_TO_EDGE: | ||
26 | return BRW_TEXCOORDMODE_CLAMP; | ||
27 | |||
28 | case PIPE_TEX_WRAP_CLAMP_TO_BORDER: | ||
29 | return BRW_TEXCOORDMODE_CLAMP_BORDER; | ||
30 | |||
31 | case PIPE_TEX_WRAP_MIRROR_REPEAT: | ||
32 | return BRW_TEXCOORDMODE_MIRROR; | ||
33 | |||
34 | case PIPE_TEX_WRAP_MIRROR_CLAMP: | ||
35 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: | ||
36 | case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: | ||
37 | return BRW_TEXCOORDMODE_MIRROR_ONCE; | ||
38 | |||
39 | default: | ||
40 | return BRW_TEXCOORDMODE_WRAP; | ||
41 | } | ||
42 | } | ||
43 | |||
44 | static GLuint translate_img_filter( unsigned filter ) | ||
45 | { | ||
46 | switch (filter) { | ||
47 | case PIPE_TEX_FILTER_NEAREST: | ||
48 | return BRW_MAPFILTER_NEAREST; | ||
49 | case PIPE_TEX_FILTER_LINEAR: | ||
50 | return BRW_MAPFILTER_LINEAR; | ||
51 | default: | ||
52 | assert(0); | ||
53 | return BRW_MAPFILTER_NEAREST; | ||
54 | } | ||
55 | } | ||
56 | |||
57 | static GLuint translate_mip_filter( unsigned filter ) | ||
58 | { | ||
59 | switch (filter) { | ||
60 | case PIPE_TEX_MIPFILTER_NONE: | ||
61 | return BRW_MIPFILTER_NONE; | ||
62 | case PIPE_TEX_MIPFILTER_NEAREST: | ||
63 | return BRW_MIPFILTER_NEAREST; | ||
64 | case PIPE_TEX_MIPFILTER_LINEAR: | ||
65 | return BRW_MIPFILTER_LINEAR; | ||
66 | default: | ||
67 | assert(0); | ||
68 | return BRW_MIPFILTER_NONE; | ||
69 | } | ||
70 | } | ||
71 | |||
72 | /* XXX: not sure why there are special translations for the shadow tex | ||
73 | * compare functions. In particular ALWAYS is translated to NEVER. | ||
74 | * Is this a hardware issue? Does i965 really suffer from this? | ||
75 | */ | ||
76 | static GLuint translate_shadow_compare_func( unsigned func ) | ||
77 | { | ||
78 | switch (func) { | ||
79 | case PIPE_FUNC_NEVER: | ||
80 | return BRW_COMPAREFUNCTION_ALWAYS; | ||
81 | case PIPE_FUNC_LESS: | ||
82 | return BRW_COMPAREFUNCTION_LEQUAL; | ||
83 | case PIPE_FUNC_LEQUAL: | ||
84 | return BRW_COMPAREFUNCTION_LESS; | ||
85 | case PIPE_FUNC_GREATER: | ||
86 | return BRW_COMPAREFUNCTION_GEQUAL; | ||
87 | case PIPE_FUNC_GEQUAL: | ||
88 | return BRW_COMPAREFUNCTION_GREATER; | ||
89 | case PIPE_FUNC_NOTEQUAL: | ||
90 | return BRW_COMPAREFUNCTION_EQUAL; | ||
91 | case PIPE_FUNC_EQUAL: | ||
92 | return BRW_COMPAREFUNCTION_NOTEQUAL; | ||
93 | case PIPE_FUNC_ALWAYS: | ||
94 | return BRW_COMPAREFUNCTION_NEVER; | ||
95 | default: | ||
96 | assert(0); | ||
97 | return BRW_COMPAREFUNCTION_NEVER; | ||
98 | } | ||
99 | } | ||
100 | |||
101 | |||
102 | |||
103 | |||
104 | static void * | ||
105 | brw_create_sampler_state( struct pipe_context *pipe, | ||
106 | const struct pipe_sampler_state *template ) | ||
107 | { | ||
108 | struct brw_sampler *sampler = CALLOC_STRUCT(brw_sampler); | ||
109 | |||
110 | sampler->ss0.min_filter = translate_img_filter( template->min_img_filter ); | ||
111 | sampler->ss0.mag_filter = translate_img_filter( template->mag_img_filter ); | ||
112 | sampler->ss0.mip_filter = translate_mip_filter( template->min_mip_filter ); | ||
113 | |||
114 | |||
115 | /* XXX: anisotropy logic slightly changed: | ||
116 | */ | ||
117 | if (template->max_anisotropy > 1) { | ||
118 | sampler->ss0.min_filter = BRW_MAPFILTER_ANISOTROPIC; | ||
119 | sampler->ss0.mag_filter = BRW_MAPFILTER_ANISOTROPIC; | ||
120 | |||
121 | sampler->ss3.max_aniso = MIN2((template->max_anisotropy - 2) / 2, | ||
122 | BRW_ANISORATIO_16); | ||
123 | } | ||
124 | |||
125 | sampler->ss1.r_wrap_mode = translate_wrap_mode(template->wrap_r); | ||
126 | sampler->ss1.s_wrap_mode = translate_wrap_mode(template->wrap_s); | ||
127 | sampler->ss1.t_wrap_mode = translate_wrap_mode(template->wrap_t); | ||
128 | |||
129 | /* Set LOD bias: | ||
130 | */ | ||
131 | sampler->ss0.lod_bias = | ||
132 | util_signed_fixed(CLAMP(template->lod_bias, -16, 15), 6); | ||
133 | |||
134 | |||
135 | sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ | ||
136 | sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ | ||
137 | |||
138 | /* Set shadow function: | ||
139 | */ | ||
140 | if (template->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) { | ||
141 | |||
142 | /* Shadowing is "enabled" by emitting a particular sampler | ||
143 | * message (sample_c). So need to recompile WM program when | ||
144 | * shadow comparison is enabled on each/any texture unit. | ||
145 | */ | ||
146 | sampler->ss0.shadow_function = | ||
147 | translate_shadow_compare_func(template->compare_func); | ||
148 | } | ||
149 | |||
150 | /* Set BaseMipLevel, MaxLOD, MinLOD: | ||
151 | */ | ||
152 | sampler->ss0.base_level = | ||
153 | util_unsigned_fixed(0, 1); | ||
154 | |||
155 | sampler->ss1.max_lod = | ||
156 | util_unsigned_fixed(CLAMP(template->max_lod, 0, 13), 6); | ||
157 | |||
158 | sampler->ss1.min_lod = | ||
159 | util_unsigned_fixed(CLAMP(template->min_lod, 0, 13), 6); | ||
160 | |||
161 | return (void *)sampler; | ||
162 | } | ||
163 | |||
164 | static void brw_bind_sampler_state(struct pipe_context *pipe, | ||
165 | unsigned num, void **sampler) | ||
166 | { | ||
167 | struct brw_context *brw = brw_context(pipe); | ||
168 | int i; | ||
169 | |||
170 | for (i = 0; i < num; i++) | ||
171 | brw->curr.sampler[i] = sampler[i]; | ||
172 | |||
173 | for (i = num; i < brw->curr.num_samplers; i++) | ||
174 | brw->curr.sampler[i] = NULL; | ||
175 | |||
176 | brw->curr.num_samplers = num; | ||
177 | brw->state.dirty.mesa |= PIPE_NEW_SAMPLERS; | ||
178 | } | ||
179 | |||
180 | static void brw_delete_sampler_state(struct pipe_context *pipe, | ||
181 | void *cso) | ||
182 | { | ||
183 | FREE(cso); | ||
184 | } | ||
185 | |||
186 | static void brw_set_fragment_sampler_views(struct pipe_context *pipe, | ||
187 | unsigned num, | ||
188 | struct pipe_sampler_view **views) | ||
189 | { | ||
190 | struct brw_context *brw = brw_context(pipe); | ||
191 | int i; | ||
192 | |||
193 | for (i = 0; i < num; i++) | ||
194 | pipe_sampler_view_reference(&brw->curr.fragment_sampler_views[i], views[i]); | ||
195 | |||
196 | for (i = num; i < brw->curr.num_fragment_sampler_views; i++) | ||
197 | pipe_sampler_view_reference(&brw->curr.fragment_sampler_views[i], NULL); | ||
198 | |||
199 | brw->curr.num_fragment_sampler_views = num; | ||
200 | brw->state.dirty.mesa |= PIPE_NEW_BOUND_TEXTURES; | ||
201 | } | ||
202 | |||
203 | static void brw_set_vertex_sampler_views(struct pipe_context *pipe, | ||
204 | unsigned num, | ||
205 | struct pipe_sampler_view **views) | ||
206 | { | ||
207 | } | ||
208 | |||
209 | static void brw_bind_vertex_sampler_state(struct pipe_context *pipe, | ||
210 | unsigned num, void **sampler) | ||
211 | { | ||
212 | } | ||
213 | |||
214 | |||
215 | static struct pipe_sampler_view * | ||
216 | brw_create_sampler_view(struct pipe_context *pipe, | ||
217 | struct pipe_resource *texture, | ||
218 | const struct pipe_sampler_view *templ) | ||
219 | { | ||
220 | struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view); | ||
221 | |||
222 | if (view) { | ||
223 | *view = *templ; | ||
224 | view->reference.count = 1; | ||
225 | view->texture = NULL; | ||
226 | pipe_resource_reference(&view->texture, texture); | ||
227 | view->context = pipe; | ||
228 | } | ||
229 | |||
230 | return view; | ||
231 | } | ||
232 | |||
233 | |||
234 | static void | ||
235 | brw_sampler_view_destroy(struct pipe_context *pipe, | ||
236 | struct pipe_sampler_view *view) | ||
237 | { | ||
238 | pipe_resource_reference(&view->texture, NULL); | ||
239 | FREE(view); | ||
240 | } | ||
241 | |||
242 | |||
243 | void brw_pipe_sampler_init( struct brw_context *brw ) | ||
244 | { | ||
245 | brw->base.create_sampler_state = brw_create_sampler_state; | ||
246 | brw->base.delete_sampler_state = brw_delete_sampler_state; | ||
247 | |||
248 | brw->base.set_fragment_sampler_views = brw_set_fragment_sampler_views; | ||
249 | brw->base.bind_fragment_sampler_states = brw_bind_sampler_state; | ||
250 | |||
251 | brw->base.set_vertex_sampler_views = brw_set_vertex_sampler_views; | ||
252 | brw->base.bind_vertex_sampler_states = brw_bind_vertex_sampler_state; | ||
253 | |||
254 | brw->base.create_sampler_view = brw_create_sampler_view; | ||
255 | brw->base.sampler_view_destroy = brw_sampler_view_destroy; | ||
256 | } | ||
257 | void brw_pipe_sampler_cleanup( struct brw_context *brw ) | ||
258 | { | ||
259 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_shader.c b/src/gallium/drivers/i965/brw_pipe_shader.c deleted file mode 100644 index d9bee96c11f..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_shader.c +++ /dev/null | |||
@@ -1,303 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_inlines.h" | ||
33 | #include "util/u_memory.h" | ||
34 | |||
35 | #include "tgsi/tgsi_parse.h" | ||
36 | #include "tgsi/tgsi_scan.h" | ||
37 | |||
38 | #include "brw_context.h" | ||
39 | #include "brw_wm.h" | ||
40 | |||
41 | |||
42 | /** | ||
43 | * Determine if the given shader uses complex features such as flow | ||
44 | * conditionals, loops, subroutines. | ||
45 | */ | ||
46 | static GLboolean has_flow_control(const struct tgsi_shader_info *info) | ||
47 | { | ||
48 | return (info->opcode_count[TGSI_OPCODE_ARL] > 0 || | ||
49 | info->opcode_count[TGSI_OPCODE_IF] > 0 || | ||
50 | info->opcode_count[TGSI_OPCODE_ENDIF] > 0 || /* redundant - IF */ | ||
51 | info->opcode_count[TGSI_OPCODE_CAL] > 0 || | ||
52 | info->opcode_count[TGSI_OPCODE_BRK] > 0 || /* redundant - BGNLOOP */ | ||
53 | info->opcode_count[TGSI_OPCODE_RET] > 0 || /* redundant - CAL */ | ||
54 | info->opcode_count[TGSI_OPCODE_BGNLOOP] > 0); | ||
55 | } | ||
56 | |||
57 | |||
58 | static void scan_immediates(const struct tgsi_token *tokens, | ||
59 | const struct tgsi_shader_info *info, | ||
60 | struct brw_immediate_data *imm) | ||
61 | { | ||
62 | struct tgsi_parse_context parse; | ||
63 | boolean done = FALSE; | ||
64 | |||
65 | imm->nr = 0; | ||
66 | imm->data = MALLOC(info->immediate_count * 4 * sizeof(float)); | ||
67 | |||
68 | tgsi_parse_init( &parse, tokens ); | ||
69 | while (!tgsi_parse_end_of_tokens( &parse ) && !done) { | ||
70 | tgsi_parse_token( &parse ); | ||
71 | |||
72 | switch (parse.FullToken.Token.Type) { | ||
73 | case TGSI_TOKEN_TYPE_DECLARATION: | ||
74 | break; | ||
75 | |||
76 | case TGSI_TOKEN_TYPE_IMMEDIATE: { | ||
77 | static const float id[4] = {0,0,0,1}; | ||
78 | const float *value = &parse.FullToken.FullImmediate.u[0].Float; | ||
79 | unsigned size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1; | ||
80 | unsigned i; | ||
81 | |||
82 | for (i = 0; i < size; i++) | ||
83 | imm->data[imm->nr][i] = value[i]; | ||
84 | |||
85 | for (; i < 4; i++) | ||
86 | imm->data[imm->nr][i] = id[i]; | ||
87 | |||
88 | imm->nr++; | ||
89 | break; | ||
90 | } | ||
91 | |||
92 | case TGSI_TOKEN_TYPE_INSTRUCTION: | ||
93 | done = 1; | ||
94 | break; | ||
95 | } | ||
96 | } | ||
97 | } | ||
98 | |||
99 | |||
100 | static void brw_bind_fs_state( struct pipe_context *pipe, void *prog ) | ||
101 | { | ||
102 | struct brw_fragment_shader *fs = (struct brw_fragment_shader *)prog; | ||
103 | struct brw_context *brw = brw_context(pipe); | ||
104 | |||
105 | if (brw->curr.fragment_shader == fs) | ||
106 | return; | ||
107 | |||
108 | if (brw->curr.fragment_shader == NULL || | ||
109 | fs == NULL || | ||
110 | memcmp(&brw->curr.fragment_shader->signature, &fs->signature, | ||
111 | brw_fs_signature_size(&fs->signature)) != 0) { | ||
112 | brw->state.dirty.mesa |= PIPE_NEW_FRAGMENT_SIGNATURE; | ||
113 | } | ||
114 | |||
115 | brw->curr.fragment_shader = fs; | ||
116 | brw->state.dirty.mesa |= PIPE_NEW_FRAGMENT_SHADER; | ||
117 | } | ||
118 | |||
119 | static void brw_bind_vs_state( struct pipe_context *pipe, void *prog ) | ||
120 | { | ||
121 | struct brw_context *brw = brw_context(pipe); | ||
122 | |||
123 | brw->curr.vertex_shader = (struct brw_vertex_shader *)prog; | ||
124 | brw->state.dirty.mesa |= PIPE_NEW_VERTEX_SHADER; | ||
125 | } | ||
126 | |||
127 | |||
128 | |||
129 | static void *brw_create_fs_state( struct pipe_context *pipe, | ||
130 | const struct pipe_shader_state *shader ) | ||
131 | { | ||
132 | struct brw_context *brw = brw_context(pipe); | ||
133 | struct brw_fragment_shader *fs; | ||
134 | int i; | ||
135 | |||
136 | fs = CALLOC_STRUCT(brw_fragment_shader); | ||
137 | if (fs == NULL) | ||
138 | return NULL; | ||
139 | |||
140 | /* Duplicate tokens, scan shader | ||
141 | */ | ||
142 | fs->id = brw->program_id++; | ||
143 | fs->has_flow_control = has_flow_control(&fs->info); | ||
144 | |||
145 | fs->tokens = tgsi_dup_tokens(shader->tokens); | ||
146 | if (fs->tokens == NULL) | ||
147 | goto fail; | ||
148 | |||
149 | tgsi_scan_shader(fs->tokens, &fs->info); | ||
150 | scan_immediates(fs->tokens, &fs->info, &fs->immediates); | ||
151 | |||
152 | fs->signature.nr_inputs = fs->info.num_inputs; | ||
153 | for (i = 0; i < fs->info.num_inputs; i++) { | ||
154 | fs->signature.input[i].interp = fs->info.input_interpolate[i]; | ||
155 | fs->signature.input[i].semantic = fs->info.input_semantic_name[i]; | ||
156 | fs->signature.input[i].semantic_index = fs->info.input_semantic_index[i]; | ||
157 | } | ||
158 | |||
159 | for (i = 0; i < fs->info.num_inputs; i++) | ||
160 | if (fs->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION) | ||
161 | fs->uses_depth = 1; | ||
162 | |||
163 | if (fs->info.uses_kill) | ||
164 | fs->iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT; | ||
165 | |||
166 | if (fs->info.writes_z) | ||
167 | fs->iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT; | ||
168 | |||
169 | return (void *)fs; | ||
170 | |||
171 | fail: | ||
172 | FREE(fs); | ||
173 | return NULL; | ||
174 | } | ||
175 | |||
176 | |||
177 | static void *brw_create_vs_state( struct pipe_context *pipe, | ||
178 | const struct pipe_shader_state *shader ) | ||
179 | { | ||
180 | struct brw_context *brw = brw_context(pipe); | ||
181 | struct brw_vertex_shader *vs; | ||
182 | unsigned i; | ||
183 | |||
184 | vs = CALLOC_STRUCT(brw_vertex_shader); | ||
185 | if (vs == NULL) | ||
186 | return NULL; | ||
187 | |||
188 | /* Duplicate tokens, scan shader | ||
189 | */ | ||
190 | vs->tokens = tgsi_dup_tokens(shader->tokens); | ||
191 | if (vs->tokens == NULL) | ||
192 | goto fail; | ||
193 | |||
194 | tgsi_scan_shader(vs->tokens, &vs->info); | ||
195 | scan_immediates(vs->tokens, &vs->info, &vs->immediates); | ||
196 | |||
197 | vs->id = brw->program_id++; | ||
198 | vs->has_flow_control = has_flow_control(&vs->info); | ||
199 | |||
200 | vs->output_hpos = BRW_OUTPUT_NOT_PRESENT; | ||
201 | vs->output_color0 = BRW_OUTPUT_NOT_PRESENT; | ||
202 | vs->output_color1 = BRW_OUTPUT_NOT_PRESENT; | ||
203 | vs->output_bfc0 = BRW_OUTPUT_NOT_PRESENT; | ||
204 | vs->output_bfc1 = BRW_OUTPUT_NOT_PRESENT; | ||
205 | vs->output_edgeflag = BRW_OUTPUT_NOT_PRESENT; | ||
206 | |||
207 | for (i = 0; i < vs->info.num_outputs; i++) { | ||
208 | int index = vs->info.output_semantic_index[i]; | ||
209 | switch (vs->info.output_semantic_name[i]) { | ||
210 | case TGSI_SEMANTIC_POSITION: | ||
211 | vs->output_hpos = i; | ||
212 | break; | ||
213 | case TGSI_SEMANTIC_COLOR: | ||
214 | if (index == 0) | ||
215 | vs->output_color0 = i; | ||
216 | else | ||
217 | vs->output_color1 = i; | ||
218 | break; | ||
219 | case TGSI_SEMANTIC_BCOLOR: | ||
220 | if (index == 0) | ||
221 | vs->output_bfc0 = i; | ||
222 | else | ||
223 | vs->output_bfc1 = i; | ||
224 | break; | ||
225 | case TGSI_SEMANTIC_EDGEFLAG: | ||
226 | vs->output_edgeflag = i; | ||
227 | break; | ||
228 | } | ||
229 | } | ||
230 | |||
231 | |||
232 | /* Done: | ||
233 | */ | ||
234 | return (void *)vs; | ||
235 | |||
236 | fail: | ||
237 | FREE(vs); | ||
238 | return NULL; | ||
239 | } | ||
240 | |||
241 | |||
242 | static void brw_delete_fs_state( struct pipe_context *pipe, void *prog ) | ||
243 | { | ||
244 | struct brw_fragment_shader *fs = (struct brw_fragment_shader *)prog; | ||
245 | |||
246 | bo_reference(&fs->const_buffer, NULL); | ||
247 | FREE( (void *)fs->tokens ); | ||
248 | FREE( fs ); | ||
249 | } | ||
250 | |||
251 | |||
252 | static void brw_delete_vs_state( struct pipe_context *pipe, void *prog ) | ||
253 | { | ||
254 | struct brw_fragment_shader *vs = (struct brw_fragment_shader *)prog; | ||
255 | |||
256 | /* Delete draw shader | ||
257 | */ | ||
258 | FREE( (void *)vs->tokens ); | ||
259 | FREE( vs ); | ||
260 | } | ||
261 | |||
262 | |||
263 | static void brw_set_constant_buffer(struct pipe_context *pipe, | ||
264 | uint shader, uint index, | ||
265 | struct pipe_resource *buf) | ||
266 | { | ||
267 | struct brw_context *brw = brw_context(pipe); | ||
268 | |||
269 | assert(index == 0); | ||
270 | |||
271 | if (shader == PIPE_SHADER_FRAGMENT) { | ||
272 | pipe_resource_reference( &brw->curr.fragment_constants, | ||
273 | buf ); | ||
274 | |||
275 | brw->state.dirty.mesa |= PIPE_NEW_FRAGMENT_CONSTANTS; | ||
276 | } | ||
277 | else { | ||
278 | pipe_resource_reference( &brw->curr.vertex_constants, | ||
279 | buf ); | ||
280 | |||
281 | brw->state.dirty.mesa |= PIPE_NEW_VERTEX_CONSTANTS; | ||
282 | } | ||
283 | } | ||
284 | |||
285 | |||
286 | void brw_pipe_shader_init( struct brw_context *brw ) | ||
287 | { | ||
288 | brw->base.set_constant_buffer = brw_set_constant_buffer; | ||
289 | |||
290 | brw->base.create_vs_state = brw_create_vs_state; | ||
291 | brw->base.bind_vs_state = brw_bind_vs_state; | ||
292 | brw->base.delete_vs_state = brw_delete_vs_state; | ||
293 | |||
294 | brw->base.create_fs_state = brw_create_fs_state; | ||
295 | brw->base.bind_fs_state = brw_bind_fs_state; | ||
296 | brw->base.delete_fs_state = brw_delete_fs_state; | ||
297 | } | ||
298 | |||
299 | void brw_pipe_shader_cleanup( struct brw_context *brw ) | ||
300 | { | ||
301 | pipe_resource_reference( &brw->curr.fragment_constants, NULL ); | ||
302 | pipe_resource_reference( &brw->curr.vertex_constants, NULL ); | ||
303 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_surface.c b/src/gallium/drivers/i965/brw_pipe_surface.c deleted file mode 100644 index 58a610089e2..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_surface.c +++ /dev/null | |||
@@ -1,258 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_memory.h" | ||
33 | #include "util/u_simple_list.h" | ||
34 | #include "util/u_math.h" | ||
35 | |||
36 | #include "pipe/p_screen.h" | ||
37 | #include "brw_screen.h" | ||
38 | #include "brw_context.h" | ||
39 | #include "brw_defines.h" | ||
40 | #include "brw_resource.h" | ||
41 | #include "brw_winsys.h" | ||
42 | |||
43 | enum { | ||
44 | BRW_VIEW_LINEAR, | ||
45 | BRW_VIEW_IN_PLACE | ||
46 | }; | ||
47 | |||
48 | |||
49 | static boolean need_linear_view( struct brw_screen *brw_screen, | ||
50 | struct brw_texture *brw_texture, | ||
51 | union brw_surface_id id, | ||
52 | unsigned usage ) | ||
53 | { | ||
54 | #if 0 | ||
55 | /* XXX: what about IDGNG? | ||
56 | */ | ||
57 | if (!BRW_IS_G4X(brw->brw_screen->pci_id)) | ||
58 | { | ||
59 | struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; | ||
60 | struct intel_renderbuffer *irb = intel_renderbuffer(rb); | ||
61 | |||
62 | /* The original gen4 hardware couldn't set up WM surfaces pointing | ||
63 | * at an offset within a tile, which can happen when rendering to | ||
64 | * anything but the base level of a texture or the +X face/0 depth. | ||
65 | * This was fixed with the 4 Series hardware. | ||
66 | * | ||
67 | * For these original chips, you would have to make the depth and | ||
68 | * color destination surfaces include information on the texture | ||
69 | * type, LOD, face, and various limits to use them as a destination. | ||
70 | * | ||
71 | * This is easy in Gallium as surfaces are all backed by | ||
72 | * textures, but there's also a nasty requirement that the depth | ||
73 | * and the color surfaces all be of the same LOD, which is | ||
74 | * harder to get around as we can't look at a surface in | ||
75 | * isolation and decide if it's legal. | ||
76 | * | ||
77 | * Instead, end up being pessimistic and say that for i965, | ||
78 | * ... ?? | ||
79 | */ | ||
80 | if (brw_tex->tiling != I915_TILING_NONE && | ||
81 | (brw_tex_image_offset(brw_tex, face, level, zslize) & 4095)) { | ||
82 | if (BRW_DEBUG & DEBUG_VIEW) | ||
83 | debug_printf("%s: need surface view for non-aligned tex image\n", | ||
84 | __FUNCTION__); | ||
85 | return GL_TRUE; | ||
86 | } | ||
87 | } | ||
88 | #endif | ||
89 | |||
90 | /* Tiled 3d textures don't have subsets that look like 2d surfaces: | ||
91 | */ | ||
92 | |||
93 | /* Everything else should be fine to render to in-place: | ||
94 | */ | ||
95 | return GL_FALSE; | ||
96 | } | ||
97 | |||
98 | /* Look at all texture views and figure out if any of them need to be | ||
99 | * back-copied into the texture for sampling | ||
100 | */ | ||
101 | void brw_update_texture( struct brw_screen *brw_screen, | ||
102 | struct brw_texture *tex ) | ||
103 | { | ||
104 | /* currently nothing to do */ | ||
105 | } | ||
106 | |||
107 | |||
108 | /* Create a new surface with linear layout to serve as a render-target | ||
109 | * where it would be illegal (perhaps due to tiling constraints) to do | ||
110 | * this in-place. | ||
111 | * | ||
112 | * Currently not implemented, not sure if it's needed. | ||
113 | */ | ||
114 | static struct brw_surface *create_linear_view( struct brw_screen *brw_screen, | ||
115 | struct pipe_context *pipe, | ||
116 | struct brw_texture *tex, | ||
117 | union brw_surface_id id, | ||
118 | unsigned usage ) | ||
119 | { | ||
120 | return NULL; | ||
121 | } | ||
122 | |||
123 | |||
124 | /* Create a pipe_surface that just points directly into the existing | ||
125 | * texture's storage. | ||
126 | */ | ||
127 | static struct brw_surface *create_in_place_view( struct brw_screen *brw_screen, | ||
128 | struct pipe_context *pipe, | ||
129 | struct brw_texture *tex, | ||
130 | union brw_surface_id id, | ||
131 | unsigned usage ) | ||
132 | { | ||
133 | struct brw_surface *surface; | ||
134 | |||
135 | surface = CALLOC_STRUCT(brw_surface); | ||
136 | if (surface == NULL) | ||
137 | return NULL; | ||
138 | |||
139 | pipe_reference_init(&surface->base.reference, 1); | ||
140 | |||
141 | /* XXX: ignoring render-to-slice-of-3d-texture | ||
142 | */ | ||
143 | assert(tex->b.b.target != PIPE_TEXTURE_3D || id.bits.layer == 0); | ||
144 | |||
145 | surface->base.context = pipe; | ||
146 | surface->base.format = tex->b.b.format; | ||
147 | surface->base.width = u_minify(tex->b.b.width0, id.bits.level); | ||
148 | surface->base.height = u_minify(tex->b.b.height0, id.bits.level); | ||
149 | surface->base.usage = usage; | ||
150 | surface->base.u.tex.first_layer = id.bits.layer; | ||
151 | surface->base.u.tex.last_layer = surface->base.u.tex.first_layer; | ||
152 | surface->base.u.tex.level = id.bits.level; | ||
153 | surface->id = id; | ||
154 | surface->offset = tex->image_offset[id.bits.level][id.bits.layer]; | ||
155 | surface->cpp = tex->cpp; | ||
156 | surface->pitch = tex->pitch; | ||
157 | surface->tiling = tex->tiling; | ||
158 | |||
159 | bo_reference( &surface->bo, tex->bo ); | ||
160 | pipe_resource_reference( &surface->base.texture, &tex->b.b ); | ||
161 | |||
162 | surface->ss.ss0.surface_format = tex->ss.ss0.surface_format; | ||
163 | surface->ss.ss0.surface_type = BRW_SURFACE_2D; | ||
164 | |||
165 | if (tex->tiling == BRW_TILING_NONE) { | ||
166 | surface->ss.ss1.base_addr = surface->offset; | ||
167 | } else { | ||
168 | uint32_t tile_offset = surface->offset % 4096; | ||
169 | |||
170 | surface->ss.ss1.base_addr = surface->offset - tile_offset; | ||
171 | |||
172 | if (tex->tiling == BRW_TILING_X) { | ||
173 | /* Note that the low bits of these fields are missing, so | ||
174 | * there's the possibility of getting in trouble. | ||
175 | */ | ||
176 | surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4; | ||
177 | surface->ss.ss5.y_offset = tile_offset / 512 / 2; | ||
178 | } else { | ||
179 | surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4; | ||
180 | surface->ss.ss5.y_offset = tile_offset / 128 / 2; | ||
181 | } | ||
182 | } | ||
183 | |||
184 | #if 0 | ||
185 | if (region_bo != NULL) | ||
186 | surface->ss.ss1.base_addr += region_bo->offset; /* reloc */ | ||
187 | #endif | ||
188 | |||
189 | surface->ss.ss2.width = surface->base.width - 1; | ||
190 | surface->ss.ss2.height = surface->base.height - 1; | ||
191 | surface->ss.ss3.tiled_surface = tex->ss.ss3.tiled_surface; | ||
192 | surface->ss.ss3.tile_walk = tex->ss.ss3.tile_walk; | ||
193 | surface->ss.ss3.pitch = tex->ss.ss3.pitch; | ||
194 | |||
195 | return surface; | ||
196 | } | ||
197 | |||
198 | /* Get a surface which is view into a texture | ||
199 | */ | ||
200 | static struct pipe_surface *brw_create_surface(struct pipe_context *pipe, | ||
201 | struct pipe_resource *pt, | ||
202 | const struct pipe_surface *surf_tmpl) | ||
203 | { | ||
204 | struct brw_texture *tex = brw_texture(pt); | ||
205 | struct brw_screen *bscreen = brw_screen(pipe->screen); | ||
206 | struct brw_surface *surface; | ||
207 | union brw_surface_id id; | ||
208 | int type; | ||
209 | |||
210 | assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); | ||
211 | id.bits.level = surf_tmpl->u.tex.level; | ||
212 | id.bits.layer = surf_tmpl->u.tex.first_layer; | ||
213 | |||
214 | if (need_linear_view(bscreen, tex, id, surf_tmpl->usage)) | ||
215 | type = BRW_VIEW_LINEAR; | ||
216 | else | ||
217 | type = BRW_VIEW_IN_PLACE; | ||
218 | |||
219 | |||
220 | foreach (surface, &tex->views[type]) { | ||
221 | if (id.value == surface->id.value) | ||
222 | return &surface->base; | ||
223 | } | ||
224 | |||
225 | switch (type) { | ||
226 | case BRW_VIEW_LINEAR: | ||
227 | surface = create_linear_view( bscreen, pipe, tex, id, surf_tmpl->usage ); | ||
228 | break; | ||
229 | case BRW_VIEW_IN_PLACE: | ||
230 | surface = create_in_place_view( bscreen, pipe, tex, id, surf_tmpl->usage ); | ||
231 | break; | ||
232 | } | ||
233 | |||
234 | insert_at_head( &tex->views[type], surface ); | ||
235 | return &surface->base; | ||
236 | } | ||
237 | |||
238 | |||
239 | static void brw_surface_destroy( struct pipe_context *pipe, | ||
240 | struct pipe_surface *surf ) | ||
241 | { | ||
242 | struct brw_surface *surface = brw_surface(surf); | ||
243 | |||
244 | /* Unreference texture, shared buffer: | ||
245 | */ | ||
246 | remove_from_list(surface); | ||
247 | bo_reference(&surface->bo, NULL); | ||
248 | pipe_resource_reference( &surface->base.texture, NULL ); | ||
249 | |||
250 | FREE(surface); | ||
251 | } | ||
252 | |||
253 | |||
254 | void brw_pipe_surface_init( struct brw_context *brw ) | ||
255 | { | ||
256 | brw->base.create_surface = brw_create_surface; | ||
257 | brw->base.surface_destroy = brw_surface_destroy; | ||
258 | } | ||
diff --git a/src/gallium/drivers/i965/brw_pipe_vertex.c b/src/gallium/drivers/i965/brw_pipe_vertex.c deleted file mode 100644 index 570ea23ff45..00000000000 --- a/src/gallium/drivers/i965/brw_pipe_vertex.c +++ /dev/null | |||
@@ -1,329 +0,0 @@ | |||
1 | #include "brw_context.h" | ||
2 | #include "brw_defines.h" | ||
3 | #include "brw_structs.h" | ||
4 | |||
5 | #include "util/u_memory.h" | ||
6 | #include "util/u_format.h" | ||
7 | #include "util/u_transfer.h" | ||
8 | |||
9 | |||
10 | static unsigned brw_translate_surface_format( unsigned id ) | ||
11 | { | ||
12 | switch (id) { | ||
13 | case PIPE_FORMAT_R64_FLOAT: | ||
14 | return BRW_SURFACEFORMAT_R64_FLOAT; | ||
15 | case PIPE_FORMAT_R64G64_FLOAT: | ||
16 | return BRW_SURFACEFORMAT_R64G64_FLOAT; | ||
17 | case PIPE_FORMAT_R64G64B64_FLOAT: | ||
18 | return BRW_SURFACEFORMAT_R64G64B64_FLOAT; | ||
19 | case PIPE_FORMAT_R64G64B64A64_FLOAT: | ||
20 | return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT; | ||
21 | |||
22 | case PIPE_FORMAT_R32_FLOAT: | ||
23 | return BRW_SURFACEFORMAT_R32_FLOAT; | ||
24 | case PIPE_FORMAT_R32G32_FLOAT: | ||
25 | return BRW_SURFACEFORMAT_R32G32_FLOAT; | ||
26 | case PIPE_FORMAT_R32G32B32_FLOAT: | ||
27 | return BRW_SURFACEFORMAT_R32G32B32_FLOAT; | ||
28 | case PIPE_FORMAT_R32G32B32A32_FLOAT: | ||
29 | return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; | ||
30 | |||
31 | case PIPE_FORMAT_R32_UNORM: | ||
32 | return BRW_SURFACEFORMAT_R32_UNORM; | ||
33 | case PIPE_FORMAT_R32G32_UNORM: | ||
34 | return BRW_SURFACEFORMAT_R32G32_UNORM; | ||
35 | case PIPE_FORMAT_R32G32B32_UNORM: | ||
36 | return BRW_SURFACEFORMAT_R32G32B32_UNORM; | ||
37 | case PIPE_FORMAT_R32G32B32A32_UNORM: | ||
38 | return BRW_SURFACEFORMAT_R32G32B32A32_UNORM; | ||
39 | |||
40 | case PIPE_FORMAT_R32_USCALED: | ||
41 | return BRW_SURFACEFORMAT_R32_USCALED; | ||
42 | case PIPE_FORMAT_R32G32_USCALED: | ||
43 | return BRW_SURFACEFORMAT_R32G32_USCALED; | ||
44 | case PIPE_FORMAT_R32G32B32_USCALED: | ||
45 | return BRW_SURFACEFORMAT_R32G32B32_USCALED; | ||
46 | case PIPE_FORMAT_R32G32B32A32_USCALED: | ||
47 | return BRW_SURFACEFORMAT_R32G32B32A32_USCALED; | ||
48 | |||
49 | case PIPE_FORMAT_R32_SNORM: | ||
50 | return BRW_SURFACEFORMAT_R32_SNORM; | ||
51 | case PIPE_FORMAT_R32G32_SNORM: | ||
52 | return BRW_SURFACEFORMAT_R32G32_SNORM; | ||
53 | case PIPE_FORMAT_R32G32B32_SNORM: | ||
54 | return BRW_SURFACEFORMAT_R32G32B32_SNORM; | ||
55 | case PIPE_FORMAT_R32G32B32A32_SNORM: | ||
56 | return BRW_SURFACEFORMAT_R32G32B32A32_SNORM; | ||
57 | |||
58 | case PIPE_FORMAT_R32_SSCALED: | ||
59 | return BRW_SURFACEFORMAT_R32_SSCALED; | ||
60 | case PIPE_FORMAT_R32G32_SSCALED: | ||
61 | return BRW_SURFACEFORMAT_R32G32_SSCALED; | ||
62 | case PIPE_FORMAT_R32G32B32_SSCALED: | ||
63 | return BRW_SURFACEFORMAT_R32G32B32_SSCALED; | ||
64 | case PIPE_FORMAT_R32G32B32A32_SSCALED: | ||
65 | return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED; | ||
66 | |||
67 | case PIPE_FORMAT_R16_UNORM: | ||
68 | return BRW_SURFACEFORMAT_R16_UNORM; | ||
69 | case PIPE_FORMAT_R16G16_UNORM: | ||
70 | return BRW_SURFACEFORMAT_R16G16_UNORM; | ||
71 | case PIPE_FORMAT_R16G16B16_UNORM: | ||
72 | return BRW_SURFACEFORMAT_R16G16B16_UNORM; | ||
73 | case PIPE_FORMAT_R16G16B16A16_UNORM: | ||
74 | return BRW_SURFACEFORMAT_R16G16B16A16_UNORM; | ||
75 | |||
76 | case PIPE_FORMAT_R16_USCALED: | ||
77 | return BRW_SURFACEFORMAT_R16_USCALED; | ||
78 | case PIPE_FORMAT_R16G16_USCALED: | ||
79 | return BRW_SURFACEFORMAT_R16G16_USCALED; | ||
80 | case PIPE_FORMAT_R16G16B16_USCALED: | ||
81 | return BRW_SURFACEFORMAT_R16G16B16_USCALED; | ||
82 | case PIPE_FORMAT_R16G16B16A16_USCALED: | ||
83 | return BRW_SURFACEFORMAT_R16G16B16A16_USCALED; | ||
84 | |||
85 | case PIPE_FORMAT_R16_SNORM: | ||
86 | return BRW_SURFACEFORMAT_R16_SNORM; | ||
87 | case PIPE_FORMAT_R16G16_SNORM: | ||
88 | return BRW_SURFACEFORMAT_R16G16_SNORM; | ||
89 | case PIPE_FORMAT_R16G16B16_SNORM: | ||
90 | return BRW_SURFACEFORMAT_R16G16B16_SNORM; | ||
91 | case PIPE_FORMAT_R16G16B16A16_SNORM: | ||
92 | return BRW_SURFACEFORMAT_R16G16B16A16_SNORM; | ||
93 | |||
94 | case PIPE_FORMAT_R16_SSCALED: | ||
95 | return BRW_SURFACEFORMAT_R16_SSCALED; | ||
96 | case PIPE_FORMAT_R16G16_SSCALED: | ||
97 | return BRW_SURFACEFORMAT_R16G16_SSCALED; | ||
98 | case PIPE_FORMAT_R16G16B16_SSCALED: | ||
99 | return BRW_SURFACEFORMAT_R16G16B16_SSCALED; | ||
100 | case PIPE_FORMAT_R16G16B16A16_SSCALED: | ||
101 | return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED; | ||
102 | |||
103 | case PIPE_FORMAT_R8_UNORM: | ||
104 | return BRW_SURFACEFORMAT_R8_UNORM; | ||
105 | case PIPE_FORMAT_R8G8_UNORM: | ||
106 | return BRW_SURFACEFORMAT_R8G8_UNORM; | ||
107 | case PIPE_FORMAT_R8G8B8_UNORM: | ||
108 | return BRW_SURFACEFORMAT_R8G8B8_UNORM; | ||
109 | case PIPE_FORMAT_R8G8B8A8_UNORM: | ||
110 | return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; | ||
111 | |||
112 | case PIPE_FORMAT_R8_USCALED: | ||
113 | return BRW_SURFACEFORMAT_R8_USCALED; | ||
114 | case PIPE_FORMAT_R8G8_USCALED: | ||
115 | return BRW_SURFACEFORMAT_R8G8_USCALED; | ||
116 | case PIPE_FORMAT_R8G8B8_USCALED: | ||
117 | return BRW_SURFACEFORMAT_R8G8B8_USCALED; | ||
118 | case PIPE_FORMAT_R8G8B8A8_USCALED: | ||
119 | return BRW_SURFACEFORMAT_R8G8B8A8_USCALED; | ||
120 | |||
121 | case PIPE_FORMAT_R8_SNORM: | ||
122 | return BRW_SURFACEFORMAT_R8_SNORM; | ||
123 | case PIPE_FORMAT_R8G8_SNORM: | ||
124 | return BRW_SURFACEFORMAT_R8G8_SNORM; | ||
125 | case PIPE_FORMAT_R8G8B8_SNORM: | ||
126 | return BRW_SURFACEFORMAT_R8G8B8_SNORM; | ||
127 | case PIPE_FORMAT_R8G8B8A8_SNORM: | ||
128 | return BRW_SURFACEFORMAT_R8G8B8A8_SNORM; | ||
129 | |||
130 | case PIPE_FORMAT_R8_SSCALED: | ||
131 | return BRW_SURFACEFORMAT_R8_SSCALED; | ||
132 | case PIPE_FORMAT_R8G8_SSCALED: | ||
133 | return BRW_SURFACEFORMAT_R8G8_SSCALED; | ||
134 | case PIPE_FORMAT_R8G8B8_SSCALED: | ||
135 | return BRW_SURFACEFORMAT_R8G8B8_SSCALED; | ||
136 | case PIPE_FORMAT_R8G8B8A8_SSCALED: | ||
137 | return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED; | ||
138 | |||
139 | default: | ||
140 | assert(0); | ||
141 | return 0; | ||
142 | } | ||
143 | } | ||
144 | |||
145 | static void brw_translate_vertex_elements(struct brw_context *brw, | ||
146 | struct brw_vertex_element_packet *brw_velems, | ||
147 | const struct pipe_vertex_element *attribs, | ||
148 | unsigned count) | ||
149 | { | ||
150 | unsigned i; | ||
151 | |||
152 | /* If the VS doesn't read any inputs (calculating vertex position from | ||
153 | * a state variable for some reason, for example), emit a single pad | ||
154 | * VERTEX_ELEMENT struct and bail. | ||
155 | * | ||
156 | * The stale VB state stays in place, but they don't do anything unless | ||
157 | * a VE loads from them. | ||
158 | */ | ||
159 | brw_velems->header.opcode = CMD_VERTEX_ELEMENT; | ||
160 | |||
161 | if (count == 0) { | ||
162 | brw_velems->header.length = 1; | ||
163 | brw_velems->ve[0].ve0.src_offset = 0; | ||
164 | brw_velems->ve[0].ve0.src_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; | ||
165 | brw_velems->ve[0].ve0.valid = 1; | ||
166 | brw_velems->ve[0].ve0.vertex_buffer_index = 0; | ||
167 | brw_velems->ve[0].ve1.dst_offset = 0; | ||
168 | brw_velems->ve[0].ve1.vfcomponent0 = BRW_VE1_COMPONENT_STORE_0; | ||
169 | brw_velems->ve[0].ve1.vfcomponent1 = BRW_VE1_COMPONENT_STORE_0; | ||
170 | brw_velems->ve[0].ve1.vfcomponent2 = BRW_VE1_COMPONENT_STORE_0; | ||
171 | brw_velems->ve[0].ve1.vfcomponent3 = BRW_VE1_COMPONENT_STORE_1_FLT; | ||
172 | return; | ||
173 | } | ||
174 | |||
175 | |||
176 | /* Now emit vertex element (VEP) state packets. | ||
177 | * | ||
178 | */ | ||
179 | brw_velems->header.length = (1 + count * 2) - 2; | ||
180 | for (i = 0; i < count; i++) { | ||
181 | const struct pipe_vertex_element *input = &attribs[i]; | ||
182 | unsigned nr_components = util_format_get_nr_components(input->src_format); | ||
183 | |||
184 | uint32_t format = brw_translate_surface_format( input->src_format ); | ||
185 | uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC; | ||
186 | uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC; | ||
187 | uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC; | ||
188 | uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC; | ||
189 | |||
190 | switch (nr_components) { | ||
191 | case 0: comp0 = BRW_VE1_COMPONENT_STORE_0; /* fallthrough */ | ||
192 | case 1: comp1 = BRW_VE1_COMPONENT_STORE_0; /* fallthrough */ | ||
193 | case 2: comp2 = BRW_VE1_COMPONENT_STORE_0; /* fallthrough */ | ||
194 | case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT; | ||
195 | break; | ||
196 | } | ||
197 | |||
198 | brw_velems->ve[i].ve0.src_offset = input->src_offset; | ||
199 | brw_velems->ve[i].ve0.src_format = format; | ||
200 | brw_velems->ve[i].ve0.valid = 1; | ||
201 | brw_velems->ve[i].ve0.vertex_buffer_index = input->vertex_buffer_index; | ||
202 | brw_velems->ve[i].ve1.vfcomponent0 = comp0; | ||
203 | brw_velems->ve[i].ve1.vfcomponent1 = comp1; | ||
204 | brw_velems->ve[i].ve1.vfcomponent2 = comp2; | ||
205 | brw_velems->ve[i].ve1.vfcomponent3 = comp3; | ||
206 | |||
207 | if (brw->gen == 5) | ||
208 | brw_velems->ve[i].ve1.dst_offset = 0; | ||
209 | else | ||
210 | brw_velems->ve[i].ve1.dst_offset = i * 4; | ||
211 | } | ||
212 | } | ||
213 | |||
214 | static void* brw_create_vertex_elements_state( struct pipe_context *pipe, | ||
215 | unsigned count, | ||
216 | const struct pipe_vertex_element *attribs ) | ||
217 | { | ||
218 | /* note: for the brw_swtnl.c code (if ever we need draw fallback) we'd also need | ||
219 | to store the original data */ | ||
220 | struct brw_context *brw = brw_context(pipe); | ||
221 | struct brw_vertex_element_packet *velems; | ||
222 | assert(count <= BRW_VEP_MAX); | ||
223 | velems = (struct brw_vertex_element_packet *) MALLOC(sizeof(struct brw_vertex_element_packet)); | ||
224 | if (velems) { | ||
225 | brw_translate_vertex_elements(brw, velems, attribs, count); | ||
226 | } | ||
227 | return velems; | ||
228 | } | ||
229 | |||
230 | static void brw_bind_vertex_elements_state(struct pipe_context *pipe, | ||
231 | void *velems) | ||
232 | { | ||
233 | struct brw_context *brw = brw_context(pipe); | ||
234 | struct brw_vertex_element_packet *brw_velems = (struct brw_vertex_element_packet *) velems; | ||
235 | |||
236 | brw->curr.velems = brw_velems; | ||
237 | |||
238 | brw->state.dirty.mesa |= PIPE_NEW_VERTEX_ELEMENT; | ||
239 | } | ||
240 | |||
241 | static void brw_delete_vertex_elements_state(struct pipe_context *pipe, void *velems) | ||
242 | { | ||
243 | FREE( velems ); | ||
244 | } | ||
245 | |||
246 | |||
247 | static void brw_set_vertex_buffers(struct pipe_context *pipe, | ||
248 | unsigned count, | ||
249 | const struct pipe_vertex_buffer *buffers) | ||
250 | { | ||
251 | struct brw_context *brw = brw_context(pipe); | ||
252 | |||
253 | /* Check for no change */ | ||
254 | if (count == brw->curr.num_vertex_buffers && | ||
255 | memcmp(brw->curr.vertex_buffer, | ||
256 | buffers, | ||
257 | count * sizeof buffers[0]) == 0) | ||
258 | return; | ||
259 | |||
260 | util_copy_vertex_buffers(brw->curr.vertex_buffer, | ||
261 | &brw->curr.num_vertex_buffers, | ||
262 | buffers, count); | ||
263 | |||
264 | brw->state.dirty.mesa |= PIPE_NEW_VERTEX_BUFFER; | ||
265 | } | ||
266 | |||
267 | |||
268 | static void brw_set_index_buffer(struct pipe_context *pipe, | ||
269 | const struct pipe_index_buffer *ib) | ||
270 | { | ||
271 | struct brw_context *brw = brw_context(pipe); | ||
272 | |||
273 | if (ib) { | ||
274 | if (brw->curr.index_buffer == ib->buffer && | ||
275 | brw->curr.index_offset == ib->offset && | ||
276 | brw->curr.index_size == ib->index_size) | ||
277 | return; | ||
278 | |||
279 | pipe_resource_reference(&brw->curr.index_buffer, ib->buffer); | ||
280 | brw->curr.index_offset = ib->offset; | ||
281 | brw->curr.index_size = ib->index_size; | ||
282 | } | ||
283 | else { | ||
284 | if (!brw->curr.index_buffer && | ||
285 | !brw->curr.index_offset && | ||
286 | !brw->curr.index_size) | ||
287 | return; | ||
288 | |||
289 | pipe_resource_reference(&brw->curr.index_buffer, NULL); | ||
290 | brw->curr.index_offset = 0; | ||
291 | brw->curr.index_size = 0; | ||
292 | } | ||
293 | |||
294 | brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER; | ||
295 | } | ||
296 | |||
297 | |||
298 | void | ||
299 | brw_pipe_vertex_init( struct brw_context *brw ) | ||
300 | { | ||
301 | brw->base.set_vertex_buffers = brw_set_vertex_buffers; | ||
302 | brw->base.set_index_buffer = brw_set_index_buffer; | ||
303 | brw->base.create_vertex_elements_state = brw_create_vertex_elements_state; | ||
304 | brw->base.bind_vertex_elements_state = brw_bind_vertex_elements_state; | ||
305 | brw->base.delete_vertex_elements_state = brw_delete_vertex_elements_state; | ||
306 | brw->base.redefine_user_buffer = u_default_redefine_user_buffer; | ||
307 | } | ||
308 | |||
309 | |||
310 | void | ||
311 | brw_pipe_vertex_cleanup( struct brw_context *brw ) | ||
312 | { | ||
313 | unsigned i; | ||
314 | |||
315 | /* Release bound pipe vertex_buffers | ||
316 | */ | ||
317 | for (i = 0; i < brw->curr.num_vertex_buffers; i++) { | ||
318 | pipe_resource_reference(&brw->curr.vertex_buffer[i].buffer, NULL); | ||
319 | } | ||
320 | |||
321 | /* Release some other stuff | ||
322 | */ | ||
323 | #if 0 | ||
324 | for (i = 0; i < PIPE_MAX_ATTRIBS; i++) { | ||
325 | bo_reference(&brw->vb.inputs[i].bo, NULL); | ||
326 | brw->vb.inputs[i].bo = NULL; | ||
327 | } | ||
328 | #endif | ||
329 | } | ||
diff --git a/src/gallium/drivers/i965/brw_public.h b/src/gallium/drivers/i965/brw_public.h deleted file mode 100644 index be2cd6b5c4d..00000000000 --- a/src/gallium/drivers/i965/brw_public.h +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | |||
2 | #ifndef BRW_PUBLIC_H | ||
3 | #define BRW_PUBLIC_H | ||
4 | |||
5 | struct brw_winsys_screen; | ||
6 | struct pipe_screen; | ||
7 | |||
8 | /** | ||
9 | * Create brw AKA i965 pipe_screen. | ||
10 | */ | ||
11 | struct pipe_screen * brw_screen_create(struct brw_winsys_screen *bws); | ||
12 | |||
13 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_reg.h b/src/gallium/drivers/i965/brw_reg.h deleted file mode 100644 index 53c7c435713..00000000000 --- a/src/gallium/drivers/i965/brw_reg.h +++ /dev/null | |||
@@ -1,151 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #ifndef BRW_REG_H | ||
29 | #define BRW_REG_H | ||
30 | |||
31 | #define CMD_MI (0x0 << 29) | ||
32 | #define CMD_2D (0x2 << 29) | ||
33 | #define CMD_3D (0x3 << 29) | ||
34 | |||
35 | #define MI_NOOP (CMD_MI | 0) | ||
36 | #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) | ||
37 | #define MI_FLUSH (CMD_MI | (4 << 23)) | ||
38 | |||
39 | #define _3DSTATE_DRAWRECT_INFO_I965 (CMD_3D | (3 << 27) | (1 << 24) | 0x2) | ||
40 | |||
41 | /** @{ | ||
42 | * | ||
43 | * PIPE_CONTROL operation, a combination MI_FLUSH and register write with | ||
44 | * additional flushing control. | ||
45 | */ | ||
46 | #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2) | ||
47 | #define PIPE_CONTROL_NO_WRITE (0 << 14) | ||
48 | #define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14) | ||
49 | #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14) | ||
50 | #define PIPE_CONTROL_WRITE_TIMESTAMP (3 << 14) | ||
51 | #define PIPE_CONTROL_DEPTH_STALL (1 << 13) | ||
52 | #define PIPE_CONTROL_WRITE_FLUSH (1 << 12) | ||
53 | #define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11) | ||
54 | #define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8) | ||
55 | #define PIPE_CONTROL_PPGTT_WRITE (0 << 2) | ||
56 | #define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2) | ||
57 | |||
58 | /** @} */ | ||
59 | |||
60 | #define XY_SETUP_BLT_CMD (CMD_2D | (0x01 << 22) | 6) | ||
61 | #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 4) | ||
62 | #define XY_SRC_COPY_BLT_CMD (CMD_2D | (0x53 << 22) | 6) | ||
63 | |||
64 | /* BR00 */ | ||
65 | #define XY_BLT_WRITE_ALPHA (1 << 21) | ||
66 | #define XY_BLT_WRITE_RGB (1 << 20) | ||
67 | #define XY_SRC_TILED (1 << 15) | ||
68 | #define XY_DST_TILED (1 << 11) | ||
69 | |||
70 | /* BR13 */ | ||
71 | #define BR13_565 (0x1 << 24) | ||
72 | #define BR13_8888 (0x3 << 24) | ||
73 | |||
74 | #define FENCE_LINEAR 0 | ||
75 | #define FENCE_XMAJOR 1 | ||
76 | #define FENCE_YMAJOR 2 | ||
77 | |||
78 | |||
79 | |||
80 | /* PCI IDs | ||
81 | */ | ||
82 | #define PCI_CHIP_I965_G 0x29A2 | ||
83 | #define PCI_CHIP_I965_Q 0x2992 | ||
84 | #define PCI_CHIP_I965_G_1 0x2982 | ||
85 | #define PCI_CHIP_I946_GZ 0x2972 | ||
86 | #define PCI_CHIP_I965_GM 0x2A02 | ||
87 | #define PCI_CHIP_I965_GME 0x2A12 | ||
88 | |||
89 | #define PCI_CHIP_GM45_GM 0x2A42 | ||
90 | |||
91 | #define PCI_CHIP_IGD_E_G 0x2E02 | ||
92 | #define PCI_CHIP_Q45_G 0x2E12 | ||
93 | #define PCI_CHIP_G45_G 0x2E22 | ||
94 | #define PCI_CHIP_G41_G 0x2E32 | ||
95 | #define PCI_CHIP_B43_G 0x2E42 | ||
96 | #define PCI_CHIP_B43_G1 0x2E92 | ||
97 | |||
98 | #define PCI_CHIP_ILD_G 0x0042 | ||
99 | #define PCI_CHIP_ILM_G 0x0046 | ||
100 | |||
101 | #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */ | ||
102 | #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 | ||
103 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 | ||
104 | #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */ | ||
105 | #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 | ||
106 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 | ||
107 | #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* Server */ | ||
108 | |||
109 | #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ | ||
110 | devid == PCI_CHIP_Q45_G || \ | ||
111 | devid == PCI_CHIP_G45_G || \ | ||
112 | devid == PCI_CHIP_G41_G || \ | ||
113 | devid == PCI_CHIP_B43_G || \ | ||
114 | devid == PCI_CHIP_B43_G1) | ||
115 | #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) | ||
116 | #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) | ||
117 | |||
118 | #define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \ | ||
119 | devid == PCI_CHIP_I965_Q || \ | ||
120 | devid == PCI_CHIP_I965_G_1 || \ | ||
121 | devid == PCI_CHIP_I965_GM || \ | ||
122 | devid == PCI_CHIP_I965_GME || \ | ||
123 | devid == PCI_CHIP_I946_GZ || \ | ||
124 | IS_G4X(devid)) | ||
125 | |||
126 | #define IS_ILD(devid) (devid == PCI_CHIP_ILD_G) | ||
127 | #define IS_ILM(devid) (devid == PCI_CHIP_ILM_G) | ||
128 | #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) | ||
129 | |||
130 | #define IS_IRONLAKE(devid) IS_GEN5(devid) | ||
131 | |||
132 | #define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ | ||
133 | devid == PCI_CHIP_SANDYBRIDGE_GT2 || \ | ||
134 | devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ | ||
135 | devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ | ||
136 | devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ | ||
137 | devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ | ||
138 | devid == PCI_CHIP_SANDYBRIDGE_S) | ||
139 | |||
140 | #define IS_965(devid) (IS_GEN4(devid) || \ | ||
141 | IS_G4X(devid) || \ | ||
142 | IS_GEN5(devid) || \ | ||
143 | IS_GEN6(devid)) | ||
144 | |||
145 | /* XXX: hacks | ||
146 | */ | ||
147 | #define VERT_RESULT_HPOS 0 /* not always true */ | ||
148 | #define VERT_RESULT_PSIZ 127 /* disabled */ | ||
149 | |||
150 | |||
151 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_resource.c b/src/gallium/drivers/i965/brw_resource.c deleted file mode 100644 index 3b61ffbd035..00000000000 --- a/src/gallium/drivers/i965/brw_resource.c +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | #include "util/u_debug.h" | ||
2 | #include "util/u_surface.h" | ||
3 | |||
4 | #include "brw_resource.h" | ||
5 | #include "brw_context.h" | ||
6 | #include "brw_screen.h" | ||
7 | |||
8 | |||
9 | static struct pipe_resource * | ||
10 | brw_resource_create(struct pipe_screen *screen, | ||
11 | const struct pipe_resource *template) | ||
12 | { | ||
13 | if (template->target == PIPE_BUFFER) | ||
14 | return brw_buffer_create(screen, template); | ||
15 | else | ||
16 | return brw_texture_create(screen, template); | ||
17 | |||
18 | } | ||
19 | |||
20 | static struct pipe_resource * | ||
21 | brw_resource_from_handle(struct pipe_screen * screen, | ||
22 | const struct pipe_resource *template, | ||
23 | struct winsys_handle *whandle) | ||
24 | { | ||
25 | if (template->target == PIPE_BUFFER) | ||
26 | return NULL; | ||
27 | else | ||
28 | return brw_texture_from_handle(screen, template, whandle); | ||
29 | } | ||
30 | |||
31 | |||
32 | void | ||
33 | brw_init_resource_functions(struct brw_context *brw ) | ||
34 | { | ||
35 | brw->base.get_transfer = u_get_transfer_vtbl; | ||
36 | brw->base.transfer_map = u_transfer_map_vtbl; | ||
37 | brw->base.transfer_flush_region = u_transfer_flush_region_vtbl; | ||
38 | brw->base.transfer_unmap = u_transfer_unmap_vtbl; | ||
39 | brw->base.transfer_destroy = u_transfer_destroy_vtbl; | ||
40 | brw->base.transfer_inline_write = u_transfer_inline_write_vtbl; | ||
41 | brw->base.resource_copy_region = util_resource_copy_region; | ||
42 | } | ||
43 | |||
44 | void | ||
45 | brw_init_screen_resource_functions(struct brw_screen *is) | ||
46 | { | ||
47 | is->base.resource_create = brw_resource_create; | ||
48 | is->base.resource_from_handle = brw_resource_from_handle; | ||
49 | is->base.resource_get_handle = u_resource_get_handle_vtbl; | ||
50 | is->base.resource_destroy = u_resource_destroy_vtbl; | ||
51 | is->base.user_buffer_create = brw_user_buffer_create; | ||
52 | } | ||
diff --git a/src/gallium/drivers/i965/brw_resource.h b/src/gallium/drivers/i965/brw_resource.h deleted file mode 100644 index 78defb37b2a..00000000000 --- a/src/gallium/drivers/i965/brw_resource.h +++ /dev/null | |||
@@ -1,152 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #ifndef BRW_RESOURCE_H | ||
29 | #define BRW_RESOURCE_H | ||
30 | |||
31 | struct brw_screen; | ||
32 | |||
33 | #include "util/u_transfer.h" | ||
34 | #include "util/u_debug.h" | ||
35 | |||
36 | #include "brw_screen.h" /* for brw_surface */ | ||
37 | |||
38 | struct brw_context; | ||
39 | struct brw_screen; | ||
40 | |||
41 | |||
42 | struct brw_buffer { | ||
43 | struct u_resource b; | ||
44 | |||
45 | /* One of either bo or user_buffer will be non-null, depending on | ||
46 | * whether this is a hardware or user buffer. | ||
47 | */ | ||
48 | struct brw_winsys_buffer *bo; | ||
49 | void *user_buffer; | ||
50 | |||
51 | /* Mapped pointer?? | ||
52 | */ | ||
53 | void *ptr; | ||
54 | }; | ||
55 | |||
56 | #define BRW_MAX_TEXTURE_2D_LEVELS 11 /* max 1024x1024 */ | ||
57 | #define BRW_MAX_TEXTURE_3D_LEVELS 8 /* max 128x128x128 */ | ||
58 | |||
59 | |||
60 | |||
61 | struct brw_texture { | ||
62 | struct u_resource b; | ||
63 | struct brw_winsys_buffer *bo; | ||
64 | struct brw_surface_state ss; | ||
65 | |||
66 | unsigned *image_offset[BRW_MAX_TEXTURE_2D_LEVELS]; | ||
67 | unsigned nr_images[BRW_MAX_TEXTURE_2D_LEVELS]; | ||
68 | unsigned level_offset[BRW_MAX_TEXTURE_2D_LEVELS]; | ||
69 | |||
70 | boolean compressed; | ||
71 | unsigned brw_target; | ||
72 | unsigned pitch; | ||
73 | unsigned tiling; | ||
74 | unsigned cpp; | ||
75 | unsigned total_height; | ||
76 | |||
77 | struct brw_surface views[2]; | ||
78 | }; | ||
79 | |||
80 | |||
81 | void brw_init_screen_resource_functions(struct brw_screen *is); | ||
82 | void brw_init_resource_functions(struct brw_context *brw ); | ||
83 | |||
84 | extern struct u_resource_vtbl brw_buffer_vtbl; | ||
85 | extern struct u_resource_vtbl brw_texture_vtbl; | ||
86 | |||
87 | static INLINE struct brw_texture *brw_texture( struct pipe_resource *resource ) | ||
88 | { | ||
89 | struct brw_texture *tex = (struct brw_texture *)resource; | ||
90 | assert(tex->b.vtbl == &brw_texture_vtbl); | ||
91 | return tex; | ||
92 | } | ||
93 | |||
94 | static INLINE struct brw_buffer *brw_buffer( struct pipe_resource *resource ) | ||
95 | { | ||
96 | struct brw_buffer *tex = (struct brw_buffer *)resource; | ||
97 | assert(tex->b.vtbl == &brw_buffer_vtbl); | ||
98 | return tex; | ||
99 | } | ||
100 | |||
101 | struct pipe_resource * | ||
102 | brw_texture_create(struct pipe_screen *screen, | ||
103 | const struct pipe_resource *template); | ||
104 | |||
105 | struct pipe_resource * | ||
106 | brw_texture_from_handle(struct pipe_screen * screen, | ||
107 | const struct pipe_resource *template, | ||
108 | struct winsys_handle *whandle); | ||
109 | |||
110 | |||
111 | struct pipe_resource * | ||
112 | brw_user_buffer_create(struct pipe_screen *screen, | ||
113 | void *ptr, | ||
114 | unsigned bytes, | ||
115 | unsigned usage); | ||
116 | |||
117 | struct pipe_resource * | ||
118 | brw_buffer_create(struct pipe_screen *screen, | ||
119 | const struct pipe_resource *template); | ||
120 | |||
121 | |||
122 | /* | ||
123 | boolean | ||
124 | brw_is_format_supported( struct pipe_screen *screen, | ||
125 | enum pipe_format format, | ||
126 | enum pipe_texture_target target, | ||
127 | unsigned sample_count, | ||
128 | unsigned tex_usage, | ||
129 | unsigned geom_flags ); | ||
130 | */ | ||
131 | |||
132 | /* Pipe buffer helpers | ||
133 | */ | ||
134 | static INLINE boolean | ||
135 | brw_buffer_is_user_buffer( const struct pipe_resource *buf ) | ||
136 | { | ||
137 | return ((const struct brw_buffer *)buf)->user_buffer != NULL; | ||
138 | } | ||
139 | |||
140 | |||
141 | /*********************************************************************** | ||
142 | * Internal functions | ||
143 | */ | ||
144 | GLboolean brw_texture_layout(struct brw_screen *brw_screen, | ||
145 | struct brw_texture *tex ); | ||
146 | |||
147 | void brw_update_texture( struct brw_screen *brw_screen, | ||
148 | struct brw_texture *tex ); | ||
149 | |||
150 | |||
151 | |||
152 | #endif /* BRW_RESOURCE_H */ | ||
diff --git a/src/gallium/drivers/i965/brw_resource_buffer.c b/src/gallium/drivers/i965/brw_resource_buffer.c deleted file mode 100644 index 32dc54f2b26..00000000000 --- a/src/gallium/drivers/i965/brw_resource_buffer.c +++ /dev/null | |||
@@ -1,182 +0,0 @@ | |||
1 | |||
2 | #include "util/u_memory.h" | ||
3 | #include "util/u_math.h" | ||
4 | |||
5 | #include "pipe/p_state.h" | ||
6 | #include "pipe/p_defines.h" | ||
7 | #include "util/u_inlines.h" | ||
8 | |||
9 | #include "brw_resource.h" | ||
10 | #include "brw_context.h" | ||
11 | #include "brw_batchbuffer.h" | ||
12 | #include "brw_winsys.h" | ||
13 | |||
14 | static boolean | ||
15 | brw_buffer_get_handle(struct pipe_screen *screen, | ||
16 | struct pipe_resource *resource, | ||
17 | struct winsys_handle *handle) | ||
18 | { | ||
19 | return FALSE; | ||
20 | } | ||
21 | |||
22 | |||
23 | static void | ||
24 | brw_buffer_destroy(struct pipe_screen *screen, | ||
25 | struct pipe_resource *resource) | ||
26 | { | ||
27 | struct brw_buffer *buf = brw_buffer( resource ); | ||
28 | |||
29 | bo_reference(&buf->bo, NULL); | ||
30 | FREE(buf); | ||
31 | } | ||
32 | |||
33 | |||
34 | static void * | ||
35 | brw_buffer_transfer_map( struct pipe_context *pipe, | ||
36 | struct pipe_transfer *transfer) | ||
37 | { | ||
38 | struct brw_screen *bscreen = brw_screen(pipe->screen); | ||
39 | struct brw_winsys_screen *sws = bscreen->sws; | ||
40 | struct brw_buffer *buf = brw_buffer(transfer->resource); | ||
41 | unsigned offset = transfer->box.x; | ||
42 | unsigned length = transfer->box.width; | ||
43 | unsigned usage = transfer->usage; | ||
44 | uint8_t *map; | ||
45 | |||
46 | if (buf->user_buffer) | ||
47 | map = buf->user_buffer; | ||
48 | else | ||
49 | map = sws->bo_map( buf->bo, | ||
50 | BRW_DATA_OTHER, | ||
51 | offset, | ||
52 | length, | ||
53 | (usage & PIPE_TRANSFER_WRITE) ? TRUE : FALSE, | ||
54 | (usage & PIPE_TRANSFER_DISCARD) ? TRUE : FALSE, | ||
55 | (usage & PIPE_TRANSFER_FLUSH_EXPLICIT) ? TRUE : FALSE); | ||
56 | |||
57 | return map + offset; | ||
58 | } | ||
59 | |||
60 | |||
61 | static void | ||
62 | brw_buffer_transfer_flush_region( struct pipe_context *pipe, | ||
63 | struct pipe_transfer *transfer, | ||
64 | const struct pipe_box *box) | ||
65 | { | ||
66 | struct brw_screen *bscreen = brw_screen(pipe->screen); | ||
67 | struct brw_winsys_screen *sws = bscreen->sws; | ||
68 | struct brw_buffer *buf = brw_buffer(transfer->resource); | ||
69 | unsigned offset = box->x; | ||
70 | unsigned length = box->width; | ||
71 | |||
72 | if (buf->user_buffer) | ||
73 | return; | ||
74 | |||
75 | sws->bo_flush_range( buf->bo, | ||
76 | offset, | ||
77 | length ); | ||
78 | } | ||
79 | |||
80 | |||
81 | static void | ||
82 | brw_buffer_transfer_unmap( struct pipe_context *pipe, | ||
83 | struct pipe_transfer *transfer) | ||
84 | { | ||
85 | struct brw_screen *bscreen = brw_screen(pipe->screen); | ||
86 | struct brw_winsys_screen *sws = bscreen->sws; | ||
87 | struct brw_buffer *buf = brw_buffer( transfer->resource ); | ||
88 | |||
89 | if (buf->bo) | ||
90 | sws->bo_unmap(buf->bo); | ||
91 | } | ||
92 | |||
93 | |||
94 | struct u_resource_vtbl brw_buffer_vtbl = | ||
95 | { | ||
96 | brw_buffer_get_handle, /* get_handle */ | ||
97 | brw_buffer_destroy, /* resource_destroy */ | ||
98 | u_default_get_transfer, /* get_transfer */ | ||
99 | u_default_transfer_destroy, /* transfer_destroy */ | ||
100 | brw_buffer_transfer_map, /* transfer_map */ | ||
101 | brw_buffer_transfer_flush_region, /* transfer_flush_region */ | ||
102 | brw_buffer_transfer_unmap, /* transfer_unmap */ | ||
103 | u_default_transfer_inline_write /* transfer_inline_write */ | ||
104 | }; | ||
105 | |||
106 | |||
107 | struct pipe_resource * | ||
108 | brw_buffer_create(struct pipe_screen *screen, | ||
109 | const struct pipe_resource *template) | ||
110 | { | ||
111 | struct brw_screen *bscreen = brw_screen(screen); | ||
112 | struct brw_winsys_screen *sws = bscreen->sws; | ||
113 | struct brw_buffer *buf; | ||
114 | unsigned buffer_type; | ||
115 | enum pipe_error ret; | ||
116 | |||
117 | buf = CALLOC_STRUCT(brw_buffer); | ||
118 | if (!buf) | ||
119 | return NULL; | ||
120 | |||
121 | buf->b.b = *template; | ||
122 | buf->b.vtbl = &brw_buffer_vtbl; | ||
123 | pipe_reference_init(&buf->b.b.reference, 1); | ||
124 | buf->b.b.screen = screen; | ||
125 | |||
126 | switch (template->bind & (PIPE_BIND_VERTEX_BUFFER | | ||
127 | PIPE_BIND_INDEX_BUFFER | | ||
128 | PIPE_BIND_CONSTANT_BUFFER)) | ||
129 | { | ||
130 | case PIPE_BIND_VERTEX_BUFFER: | ||
131 | case PIPE_BIND_INDEX_BUFFER: | ||
132 | case (PIPE_BIND_VERTEX_BUFFER|PIPE_BIND_INDEX_BUFFER): | ||
133 | buffer_type = BRW_BUFFER_TYPE_VERTEX; | ||
134 | break; | ||
135 | |||
136 | case PIPE_BIND_CONSTANT_BUFFER: | ||
137 | buffer_type = BRW_BUFFER_TYPE_SHADER_CONSTANTS; | ||
138 | break; | ||
139 | |||
140 | default: | ||
141 | buffer_type = BRW_BUFFER_TYPE_GENERIC; | ||
142 | break; | ||
143 | } | ||
144 | |||
145 | ret = sws->bo_alloc( sws, buffer_type, | ||
146 | template->width0, | ||
147 | 64, /* alignment */ | ||
148 | &buf->bo ); | ||
149 | if (ret != PIPE_OK) | ||
150 | return NULL; | ||
151 | |||
152 | return &buf->b.b; | ||
153 | } | ||
154 | |||
155 | |||
156 | struct pipe_resource * | ||
157 | brw_user_buffer_create(struct pipe_screen *screen, | ||
158 | void *ptr, | ||
159 | unsigned bytes, | ||
160 | unsigned bind) | ||
161 | { | ||
162 | struct brw_buffer *buf; | ||
163 | |||
164 | buf = CALLOC_STRUCT(brw_buffer); | ||
165 | if (!buf) | ||
166 | return NULL; | ||
167 | |||
168 | pipe_reference_init(&buf->b.b.reference, 1); | ||
169 | buf->b.vtbl = &brw_buffer_vtbl; | ||
170 | buf->b.b.screen = screen; | ||
171 | buf->b.b.format = PIPE_FORMAT_R8_UNORM; /* ?? */ | ||
172 | buf->b.b.usage = PIPE_USAGE_IMMUTABLE; | ||
173 | buf->b.b.bind = bind; | ||
174 | buf->b.b.width0 = bytes; | ||
175 | buf->b.b.height0 = 1; | ||
176 | buf->b.b.depth0 = 1; | ||
177 | buf->b.b.array_size = 1; | ||
178 | |||
179 | buf->user_buffer = ptr; | ||
180 | |||
181 | return &buf->b.b; | ||
182 | } | ||
diff --git a/src/gallium/drivers/i965/brw_resource_texture.c b/src/gallium/drivers/i965/brw_resource_texture.c deleted file mode 100644 index 630efcbd970..00000000000 --- a/src/gallium/drivers/i965/brw_resource_texture.c +++ /dev/null | |||
@@ -1,555 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_memory.h" | ||
33 | #include "util/u_simple_list.h" | ||
34 | #include "util/u_format.h" | ||
35 | |||
36 | #include "brw_screen.h" | ||
37 | #include "brw_defines.h" | ||
38 | #include "brw_structs.h" | ||
39 | #include "brw_winsys.h" | ||
40 | #include "brw_batchbuffer.h" | ||
41 | #include "brw_context.h" | ||
42 | #include "brw_resource.h" | ||
43 | |||
44 | |||
45 | /** | ||
46 | * Subclass of pipe_transfer | ||
47 | */ | ||
48 | struct brw_transfer | ||
49 | { | ||
50 | struct pipe_transfer base; | ||
51 | |||
52 | unsigned offset; | ||
53 | }; | ||
54 | |||
55 | static INLINE struct brw_transfer * | ||
56 | brw_transfer(struct pipe_transfer *transfer) | ||
57 | { | ||
58 | return (struct brw_transfer *)transfer; | ||
59 | } | ||
60 | |||
61 | |||
62 | static GLuint translate_tex_target( unsigned target ) | ||
63 | { | ||
64 | switch (target) { | ||
65 | case PIPE_TEXTURE_1D: | ||
66 | return BRW_SURFACE_1D; | ||
67 | |||
68 | case PIPE_TEXTURE_2D: | ||
69 | case PIPE_TEXTURE_RECT: | ||
70 | return BRW_SURFACE_2D; | ||
71 | |||
72 | case PIPE_TEXTURE_3D: | ||
73 | return BRW_SURFACE_3D; | ||
74 | |||
75 | case PIPE_TEXTURE_CUBE: | ||
76 | return BRW_SURFACE_CUBE; | ||
77 | |||
78 | default: | ||
79 | assert(0); | ||
80 | return BRW_SURFACE_1D; | ||
81 | } | ||
82 | } | ||
83 | |||
84 | |||
85 | static GLuint translate_tex_format( enum pipe_format pf ) | ||
86 | { | ||
87 | switch( pf ) { | ||
88 | case PIPE_FORMAT_L8_UNORM: | ||
89 | return BRW_SURFACEFORMAT_L8_UNORM; | ||
90 | |||
91 | case PIPE_FORMAT_I8_UNORM: | ||
92 | return BRW_SURFACEFORMAT_I8_UNORM; | ||
93 | |||
94 | case PIPE_FORMAT_A8_UNORM: | ||
95 | return BRW_SURFACEFORMAT_A8_UNORM; | ||
96 | |||
97 | case PIPE_FORMAT_L16_UNORM: | ||
98 | return BRW_SURFACEFORMAT_L16_UNORM; | ||
99 | |||
100 | /* XXX: Add these to gallium | ||
101 | case PIPE_FORMAT_I16_UNORM: | ||
102 | return BRW_SURFACEFORMAT_I16_UNORM; | ||
103 | |||
104 | case PIPE_FORMAT_A16_UNORM: | ||
105 | return BRW_SURFACEFORMAT_A16_UNORM; | ||
106 | */ | ||
107 | |||
108 | case PIPE_FORMAT_L8A8_UNORM: | ||
109 | return BRW_SURFACEFORMAT_L8A8_UNORM; | ||
110 | |||
111 | case PIPE_FORMAT_B5G6R5_UNORM: | ||
112 | return BRW_SURFACEFORMAT_B5G6R5_UNORM; | ||
113 | |||
114 | case PIPE_FORMAT_B5G5R5A1_UNORM: | ||
115 | return BRW_SURFACEFORMAT_B5G5R5A1_UNORM; | ||
116 | |||
117 | case PIPE_FORMAT_B4G4R4A4_UNORM: | ||
118 | return BRW_SURFACEFORMAT_B4G4R4A4_UNORM; | ||
119 | |||
120 | case PIPE_FORMAT_B8G8R8X8_UNORM: | ||
121 | return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; | ||
122 | |||
123 | case PIPE_FORMAT_B8G8R8A8_UNORM: | ||
124 | return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; | ||
125 | |||
126 | /* | ||
127 | * Video formats | ||
128 | */ | ||
129 | |||
130 | case PIPE_FORMAT_YUYV: | ||
131 | return BRW_SURFACEFORMAT_YCRCB_NORMAL; | ||
132 | |||
133 | case PIPE_FORMAT_UYVY: | ||
134 | return BRW_SURFACEFORMAT_YCRCB_SWAPUVY; | ||
135 | |||
136 | /* | ||
137 | * Compressed formats. | ||
138 | */ | ||
139 | /* XXX: Add FXT to gallium? | ||
140 | case PIPE_FORMAT_FXT1_RGBA: | ||
141 | return BRW_SURFACEFORMAT_FXT1; | ||
142 | */ | ||
143 | |||
144 | case PIPE_FORMAT_DXT1_RGB: | ||
145 | return BRW_SURFACEFORMAT_DXT1_RGB; | ||
146 | |||
147 | case PIPE_FORMAT_DXT1_RGBA: | ||
148 | return BRW_SURFACEFORMAT_BC1_UNORM; | ||
149 | |||
150 | case PIPE_FORMAT_DXT3_RGBA: | ||
151 | return BRW_SURFACEFORMAT_BC2_UNORM; | ||
152 | |||
153 | case PIPE_FORMAT_DXT5_RGBA: | ||
154 | return BRW_SURFACEFORMAT_BC3_UNORM; | ||
155 | |||
156 | /* | ||
157 | * sRGB formats | ||
158 | */ | ||
159 | |||
160 | case PIPE_FORMAT_A8B8G8R8_SRGB: | ||
161 | return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB; | ||
162 | |||
163 | case PIPE_FORMAT_L8A8_SRGB: | ||
164 | return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB; | ||
165 | |||
166 | case PIPE_FORMAT_L8_SRGB: | ||
167 | return BRW_SURFACEFORMAT_L8_UNORM_SRGB; | ||
168 | |||
169 | case PIPE_FORMAT_DXT1_SRGB: | ||
170 | return BRW_SURFACEFORMAT_BC1_UNORM_SRGB; | ||
171 | |||
172 | /* | ||
173 | * Depth formats | ||
174 | */ | ||
175 | |||
176 | case PIPE_FORMAT_Z16_UNORM: | ||
177 | return BRW_SURFACEFORMAT_I16_UNORM; | ||
178 | |||
179 | case PIPE_FORMAT_Z24_UNORM_S8_UINT: | ||
180 | case PIPE_FORMAT_Z24X8_UNORM: | ||
181 | return BRW_SURFACEFORMAT_I24X8_UNORM; | ||
182 | |||
183 | case PIPE_FORMAT_Z32_FLOAT: | ||
184 | return BRW_SURFACEFORMAT_I32_FLOAT; | ||
185 | |||
186 | /* XXX: presumably for bump mapping. Add this to mesa state | ||
187 | * tracker? | ||
188 | * | ||
189 | * XXX: Add flipped versions of these formats to Gallium. | ||
190 | */ | ||
191 | case PIPE_FORMAT_R8G8_SNORM: | ||
192 | return BRW_SURFACEFORMAT_R8G8_SNORM; | ||
193 | |||
194 | case PIPE_FORMAT_R8G8B8A8_SNORM: | ||
195 | return BRW_SURFACEFORMAT_R8G8B8A8_SNORM; | ||
196 | |||
197 | default: | ||
198 | return BRW_SURFACEFORMAT_INVALID; | ||
199 | } | ||
200 | } | ||
201 | |||
202 | |||
203 | static boolean | ||
204 | brw_texture_get_handle(struct pipe_screen *screen, | ||
205 | struct pipe_resource *texture, | ||
206 | struct winsys_handle *whandle) | ||
207 | { | ||
208 | struct brw_screen *bscreen = brw_screen(screen); | ||
209 | struct brw_texture *tex = brw_texture(texture); | ||
210 | unsigned stride; | ||
211 | |||
212 | stride = tex->pitch * tex->cpp; | ||
213 | |||
214 | return bscreen->sws->bo_get_handle(tex->bo, whandle, stride) == PIPE_OK; | ||
215 | } | ||
216 | |||
217 | |||
218 | |||
219 | static void brw_texture_destroy(struct pipe_screen *screen, | ||
220 | struct pipe_resource *pt) | ||
221 | { | ||
222 | struct brw_texture *tex = brw_texture(pt); | ||
223 | bo_reference(&tex->bo, NULL); | ||
224 | FREE(pt); | ||
225 | } | ||
226 | |||
227 | |||
228 | /* | ||
229 | * Transfer functions | ||
230 | */ | ||
231 | |||
232 | |||
233 | static struct pipe_transfer * | ||
234 | brw_texture_get_transfer(struct pipe_context *context, | ||
235 | struct pipe_resource *resource, | ||
236 | unsigned level, | ||
237 | unsigned usage, | ||
238 | const struct pipe_box *box) | ||
239 | { | ||
240 | struct brw_texture *tex = brw_texture(resource); | ||
241 | struct pipe_transfer *transfer = CALLOC_STRUCT(pipe_transfer); | ||
242 | if (transfer == NULL) | ||
243 | return NULL; | ||
244 | |||
245 | transfer->resource = resource; | ||
246 | transfer->level = level; | ||
247 | transfer->usage = usage; | ||
248 | transfer->box = *box; | ||
249 | transfer->stride = tex->pitch * tex->cpp; | ||
250 | /* FIXME: layer_stride */ | ||
251 | |||
252 | return transfer; | ||
253 | } | ||
254 | |||
255 | |||
256 | static void * | ||
257 | brw_texture_transfer_map(struct pipe_context *pipe, | ||
258 | struct pipe_transfer *transfer) | ||
259 | { | ||
260 | struct pipe_resource *resource = transfer->resource; | ||
261 | struct brw_texture *tex = brw_texture(transfer->resource); | ||
262 | struct brw_winsys_screen *sws = brw_screen(pipe->screen)->sws; | ||
263 | struct pipe_box *box = &transfer->box; | ||
264 | enum pipe_format format = resource->format; | ||
265 | unsigned usage = transfer->usage; | ||
266 | unsigned offset; | ||
267 | char *map; | ||
268 | |||
269 | if (resource->target != PIPE_TEXTURE_3D && | ||
270 | resource->target != PIPE_TEXTURE_CUBE) | ||
271 | assert(box->z == 0); | ||
272 | offset = tex->image_offset[transfer->level][box->z]; | ||
273 | |||
274 | map = sws->bo_map(tex->bo, | ||
275 | BRW_DATA_OTHER, | ||
276 | 0, | ||
277 | tex->bo->size, | ||
278 | (usage & PIPE_TRANSFER_WRITE) ? TRUE : FALSE, | ||
279 | (usage & 0) ? TRUE : FALSE, | ||
280 | (usage & 0) ? TRUE : FALSE); | ||
281 | |||
282 | if (!map) | ||
283 | return NULL; | ||
284 | |||
285 | return map + offset + | ||
286 | box->y / util_format_get_blockheight(format) * transfer->stride + | ||
287 | box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); | ||
288 | } | ||
289 | |||
290 | static void | ||
291 | brw_texture_transfer_unmap(struct pipe_context *pipe, | ||
292 | struct pipe_transfer *transfer) | ||
293 | { | ||
294 | struct brw_texture *tex = brw_texture(transfer->resource); | ||
295 | struct brw_winsys_screen *sws = brw_screen(pipe->screen)->sws; | ||
296 | |||
297 | sws->bo_unmap(tex->bo); | ||
298 | } | ||
299 | |||
300 | |||
301 | |||
302 | |||
303 | |||
304 | struct u_resource_vtbl brw_texture_vtbl = | ||
305 | { | ||
306 | brw_texture_get_handle, /* get_handle */ | ||
307 | brw_texture_destroy, /* resource_destroy */ | ||
308 | brw_texture_get_transfer, /* get_transfer */ | ||
309 | u_default_transfer_destroy, /* transfer_destroy */ | ||
310 | brw_texture_transfer_map, /* transfer_map */ | ||
311 | u_default_transfer_flush_region, /* transfer_flush_region */ | ||
312 | brw_texture_transfer_unmap, /* transfer_unmap */ | ||
313 | u_default_transfer_inline_write /* transfer_inline_write */ | ||
314 | }; | ||
315 | |||
316 | |||
317 | |||
318 | |||
319 | |||
320 | struct pipe_resource * | ||
321 | brw_texture_create( struct pipe_screen *screen, | ||
322 | const struct pipe_resource *template ) | ||
323 | { | ||
324 | struct brw_screen *bscreen = brw_screen(screen); | ||
325 | struct brw_texture *tex; | ||
326 | enum brw_buffer_type buffer_type; | ||
327 | enum pipe_error ret; | ||
328 | GLuint format; | ||
329 | |||
330 | tex = CALLOC_STRUCT(brw_texture); | ||
331 | if (tex == NULL) | ||
332 | return NULL; | ||
333 | |||
334 | tex->b.b = *template; | ||
335 | tex->b.vtbl = &brw_texture_vtbl; | ||
336 | pipe_reference_init(&tex->b.b.reference, 1); | ||
337 | tex->b.b.screen = screen; | ||
338 | |||
339 | /* XXX: compressed textures need special treatment here | ||
340 | */ | ||
341 | tex->cpp = util_format_get_blocksize(tex->b.b.format); | ||
342 | tex->compressed = util_format_is_s3tc(tex->b.b.format); | ||
343 | |||
344 | make_empty_list(&tex->views[0]); | ||
345 | make_empty_list(&tex->views[1]); | ||
346 | |||
347 | /* XXX: No tiling with compressed textures?? | ||
348 | */ | ||
349 | if (tex->compressed == 0 && | ||
350 | !bscreen->no_tiling) | ||
351 | { | ||
352 | if (bscreen->gen < 5 && | ||
353 | util_format_is_depth_or_stencil(template->format)) | ||
354 | tex->tiling = BRW_TILING_Y; | ||
355 | else | ||
356 | tex->tiling = BRW_TILING_X; | ||
357 | } | ||
358 | else { | ||
359 | tex->tiling = BRW_TILING_NONE; | ||
360 | } | ||
361 | |||
362 | |||
363 | if (!brw_texture_layout( bscreen, tex )) | ||
364 | goto fail; | ||
365 | |||
366 | |||
367 | if (template->bind & (PIPE_BIND_SCANOUT | | ||
368 | PIPE_BIND_SHARED)) { | ||
369 | buffer_type = BRW_BUFFER_TYPE_SCANOUT; | ||
370 | } | ||
371 | else { | ||
372 | buffer_type = BRW_BUFFER_TYPE_TEXTURE; | ||
373 | } | ||
374 | |||
375 | ret = bscreen->sws->bo_alloc( bscreen->sws, | ||
376 | buffer_type, | ||
377 | tex->pitch * tex->total_height * tex->cpp, | ||
378 | 64, | ||
379 | &tex->bo ); | ||
380 | if (ret) | ||
381 | goto fail; | ||
382 | |||
383 | tex->ss.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; | ||
384 | tex->ss.ss0.surface_type = translate_tex_target(tex->b.b.target); | ||
385 | |||
386 | format = translate_tex_format(tex->b.b.format); | ||
387 | assert(format != BRW_SURFACEFORMAT_INVALID); | ||
388 | tex->ss.ss0.surface_format = format; | ||
389 | |||
390 | /* This is ok for all textures with channel width 8bit or less: | ||
391 | */ | ||
392 | /* tex->ss.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ | ||
393 | |||
394 | |||
395 | /* XXX: what happens when tex->bo->offset changes??? | ||
396 | */ | ||
397 | tex->ss.ss1.base_addr = 0; /* reloc */ | ||
398 | tex->ss.ss2.mip_count = tex->b.b.last_level; | ||
399 | tex->ss.ss2.width = tex->b.b.width0 - 1; | ||
400 | tex->ss.ss2.height = tex->b.b.height0 - 1; | ||
401 | |||
402 | switch (tex->tiling) { | ||
403 | case BRW_TILING_NONE: | ||
404 | tex->ss.ss3.tiled_surface = 0; | ||
405 | tex->ss.ss3.tile_walk = 0; | ||
406 | break; | ||
407 | case BRW_TILING_X: | ||
408 | tex->ss.ss3.tiled_surface = 1; | ||
409 | tex->ss.ss3.tile_walk = BRW_TILEWALK_XMAJOR; | ||
410 | break; | ||
411 | case BRW_TILING_Y: | ||
412 | tex->ss.ss3.tiled_surface = 1; | ||
413 | tex->ss.ss3.tile_walk = BRW_TILEWALK_YMAJOR; | ||
414 | break; | ||
415 | } | ||
416 | |||
417 | tex->ss.ss3.pitch = (tex->pitch * tex->cpp) - 1; | ||
418 | tex->ss.ss3.depth = tex->b.b.depth0 - 1; | ||
419 | |||
420 | tex->ss.ss4.min_lod = 0; | ||
421 | |||
422 | if (tex->b.b.target == PIPE_TEXTURE_CUBE) { | ||
423 | tex->ss.ss0.cube_pos_x = 1; | ||
424 | tex->ss.ss0.cube_pos_y = 1; | ||
425 | tex->ss.ss0.cube_pos_z = 1; | ||
426 | tex->ss.ss0.cube_neg_x = 1; | ||
427 | tex->ss.ss0.cube_neg_y = 1; | ||
428 | tex->ss.ss0.cube_neg_z = 1; | ||
429 | } | ||
430 | |||
431 | return &tex->b.b; | ||
432 | |||
433 | fail: | ||
434 | bo_reference(&tex->bo, NULL); | ||
435 | FREE(tex); | ||
436 | return NULL; | ||
437 | } | ||
438 | |||
439 | |||
440 | struct pipe_resource * | ||
441 | brw_texture_from_handle(struct pipe_screen *screen, | ||
442 | const struct pipe_resource *template, | ||
443 | struct winsys_handle *whandle) | ||
444 | { | ||
445 | struct brw_screen *bscreen = brw_screen(screen); | ||
446 | struct brw_texture *tex; | ||
447 | struct brw_winsys_buffer *buffer; | ||
448 | unsigned tiling; | ||
449 | unsigned pitch; | ||
450 | GLuint format; | ||
451 | |||
452 | if ((template->target != PIPE_TEXTURE_2D | ||
453 | && template->target != PIPE_TEXTURE_RECT) || | ||
454 | template->last_level != 0 || | ||
455 | template->depth0 != 1) | ||
456 | return NULL; | ||
457 | |||
458 | if (util_format_is_s3tc(template->format)) | ||
459 | return NULL; | ||
460 | |||
461 | tex = CALLOC_STRUCT(brw_texture); | ||
462 | if (!tex) | ||
463 | return NULL; | ||
464 | |||
465 | if (bscreen->sws->bo_from_handle(bscreen->sws, whandle, &pitch, &tiling, &buffer) != PIPE_OK) | ||
466 | goto fail; | ||
467 | |||
468 | tex->b.b = *template; | ||
469 | tex->b.vtbl = &brw_texture_vtbl; | ||
470 | pipe_reference_init(&tex->b.b.reference, 1); | ||
471 | tex->b.b.screen = screen; | ||
472 | |||
473 | /* XXX: cpp vs. blocksize | ||
474 | */ | ||
475 | tex->cpp = util_format_get_blocksize(tex->b.b.format); | ||
476 | tex->tiling = tiling; | ||
477 | |||
478 | make_empty_list(&tex->views[0]); | ||
479 | make_empty_list(&tex->views[1]); | ||
480 | |||
481 | if (!brw_texture_layout(bscreen, tex)) | ||
482 | goto fail; | ||
483 | |||
484 | /* XXX Maybe some more checks? */ | ||
485 | if ((pitch / tex->cpp) < tex->pitch) | ||
486 | goto fail; | ||
487 | |||
488 | tex->pitch = pitch / tex->cpp; | ||
489 | |||
490 | tex->bo = buffer; | ||
491 | |||
492 | /* fix this warning */ | ||
493 | #if 0 | ||
494 | if (tex->size > buffer->size) | ||
495 | goto fail; | ||
496 | #endif | ||
497 | |||
498 | tex->ss.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; | ||
499 | tex->ss.ss0.surface_type = translate_tex_target(tex->b.b.target); | ||
500 | |||
501 | format = translate_tex_format(tex->b.b.format); | ||
502 | assert(format != BRW_SURFACEFORMAT_INVALID); | ||
503 | tex->ss.ss0.surface_format = format; | ||
504 | |||
505 | /* This is ok for all textures with channel width 8bit or less: | ||
506 | */ | ||
507 | /* tex->ss.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ | ||
508 | |||
509 | |||
510 | /* XXX: what happens when tex->bo->offset changes??? | ||
511 | */ | ||
512 | tex->ss.ss1.base_addr = 0; /* reloc */ | ||
513 | tex->ss.ss2.mip_count = tex->b.b.last_level; | ||
514 | tex->ss.ss2.width = tex->b.b.width0 - 1; | ||
515 | tex->ss.ss2.height = tex->b.b.height0 - 1; | ||
516 | |||
517 | switch (tex->tiling) { | ||
518 | case BRW_TILING_NONE: | ||
519 | tex->ss.ss3.tiled_surface = 0; | ||
520 | tex->ss.ss3.tile_walk = 0; | ||
521 | break; | ||
522 | case BRW_TILING_X: | ||
523 | tex->ss.ss3.tiled_surface = 1; | ||
524 | tex->ss.ss3.tile_walk = BRW_TILEWALK_XMAJOR; | ||
525 | break; | ||
526 | case BRW_TILING_Y: | ||
527 | tex->ss.ss3.tiled_surface = 1; | ||
528 | tex->ss.ss3.tile_walk = BRW_TILEWALK_YMAJOR; | ||
529 | break; | ||
530 | } | ||
531 | |||
532 | tex->ss.ss3.pitch = (tex->pitch * tex->cpp) - 1; | ||
533 | tex->ss.ss3.depth = tex->b.b.depth0 - 1; | ||
534 | |||
535 | tex->ss.ss4.min_lod = 0; | ||
536 | |||
537 | return &tex->b.b; | ||
538 | |||
539 | fail: | ||
540 | FREE(tex); | ||
541 | return NULL; | ||
542 | } | ||
543 | |||
544 | |||
545 | #if 0 | ||
546 | boolean brw_is_format_supported( struct pipe_screen *screen, | ||
547 | enum pipe_format format, | ||
548 | enum pipe_texture_target target, | ||
549 | unsigned sample_count, | ||
550 | unsigned tex_usage, | ||
551 | unsigned geom_flags ) | ||
552 | { | ||
553 | return translate_tex_format(format) != BRW_SURFACEFORMAT_INVALID; | ||
554 | } | ||
555 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_resource_texture_layout.c b/src/gallium/drivers/i965/brw_resource_texture_layout.c deleted file mode 100644 index afecc77e312..00000000000 --- a/src/gallium/drivers/i965/brw_resource_texture_layout.c +++ /dev/null | |||
@@ -1,414 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | |||
28 | #include "pipe/p_format.h" | ||
29 | |||
30 | #include "util/u_math.h" | ||
31 | #include "util/u_memory.h" | ||
32 | |||
33 | #include "brw_resource.h" | ||
34 | #include "brw_debug.h" | ||
35 | #include "brw_winsys.h" | ||
36 | |||
37 | /* Code to layout images in a mipmap tree for i965. | ||
38 | */ | ||
39 | |||
40 | static int | ||
41 | brw_tex_pitch_align (struct brw_texture *tex, | ||
42 | int pitch) | ||
43 | { | ||
44 | if (!tex->compressed) { | ||
45 | int pitch_align; | ||
46 | |||
47 | switch (tex->tiling) { | ||
48 | case BRW_TILING_X: | ||
49 | pitch_align = 512; | ||
50 | break; | ||
51 | case BRW_TILING_Y: | ||
52 | pitch_align = 128; | ||
53 | break; | ||
54 | default: | ||
55 | /* XXX: Untiled pitch alignment of 64 bytes for now to allow | ||
56 | * render-to-texture to work in all cases. This should | ||
57 | * probably be replaced at some point by some scheme to only | ||
58 | * do this when really necessary, for example standalone | ||
59 | * render target views. | ||
60 | */ | ||
61 | pitch_align = 64; | ||
62 | break; | ||
63 | } | ||
64 | |||
65 | pitch = align(pitch * tex->cpp, pitch_align); | ||
66 | pitch /= tex->cpp; | ||
67 | } | ||
68 | |||
69 | return pitch; | ||
70 | } | ||
71 | |||
72 | |||
73 | static void | ||
74 | brw_tex_alignment_unit(enum pipe_format pf, | ||
75 | GLuint *w, GLuint *h) | ||
76 | { | ||
77 | switch (pf) { | ||
78 | case PIPE_FORMAT_DXT1_RGB: | ||
79 | case PIPE_FORMAT_DXT1_RGBA: | ||
80 | case PIPE_FORMAT_DXT3_RGBA: | ||
81 | case PIPE_FORMAT_DXT5_RGBA: | ||
82 | case PIPE_FORMAT_DXT1_SRGB: | ||
83 | case PIPE_FORMAT_DXT1_SRGBA: | ||
84 | case PIPE_FORMAT_DXT3_SRGBA: | ||
85 | case PIPE_FORMAT_DXT5_SRGBA: | ||
86 | *w = 4; | ||
87 | *h = 4; | ||
88 | break; | ||
89 | |||
90 | default: | ||
91 | *w = 4; | ||
92 | *h = 2; | ||
93 | break; | ||
94 | } | ||
95 | } | ||
96 | |||
97 | |||
98 | static void | ||
99 | brw_tex_set_level_info(struct brw_texture *tex, | ||
100 | GLuint level, | ||
101 | GLuint nr_images, | ||
102 | GLuint x, GLuint y, | ||
103 | GLuint w, GLuint h, GLuint d) | ||
104 | { | ||
105 | |||
106 | if (BRW_DEBUG & DEBUG_TEXTURE) | ||
107 | debug_printf("%s level %d size: %d,%d,%d offset %d,%d (0x%x)\n", __FUNCTION__, | ||
108 | level, w, h, d, x, y, tex->level_offset[level]); | ||
109 | |||
110 | assert(tex->image_offset[level] == NULL); | ||
111 | assert(nr_images >= 1); | ||
112 | |||
113 | tex->level_offset[level] = (x + y * tex->pitch) * tex->cpp; | ||
114 | tex->nr_images[level] = nr_images; | ||
115 | |||
116 | tex->image_offset[level] = MALLOC(nr_images * sizeof(GLuint)); | ||
117 | tex->image_offset[level][0] = 0; | ||
118 | } | ||
119 | |||
120 | |||
121 | static void | ||
122 | brw_tex_set_image_offset(struct brw_texture *tex, | ||
123 | GLuint level, GLuint img, | ||
124 | GLuint x, GLuint y, | ||
125 | GLuint offset) | ||
126 | { | ||
127 | assert((x == 0 && y == 0) || img != 0 || level != 0); | ||
128 | assert(img < tex->nr_images[level]); | ||
129 | |||
130 | if (BRW_DEBUG & DEBUG_TEXTURE) | ||
131 | debug_printf("%s level %d img %d pos %d,%d image_offset %x\n", | ||
132 | __FUNCTION__, level, img, x, y, | ||
133 | tex->image_offset[level][img]); | ||
134 | |||
135 | tex->image_offset[level][img] = (x + y * tex->pitch) * tex->cpp + offset; | ||
136 | } | ||
137 | |||
138 | |||
139 | |||
140 | static void brw_layout_2d( struct brw_texture *tex ) | ||
141 | { | ||
142 | GLuint align_h = 2, align_w = 4; | ||
143 | GLuint level; | ||
144 | GLuint x = 0; | ||
145 | GLuint y = 0; | ||
146 | GLuint width = tex->b.b.width0; | ||
147 | GLuint height = tex->b.b.height0; | ||
148 | |||
149 | tex->pitch = tex->b.b.width0; | ||
150 | brw_tex_alignment_unit(tex->b.b.format, &align_w, &align_h); | ||
151 | |||
152 | if (tex->compressed) { | ||
153 | tex->pitch = align(tex->b.b.width0, align_w); | ||
154 | } | ||
155 | |||
156 | /* May need to adjust pitch to accomodate the placement of | ||
157 | * the 2nd mipmap. This occurs when the alignment | ||
158 | * constraints of mipmap placement push the right edge of the | ||
159 | * 2nd mipmap out past the width of its parent. | ||
160 | */ | ||
161 | if (tex->b.b.last_level > 0) { | ||
162 | GLuint mip1_width; | ||
163 | |||
164 | if (tex->compressed) { | ||
165 | mip1_width = (align(u_minify(tex->b.b.width0, 1), align_w) + | ||
166 | align(u_minify(tex->b.b.width0, 2), align_w)); | ||
167 | } else { | ||
168 | mip1_width = (align(u_minify(tex->b.b.width0, 1), align_w) + | ||
169 | u_minify(tex->b.b.width0, 2)); | ||
170 | } | ||
171 | |||
172 | if (mip1_width > tex->pitch) { | ||
173 | tex->pitch = mip1_width; | ||
174 | } | ||
175 | } | ||
176 | |||
177 | /* Pitch must be a whole number of dwords, even though we | ||
178 | * express it in texels. | ||
179 | */ | ||
180 | tex->pitch = brw_tex_pitch_align (tex, tex->pitch); | ||
181 | tex->total_height = 0; | ||
182 | |||
183 | for ( level = 0 ; level <= tex->b.b.last_level ; level++ ) { | ||
184 | GLuint img_height; | ||
185 | |||
186 | brw_tex_set_level_info(tex, level, 1, x, y, width, height, 1); | ||
187 | |||
188 | if (tex->compressed) | ||
189 | img_height = MAX2(1, height/4); | ||
190 | else | ||
191 | img_height = align(height, align_h); | ||
192 | |||
193 | |||
194 | /* Because the images are packed better, the final offset | ||
195 | * might not be the maximal one: | ||
196 | */ | ||
197 | tex->total_height = MAX2(tex->total_height, y + img_height); | ||
198 | |||
199 | /* Layout_below: step right after second mipmap. | ||
200 | */ | ||
201 | if (level == 1) { | ||
202 | x += align(width, align_w); | ||
203 | } | ||
204 | else { | ||
205 | y += img_height; | ||
206 | } | ||
207 | |||
208 | width = u_minify(width, 1); | ||
209 | height = u_minify(height, 1); | ||
210 | } | ||
211 | } | ||
212 | |||
213 | |||
214 | static boolean | ||
215 | brw_layout_cubemap_idgng( struct brw_texture *tex ) | ||
216 | { | ||
217 | GLuint align_h = 2, align_w = 4; | ||
218 | GLuint level; | ||
219 | GLuint x = 0; | ||
220 | GLuint y = 0; | ||
221 | GLuint width = tex->b.b.width0; | ||
222 | GLuint height = tex->b.b.height0; | ||
223 | GLuint qpitch = 0; | ||
224 | GLuint y_pitch = 0; | ||
225 | |||
226 | tex->pitch = tex->b.b.width0; | ||
227 | brw_tex_alignment_unit(tex->b.b.format, &align_w, &align_h); | ||
228 | y_pitch = align(height, align_h); | ||
229 | |||
230 | if (tex->compressed) { | ||
231 | tex->pitch = align(tex->b.b.width0, align_w); | ||
232 | } | ||
233 | |||
234 | if (tex->b.b.last_level != 0) { | ||
235 | GLuint mip1_width; | ||
236 | |||
237 | if (tex->compressed) { | ||
238 | mip1_width = (align(u_minify(tex->b.b.width0, 1), align_w) + | ||
239 | align(u_minify(tex->b.b.width0, 2), align_w)); | ||
240 | } else { | ||
241 | mip1_width = (align(u_minify(tex->b.b.width0, 1), align_w) + | ||
242 | u_minify(tex->b.b.width0, 2)); | ||
243 | } | ||
244 | |||
245 | if (mip1_width > tex->pitch) { | ||
246 | tex->pitch = mip1_width; | ||
247 | } | ||
248 | } | ||
249 | |||
250 | tex->pitch = brw_tex_pitch_align(tex, tex->pitch); | ||
251 | |||
252 | if (tex->compressed) { | ||
253 | qpitch = ((y_pitch + | ||
254 | align(u_minify(y_pitch, 1), align_h) + | ||
255 | 11 * align_h) / 4) * tex->pitch * tex->cpp; | ||
256 | |||
257 | tex->total_height = ((y_pitch + | ||
258 | align(u_minify(y_pitch, 1), align_h) + | ||
259 | 11 * align_h) / 4) * 6; | ||
260 | } else { | ||
261 | qpitch = (y_pitch + | ||
262 | align(u_minify(y_pitch, 1), align_h) + | ||
263 | 11 * align_h) * tex->pitch * tex->cpp; | ||
264 | |||
265 | tex->total_height = (y_pitch + | ||
266 | align(u_minify(y_pitch, 1), align_h) + | ||
267 | 11 * align_h) * 6; | ||
268 | } | ||
269 | |||
270 | for (level = 0; level <= tex->b.b.last_level; level++) { | ||
271 | GLuint img_height; | ||
272 | GLuint nr_images = 6; | ||
273 | GLuint q = 0; | ||
274 | |||
275 | brw_tex_set_level_info(tex, level, nr_images, x, y, width, height, 1); | ||
276 | |||
277 | for (q = 0; q < nr_images; q++) | ||
278 | brw_tex_set_image_offset(tex, level, q, x, y, q * qpitch); | ||
279 | |||
280 | if (tex->compressed) | ||
281 | img_height = MAX2(1, height/4); | ||
282 | else | ||
283 | img_height = align(height, align_h); | ||
284 | |||
285 | if (level == 1) { | ||
286 | x += align(width, align_w); | ||
287 | } | ||
288 | else { | ||
289 | y += img_height; | ||
290 | } | ||
291 | |||
292 | width = u_minify(width, 1); | ||
293 | height = u_minify(height, 1); | ||
294 | } | ||
295 | |||
296 | return TRUE; | ||
297 | } | ||
298 | |||
299 | |||
300 | static boolean | ||
301 | brw_layout_3d_cube( struct brw_texture *tex ) | ||
302 | { | ||
303 | GLuint width = tex->b.b.width0; | ||
304 | GLuint height = tex->b.b.height0; | ||
305 | GLuint depth = tex->b.b.depth0; | ||
306 | GLuint pack_x_pitch, pack_x_nr; | ||
307 | GLuint pack_y_pitch; | ||
308 | GLuint level; | ||
309 | GLuint align_h = 2; | ||
310 | GLuint align_w = 4; | ||
311 | |||
312 | tex->total_height = 0; | ||
313 | brw_tex_alignment_unit(tex->b.b.format, &align_w, &align_h); | ||
314 | |||
315 | if (tex->compressed) { | ||
316 | tex->pitch = align(width, align_w); | ||
317 | pack_y_pitch = (height + 3) / 4; | ||
318 | } else { | ||
319 | tex->pitch = brw_tex_pitch_align(tex, tex->b.b.width0); | ||
320 | pack_y_pitch = align(tex->b.b.height0, align_h); | ||
321 | } | ||
322 | |||
323 | pack_x_pitch = width; | ||
324 | pack_x_nr = 1; | ||
325 | |||
326 | for (level = 0 ; level <= tex->b.b.last_level ; level++) { | ||
327 | GLuint nr_images = tex->b.b.target == PIPE_TEXTURE_3D ? depth : 6; | ||
328 | GLint x = 0; | ||
329 | GLint y = 0; | ||
330 | GLint q, j; | ||
331 | |||
332 | brw_tex_set_level_info(tex, level, nr_images, | ||
333 | 0, tex->total_height, | ||
334 | width, height, depth); | ||
335 | |||
336 | for (q = 0; q < nr_images;) { | ||
337 | for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) { | ||
338 | brw_tex_set_image_offset(tex, level, q, x, y, 0); | ||
339 | x += pack_x_pitch; | ||
340 | } | ||
341 | |||
342 | x = 0; | ||
343 | y += pack_y_pitch; | ||
344 | } | ||
345 | |||
346 | |||
347 | tex->total_height += y; | ||
348 | width = u_minify(width, 1); | ||
349 | height = u_minify(height, 1); | ||
350 | depth = u_minify(depth, 1); | ||
351 | |||
352 | if (tex->compressed) { | ||
353 | pack_y_pitch = (height + 3) / 4; | ||
354 | |||
355 | if (pack_x_pitch > align(width, align_w)) { | ||
356 | pack_x_pitch = align(width, align_w); | ||
357 | pack_x_nr <<= 1; | ||
358 | } | ||
359 | } else { | ||
360 | if (pack_x_pitch > 4) { | ||
361 | pack_x_pitch >>= 1; | ||
362 | pack_x_nr <<= 1; | ||
363 | assert(pack_x_pitch * pack_x_nr <= tex->pitch); | ||
364 | } | ||
365 | |||
366 | if (pack_y_pitch > 2) { | ||
367 | pack_y_pitch >>= 1; | ||
368 | pack_y_pitch = align(pack_y_pitch, align_h); | ||
369 | } | ||
370 | } | ||
371 | } | ||
372 | |||
373 | /* The 965's sampler lays cachelines out according to how accesses | ||
374 | * in the texture surfaces run, so they may be "vertical" through | ||
375 | * memory. As a result, the docs say in Surface Padding Requirements: | ||
376 | * Sampling Engine Surfaces that two extra rows of padding are required. | ||
377 | */ | ||
378 | if (tex->b.b.target == PIPE_TEXTURE_CUBE) | ||
379 | tex->total_height += 2; | ||
380 | |||
381 | return TRUE; | ||
382 | } | ||
383 | |||
384 | |||
385 | |||
386 | GLboolean brw_texture_layout(struct brw_screen *brw_screen, | ||
387 | struct brw_texture *tex ) | ||
388 | { | ||
389 | switch (tex->b.b.target) { | ||
390 | case PIPE_TEXTURE_CUBE: | ||
391 | if (brw_screen->gen == 5) | ||
392 | brw_layout_cubemap_idgng( tex ); | ||
393 | else | ||
394 | brw_layout_3d_cube( tex ); | ||
395 | break; | ||
396 | |||
397 | case PIPE_TEXTURE_3D: | ||
398 | brw_layout_3d_cube( tex ); | ||
399 | break; | ||
400 | |||
401 | default: | ||
402 | brw_layout_2d( tex ); | ||
403 | break; | ||
404 | } | ||
405 | |||
406 | if (BRW_DEBUG & DEBUG_TEXTURE) | ||
407 | debug_printf("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__, | ||
408 | tex->pitch, | ||
409 | tex->total_height, | ||
410 | tex->cpp, | ||
411 | tex->pitch * tex->total_height * tex->cpp ); | ||
412 | |||
413 | return GL_TRUE; | ||
414 | } | ||
diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c deleted file mode 100644 index b382e703a0c..00000000000 --- a/src/gallium/drivers/i965/brw_screen.c +++ /dev/null | |||
@@ -1,460 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | |||
29 | #include "util/u_format.h" | ||
30 | #include "util/u_inlines.h" | ||
31 | #include "util/u_memory.h" | ||
32 | #include "util/u_string.h" | ||
33 | |||
34 | #include "brw_reg.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_screen.h" | ||
37 | #include "brw_winsys.h" | ||
38 | #include "brw_public.h" | ||
39 | #include "brw_debug.h" | ||
40 | #include "brw_resource.h" | ||
41 | |||
42 | #ifdef DEBUG | ||
43 | static const struct debug_named_value debug_names[] = { | ||
44 | { "tex", DEBUG_TEXTURE, NULL }, | ||
45 | { "state", DEBUG_STATE, NULL }, | ||
46 | { "ioctl", DEBUG_IOCTL, NULL }, | ||
47 | { "blit", DEBUG_BLIT, NULL }, | ||
48 | { "curbe", DEBUG_CURBE, NULL }, | ||
49 | { "fall", DEBUG_FALLBACKS, NULL }, | ||
50 | { "verb", DEBUG_VERBOSE, NULL }, | ||
51 | { "bat", DEBUG_BATCH, NULL }, | ||
52 | { "pix", DEBUG_PIXEL, NULL }, | ||
53 | { "wins", DEBUG_WINSYS, NULL }, | ||
54 | { "min", DEBUG_MIN_URB, NULL }, | ||
55 | { "dis", DEBUG_DISASSEM, NULL }, | ||
56 | { "sync", DEBUG_SYNC, NULL }, | ||
57 | { "prim", DEBUG_PRIMS, NULL }, | ||
58 | { "vert", DEBUG_VERTS, NULL }, | ||
59 | { "dma", DEBUG_DMA, NULL }, | ||
60 | { "san", DEBUG_SANITY, NULL }, | ||
61 | { "sleep", DEBUG_SLEEP, NULL }, | ||
62 | { "stats", DEBUG_STATS, NULL }, | ||
63 | { "sing", DEBUG_SINGLE_THREAD, NULL }, | ||
64 | { "thre", DEBUG_SINGLE_THREAD, NULL }, | ||
65 | { "wm", DEBUG_WM, NULL }, | ||
66 | { "urb", DEBUG_URB, NULL }, | ||
67 | { "vs", DEBUG_VS, NULL }, | ||
68 | DEBUG_NAMED_VALUE_END | ||
69 | }; | ||
70 | |||
71 | static const struct debug_named_value dump_names[] = { | ||
72 | { "asm", DUMP_ASM, NULL }, | ||
73 | { "state", DUMP_STATE, NULL }, | ||
74 | { "batch", DUMP_BATCH, NULL }, | ||
75 | DEBUG_NAMED_VALUE_END | ||
76 | }; | ||
77 | |||
78 | int BRW_DEBUG = 0; | ||
79 | int BRW_DUMP = 0; | ||
80 | |||
81 | #endif | ||
82 | |||
83 | |||
84 | /* | ||
85 | * Probe functions | ||
86 | */ | ||
87 | |||
88 | |||
89 | static const char * | ||
90 | brw_get_vendor(struct pipe_screen *screen) | ||
91 | { | ||
92 | return "VMware, Inc."; | ||
93 | } | ||
94 | |||
95 | static const char * | ||
96 | brw_get_name(struct pipe_screen *screen) | ||
97 | { | ||
98 | static char buffer[128]; | ||
99 | const char *chipset; | ||
100 | |||
101 | switch (brw_screen(screen)->pci_id) { | ||
102 | case PCI_CHIP_I965_G: | ||
103 | chipset = "I965_G"; | ||
104 | break; | ||
105 | case PCI_CHIP_I965_Q: | ||
106 | chipset = "I965_Q"; | ||
107 | break; | ||
108 | case PCI_CHIP_I965_G_1: | ||
109 | chipset = "I965_G_1"; | ||
110 | break; | ||
111 | case PCI_CHIP_I946_GZ: | ||
112 | chipset = "I946_GZ"; | ||
113 | break; | ||
114 | case PCI_CHIP_I965_GM: | ||
115 | chipset = "I965_GM"; | ||
116 | break; | ||
117 | case PCI_CHIP_I965_GME: | ||
118 | chipset = "I965_GME"; | ||
119 | break; | ||
120 | case PCI_CHIP_GM45_GM: | ||
121 | chipset = "GM45_GM"; | ||
122 | break; | ||
123 | case PCI_CHIP_IGD_E_G: | ||
124 | chipset = "IGD_E_G"; | ||
125 | break; | ||
126 | case PCI_CHIP_Q45_G: | ||
127 | chipset = "Q45_G"; | ||
128 | break; | ||
129 | case PCI_CHIP_G45_G: | ||
130 | chipset = "G45_G"; | ||
131 | break; | ||
132 | case PCI_CHIP_G41_G: | ||
133 | chipset = "G41_G"; | ||
134 | break; | ||
135 | case PCI_CHIP_B43_G: | ||
136 | chipset = "B43_G"; | ||
137 | break; | ||
138 | case PCI_CHIP_ILD_G: | ||
139 | chipset = "ILD_G"; | ||
140 | break; | ||
141 | case PCI_CHIP_ILM_G: | ||
142 | chipset = "ILM_G"; | ||
143 | break; | ||
144 | default: | ||
145 | chipset = "unknown"; | ||
146 | break; | ||
147 | } | ||
148 | |||
149 | util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset); | ||
150 | return buffer; | ||
151 | } | ||
152 | |||
153 | static int | ||
154 | brw_get_param(struct pipe_screen *screen, enum pipe_cap param) | ||
155 | { | ||
156 | switch (param) { | ||
157 | case PIPE_CAP_MAX_COMBINED_SAMPLERS: | ||
158 | return 16; /* XXX correct? */ | ||
159 | case PIPE_CAP_NPOT_TEXTURES: | ||
160 | return 1; | ||
161 | case PIPE_CAP_TWO_SIDED_STENCIL: | ||
162 | return 1; | ||
163 | case PIPE_CAP_ANISOTROPIC_FILTER: | ||
164 | return 0; | ||
165 | case PIPE_CAP_POINT_SPRITE: | ||
166 | return 0; | ||
167 | case PIPE_CAP_MAX_RENDER_TARGETS: | ||
168 | return 1; | ||
169 | case PIPE_CAP_OCCLUSION_QUERY: | ||
170 | return 0; | ||
171 | case PIPE_CAP_TIMER_QUERY: | ||
172 | return 0; | ||
173 | case PIPE_CAP_TEXTURE_SHADOW_MAP: | ||
174 | return 1; | ||
175 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: | ||
176 | return BRW_MAX_TEXTURE_2D_LEVELS; | ||
177 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: | ||
178 | return BRW_MAX_TEXTURE_3D_LEVELS; | ||
179 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: | ||
180 | return BRW_MAX_TEXTURE_2D_LEVELS; | ||
181 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: | ||
182 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: | ||
183 | return 1; | ||
184 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: | ||
185 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: | ||
186 | return 0; | ||
187 | case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: | ||
188 | /* disable for now */ | ||
189 | return 0; | ||
190 | default: | ||
191 | return 0; | ||
192 | } | ||
193 | } | ||
194 | |||
195 | static int | ||
196 | brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param) | ||
197 | { | ||
198 | switch(shader) { | ||
199 | case PIPE_SHADER_VERTEX: | ||
200 | case PIPE_SHADER_FRAGMENT: | ||
201 | case PIPE_SHADER_GEOMETRY: | ||
202 | break; | ||
203 | default: | ||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | /* XXX: these are just shader model 4.0 values, fix this! */ | ||
208 | switch(param) { | ||
209 | case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: | ||
210 | return 65536; | ||
211 | case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: | ||
212 | return 65536; | ||
213 | case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: | ||
214 | return 65536; | ||
215 | case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: | ||
216 | return 65536; | ||
217 | case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: | ||
218 | return 65536; | ||
219 | case PIPE_SHADER_CAP_MAX_INPUTS: | ||
220 | return 32; | ||
221 | case PIPE_SHADER_CAP_MAX_CONSTS: | ||
222 | return 4096; | ||
223 | case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: | ||
224 | return PIPE_MAX_CONSTANT_BUFFERS; | ||
225 | case PIPE_SHADER_CAP_MAX_TEMPS: | ||
226 | return 4096; | ||
227 | case PIPE_SHADER_CAP_MAX_ADDRS: | ||
228 | return 0; | ||
229 | case PIPE_SHADER_CAP_MAX_PREDS: | ||
230 | return 0; | ||
231 | case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: | ||
232 | return 1; | ||
233 | case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: | ||
234 | case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: | ||
235 | case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: | ||
236 | case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: | ||
237 | return 1; | ||
238 | case PIPE_SHADER_CAP_SUBROUTINES: | ||
239 | return 1; | ||
240 | case PIPE_SHADER_CAP_INTEGERS: | ||
241 | return 0; | ||
242 | case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: | ||
243 | return 8; | ||
244 | default: | ||
245 | assert(0); | ||
246 | return 0; | ||
247 | } | ||
248 | } | ||
249 | |||
250 | static float | ||
251 | brw_get_paramf(struct pipe_screen *screen, enum pipe_capf param) | ||
252 | { | ||
253 | switch (param) { | ||
254 | case PIPE_CAPF_MAX_LINE_WIDTH: | ||
255 | /* fall-through */ | ||
256 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: | ||
257 | return 7.5; | ||
258 | |||
259 | case PIPE_CAPF_MAX_POINT_WIDTH: | ||
260 | /* fall-through */ | ||
261 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: | ||
262 | return 255.0; | ||
263 | |||
264 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: | ||
265 | return 4.0; | ||
266 | |||
267 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: | ||
268 | return 16.0; | ||
269 | |||
270 | default: | ||
271 | return 0; | ||
272 | } | ||
273 | } | ||
274 | |||
275 | static boolean | ||
276 | brw_is_format_supported(struct pipe_screen *screen, | ||
277 | enum pipe_format format, | ||
278 | enum pipe_texture_target target, | ||
279 | unsigned sample_count, | ||
280 | unsigned tex_usage) | ||
281 | { | ||
282 | static const enum pipe_format tex_supported[] = { | ||
283 | PIPE_FORMAT_L8_UNORM, | ||
284 | PIPE_FORMAT_I8_UNORM, | ||
285 | PIPE_FORMAT_A8_UNORM, | ||
286 | PIPE_FORMAT_L16_UNORM, | ||
287 | /*PIPE_FORMAT_I16_UNORM,*/ | ||
288 | /*PIPE_FORMAT_A16_UNORM,*/ | ||
289 | PIPE_FORMAT_L8A8_UNORM, | ||
290 | PIPE_FORMAT_B5G6R5_UNORM, | ||
291 | PIPE_FORMAT_B5G5R5A1_UNORM, | ||
292 | PIPE_FORMAT_B4G4R4A4_UNORM, | ||
293 | PIPE_FORMAT_B8G8R8X8_UNORM, | ||
294 | PIPE_FORMAT_B8G8R8A8_UNORM, | ||
295 | /* video */ | ||
296 | PIPE_FORMAT_UYVY, | ||
297 | PIPE_FORMAT_YUYV, | ||
298 | /* compressed */ | ||
299 | /*PIPE_FORMAT_FXT1_RGBA,*/ | ||
300 | PIPE_FORMAT_DXT1_RGB, | ||
301 | PIPE_FORMAT_DXT1_RGBA, | ||
302 | PIPE_FORMAT_DXT3_RGBA, | ||
303 | PIPE_FORMAT_DXT5_RGBA, | ||
304 | /* sRGB */ | ||
305 | PIPE_FORMAT_A8B8G8R8_SRGB, | ||
306 | PIPE_FORMAT_L8A8_SRGB, | ||
307 | PIPE_FORMAT_L8_SRGB, | ||
308 | PIPE_FORMAT_DXT1_SRGB, | ||
309 | /* depth */ | ||
310 | PIPE_FORMAT_Z32_FLOAT, | ||
311 | PIPE_FORMAT_Z24X8_UNORM, | ||
312 | PIPE_FORMAT_Z24_UNORM_S8_UINT, | ||
313 | PIPE_FORMAT_Z16_UNORM, | ||
314 | /* signed */ | ||
315 | PIPE_FORMAT_R8G8_SNORM, | ||
316 | PIPE_FORMAT_R8G8B8A8_SNORM, | ||
317 | PIPE_FORMAT_NONE /* list terminator */ | ||
318 | }; | ||
319 | static const enum pipe_format render_supported[] = { | ||
320 | PIPE_FORMAT_B8G8R8X8_UNORM, | ||
321 | PIPE_FORMAT_B8G8R8A8_UNORM, | ||
322 | PIPE_FORMAT_B5G6R5_UNORM, | ||
323 | PIPE_FORMAT_NONE /* list terminator */ | ||
324 | }; | ||
325 | static const enum pipe_format depth_supported[] = { | ||
326 | PIPE_FORMAT_Z32_FLOAT, | ||
327 | PIPE_FORMAT_Z24X8_UNORM, | ||
328 | PIPE_FORMAT_Z24_UNORM_S8_UINT, | ||
329 | PIPE_FORMAT_Z16_UNORM, | ||
330 | PIPE_FORMAT_NONE /* list terminator */ | ||
331 | }; | ||
332 | const enum pipe_format *list; | ||
333 | uint i; | ||
334 | |||
335 | if (!util_format_is_supported(format, tex_usage)) | ||
336 | return FALSE; | ||
337 | |||
338 | if (sample_count > 1) | ||
339 | return FALSE; | ||
340 | |||
341 | if (tex_usage & PIPE_BIND_DEPTH_STENCIL) | ||
342 | list = depth_supported; | ||
343 | else if (tex_usage & PIPE_BIND_RENDER_TARGET) | ||
344 | list = render_supported; | ||
345 | else | ||
346 | list = tex_supported; | ||
347 | |||
348 | for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) { | ||
349 | if (list[i] == format) | ||
350 | return TRUE; | ||
351 | } | ||
352 | |||
353 | return FALSE; | ||
354 | } | ||
355 | |||
356 | |||
357 | /* | ||
358 | * Fence functions | ||
359 | */ | ||
360 | |||
361 | |||
362 | static void | ||
363 | brw_fence_reference(struct pipe_screen *screen, | ||
364 | struct pipe_fence_handle **ptr, | ||
365 | struct pipe_fence_handle *fence) | ||
366 | { | ||
367 | } | ||
368 | |||
369 | static boolean | ||
370 | brw_fence_signalled(struct pipe_screen *screen, | ||
371 | struct pipe_fence_handle *fence) | ||
372 | { | ||
373 | return TRUE; | ||
374 | } | ||
375 | |||
376 | static boolean | ||
377 | brw_fence_finish(struct pipe_screen *screen, | ||
378 | struct pipe_fence_handle *fence, | ||
379 | uint64_t timeout) | ||
380 | { | ||
381 | return TRUE; | ||
382 | } | ||
383 | |||
384 | |||
385 | /* | ||
386 | * Generic functions | ||
387 | */ | ||
388 | |||
389 | |||
390 | static void | ||
391 | brw_destroy_screen(struct pipe_screen *screen) | ||
392 | { | ||
393 | struct brw_screen *bscreen = brw_screen(screen); | ||
394 | |||
395 | if (bscreen->sws) | ||
396 | bscreen->sws->destroy(bscreen->sws); | ||
397 | |||
398 | FREE(bscreen); | ||
399 | } | ||
400 | |||
401 | /** | ||
402 | * Create a new brw_screen object | ||
403 | */ | ||
404 | struct pipe_screen * | ||
405 | brw_screen_create(struct brw_winsys_screen *sws) | ||
406 | { | ||
407 | struct brw_screen *bscreen; | ||
408 | #ifdef DEBUG | ||
409 | BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0); | ||
410 | BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0); | ||
411 | BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM; | ||
412 | |||
413 | BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0); | ||
414 | #endif | ||
415 | |||
416 | bscreen = CALLOC_STRUCT(brw_screen); | ||
417 | if (!bscreen) | ||
418 | return NULL; | ||
419 | |||
420 | bscreen->pci_id = sws->pci_id; | ||
421 | if (IS_GEN6(sws->pci_id)) { | ||
422 | bscreen->gen = 6; | ||
423 | bscreen->needs_ff_sync = TRUE; | ||
424 | } else if (IS_GEN5(sws->pci_id)) { | ||
425 | bscreen->gen = 5; | ||
426 | bscreen->needs_ff_sync = TRUE; | ||
427 | } else if (IS_965(sws->pci_id)) { | ||
428 | bscreen->gen = 4; | ||
429 | if (IS_G4X(sws->pci_id)) { | ||
430 | bscreen->is_g4x = true; | ||
431 | } | ||
432 | } else { | ||
433 | debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", | ||
434 | __FUNCTION__, sws->pci_id); | ||
435 | free(bscreen); | ||
436 | return NULL; | ||
437 | } | ||
438 | |||
439 | sws->gen = bscreen->gen; | ||
440 | bscreen->sws = sws; | ||
441 | bscreen->base.winsys = NULL; | ||
442 | bscreen->base.destroy = brw_destroy_screen; | ||
443 | bscreen->base.get_name = brw_get_name; | ||
444 | bscreen->base.get_vendor = brw_get_vendor; | ||
445 | bscreen->base.get_param = brw_get_param; | ||
446 | bscreen->base.get_shader_param = brw_get_shader_param; | ||
447 | bscreen->base.get_paramf = brw_get_paramf; | ||
448 | bscreen->base.is_format_supported = brw_is_format_supported; | ||
449 | bscreen->base.context_create = brw_create_context; | ||
450 | bscreen->base.fence_reference = brw_fence_reference; | ||
451 | bscreen->base.fence_signalled = brw_fence_signalled; | ||
452 | bscreen->base.fence_finish = brw_fence_finish; | ||
453 | |||
454 | brw_init_screen_resource_functions(bscreen); | ||
455 | |||
456 | bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL; | ||
457 | |||
458 | |||
459 | return &bscreen->base; | ||
460 | } | ||
diff --git a/src/gallium/drivers/i965/brw_screen.h b/src/gallium/drivers/i965/brw_screen.h deleted file mode 100644 index a62e1afc405..00000000000 --- a/src/gallium/drivers/i965/brw_screen.h +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | #ifndef BRW_SCREEN_H | ||
29 | #define BRW_SCREEN_H | ||
30 | |||
31 | #include "pipe/p_state.h" | ||
32 | #include "pipe/p_screen.h" | ||
33 | |||
34 | #include "brw_reg.h" | ||
35 | #include "brw_structs.h" | ||
36 | |||
37 | struct brw_winsys_screen; | ||
38 | |||
39 | |||
40 | /** | ||
41 | * Subclass of pipe_screen | ||
42 | */ | ||
43 | struct brw_screen | ||
44 | { | ||
45 | struct pipe_screen base; | ||
46 | int gen; | ||
47 | boolean has_negative_rhw_bug; | ||
48 | boolean needs_ff_sync; | ||
49 | boolean is_g4x; | ||
50 | int pci_id; | ||
51 | struct brw_winsys_screen *sws; | ||
52 | boolean no_tiling; | ||
53 | }; | ||
54 | |||
55 | |||
56 | |||
57 | union brw_surface_id { | ||
58 | struct { | ||
59 | unsigned level:16; | ||
60 | unsigned layer:16; | ||
61 | } bits; | ||
62 | unsigned value; | ||
63 | }; | ||
64 | |||
65 | |||
66 | struct brw_surface | ||
67 | { | ||
68 | struct pipe_surface base; | ||
69 | |||
70 | union brw_surface_id id; | ||
71 | unsigned offset; | ||
72 | unsigned cpp; | ||
73 | unsigned pitch; | ||
74 | unsigned draw_offset; | ||
75 | unsigned tiling; | ||
76 | |||
77 | struct brw_surface_state ss; | ||
78 | struct brw_winsys_buffer *bo; | ||
79 | struct brw_surface *next, *prev; | ||
80 | }; | ||
81 | |||
82 | |||
83 | |||
84 | /* | ||
85 | * Cast wrappers | ||
86 | */ | ||
87 | static INLINE struct brw_screen * | ||
88 | brw_screen(struct pipe_screen *pscreen) | ||
89 | { | ||
90 | return (struct brw_screen *) pscreen; | ||
91 | } | ||
92 | |||
93 | |||
94 | static INLINE struct brw_surface * | ||
95 | brw_surface(struct pipe_surface *surface) | ||
96 | { | ||
97 | return (struct brw_surface *)surface; | ||
98 | } | ||
99 | |||
100 | unsigned | ||
101 | brw_surface_pitch( const struct pipe_surface *surface ); | ||
102 | |||
103 | |||
104 | #endif /* BRW_SCREEN_H */ | ||
diff --git a/src/gallium/drivers/i965/brw_sf.c b/src/gallium/drivers/i965/brw_sf.c deleted file mode 100644 index 5abf3848ab4..00000000000 --- a/src/gallium/drivers/i965/brw_sf.c +++ /dev/null | |||
@@ -1,216 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "pipe/p_state.h" | ||
33 | |||
34 | #include "brw_batchbuffer.h" | ||
35 | #include "brw_defines.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_pipe_rast.h" | ||
38 | #include "brw_eu.h" | ||
39 | #include "brw_sf.h" | ||
40 | #include "brw_state.h" | ||
41 | |||
42 | static enum pipe_error compile_sf_prog( struct brw_context *brw, | ||
43 | struct brw_sf_prog_key *key, | ||
44 | struct brw_winsys_buffer **bo_out ) | ||
45 | { | ||
46 | enum pipe_error ret; | ||
47 | struct brw_sf_compile c; | ||
48 | const GLuint *program; | ||
49 | GLuint program_size; | ||
50 | |||
51 | memset(&c, 0, sizeof(c)); | ||
52 | |||
53 | /* Begin the compilation: | ||
54 | */ | ||
55 | brw_init_compile(brw, &c.func); | ||
56 | |||
57 | c.key = *key; | ||
58 | c.nr_attrs = c.key.nr_attrs; | ||
59 | c.nr_attr_regs = (c.nr_attrs+1)/2; | ||
60 | c.nr_setup_attrs = c.key.nr_attrs; | ||
61 | c.nr_setup_regs = (c.nr_setup_attrs+1)/2; | ||
62 | |||
63 | c.prog_data.urb_read_length = c.nr_attr_regs; | ||
64 | c.prog_data.urb_entry_size = c.nr_setup_regs * 2; | ||
65 | |||
66 | /* Special case when there are no attributes to setup. | ||
67 | * | ||
68 | * XXX: should be able to set nr_setup_attrs to nr_attrs-1 -- but | ||
69 | * breaks vp-tris.c | ||
70 | */ | ||
71 | if (c.nr_attrs - 1 == 0) { | ||
72 | c.nr_verts = 0; | ||
73 | brw_emit_null_setup( &c ); | ||
74 | } | ||
75 | else { | ||
76 | /* Which primitive? Or all three? | ||
77 | */ | ||
78 | switch (key->primitive) { | ||
79 | case SF_TRIANGLES: | ||
80 | c.nr_verts = 3; | ||
81 | brw_emit_tri_setup( &c, GL_TRUE ); | ||
82 | break; | ||
83 | case SF_LINES: | ||
84 | c.nr_verts = 2; | ||
85 | brw_emit_line_setup( &c, GL_TRUE ); | ||
86 | break; | ||
87 | case SF_POINTS: | ||
88 | c.nr_verts = 1; | ||
89 | if (key->do_point_sprite) | ||
90 | brw_emit_point_sprite_setup( &c, GL_TRUE ); | ||
91 | else | ||
92 | brw_emit_point_setup( &c, GL_TRUE ); | ||
93 | break; | ||
94 | case SF_UNFILLED_TRIS: | ||
95 | c.nr_verts = 3; | ||
96 | brw_emit_anyprim_setup( &c ); | ||
97 | break; | ||
98 | default: | ||
99 | assert(0); | ||
100 | return PIPE_ERROR_BAD_INPUT; | ||
101 | } | ||
102 | } | ||
103 | |||
104 | /* get the program | ||
105 | */ | ||
106 | ret = brw_get_program(&c.func, &program, &program_size); | ||
107 | if (ret) | ||
108 | return ret; | ||
109 | |||
110 | /* Upload | ||
111 | */ | ||
112 | ret = brw_upload_cache( &brw->cache, BRW_SF_PROG, | ||
113 | &c.key, sizeof(c.key), | ||
114 | NULL, 0, | ||
115 | program, program_size, | ||
116 | &c.prog_data, | ||
117 | &brw->sf.prog_data, | ||
118 | bo_out); | ||
119 | if (ret) | ||
120 | return ret; | ||
121 | |||
122 | return PIPE_OK; | ||
123 | } | ||
124 | |||
125 | /* Calculate interpolants for triangle and line rasterization. | ||
126 | */ | ||
127 | static enum pipe_error upload_sf_prog(struct brw_context *brw) | ||
128 | { | ||
129 | const struct brw_fs_signature *sig = &brw->curr.fragment_shader->signature; | ||
130 | const struct pipe_rasterizer_state *rast = &brw->curr.rast->templ; | ||
131 | struct brw_sf_prog_key key; | ||
132 | enum pipe_error ret; | ||
133 | unsigned i; | ||
134 | |||
135 | memset(&key, 0, sizeof(key)); | ||
136 | |||
137 | /* Populate the key, noting state dependencies: | ||
138 | */ | ||
139 | |||
140 | /* XXX: Add one to account for the position input. | ||
141 | */ | ||
142 | /* PIPE_NEW_FRAGMENT_SIGNATURE */ | ||
143 | key.nr_attrs = sig->nr_inputs + 1; | ||
144 | |||
145 | |||
146 | /* XXX: why is position required to be linear? why do we care | ||
147 | * about it at all? | ||
148 | */ | ||
149 | key.linear_attrs = 1; /* position -- but why? */ | ||
150 | |||
151 | for (i = 0; i < sig->nr_inputs; i++) { | ||
152 | switch (sig->input[i].interp) { | ||
153 | case TGSI_INTERPOLATE_CONSTANT: | ||
154 | break; | ||
155 | case TGSI_INTERPOLATE_LINEAR: | ||
156 | key.linear_attrs |= 1 << (i+1); | ||
157 | break; | ||
158 | case TGSI_INTERPOLATE_PERSPECTIVE: | ||
159 | key.persp_attrs |= 1 << (i+1); | ||
160 | break; | ||
161 | } | ||
162 | } | ||
163 | |||
164 | /* BRW_NEW_REDUCED_PRIMITIVE */ | ||
165 | switch (brw->reduced_primitive) { | ||
166 | case PIPE_PRIM_TRIANGLES: | ||
167 | /* PIPE_NEW_RAST | ||
168 | */ | ||
169 | if (rast->fill_front != PIPE_POLYGON_MODE_FILL || | ||
170 | rast->fill_back != PIPE_POLYGON_MODE_FILL) | ||
171 | key.primitive = SF_UNFILLED_TRIS; | ||
172 | else | ||
173 | key.primitive = SF_TRIANGLES; | ||
174 | break; | ||
175 | case PIPE_PRIM_LINES: | ||
176 | key.primitive = SF_LINES; | ||
177 | break; | ||
178 | case PIPE_PRIM_POINTS: | ||
179 | key.primitive = SF_POINTS; | ||
180 | break; | ||
181 | } | ||
182 | |||
183 | key.do_point_sprite = rast->sprite_coord_enable ? 1 : 0; | ||
184 | key.sprite_origin_lower_left = (rast->sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT); | ||
185 | key.point_coord_replace_attrs = rast->sprite_coord_enable; | ||
186 | key.do_flat_shading = rast->flatshade; | ||
187 | key.do_twoside_color = rast->light_twoside; | ||
188 | |||
189 | if (key.do_twoside_color) { | ||
190 | key.frontface_ccw = rast->front_ccw; | ||
191 | } | ||
192 | |||
193 | if (brw_search_cache(&brw->cache, BRW_SF_PROG, | ||
194 | &key, sizeof(key), | ||
195 | NULL, 0, | ||
196 | &brw->sf.prog_data, | ||
197 | &brw->sf.prog_bo)) | ||
198 | return PIPE_OK; | ||
199 | |||
200 | ret = compile_sf_prog( brw, &key, &brw->sf.prog_bo ); | ||
201 | if (ret) | ||
202 | return ret; | ||
203 | |||
204 | return PIPE_OK; | ||
205 | } | ||
206 | |||
207 | |||
208 | const struct brw_tracked_state brw_sf_prog = { | ||
209 | .dirty = { | ||
210 | .mesa = (PIPE_NEW_RAST | PIPE_NEW_FRAGMENT_SIGNATURE), | ||
211 | .brw = (BRW_NEW_REDUCED_PRIMITIVE), | ||
212 | .cache = 0 | ||
213 | }, | ||
214 | .prepare = upload_sf_prog | ||
215 | }; | ||
216 | |||
diff --git a/src/gallium/drivers/i965/brw_sf.h b/src/gallium/drivers/i965/brw_sf.h deleted file mode 100644 index a895c7d2f6a..00000000000 --- a/src/gallium/drivers/i965/brw_sf.h +++ /dev/null | |||
@@ -1,122 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_SF_H | ||
34 | #define BRW_SF_H | ||
35 | |||
36 | |||
37 | #include "brw_context.h" | ||
38 | #include "brw_eu.h" | ||
39 | |||
40 | |||
41 | #define SF_POINTS 0 | ||
42 | #define SF_LINES 1 | ||
43 | #define SF_TRIANGLES 2 | ||
44 | #define SF_UNFILLED_TRIS 3 | ||
45 | |||
46 | struct brw_sf_prog_key { | ||
47 | |||
48 | /* Bitmask of linear and perspective interpolated inputs, 0..nr | ||
49 | */ | ||
50 | GLuint persp_attrs:32; | ||
51 | GLuint linear_attrs:32; | ||
52 | GLuint point_coord_replace_attrs:32; | ||
53 | |||
54 | GLuint nr_attrs:8; | ||
55 | GLuint primitive:2; | ||
56 | GLuint do_twoside_color:1; | ||
57 | GLuint do_flat_shading:1; | ||
58 | GLuint frontface_ccw:1; | ||
59 | GLuint do_point_sprite:1; | ||
60 | GLuint sprite_origin_lower_left:1; | ||
61 | GLuint pad:17; | ||
62 | |||
63 | GLuint attr_col0:8; | ||
64 | GLuint attr_col1:8; | ||
65 | GLuint attr_bfc0:8; | ||
66 | GLuint attr_bfc1:8; | ||
67 | }; | ||
68 | |||
69 | struct brw_sf_point_tex { | ||
70 | GLboolean CoordReplace; | ||
71 | }; | ||
72 | |||
73 | struct brw_sf_compile { | ||
74 | struct brw_compile func; | ||
75 | struct brw_sf_prog_key key; | ||
76 | struct brw_sf_prog_data prog_data; | ||
77 | |||
78 | struct brw_reg pv; | ||
79 | struct brw_reg det; | ||
80 | struct brw_reg dx0; | ||
81 | struct brw_reg dx2; | ||
82 | struct brw_reg dy0; | ||
83 | struct brw_reg dy2; | ||
84 | |||
85 | /* z and 1/w passed in seperately: | ||
86 | */ | ||
87 | struct brw_reg z[3]; | ||
88 | struct brw_reg inv_w[3]; | ||
89 | |||
90 | /* The vertices: | ||
91 | */ | ||
92 | struct brw_reg vert[3]; | ||
93 | |||
94 | /* Temporaries, allocated after last vertex reg. | ||
95 | */ | ||
96 | struct brw_reg inv_det; | ||
97 | struct brw_reg a1_sub_a0; | ||
98 | struct brw_reg a2_sub_a0; | ||
99 | struct brw_reg tmp; | ||
100 | |||
101 | struct brw_reg m1Cx; | ||
102 | struct brw_reg m2Cy; | ||
103 | struct brw_reg m3C0; | ||
104 | |||
105 | GLuint nr_verts; | ||
106 | GLuint nr_attrs; | ||
107 | GLuint nr_attr_regs; | ||
108 | GLuint nr_setup_attrs; | ||
109 | GLuint nr_setup_regs; | ||
110 | |||
111 | GLuint point_coord_replace_mask; | ||
112 | }; | ||
113 | |||
114 | |||
115 | void brw_emit_null_setup( struct brw_sf_compile *c ); | ||
116 | void brw_emit_tri_setup( struct brw_sf_compile *c, GLboolean allocate ); | ||
117 | void brw_emit_line_setup( struct brw_sf_compile *c, GLboolean allocate ); | ||
118 | void brw_emit_point_setup( struct brw_sf_compile *c, GLboolean allocate ); | ||
119 | void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate ); | ||
120 | void brw_emit_anyprim_setup( struct brw_sf_compile *c ); | ||
121 | |||
122 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_sf_emit.c b/src/gallium/drivers/i965/brw_sf_emit.c deleted file mode 100644 index 901c3341642..00000000000 --- a/src/gallium/drivers/i965/brw_sf_emit.c +++ /dev/null | |||
@@ -1,764 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_batchbuffer.h" | ||
34 | |||
35 | #include "brw_defines.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_eu.h" | ||
38 | #include "brw_sf.h" | ||
39 | |||
40 | |||
41 | static struct brw_reg get_vert_attr(struct brw_sf_compile *c, | ||
42 | struct brw_reg vert, | ||
43 | GLuint attr) | ||
44 | { | ||
45 | GLuint off = attr / 2; | ||
46 | GLuint sub = attr % 2; | ||
47 | |||
48 | return brw_vec4_grf(vert.nr + off, sub * 4); | ||
49 | } | ||
50 | |||
51 | |||
52 | /*********************************************************************** | ||
53 | * Twoside lighting | ||
54 | */ | ||
55 | static void copy_bfc( struct brw_sf_compile *c, | ||
56 | struct brw_reg vert ) | ||
57 | { | ||
58 | struct brw_compile *p = &c->func; | ||
59 | |||
60 | if (c->key.attr_col0 && c->key.attr_bfc0) | ||
61 | brw_MOV(p, | ||
62 | get_vert_attr(c, vert, c->key.attr_col0), | ||
63 | get_vert_attr(c, vert, c->key.attr_bfc0)); | ||
64 | |||
65 | if (c->key.attr_col1 && c->key.attr_bfc1) | ||
66 | brw_MOV(p, | ||
67 | get_vert_attr(c, vert, c->key.attr_col1), | ||
68 | get_vert_attr(c, vert, c->key.attr_bfc1)); | ||
69 | } | ||
70 | |||
71 | |||
72 | static void do_twoside_color( struct brw_sf_compile *c ) | ||
73 | { | ||
74 | struct brw_compile *p = &c->func; | ||
75 | struct brw_instruction *if_insn; | ||
76 | GLuint backface_conditional = c->key.frontface_ccw ? BRW_CONDITIONAL_G : BRW_CONDITIONAL_L; | ||
77 | |||
78 | /* Already done in clip program: | ||
79 | */ | ||
80 | if (c->key.primitive == SF_UNFILLED_TRIS) | ||
81 | return; | ||
82 | |||
83 | /* XXX: What happens if BFC isn't present? This could only happen | ||
84 | * for user-supplied vertex programs, as t_vp_build.c always does | ||
85 | * the right thing. | ||
86 | */ | ||
87 | if (!(c->key.attr_col0 && c->key.attr_bfc0) && | ||
88 | !(c->key.attr_col1 && c->key.attr_bfc1)) | ||
89 | return; | ||
90 | |||
91 | /* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order | ||
92 | * to get all channels active inside the IF. In the clipping code | ||
93 | * we run with NoMask, so it's not an option and we can use | ||
94 | * BRW_EXECUTE_1 for all comparisions. | ||
95 | */ | ||
96 | brw_push_insn_state(p); | ||
97 | brw_CMP(p, vec4(brw_null_reg()), backface_conditional, c->det, brw_imm_f(0)); | ||
98 | if_insn = brw_IF(p, BRW_EXECUTE_4); | ||
99 | { | ||
100 | switch (c->nr_verts) { | ||
101 | case 3: copy_bfc(c, c->vert[2]); | ||
102 | case 2: copy_bfc(c, c->vert[1]); | ||
103 | case 1: copy_bfc(c, c->vert[0]); | ||
104 | } | ||
105 | } | ||
106 | brw_ENDIF(p, if_insn); | ||
107 | brw_pop_insn_state(p); | ||
108 | } | ||
109 | |||
110 | |||
111 | |||
112 | /*********************************************************************** | ||
113 | * Flat shading | ||
114 | */ | ||
115 | |||
116 | #define VERT_RESULT_COLOR_BITS ((1<<VERT_RESULT_COL0) | \ | ||
117 | (1<<VERT_RESULT_COL1)) | ||
118 | |||
119 | static void copy_colors( struct brw_sf_compile *c, | ||
120 | struct brw_reg dst, | ||
121 | struct brw_reg src) | ||
122 | { | ||
123 | struct brw_compile *p = &c->func; | ||
124 | |||
125 | if (c->key.attr_col0) | ||
126 | brw_MOV(p, | ||
127 | get_vert_attr(c, dst, c->key.attr_col0), | ||
128 | get_vert_attr(c, src, c->key.attr_col0)); | ||
129 | |||
130 | if (c->key.attr_col1) | ||
131 | brw_MOV(p, | ||
132 | get_vert_attr(c, dst, c->key.attr_col1), | ||
133 | get_vert_attr(c, src, c->key.attr_col1)); | ||
134 | |||
135 | } | ||
136 | |||
137 | |||
138 | |||
139 | /* Need to use a computed jump to copy flatshaded attributes as the | ||
140 | * vertices are ordered according to y-coordinate before reaching this | ||
141 | * point, so the PV could be anywhere. | ||
142 | */ | ||
143 | static void do_flatshade_triangle( struct brw_sf_compile *c ) | ||
144 | { | ||
145 | struct brw_compile *p = &c->func; | ||
146 | struct brw_reg ip = brw_ip_reg(); | ||
147 | GLuint jmpi = 1; | ||
148 | GLuint nr = 0; | ||
149 | |||
150 | if (c->key.attr_col0) | ||
151 | nr++; | ||
152 | |||
153 | if (c->key.attr_col1) | ||
154 | nr++; | ||
155 | |||
156 | if (nr == 0) | ||
157 | return; | ||
158 | |||
159 | /* Already done in clip program: | ||
160 | */ | ||
161 | if (c->key.primitive == SF_UNFILLED_TRIS) | ||
162 | return; | ||
163 | |||
164 | if (p->brw->gen == 5) | ||
165 | jmpi = 2; | ||
166 | |||
167 | brw_push_insn_state(p); | ||
168 | |||
169 | brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr*2+1))); | ||
170 | brw_JMPI(p, ip, ip, c->pv); | ||
171 | |||
172 | copy_colors(c, c->vert[1], c->vert[0]); | ||
173 | copy_colors(c, c->vert[2], c->vert[0]); | ||
174 | brw_JMPI(p, ip, ip, brw_imm_d(jmpi*(nr*4+1))); | ||
175 | |||
176 | copy_colors(c, c->vert[0], c->vert[1]); | ||
177 | copy_colors(c, c->vert[2], c->vert[1]); | ||
178 | brw_JMPI(p, ip, ip, brw_imm_d(jmpi*nr*2)); | ||
179 | |||
180 | copy_colors(c, c->vert[0], c->vert[2]); | ||
181 | copy_colors(c, c->vert[1], c->vert[2]); | ||
182 | |||
183 | brw_pop_insn_state(p); | ||
184 | } | ||
185 | |||
186 | |||
187 | static void do_flatshade_line( struct brw_sf_compile *c ) | ||
188 | { | ||
189 | struct brw_compile *p = &c->func; | ||
190 | struct brw_reg ip = brw_ip_reg(); | ||
191 | GLuint jmpi = 1; | ||
192 | GLuint nr = 0; | ||
193 | |||
194 | if (c->key.attr_col0) | ||
195 | nr++; | ||
196 | |||
197 | if (c->key.attr_col1) | ||
198 | nr++; | ||
199 | |||
200 | if (nr == 0) | ||
201 | return; | ||
202 | |||
203 | /* Already done in clip program: | ||
204 | */ | ||
205 | if (c->key.primitive == SF_UNFILLED_TRIS) | ||
206 | return; | ||
207 | |||
208 | if (p->brw->gen == 5) | ||
209 | jmpi = 2; | ||
210 | |||
211 | brw_push_insn_state(p); | ||
212 | |||
213 | brw_MUL(p, c->pv, c->pv, brw_imm_d(jmpi*(nr+1))); | ||
214 | brw_JMPI(p, ip, ip, c->pv); | ||
215 | copy_colors(c, c->vert[1], c->vert[0]); | ||
216 | |||
217 | brw_JMPI(p, ip, ip, brw_imm_ud(jmpi*nr)); | ||
218 | copy_colors(c, c->vert[0], c->vert[1]); | ||
219 | |||
220 | brw_pop_insn_state(p); | ||
221 | } | ||
222 | |||
223 | |||
224 | |||
225 | /*********************************************************************** | ||
226 | * Triangle setup. | ||
227 | */ | ||
228 | |||
229 | |||
230 | static void alloc_regs( struct brw_sf_compile *c ) | ||
231 | { | ||
232 | GLuint reg, i; | ||
233 | |||
234 | /* Values computed by fixed function unit: | ||
235 | */ | ||
236 | c->pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_D); | ||
237 | c->det = brw_vec1_grf(1, 2); | ||
238 | c->dx0 = brw_vec1_grf(1, 3); | ||
239 | c->dx2 = brw_vec1_grf(1, 4); | ||
240 | c->dy0 = brw_vec1_grf(1, 5); | ||
241 | c->dy2 = brw_vec1_grf(1, 6); | ||
242 | |||
243 | /* z and 1/w passed in seperately: | ||
244 | */ | ||
245 | c->z[0] = brw_vec1_grf(2, 0); | ||
246 | c->inv_w[0] = brw_vec1_grf(2, 1); | ||
247 | c->z[1] = brw_vec1_grf(2, 2); | ||
248 | c->inv_w[1] = brw_vec1_grf(2, 3); | ||
249 | c->z[2] = brw_vec1_grf(2, 4); | ||
250 | c->inv_w[2] = brw_vec1_grf(2, 5); | ||
251 | |||
252 | /* The vertices: | ||
253 | */ | ||
254 | reg = 3; | ||
255 | for (i = 0; i < c->nr_verts; i++) { | ||
256 | c->vert[i] = brw_vec8_grf(reg, 0); | ||
257 | reg += c->nr_attr_regs; | ||
258 | } | ||
259 | |||
260 | /* Temporaries, allocated after last vertex reg. | ||
261 | */ | ||
262 | c->inv_det = brw_vec1_grf(reg, 0); reg++; | ||
263 | c->a1_sub_a0 = brw_vec8_grf(reg, 0); reg++; | ||
264 | c->a2_sub_a0 = brw_vec8_grf(reg, 0); reg++; | ||
265 | c->tmp = brw_vec8_grf(reg, 0); reg++; | ||
266 | |||
267 | /* Note grf allocation: | ||
268 | */ | ||
269 | c->prog_data.total_grf = reg; | ||
270 | |||
271 | |||
272 | /* Outputs of this program - interpolation coefficients for | ||
273 | * rasterization: | ||
274 | */ | ||
275 | c->m1Cx = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 1, 0); | ||
276 | c->m2Cy = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 2, 0); | ||
277 | c->m3C0 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 3, 0); | ||
278 | } | ||
279 | |||
280 | |||
281 | static void copy_z_inv_w( struct brw_sf_compile *c ) | ||
282 | { | ||
283 | struct brw_compile *p = &c->func; | ||
284 | GLuint i; | ||
285 | |||
286 | brw_push_insn_state(p); | ||
287 | |||
288 | /* Copy both scalars with a single MOV: | ||
289 | */ | ||
290 | for (i = 0; i < c->nr_verts; i++) | ||
291 | brw_MOV(p, vec2(suboffset(c->vert[i], 2)), vec2(c->z[i])); | ||
292 | |||
293 | brw_pop_insn_state(p); | ||
294 | } | ||
295 | |||
296 | |||
297 | static void invert_det( struct brw_sf_compile *c) | ||
298 | { | ||
299 | /* Looks like we invert all 8 elements just to get 1/det in | ||
300 | * position 2 !?! | ||
301 | */ | ||
302 | brw_math(&c->func, | ||
303 | c->inv_det, | ||
304 | BRW_MATH_FUNCTION_INV, | ||
305 | BRW_MATH_SATURATE_NONE, | ||
306 | 0, | ||
307 | c->det, | ||
308 | BRW_MATH_DATA_SCALAR, | ||
309 | BRW_MATH_PRECISION_FULL); | ||
310 | |||
311 | } | ||
312 | |||
313 | |||
314 | /* Two attributes packed into a wide register. Figure out if either | ||
315 | * or both of them need linear/perspective interpolation. Constant | ||
316 | * regs are left as-is. | ||
317 | */ | ||
318 | static GLboolean calculate_masks( struct brw_sf_compile *c, | ||
319 | GLuint reg, | ||
320 | GLushort *pc, | ||
321 | GLushort *pc_persp, | ||
322 | GLushort *pc_linear) | ||
323 | { | ||
324 | GLboolean is_last_attr = (reg == c->nr_setup_regs - 1); | ||
325 | GLuint persp_mask = c->key.persp_attrs; | ||
326 | GLuint linear_mask = (c->key.persp_attrs | c->key.linear_attrs); | ||
327 | |||
328 | *pc_persp = 0; | ||
329 | *pc_linear = 0; | ||
330 | *pc = 0xf; | ||
331 | |||
332 | if (persp_mask & (1 << (reg*2))) | ||
333 | *pc_persp = 0xf; | ||
334 | |||
335 | if (linear_mask & (1 << (reg*2))) | ||
336 | *pc_linear = 0xf; | ||
337 | |||
338 | /* Maybe only processs one attribute on the final round: | ||
339 | */ | ||
340 | if (reg*2+1 < c->nr_setup_attrs) { | ||
341 | *pc |= 0xf0; | ||
342 | |||
343 | if (persp_mask & (1 << (reg*2+1))) | ||
344 | *pc_persp |= 0xf0; | ||
345 | |||
346 | if (linear_mask & (1 << (reg*2+1))) | ||
347 | *pc_linear |= 0xf0; | ||
348 | } | ||
349 | |||
350 | return is_last_attr; | ||
351 | } | ||
352 | |||
353 | |||
354 | void brw_emit_null_setup( struct brw_sf_compile *c ) | ||
355 | { | ||
356 | struct brw_compile *p = &c->func; | ||
357 | |||
358 | /* m0 is implicitly copied from r0 in the send instruction: | ||
359 | */ | ||
360 | brw_urb_WRITE(p, | ||
361 | brw_null_reg(), | ||
362 | 0, | ||
363 | brw_vec8_grf(0, 0), /* r0, will be copied to m0 */ | ||
364 | 0, /* allocate */ | ||
365 | 1, /* used */ | ||
366 | 1, /* msg len */ | ||
367 | 0, /* response len */ | ||
368 | 1, /* eot */ | ||
369 | 1, /* writes complete */ | ||
370 | 0, /* offset */ | ||
371 | BRW_URB_SWIZZLE_TRANSPOSE); | ||
372 | } | ||
373 | |||
374 | void brw_emit_tri_setup( struct brw_sf_compile *c, GLboolean allocate) | ||
375 | { | ||
376 | struct brw_compile *p = &c->func; | ||
377 | GLuint i; | ||
378 | |||
379 | c->nr_verts = 3; | ||
380 | |||
381 | if (allocate) | ||
382 | alloc_regs(c); | ||
383 | |||
384 | invert_det(c); | ||
385 | copy_z_inv_w(c); | ||
386 | |||
387 | if (c->key.do_twoside_color) | ||
388 | do_twoside_color(c); | ||
389 | |||
390 | if (c->key.do_flat_shading) | ||
391 | do_flatshade_triangle(c); | ||
392 | |||
393 | |||
394 | for (i = 0; i < c->nr_setup_regs; i++) | ||
395 | { | ||
396 | /* Pair of incoming attributes: | ||
397 | */ | ||
398 | struct brw_reg a0 = offset(c->vert[0], i); | ||
399 | struct brw_reg a1 = offset(c->vert[1], i); | ||
400 | struct brw_reg a2 = offset(c->vert[2], i); | ||
401 | GLushort pc, pc_persp, pc_linear; | ||
402 | GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); | ||
403 | |||
404 | if (pc_persp) | ||
405 | { | ||
406 | brw_set_predicate_control_flag_value(p, pc_persp); | ||
407 | brw_MUL(p, a0, a0, c->inv_w[0]); | ||
408 | brw_MUL(p, a1, a1, c->inv_w[1]); | ||
409 | brw_MUL(p, a2, a2, c->inv_w[2]); | ||
410 | } | ||
411 | |||
412 | |||
413 | /* Calculate coefficients for interpolated values: | ||
414 | */ | ||
415 | if (pc_linear) | ||
416 | { | ||
417 | brw_set_predicate_control_flag_value(p, pc_linear); | ||
418 | |||
419 | brw_ADD(p, c->a1_sub_a0, a1, negate(a0)); | ||
420 | brw_ADD(p, c->a2_sub_a0, a2, negate(a0)); | ||
421 | |||
422 | /* calculate dA/dx | ||
423 | */ | ||
424 | brw_MUL(p, brw_null_reg(), c->a1_sub_a0, c->dy2); | ||
425 | brw_MAC(p, c->tmp, c->a2_sub_a0, negate(c->dy0)); | ||
426 | brw_MUL(p, c->m1Cx, c->tmp, c->inv_det); | ||
427 | |||
428 | /* calculate dA/dy | ||
429 | */ | ||
430 | brw_MUL(p, brw_null_reg(), c->a2_sub_a0, c->dx0); | ||
431 | brw_MAC(p, c->tmp, c->a1_sub_a0, negate(c->dx2)); | ||
432 | brw_MUL(p, c->m2Cy, c->tmp, c->inv_det); | ||
433 | } | ||
434 | |||
435 | { | ||
436 | brw_set_predicate_control_flag_value(p, pc); | ||
437 | /* start point for interpolation | ||
438 | */ | ||
439 | brw_MOV(p, c->m3C0, a0); | ||
440 | |||
441 | /* Copy m0..m3 to URB. m0 is implicitly copied from r0 in | ||
442 | * the send instruction: | ||
443 | */ | ||
444 | brw_urb_WRITE(p, | ||
445 | brw_null_reg(), | ||
446 | 0, | ||
447 | brw_vec8_grf(0, 0), /* r0, will be copied to m0 */ | ||
448 | 0, /* allocate */ | ||
449 | 1, /* used */ | ||
450 | 4, /* msg len */ | ||
451 | 0, /* response len */ | ||
452 | last, /* eot */ | ||
453 | last, /* writes complete */ | ||
454 | i*4, /* offset */ | ||
455 | BRW_URB_SWIZZLE_TRANSPOSE); /* XXX: Swizzle control "SF to windower" */ | ||
456 | } | ||
457 | } | ||
458 | } | ||
459 | |||
460 | |||
461 | |||
462 | void brw_emit_line_setup( struct brw_sf_compile *c, GLboolean allocate) | ||
463 | { | ||
464 | struct brw_compile *p = &c->func; | ||
465 | GLuint i; | ||
466 | |||
467 | |||
468 | c->nr_verts = 2; | ||
469 | |||
470 | if (allocate) | ||
471 | alloc_regs(c); | ||
472 | |||
473 | invert_det(c); | ||
474 | copy_z_inv_w(c); | ||
475 | |||
476 | if (c->key.do_flat_shading) | ||
477 | do_flatshade_line(c); | ||
478 | |||
479 | for (i = 0; i < c->nr_setup_regs; i++) | ||
480 | { | ||
481 | /* Pair of incoming attributes: | ||
482 | */ | ||
483 | struct brw_reg a0 = offset(c->vert[0], i); | ||
484 | struct brw_reg a1 = offset(c->vert[1], i); | ||
485 | GLushort pc, pc_persp, pc_linear; | ||
486 | GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); | ||
487 | |||
488 | if (pc_persp) | ||
489 | { | ||
490 | brw_set_predicate_control_flag_value(p, pc_persp); | ||
491 | brw_MUL(p, a0, a0, c->inv_w[0]); | ||
492 | brw_MUL(p, a1, a1, c->inv_w[1]); | ||
493 | } | ||
494 | |||
495 | /* Calculate coefficients for position, color: | ||
496 | */ | ||
497 | if (pc_linear) { | ||
498 | brw_set_predicate_control_flag_value(p, pc_linear); | ||
499 | |||
500 | brw_ADD(p, c->a1_sub_a0, a1, negate(a0)); | ||
501 | |||
502 | brw_MUL(p, c->tmp, c->a1_sub_a0, c->dx0); | ||
503 | brw_MUL(p, c->m1Cx, c->tmp, c->inv_det); | ||
504 | |||
505 | brw_MUL(p, c->tmp, c->a1_sub_a0, c->dy0); | ||
506 | brw_MUL(p, c->m2Cy, c->tmp, c->inv_det); | ||
507 | } | ||
508 | |||
509 | { | ||
510 | brw_set_predicate_control_flag_value(p, pc); | ||
511 | |||
512 | /* start point for interpolation | ||
513 | */ | ||
514 | brw_MOV(p, c->m3C0, a0); | ||
515 | |||
516 | /* Copy m0..m3 to URB. | ||
517 | */ | ||
518 | brw_urb_WRITE(p, | ||
519 | brw_null_reg(), | ||
520 | 0, | ||
521 | brw_vec8_grf(0, 0), | ||
522 | 0, /* allocate */ | ||
523 | 1, /* used */ | ||
524 | 4, /* msg len */ | ||
525 | 0, /* response len */ | ||
526 | last, /* eot */ | ||
527 | last, /* writes complete */ | ||
528 | i*4, /* urb destination offset */ | ||
529 | BRW_URB_SWIZZLE_TRANSPOSE); | ||
530 | } | ||
531 | } | ||
532 | } | ||
533 | |||
534 | void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate) | ||
535 | { | ||
536 | struct brw_compile *p = &c->func; | ||
537 | GLuint i; | ||
538 | |||
539 | c->nr_verts = 1; | ||
540 | |||
541 | if (allocate) | ||
542 | alloc_regs(c); | ||
543 | |||
544 | copy_z_inv_w(c); | ||
545 | |||
546 | for (i = 0; i < c->nr_setup_regs; i++) | ||
547 | { | ||
548 | /* XXX: only seems to check point_coord_replace_attrs for every | ||
549 | * second attribute?!? | ||
550 | */ | ||
551 | boolean coord_replace = !!(c->key.point_coord_replace_attrs & (1<<(2*i))); | ||
552 | struct brw_reg a0 = offset(c->vert[0], i); | ||
553 | GLushort pc, pc_persp, pc_linear; | ||
554 | GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); | ||
555 | |||
556 | if (pc_persp) | ||
557 | { | ||
558 | if (coord_replace) { | ||
559 | brw_set_predicate_control_flag_value(p, pc_persp); | ||
560 | brw_MUL(p, a0, a0, c->inv_w[0]); | ||
561 | } | ||
562 | } | ||
563 | |||
564 | if (coord_replace) { | ||
565 | /* Caculate 1.0/PointWidth */ | ||
566 | brw_math(&c->func, | ||
567 | c->tmp, | ||
568 | BRW_MATH_FUNCTION_INV, | ||
569 | BRW_MATH_SATURATE_NONE, | ||
570 | 0, | ||
571 | c->dx0, | ||
572 | BRW_MATH_DATA_SCALAR, | ||
573 | BRW_MATH_PRECISION_FULL); | ||
574 | |||
575 | if (c->key.sprite_origin_lower_left) { | ||
576 | brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]); | ||
577 | brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0)); | ||
578 | brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0])); | ||
579 | brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0)); | ||
580 | } | ||
581 | else { | ||
582 | brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]); | ||
583 | brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0)); | ||
584 | brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]); | ||
585 | brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0)); | ||
586 | } | ||
587 | } | ||
588 | else { | ||
589 | brw_MOV(p, c->m1Cx, brw_imm_ud(0)); | ||
590 | brw_MOV(p, c->m2Cy, brw_imm_ud(0)); | ||
591 | } | ||
592 | |||
593 | { | ||
594 | brw_set_predicate_control_flag_value(p, pc); | ||
595 | if (coord_replace) { | ||
596 | if (c->key.sprite_origin_lower_left) { | ||
597 | brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0)); | ||
598 | brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0)); | ||
599 | } | ||
600 | else { | ||
601 | brw_MOV(p, c->m3C0, brw_imm_f(0.0)); | ||
602 | } | ||
603 | } | ||
604 | else { | ||
605 | brw_MOV(p, c->m3C0, a0); /* constant value */ | ||
606 | } | ||
607 | |||
608 | /* Copy m0..m3 to URB. | ||
609 | */ | ||
610 | brw_urb_WRITE(p, | ||
611 | brw_null_reg(), | ||
612 | 0, | ||
613 | brw_vec8_grf(0, 0), | ||
614 | 0, /* allocate */ | ||
615 | 1, /* used */ | ||
616 | 4, /* msg len */ | ||
617 | 0, /* response len */ | ||
618 | last, /* eot */ | ||
619 | last, /* writes complete */ | ||
620 | i*4, /* urb destination offset */ | ||
621 | BRW_URB_SWIZZLE_TRANSPOSE); | ||
622 | } | ||
623 | } | ||
624 | } | ||
625 | |||
626 | /* Points setup - several simplifications as all attributes are | ||
627 | * constant across the face of the point (point sprites excluded!) | ||
628 | */ | ||
629 | void brw_emit_point_setup( struct brw_sf_compile *c, GLboolean allocate) | ||
630 | { | ||
631 | struct brw_compile *p = &c->func; | ||
632 | GLuint i; | ||
633 | |||
634 | c->nr_verts = 1; | ||
635 | |||
636 | if (allocate) | ||
637 | alloc_regs(c); | ||
638 | |||
639 | copy_z_inv_w(c); | ||
640 | |||
641 | brw_MOV(p, c->m1Cx, brw_imm_ud(0)); /* zero - move out of loop */ | ||
642 | brw_MOV(p, c->m2Cy, brw_imm_ud(0)); /* zero - move out of loop */ | ||
643 | |||
644 | for (i = 0; i < c->nr_setup_regs; i++) | ||
645 | { | ||
646 | struct brw_reg a0 = offset(c->vert[0], i); | ||
647 | GLushort pc, pc_persp, pc_linear; | ||
648 | GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear); | ||
649 | |||
650 | if (pc_persp) | ||
651 | { | ||
652 | /* This seems odd as the values are all constant, but the | ||
653 | * fragment shader will be expecting it: | ||
654 | */ | ||
655 | brw_set_predicate_control_flag_value(p, pc_persp); | ||
656 | brw_MUL(p, a0, a0, c->inv_w[0]); | ||
657 | } | ||
658 | |||
659 | |||
660 | /* The delta values are always zero, just send the starting | ||
661 | * coordinate. Again, this is to fit in with the interpolation | ||
662 | * code in the fragment shader. | ||
663 | */ | ||
664 | { | ||
665 | brw_set_predicate_control_flag_value(p, pc); | ||
666 | |||
667 | brw_MOV(p, c->m3C0, a0); /* constant value */ | ||
668 | |||
669 | /* Copy m0..m3 to URB. | ||
670 | */ | ||
671 | brw_urb_WRITE(p, | ||
672 | brw_null_reg(), | ||
673 | 0, | ||
674 | brw_vec8_grf(0, 0), | ||
675 | 0, /* allocate */ | ||
676 | 1, /* used */ | ||
677 | 4, /* msg len */ | ||
678 | 0, /* response len */ | ||
679 | last, /* eot */ | ||
680 | last, /* writes complete */ | ||
681 | i*4, /* urb destination offset */ | ||
682 | BRW_URB_SWIZZLE_TRANSPOSE); | ||
683 | } | ||
684 | } | ||
685 | } | ||
686 | |||
687 | void brw_emit_anyprim_setup( struct brw_sf_compile *c ) | ||
688 | { | ||
689 | struct brw_compile *p = &c->func; | ||
690 | struct brw_reg ip = brw_ip_reg(); | ||
691 | struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0); | ||
692 | struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0); | ||
693 | struct brw_reg primmask; | ||
694 | struct brw_instruction *jmp; | ||
695 | struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); | ||
696 | |||
697 | GLuint saveflag; | ||
698 | |||
699 | c->nr_verts = 3; | ||
700 | alloc_regs(c); | ||
701 | |||
702 | primmask = retype(get_element(c->tmp, 0), BRW_REGISTER_TYPE_UD); | ||
703 | |||
704 | brw_MOV(p, primmask, brw_imm_ud(1)); | ||
705 | brw_SHL(p, primmask, primmask, payload_prim); | ||
706 | |||
707 | brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); | ||
708 | brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_TRILIST) | | ||
709 | (1<<_3DPRIM_TRISTRIP) | | ||
710 | (1<<_3DPRIM_TRIFAN) | | ||
711 | (1<<_3DPRIM_TRISTRIP_REVERSE) | | ||
712 | (1<<_3DPRIM_POLYGON) | | ||
713 | (1<<_3DPRIM_RECTLIST) | | ||
714 | (1<<_3DPRIM_TRIFAN_NOSTIPPLE))); | ||
715 | jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)); | ||
716 | { | ||
717 | saveflag = p->flag_value; | ||
718 | brw_push_insn_state(p); | ||
719 | brw_emit_tri_setup( c, GL_FALSE ); | ||
720 | brw_pop_insn_state(p); | ||
721 | p->flag_value = saveflag; | ||
722 | /* note - thread killed in subroutine, so must | ||
723 | * restore the flag which is changed when building | ||
724 | * the subroutine. fix #13240 | ||
725 | */ | ||
726 | } | ||
727 | brw_land_fwd_jump(p, jmp); | ||
728 | |||
729 | brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); | ||
730 | brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_LINELIST) | | ||
731 | (1<<_3DPRIM_LINESTRIP) | | ||
732 | (1<<_3DPRIM_LINELOOP) | | ||
733 | (1<<_3DPRIM_LINESTRIP_CONT) | | ||
734 | (1<<_3DPRIM_LINESTRIP_BF) | | ||
735 | (1<<_3DPRIM_LINESTRIP_CONT_BF))); | ||
736 | jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)); | ||
737 | { | ||
738 | saveflag = p->flag_value; | ||
739 | brw_push_insn_state(p); | ||
740 | brw_emit_line_setup( c, GL_FALSE ); | ||
741 | brw_pop_insn_state(p); | ||
742 | p->flag_value = saveflag; | ||
743 | /* note - thread killed in subroutine */ | ||
744 | } | ||
745 | brw_land_fwd_jump(p, jmp); | ||
746 | |||
747 | brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); | ||
748 | brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE)); | ||
749 | jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)); | ||
750 | { | ||
751 | saveflag = p->flag_value; | ||
752 | brw_push_insn_state(p); | ||
753 | brw_emit_point_sprite_setup( c, GL_FALSE ); | ||
754 | brw_pop_insn_state(p); | ||
755 | p->flag_value = saveflag; | ||
756 | } | ||
757 | brw_land_fwd_jump(p, jmp); | ||
758 | |||
759 | brw_emit_point_setup( c, GL_FALSE ); | ||
760 | } | ||
761 | |||
762 | |||
763 | |||
764 | |||
diff --git a/src/gallium/drivers/i965/brw_sf_state.c b/src/gallium/drivers/i965/brw_sf_state.c deleted file mode 100644 index eec024650ce..00000000000 --- a/src/gallium/drivers/i965/brw_sf_state.c +++ /dev/null | |||
@@ -1,331 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | |||
34 | #include "pipe/p_state.h" | ||
35 | |||
36 | #include "brw_context.h" | ||
37 | #include "brw_state.h" | ||
38 | #include "brw_defines.h" | ||
39 | #include "brw_debug.h" | ||
40 | #include "brw_pipe_rast.h" | ||
41 | |||
42 | static enum pipe_error upload_sf_vp(struct brw_context *brw) | ||
43 | { | ||
44 | const struct pipe_viewport_state *vp = &brw->curr.viewport; | ||
45 | const struct pipe_scissor_state *scissor = &brw->curr.scissor; | ||
46 | struct brw_sf_viewport sfv; | ||
47 | enum pipe_error ret; | ||
48 | |||
49 | memset(&sfv, 0, sizeof(sfv)); | ||
50 | |||
51 | /* PIPE_NEW_VIEWPORT, PIPE_NEW_SCISSOR */ | ||
52 | |||
53 | sfv.viewport.m00 = vp->scale[0]; | ||
54 | sfv.viewport.m11 = vp->scale[1]; | ||
55 | sfv.viewport.m22 = vp->scale[2]; | ||
56 | sfv.viewport.m30 = vp->translate[0]; | ||
57 | sfv.viewport.m31 = vp->translate[1]; | ||
58 | sfv.viewport.m32 = vp->translate[2]; | ||
59 | |||
60 | sfv.scissor.xmin = scissor->minx; | ||
61 | sfv.scissor.xmax = scissor->maxx - 1; /* ? */ | ||
62 | sfv.scissor.ymin = scissor->miny; | ||
63 | sfv.scissor.ymax = scissor->maxy - 1; /* ? */ | ||
64 | |||
65 | ret = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0, | ||
66 | &brw->sf.vp_bo ); | ||
67 | if (ret) | ||
68 | return ret; | ||
69 | |||
70 | return PIPE_OK; | ||
71 | } | ||
72 | |||
73 | const struct brw_tracked_state brw_sf_vp = { | ||
74 | .dirty = { | ||
75 | .mesa = (PIPE_NEW_VIEWPORT | | ||
76 | PIPE_NEW_SCISSOR), | ||
77 | .brw = 0, | ||
78 | .cache = 0 | ||
79 | }, | ||
80 | .prepare = upload_sf_vp | ||
81 | }; | ||
82 | |||
83 | struct brw_sf_unit_key { | ||
84 | unsigned int total_grf; | ||
85 | unsigned int urb_entry_read_length; | ||
86 | unsigned int nr_urb_entries, urb_size, sfsize; | ||
87 | |||
88 | unsigned scissor:1; | ||
89 | unsigned line_smooth:1; | ||
90 | unsigned point_sprite:1; | ||
91 | unsigned point_attenuated:1; | ||
92 | unsigned front_ccw:1; | ||
93 | unsigned cull_face:2; | ||
94 | unsigned flatshade_first:1; | ||
95 | unsigned gl_rasterization_rules:1; | ||
96 | unsigned line_last_pixel_enable:1; | ||
97 | float line_width; | ||
98 | float point_size; | ||
99 | }; | ||
100 | |||
101 | static void | ||
102 | sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key) | ||
103 | { | ||
104 | const struct pipe_rasterizer_state *rast = &brw->curr.rast->templ; | ||
105 | memset(key, 0, sizeof(*key)); | ||
106 | |||
107 | /* CACHE_NEW_SF_PROG */ | ||
108 | key->total_grf = brw->sf.prog_data->total_grf; | ||
109 | key->urb_entry_read_length = brw->sf.prog_data->urb_read_length; | ||
110 | |||
111 | /* BRW_NEW_URB_FENCE */ | ||
112 | key->nr_urb_entries = brw->urb.nr_sf_entries; | ||
113 | key->urb_size = brw->urb.vsize; | ||
114 | key->sfsize = brw->urb.sfsize; | ||
115 | |||
116 | /* PIPE_NEW_RAST */ | ||
117 | key->scissor = rast->scissor; | ||
118 | key->front_ccw = rast->front_ccw; | ||
119 | key->cull_face = rast->cull_face; | ||
120 | key->line_smooth = rast->line_smooth; | ||
121 | key->line_width = rast->line_width; | ||
122 | key->flatshade_first = rast->flatshade_first; | ||
123 | key->line_last_pixel_enable = rast->line_last_pixel; | ||
124 | key->gl_rasterization_rules = rast->gl_rasterization_rules; | ||
125 | |||
126 | key->point_sprite = rast->sprite_coord_enable ? 1 : 0; | ||
127 | key->point_attenuated = rast->point_size_per_vertex; | ||
128 | |||
129 | key->point_size = rast->point_size; | ||
130 | } | ||
131 | |||
132 | static enum pipe_error | ||
133 | sf_unit_create_from_key(struct brw_context *brw, | ||
134 | struct brw_sf_unit_key *key, | ||
135 | struct brw_winsys_reloc *reloc, | ||
136 | struct brw_winsys_buffer **bo_out) | ||
137 | { | ||
138 | struct brw_sf_unit_state sf; | ||
139 | enum pipe_error ret; | ||
140 | int chipset_max_threads; | ||
141 | memset(&sf, 0, sizeof(sf)); | ||
142 | |||
143 | sf.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1; | ||
144 | /* reloc */ | ||
145 | sf.thread0.kernel_start_pointer = 0; | ||
146 | |||
147 | sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; | ||
148 | |||
149 | sf.thread3.dispatch_grf_start_reg = 3; | ||
150 | |||
151 | if (brw->gen == 5) | ||
152 | sf.thread3.urb_entry_read_offset = 3; | ||
153 | else | ||
154 | sf.thread3.urb_entry_read_offset = 1; | ||
155 | |||
156 | sf.thread3.urb_entry_read_length = key->urb_entry_read_length; | ||
157 | |||
158 | sf.thread4.nr_urb_entries = key->nr_urb_entries; | ||
159 | sf.thread4.urb_entry_allocation_size = key->sfsize - 1; | ||
160 | |||
161 | /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or | ||
162 | * 48(IGDNG) threads | ||
163 | */ | ||
164 | if (brw->gen == 5) | ||
165 | chipset_max_threads = 48; | ||
166 | else | ||
167 | chipset_max_threads = 24; | ||
168 | |||
169 | sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1; | ||
170 | |||
171 | if (BRW_DEBUG & DEBUG_SINGLE_THREAD) | ||
172 | sf.thread4.max_threads = 0; | ||
173 | |||
174 | if (BRW_DEBUG & DEBUG_STATS) | ||
175 | sf.thread4.stats_enable = 1; | ||
176 | |||
177 | /* CACHE_NEW_SF_VP */ | ||
178 | /* reloc */ | ||
179 | sf.sf5.sf_viewport_state_offset = 0; | ||
180 | |||
181 | sf.sf5.viewport_transform = 1; | ||
182 | |||
183 | if (key->scissor) | ||
184 | sf.sf6.scissor = 1; | ||
185 | |||
186 | if (key->front_ccw) | ||
187 | sf.sf5.front_winding = BRW_FRONTWINDING_CCW; | ||
188 | else | ||
189 | sf.sf5.front_winding = BRW_FRONTWINDING_CW; | ||
190 | |||
191 | switch (key->cull_face) { | ||
192 | case PIPE_FACE_FRONT: | ||
193 | sf.sf6.cull_mode = BRW_CULLMODE_FRONT; | ||
194 | break; | ||
195 | case PIPE_FACE_BACK: | ||
196 | sf.sf6.cull_mode = BRW_CULLMODE_BACK; | ||
197 | break; | ||
198 | case PIPE_FACE_FRONT_AND_BACK: | ||
199 | sf.sf6.cull_mode = BRW_CULLMODE_BOTH; | ||
200 | break; | ||
201 | case PIPE_FACE_NONE: | ||
202 | sf.sf6.cull_mode = BRW_CULLMODE_NONE; | ||
203 | break; | ||
204 | default: | ||
205 | assert(0); | ||
206 | sf.sf6.cull_mode = BRW_CULLMODE_NONE; | ||
207 | break; | ||
208 | } | ||
209 | |||
210 | /* _NEW_LINE */ | ||
211 | /* XXX use ctx->Const.Min/MaxLineWidth here */ | ||
212 | sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1); | ||
213 | |||
214 | sf.sf6.line_endcap_aa_region_width = 1; | ||
215 | if (key->line_smooth) | ||
216 | sf.sf6.aa_enable = 1; | ||
217 | else if (sf.sf6.line_width <= 0x2) | ||
218 | sf.sf6.line_width = 0; | ||
219 | |||
220 | /* XXX: gl_rasterization_rules? something else? | ||
221 | */ | ||
222 | sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT; | ||
223 | sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT; | ||
224 | sf.sf6.point_rast_rule = 1; | ||
225 | |||
226 | /* XXX clamp max depends on AA vs. non-AA */ | ||
227 | |||
228 | /* _NEW_POINT */ | ||
229 | sf.sf7.sprite_point = key->point_sprite; | ||
230 | sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3); | ||
231 | sf.sf7.use_point_size_state = !key->point_attenuated; | ||
232 | sf.sf7.aa_line_distance_mode = 0; | ||
233 | |||
234 | /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons: | ||
235 | */ | ||
236 | if (!key->flatshade_first) { | ||
237 | sf.sf7.trifan_pv = 2; | ||
238 | sf.sf7.linestrip_pv = 1; | ||
239 | sf.sf7.tristrip_pv = 2; | ||
240 | } else { | ||
241 | sf.sf7.trifan_pv = 1; | ||
242 | sf.sf7.linestrip_pv = 0; | ||
243 | sf.sf7.tristrip_pv = 0; | ||
244 | } | ||
245 | |||
246 | sf.sf7.line_last_pixel_enable = key->line_last_pixel_enable; | ||
247 | |||
248 | /* Set bias for OpenGL rasterization rules: | ||
249 | */ | ||
250 | if (key->gl_rasterization_rules) { | ||
251 | sf.sf6.dest_org_vbias = 0x8; | ||
252 | sf.sf6.dest_org_hbias = 0x8; | ||
253 | } | ||
254 | else { | ||
255 | sf.sf6.dest_org_vbias = 0x0; | ||
256 | sf.sf6.dest_org_hbias = 0x0; | ||
257 | } | ||
258 | |||
259 | ret = brw_upload_cache(&brw->cache, BRW_SF_UNIT, | ||
260 | key, sizeof(*key), | ||
261 | reloc, 2, | ||
262 | &sf, sizeof(sf), | ||
263 | NULL, NULL, | ||
264 | bo_out); | ||
265 | if (ret) | ||
266 | return ret; | ||
267 | |||
268 | |||
269 | return PIPE_OK; | ||
270 | } | ||
271 | |||
272 | static enum pipe_error upload_sf_unit( struct brw_context *brw ) | ||
273 | { | ||
274 | struct brw_sf_unit_key key; | ||
275 | struct brw_winsys_reloc reloc[2]; | ||
276 | unsigned total_grf; | ||
277 | unsigned viewport_transform; | ||
278 | unsigned front_winding; | ||
279 | enum pipe_error ret; | ||
280 | |||
281 | sf_unit_populate_key(brw, &key); | ||
282 | |||
283 | /* XXX: cut this crap and pre calculate the key: | ||
284 | */ | ||
285 | total_grf = (align(key.total_grf, 16) / 16 - 1); | ||
286 | viewport_transform = 1; | ||
287 | front_winding = (key.front_ccw ? | ||
288 | BRW_FRONTWINDING_CCW : | ||
289 | BRW_FRONTWINDING_CW); | ||
290 | |||
291 | /* Emit SF program relocation */ | ||
292 | make_reloc(&reloc[0], | ||
293 | BRW_USAGE_STATE, | ||
294 | total_grf << 1, | ||
295 | offsetof(struct brw_sf_unit_state, thread0), | ||
296 | brw->sf.prog_bo); | ||
297 | |||
298 | /* Emit SF viewport relocation */ | ||
299 | make_reloc(&reloc[1], | ||
300 | BRW_USAGE_STATE, | ||
301 | front_winding | (viewport_transform << 1), | ||
302 | offsetof(struct brw_sf_unit_state, sf5), | ||
303 | brw->sf.vp_bo); | ||
304 | |||
305 | |||
306 | if (brw_search_cache(&brw->cache, BRW_SF_UNIT, | ||
307 | &key, sizeof(key), | ||
308 | reloc, 2, | ||
309 | NULL, | ||
310 | &brw->sf.state_bo)) | ||
311 | return PIPE_OK; | ||
312 | |||
313 | |||
314 | ret = sf_unit_create_from_key(brw, &key, | ||
315 | reloc, | ||
316 | &brw->sf.state_bo); | ||
317 | if (ret) | ||
318 | return ret; | ||
319 | |||
320 | return PIPE_OK; | ||
321 | } | ||
322 | |||
323 | const struct brw_tracked_state brw_sf_unit = { | ||
324 | .dirty = { | ||
325 | .mesa = (PIPE_NEW_RAST), | ||
326 | .brw = BRW_NEW_URB_FENCE, | ||
327 | .cache = (CACHE_NEW_SF_VP | | ||
328 | CACHE_NEW_SF_PROG) | ||
329 | }, | ||
330 | .prepare = upload_sf_unit, | ||
331 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_state.h b/src/gallium/drivers/i965/brw_state.h deleted file mode 100644 index 380d511f9bb..00000000000 --- a/src/gallium/drivers/i965/brw_state.h +++ /dev/null | |||
@@ -1,174 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_STATE_H | ||
34 | #define BRW_STATE_H | ||
35 | |||
36 | #include "pipe/p_defines.h" | ||
37 | #include "util/u_memory.h" | ||
38 | |||
39 | #include "brw_context.h" | ||
40 | |||
41 | static INLINE void | ||
42 | brw_add_validated_bo(struct brw_context *brw, struct brw_winsys_buffer *bo) | ||
43 | { | ||
44 | assert(brw->state.validated_bo_count < Elements(brw->state.validated_bos)); | ||
45 | |||
46 | if (bo != NULL) { | ||
47 | bo_reference( &brw->state.validated_bos[brw->state.validated_bo_count++], | ||
48 | bo ); | ||
49 | } | ||
50 | } | ||
51 | |||
52 | const struct brw_tracked_state brw_blend_constant_color; | ||
53 | const struct brw_tracked_state brw_cc_unit; | ||
54 | const struct brw_tracked_state brw_cc_vp; | ||
55 | const struct brw_tracked_state brw_clip_prog; | ||
56 | const struct brw_tracked_state brw_clip_unit; | ||
57 | const struct brw_tracked_state brw_curbe_buffer; | ||
58 | const struct brw_tracked_state brw_curbe_offsets; | ||
59 | const struct brw_tracked_state brw_invariant_state; | ||
60 | const struct brw_tracked_state brw_gs_prog; | ||
61 | const struct brw_tracked_state brw_gs_unit; | ||
62 | const struct brw_tracked_state brw_line_stipple; | ||
63 | const struct brw_tracked_state brw_aa_line_parameters; | ||
64 | const struct brw_tracked_state brw_pipelined_state_pointers; | ||
65 | const struct brw_tracked_state brw_binding_table_pointers; | ||
66 | const struct brw_tracked_state brw_depthbuffer; | ||
67 | const struct brw_tracked_state brw_polygon_stipple; | ||
68 | const struct brw_tracked_state brw_program_parameters; | ||
69 | const struct brw_tracked_state brw_recalculate_urb_fence; | ||
70 | const struct brw_tracked_state brw_sf_prog; | ||
71 | const struct brw_tracked_state brw_sf_unit; | ||
72 | const struct brw_tracked_state brw_sf_vp; | ||
73 | const struct brw_tracked_state brw_state_base_address; | ||
74 | const struct brw_tracked_state brw_urb_fence; | ||
75 | const struct brw_tracked_state brw_vertex_state; | ||
76 | const struct brw_tracked_state brw_vs_surfaces; | ||
77 | const struct brw_tracked_state brw_vs_prog; | ||
78 | const struct brw_tracked_state brw_vs_unit; | ||
79 | const struct brw_tracked_state brw_wm_input_sizes; | ||
80 | const struct brw_tracked_state brw_wm_prog; | ||
81 | const struct brw_tracked_state brw_wm_samplers; | ||
82 | const struct brw_tracked_state brw_wm_constant_surface; | ||
83 | const struct brw_tracked_state brw_wm_surfaces; | ||
84 | const struct brw_tracked_state brw_wm_unit; | ||
85 | |||
86 | const struct brw_tracked_state brw_psp_urb_cbs; | ||
87 | |||
88 | const struct brw_tracked_state brw_pipe_control; | ||
89 | |||
90 | const struct brw_tracked_state brw_drawing_rect; | ||
91 | const struct brw_tracked_state brw_indices; | ||
92 | const struct brw_tracked_state brw_vertices; | ||
93 | const struct brw_tracked_state brw_index_buffer; | ||
94 | |||
95 | |||
96 | /*********************************************************************** | ||
97 | * brw_state.c | ||
98 | */ | ||
99 | int brw_validate_state(struct brw_context *brw); | ||
100 | int brw_upload_state(struct brw_context *brw); | ||
101 | void brw_init_state(struct brw_context *brw); | ||
102 | void brw_destroy_state(struct brw_context *brw); | ||
103 | |||
104 | /*********************************************************************** | ||
105 | * brw_state_cache.c | ||
106 | */ | ||
107 | enum pipe_error brw_cache_data(struct brw_cache *cache, | ||
108 | enum brw_cache_id cache_id, | ||
109 | const void *data, | ||
110 | struct brw_winsys_reloc *relocs, | ||
111 | GLuint nr_relocs, | ||
112 | struct brw_winsys_buffer **bo_out ); | ||
113 | |||
114 | enum pipe_error brw_cache_data_sz(struct brw_cache *cache, | ||
115 | enum brw_cache_id cache_id, | ||
116 | const void *data, | ||
117 | GLuint data_size, | ||
118 | struct brw_winsys_reloc *relocs, | ||
119 | GLuint nr_relocs, | ||
120 | struct brw_winsys_buffer **bo_out); | ||
121 | |||
122 | enum pipe_error brw_upload_cache( struct brw_cache *cache, | ||
123 | enum brw_cache_id cache_id, | ||
124 | const void *key, | ||
125 | GLuint key_sz, | ||
126 | struct brw_winsys_reloc *relocs, | ||
127 | GLuint nr_relocs, | ||
128 | const void *data, | ||
129 | GLuint data_sz, | ||
130 | const void *aux, | ||
131 | void *aux_return , | ||
132 | struct brw_winsys_buffer **bo_out); | ||
133 | |||
134 | boolean brw_search_cache( struct brw_cache *cache, | ||
135 | enum brw_cache_id cache_id, | ||
136 | const void *key, | ||
137 | GLuint key_size, | ||
138 | struct brw_winsys_reloc *relocs, | ||
139 | GLuint nr_relocs, | ||
140 | void *aux_return, | ||
141 | struct brw_winsys_buffer **bo_out); | ||
142 | |||
143 | void brw_state_cache_check_size( struct brw_context *brw ); | ||
144 | |||
145 | void brw_init_caches( struct brw_context *brw ); | ||
146 | void brw_destroy_caches( struct brw_context *brw ); | ||
147 | void brw_state_cache_bo_delete(struct brw_cache *cache, struct brw_winsys_buffer *bo); | ||
148 | |||
149 | /*********************************************************************** | ||
150 | * brw_state_batch.c | ||
151 | */ | ||
152 | #define BRW_BATCH_STRUCT(brw, s) brw_batchbuffer_data( brw->batch, (s), sizeof(*(s)), IGNORE_CLIPRECTS) | ||
153 | #define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) ) | ||
154 | |||
155 | GLboolean brw_cached_batch_struct( struct brw_context *brw, | ||
156 | const void *data, | ||
157 | GLuint sz ); | ||
158 | void brw_destroy_batch_cache( struct brw_context *brw ); | ||
159 | void brw_clear_batch_cache( struct brw_context *brw ); | ||
160 | |||
161 | /*********************************************************************** | ||
162 | * brw_wm_surface_state.c | ||
163 | */ | ||
164 | |||
165 | /*********************************************************************** | ||
166 | * brw_state_debug.c | ||
167 | */ | ||
168 | void brw_update_dirty_counts( unsigned mesa, | ||
169 | unsigned brw, | ||
170 | unsigned cache ); | ||
171 | |||
172 | |||
173 | |||
174 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_state_batch.c b/src/gallium/drivers/i965/brw_state_batch.c deleted file mode 100644 index ce5ed0a9ed2..00000000000 --- a/src/gallium/drivers/i965/brw_state_batch.c +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | |||
34 | #include "brw_state.h" | ||
35 | #include "brw_batchbuffer.h" | ||
36 | |||
37 | |||
38 | |||
39 | /* A facility similar to the data caching code above, which aims to | ||
40 | * prevent identical commands being issued repeatedly. | ||
41 | */ | ||
42 | GLboolean brw_cached_batch_struct( struct brw_context *brw, | ||
43 | const void *data, | ||
44 | GLuint sz ) | ||
45 | { | ||
46 | struct brw_cached_batch_item *item = brw->cached_batch_items; | ||
47 | struct header *newheader = (struct header *)data; | ||
48 | |||
49 | if (brw->flags.always_emit_state) { | ||
50 | brw_batchbuffer_data(brw->batch, data, sz, IGNORE_CLIPRECTS); | ||
51 | return GL_TRUE; | ||
52 | } | ||
53 | |||
54 | while (item) { | ||
55 | if (item->header->opcode == newheader->opcode) { | ||
56 | if (item->sz == sz && memcmp(item->header, newheader, sz) == 0) | ||
57 | return GL_FALSE; | ||
58 | if (item->sz != sz) { | ||
59 | FREE(item->header); | ||
60 | item->header = MALLOC(sz); | ||
61 | item->sz = sz; | ||
62 | } | ||
63 | goto emit; | ||
64 | } | ||
65 | item = item->next; | ||
66 | } | ||
67 | |||
68 | assert(!item); | ||
69 | item = CALLOC_STRUCT(brw_cached_batch_item); | ||
70 | item->header = MALLOC(sz); | ||
71 | item->sz = sz; | ||
72 | item->next = brw->cached_batch_items; | ||
73 | brw->cached_batch_items = item; | ||
74 | |||
75 | emit: | ||
76 | memcpy(item->header, newheader, sz); | ||
77 | brw_batchbuffer_data(brw->batch, data, sz, IGNORE_CLIPRECTS); | ||
78 | return GL_TRUE; | ||
79 | } | ||
80 | |||
81 | void brw_clear_batch_cache( struct brw_context *brw ) | ||
82 | { | ||
83 | struct brw_cached_batch_item *item = brw->cached_batch_items; | ||
84 | |||
85 | while (item) { | ||
86 | struct brw_cached_batch_item *next = item->next; | ||
87 | FREE((void *)item->header); | ||
88 | FREE(item); | ||
89 | item = next; | ||
90 | } | ||
91 | |||
92 | brw->cached_batch_items = NULL; | ||
93 | } | ||
94 | |||
95 | void brw_destroy_batch_cache( struct brw_context *brw ) | ||
96 | { | ||
97 | brw_clear_batch_cache(brw); | ||
98 | } | ||
diff --git a/src/gallium/drivers/i965/brw_state_cache.c b/src/gallium/drivers/i965/brw_state_cache.c deleted file mode 100644 index c911f3997d1..00000000000 --- a/src/gallium/drivers/i965/brw_state_cache.c +++ /dev/null | |||
@@ -1,617 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | /** @file brw_state_cache.c | ||
33 | * | ||
34 | * This file implements a simple static state cache for 965. The consumers | ||
35 | * can query the hash table of state using a cache_id, opaque key data, | ||
36 | * and list of buffers that will be used in relocations, and receive the | ||
37 | * corresponding state buffer object of state (plus associated auxiliary | ||
38 | * data) in return. | ||
39 | * | ||
40 | * The inner workings are a simple hash table based on a CRC of the key data. | ||
41 | * The cache_id and relocation target buffers associated with the state | ||
42 | * buffer are included as auxiliary key data, but are not part of the hash | ||
43 | * value (this should be fixed, but will likely be fixed instead by making | ||
44 | * consumers use structured keys). | ||
45 | * | ||
46 | * Replacement is not implemented. Instead, when the cache gets too big, at | ||
47 | * a safe point (unlock) we throw out all of the cache data and let it | ||
48 | * regenerate for the next rendering operation. | ||
49 | * | ||
50 | * The reloc structs need to be included as key data, otherwise the | ||
51 | * non-unique values stuffed in the offset in key data through | ||
52 | * brw_cache_data() may result in successful probe for state buffers | ||
53 | * even when the buffer being referenced doesn't match. The result would be | ||
54 | * that the same state cache entry is used twice for different buffers, | ||
55 | * only one of the two buffers referenced gets put into the offset, and the | ||
56 | * incorrect program is run for the other instance. | ||
57 | */ | ||
58 | #include "util/u_memory.h" | ||
59 | |||
60 | #include "brw_debug.h" | ||
61 | #include "brw_state.h" | ||
62 | |||
63 | /* XXX: Fixme - have to include these to get the sizes of the prog_key | ||
64 | * structs: | ||
65 | */ | ||
66 | #include "brw_wm.h" | ||
67 | #include "brw_vs.h" | ||
68 | #include "brw_clip.h" | ||
69 | #include "brw_sf.h" | ||
70 | #include "brw_gs.h" | ||
71 | |||
72 | |||
73 | static GLuint | ||
74 | hash_key(const void *key, GLuint key_size, | ||
75 | struct brw_winsys_reloc *relocs, GLuint nr_relocs) | ||
76 | { | ||
77 | GLuint *ikey = (GLuint *)key; | ||
78 | GLuint hash = 0, i; | ||
79 | |||
80 | assert(key_size % 4 == 0); | ||
81 | |||
82 | /* I'm sure this can be improved on: | ||
83 | */ | ||
84 | for (i = 0; i < key_size/4; i++) { | ||
85 | hash ^= ikey[i]; | ||
86 | hash = (hash << 5) | (hash >> 27); | ||
87 | } | ||
88 | |||
89 | /* Include the BO pointers as key data as well */ | ||
90 | ikey = (GLuint *)relocs; | ||
91 | key_size = nr_relocs * sizeof(struct brw_winsys_reloc); | ||
92 | for (i = 0; i < key_size/4; i++) { | ||
93 | hash ^= ikey[i]; | ||
94 | hash = (hash << 5) | (hash >> 27); | ||
95 | } | ||
96 | |||
97 | return hash; | ||
98 | } | ||
99 | |||
100 | |||
101 | /** | ||
102 | * Marks a new buffer as being chosen for the given cache id. | ||
103 | */ | ||
104 | static void | ||
105 | update_cache_last(struct brw_cache *cache, enum brw_cache_id cache_id, | ||
106 | struct brw_winsys_buffer *bo) | ||
107 | { | ||
108 | if (bo == cache->last_bo[cache_id]) | ||
109 | return; /* no change */ | ||
110 | |||
111 | bo_reference( &cache->last_bo[cache_id], bo ); | ||
112 | |||
113 | cache->brw->state.dirty.cache |= 1 << cache_id; | ||
114 | } | ||
115 | |||
116 | |||
117 | static struct brw_cache_item * | ||
118 | search_cache(struct brw_cache *cache, enum brw_cache_id cache_id, | ||
119 | GLuint hash, const void *key, GLuint key_size, | ||
120 | struct brw_winsys_reloc *relocs, GLuint nr_relocs) | ||
121 | { | ||
122 | struct brw_cache_item *c; | ||
123 | |||
124 | #if 0 | ||
125 | int bucketcount = 0; | ||
126 | |||
127 | for (c = cache->items[hash % cache->size]; c; c = c->next) | ||
128 | bucketcount++; | ||
129 | |||
130 | debug_printf("bucket %d/%d = %d/%d items\n", hash % cache->size, | ||
131 | cache->size, bucketcount, cache->n_items); | ||
132 | #endif | ||
133 | |||
134 | for (c = cache->items[hash % cache->size]; c; c = c->next) { | ||
135 | if (c->cache_id == cache_id && | ||
136 | c->hash == hash && | ||
137 | c->key_size == key_size && | ||
138 | memcmp(c->key, key, key_size) == 0 && | ||
139 | c->nr_relocs == nr_relocs && | ||
140 | memcmp(c->relocs, relocs, nr_relocs * sizeof *relocs) == 0) | ||
141 | return c; | ||
142 | } | ||
143 | |||
144 | return NULL; | ||
145 | } | ||
146 | |||
147 | |||
148 | static void | ||
149 | rehash(struct brw_cache *cache) | ||
150 | { | ||
151 | struct brw_cache_item **items; | ||
152 | struct brw_cache_item *c, *next; | ||
153 | GLuint size, i; | ||
154 | |||
155 | size = cache->size * 3; | ||
156 | items = (struct brw_cache_item**) CALLOC(size, sizeof(*items)); | ||
157 | |||
158 | for (i = 0; i < cache->size; i++) | ||
159 | for (c = cache->items[i]; c; c = next) { | ||
160 | next = c->next; | ||
161 | c->next = items[c->hash % size]; | ||
162 | items[c->hash % size] = c; | ||
163 | } | ||
164 | |||
165 | FREE(cache->items); | ||
166 | cache->items = items; | ||
167 | cache->size = size; | ||
168 | } | ||
169 | |||
170 | |||
171 | /** | ||
172 | * Returns the buffer object matching cache_id and key, or NULL. | ||
173 | */ | ||
174 | boolean | ||
175 | brw_search_cache(struct brw_cache *cache, | ||
176 | enum brw_cache_id cache_id, | ||
177 | const void *key, | ||
178 | GLuint key_size, | ||
179 | struct brw_winsys_reloc *relocs, | ||
180 | GLuint nr_relocs, | ||
181 | void *aux_return, | ||
182 | struct brw_winsys_buffer **bo_out) | ||
183 | { | ||
184 | struct brw_cache_item *item; | ||
185 | GLuint hash = hash_key(key, key_size, relocs, nr_relocs); | ||
186 | |||
187 | item = search_cache(cache, cache_id, hash, key, key_size, | ||
188 | relocs, nr_relocs); | ||
189 | |||
190 | if (item) { | ||
191 | if (aux_return) | ||
192 | *(void **)aux_return = (void *)((char *)item->key + item->key_size); | ||
193 | |||
194 | update_cache_last(cache, cache_id, item->bo); | ||
195 | bo_reference(bo_out, item->bo); | ||
196 | return TRUE; | ||
197 | } | ||
198 | |||
199 | return FALSE; | ||
200 | } | ||
201 | |||
202 | |||
203 | enum pipe_error | ||
204 | brw_upload_cache( struct brw_cache *cache, | ||
205 | enum brw_cache_id cache_id, | ||
206 | const void *key, | ||
207 | GLuint key_size, | ||
208 | struct brw_winsys_reloc *relocs, | ||
209 | GLuint nr_relocs, | ||
210 | const void *data, | ||
211 | GLuint data_size, | ||
212 | const void *aux, | ||
213 | void *aux_return, | ||
214 | struct brw_winsys_buffer **bo_out) | ||
215 | { | ||
216 | struct brw_cache_item *item; | ||
217 | GLuint hash = hash_key(key, key_size, relocs, nr_relocs); | ||
218 | GLuint relocs_size = nr_relocs * sizeof relocs[0]; | ||
219 | GLuint aux_size = cache->aux_size[cache_id]; | ||
220 | enum pipe_error ret; | ||
221 | void *tmp; | ||
222 | int i; | ||
223 | |||
224 | /* Create the buffer object to contain the data. For now, use a | ||
225 | * single buffer type to describe all cached state atoms. Later, | ||
226 | * may want to take advantage of hardware distinctions between | ||
227 | * these various entities. | ||
228 | */ | ||
229 | ret = cache->sws->bo_alloc(cache->sws, | ||
230 | cache->buffer_type, | ||
231 | data_size, 1 << 6, | ||
232 | bo_out); | ||
233 | if (ret) | ||
234 | return ret; | ||
235 | |||
236 | item = CALLOC_STRUCT(brw_cache_item); | ||
237 | |||
238 | /* Set up the memory containing the key, aux_data, and relocs */ | ||
239 | tmp = MALLOC(key_size + aux_size + relocs_size); | ||
240 | |||
241 | memcpy(tmp, key, key_size); | ||
242 | memcpy((char *)tmp + key_size, aux, cache->aux_size[cache_id]); | ||
243 | memcpy((char *)tmp + key_size + aux_size, relocs, relocs_size); | ||
244 | for (i = 0; i < nr_relocs; i++) { | ||
245 | p_atomic_inc(&relocs[i].bo->reference.count); | ||
246 | } | ||
247 | |||
248 | item->cache_id = cache_id; | ||
249 | item->key = tmp; | ||
250 | item->hash = hash; | ||
251 | item->key_size = key_size; | ||
252 | item->relocs = (struct brw_winsys_reloc *)((char *)tmp + key_size + aux_size); | ||
253 | item->nr_relocs = nr_relocs; | ||
254 | bo_reference( &item->bo, *bo_out ); | ||
255 | item->data_size = data_size; | ||
256 | |||
257 | if (cache->n_items > cache->size * 1.5) | ||
258 | rehash(cache); | ||
259 | |||
260 | hash %= cache->size; | ||
261 | item->next = cache->items[hash]; | ||
262 | cache->items[hash] = item; | ||
263 | cache->n_items++; | ||
264 | |||
265 | if (aux_return) { | ||
266 | assert(cache->aux_size[cache_id]); | ||
267 | *(void **)aux_return = (void *)((char *)item->key + item->key_size); | ||
268 | } | ||
269 | |||
270 | if (BRW_DEBUG & DEBUG_STATE) | ||
271 | debug_printf("upload %s: %d bytes to cache id %d\n", | ||
272 | cache->name[cache_id], | ||
273 | data_size, cache_id); | ||
274 | |||
275 | /* Copy data to the buffer */ | ||
276 | ret = cache->sws->bo_subdata(item->bo, | ||
277 | cache_id, | ||
278 | 0, data_size, data, | ||
279 | relocs, nr_relocs); | ||
280 | if (ret) | ||
281 | return ret; | ||
282 | |||
283 | update_cache_last(cache, cache_id, item->bo); | ||
284 | |||
285 | return PIPE_OK; | ||
286 | } | ||
287 | |||
288 | |||
289 | /** | ||
290 | * This doesn't really work with aux data. Use search/upload instead | ||
291 | */ | ||
292 | enum pipe_error | ||
293 | brw_cache_data_sz(struct brw_cache *cache, | ||
294 | enum brw_cache_id cache_id, | ||
295 | const void *data, | ||
296 | GLuint data_size, | ||
297 | struct brw_winsys_reloc *relocs, | ||
298 | GLuint nr_relocs, | ||
299 | struct brw_winsys_buffer **bo_out) | ||
300 | { | ||
301 | struct brw_cache_item *item; | ||
302 | GLuint hash = hash_key(data, data_size, relocs, nr_relocs); | ||
303 | |||
304 | item = search_cache(cache, cache_id, hash, data, data_size, | ||
305 | relocs, nr_relocs); | ||
306 | if (item) { | ||
307 | update_cache_last(cache, cache_id, item->bo); | ||
308 | |||
309 | bo_reference(bo_out, item->bo); | ||
310 | return PIPE_OK; | ||
311 | } | ||
312 | |||
313 | return brw_upload_cache(cache, cache_id, | ||
314 | data, data_size, | ||
315 | relocs, nr_relocs, | ||
316 | data, data_size, | ||
317 | NULL, NULL, | ||
318 | bo_out); | ||
319 | } | ||
320 | |||
321 | |||
322 | /** | ||
323 | * Wrapper around brw_cache_data_sz using the cache_id's canonical key size. | ||
324 | * | ||
325 | * If nr_relocs is nonzero, brw_search_cache()/brw_upload_cache() would be | ||
326 | * better to use, as the potentially changing offsets in the data-used-as-key | ||
327 | * will result in excessive cache misses. | ||
328 | * | ||
329 | * XXX: above is no longer true -- can we remove some code? | ||
330 | */ | ||
331 | enum pipe_error | ||
332 | brw_cache_data(struct brw_cache *cache, | ||
333 | enum brw_cache_id cache_id, | ||
334 | const void *data, | ||
335 | struct brw_winsys_reloc *relocs, | ||
336 | GLuint nr_relocs, | ||
337 | struct brw_winsys_buffer **bo_out) | ||
338 | { | ||
339 | return brw_cache_data_sz(cache, cache_id, data, cache->key_size[cache_id], | ||
340 | relocs, nr_relocs, bo_out); | ||
341 | } | ||
342 | |||
343 | |||
344 | static void | ||
345 | brw_init_cache_id(struct brw_cache *cache, | ||
346 | const char *name, | ||
347 | enum brw_cache_id id, | ||
348 | GLuint key_size, | ||
349 | GLuint aux_size) | ||
350 | { | ||
351 | cache->name[id] = strdup(name); | ||
352 | cache->key_size[id] = key_size; | ||
353 | cache->aux_size[id] = aux_size; | ||
354 | } | ||
355 | |||
356 | |||
357 | static void | ||
358 | brw_init_general_state_cache(struct brw_context *brw) | ||
359 | { | ||
360 | struct brw_cache *cache = &brw->cache; | ||
361 | |||
362 | cache->brw = brw; | ||
363 | cache->sws = brw->sws; | ||
364 | |||
365 | cache->buffer_type = BRW_BUFFER_TYPE_GENERAL_STATE; | ||
366 | |||
367 | cache->size = 7; | ||
368 | cache->n_items = 0; | ||
369 | cache->items = (struct brw_cache_item **) | ||
370 | CALLOC(cache->size, sizeof(struct brw_cache_item)); | ||
371 | |||
372 | brw_init_cache_id(cache, | ||
373 | "CC_VP", | ||
374 | BRW_CC_VP, | ||
375 | sizeof(struct brw_cc_viewport), | ||
376 | 0); | ||
377 | |||
378 | brw_init_cache_id(cache, | ||
379 | "CC_UNIT", | ||
380 | BRW_CC_UNIT, | ||
381 | sizeof(struct brw_cc_unit_state), | ||
382 | 0); | ||
383 | |||
384 | brw_init_cache_id(cache, | ||
385 | "WM_PROG", | ||
386 | BRW_WM_PROG, | ||
387 | sizeof(struct brw_wm_prog_key), | ||
388 | sizeof(struct brw_wm_prog_data)); | ||
389 | |||
390 | brw_init_cache_id(cache, | ||
391 | "SAMPLER_DEFAULT_COLOR", | ||
392 | BRW_SAMPLER_DEFAULT_COLOR, | ||
393 | sizeof(struct brw_sampler_default_color), | ||
394 | 0); | ||
395 | |||
396 | brw_init_cache_id(cache, | ||
397 | "SAMPLER", | ||
398 | BRW_SAMPLER, | ||
399 | 0, /* variable key/data size */ | ||
400 | 0); | ||
401 | |||
402 | brw_init_cache_id(cache, | ||
403 | "WM_UNIT", | ||
404 | BRW_WM_UNIT, | ||
405 | sizeof(struct brw_wm_unit_state), | ||
406 | 0); | ||
407 | |||
408 | brw_init_cache_id(cache, | ||
409 | "SF_PROG", | ||
410 | BRW_SF_PROG, | ||
411 | sizeof(struct brw_sf_prog_key), | ||
412 | sizeof(struct brw_sf_prog_data)); | ||
413 | |||
414 | brw_init_cache_id(cache, | ||
415 | "SF_VP", | ||
416 | BRW_SF_VP, | ||
417 | sizeof(struct brw_sf_viewport), | ||
418 | 0); | ||
419 | |||
420 | brw_init_cache_id(cache, | ||
421 | "SF_UNIT", | ||
422 | BRW_SF_UNIT, | ||
423 | sizeof(struct brw_sf_unit_state), | ||
424 | 0); | ||
425 | |||
426 | brw_init_cache_id(cache, | ||
427 | "VS_UNIT", | ||
428 | BRW_VS_UNIT, | ||
429 | sizeof(struct brw_vs_unit_state), | ||
430 | 0); | ||
431 | |||
432 | brw_init_cache_id(cache, | ||
433 | "VS_PROG", | ||
434 | BRW_VS_PROG, | ||
435 | sizeof(struct brw_vs_prog_key), | ||
436 | sizeof(struct brw_vs_prog_data)); | ||
437 | |||
438 | brw_init_cache_id(cache, | ||
439 | "CLIP_UNIT", | ||
440 | BRW_CLIP_UNIT, | ||
441 | sizeof(struct brw_clip_unit_state), | ||
442 | 0); | ||
443 | |||
444 | brw_init_cache_id(cache, | ||
445 | "CLIP_PROG", | ||
446 | BRW_CLIP_PROG, | ||
447 | sizeof(struct brw_clip_prog_key), | ||
448 | sizeof(struct brw_clip_prog_data)); | ||
449 | |||
450 | brw_init_cache_id(cache, | ||
451 | "GS_UNIT", | ||
452 | BRW_GS_UNIT, | ||
453 | sizeof(struct brw_gs_unit_state), | ||
454 | 0); | ||
455 | |||
456 | brw_init_cache_id(cache, | ||
457 | "GS_PROG", | ||
458 | BRW_GS_PROG, | ||
459 | sizeof(struct brw_gs_prog_key), | ||
460 | sizeof(struct brw_gs_prog_data)); | ||
461 | } | ||
462 | |||
463 | |||
464 | static void | ||
465 | brw_init_surface_state_cache(struct brw_context *brw) | ||
466 | { | ||
467 | struct brw_cache *cache = &brw->surface_cache; | ||
468 | |||
469 | cache->brw = brw; | ||
470 | cache->sws = brw->sws; | ||
471 | |||
472 | cache->buffer_type = BRW_BUFFER_TYPE_SURFACE_STATE; | ||
473 | |||
474 | cache->size = 7; | ||
475 | cache->n_items = 0; | ||
476 | cache->items = (struct brw_cache_item **) | ||
477 | CALLOC(cache->size, sizeof(struct brw_cache_item)); | ||
478 | |||
479 | brw_init_cache_id(cache, | ||
480 | "SS_SURFACE", | ||
481 | BRW_SS_SURFACE, | ||
482 | sizeof(struct brw_surface_state), | ||
483 | 0); | ||
484 | |||
485 | brw_init_cache_id(cache, | ||
486 | "SS_SURF_BIND", | ||
487 | BRW_SS_SURF_BIND, | ||
488 | 0, | ||
489 | 0); | ||
490 | } | ||
491 | |||
492 | |||
493 | void | ||
494 | brw_init_caches(struct brw_context *brw) | ||
495 | { | ||
496 | brw_init_general_state_cache(brw); | ||
497 | brw_init_surface_state_cache(brw); | ||
498 | } | ||
499 | |||
500 | |||
501 | static void | ||
502 | brw_clear_cache(struct brw_context *brw, struct brw_cache *cache) | ||
503 | { | ||
504 | struct brw_cache_item *c, *next; | ||
505 | GLuint i; | ||
506 | |||
507 | if (BRW_DEBUG & DEBUG_STATE) | ||
508 | debug_printf("%s\n", __FUNCTION__); | ||
509 | |||
510 | for (i = 0; i < cache->size; i++) { | ||
511 | for (c = cache->items[i]; c; c = next) { | ||
512 | int j; | ||
513 | |||
514 | next = c->next; | ||
515 | |||
516 | for (j = 0; j < c->nr_relocs; j++) | ||
517 | bo_reference(&c->relocs[j].bo, NULL); | ||
518 | |||
519 | bo_reference(&c->bo, NULL); | ||
520 | FREE((void *)c->key); | ||
521 | FREE(c); | ||
522 | } | ||
523 | cache->items[i] = NULL; | ||
524 | } | ||
525 | |||
526 | cache->n_items = 0; | ||
527 | |||
528 | if (brw->curbe.last_buf) { | ||
529 | FREE(brw->curbe.last_buf); | ||
530 | brw->curbe.last_buf = NULL; | ||
531 | } | ||
532 | |||
533 | brw->state.dirty.mesa |= ~0; | ||
534 | brw->state.dirty.brw |= ~0; | ||
535 | brw->state.dirty.cache |= ~0; | ||
536 | } | ||
537 | |||
538 | /* Clear all entries from the cache that point to the given bo. | ||
539 | * | ||
540 | * This lets us release memory for reuse earlier for known-dead buffers, | ||
541 | * at the cost of walking the entire hash table. | ||
542 | */ | ||
543 | void | ||
544 | brw_state_cache_bo_delete(struct brw_cache *cache, struct brw_winsys_buffer *bo) | ||
545 | { | ||
546 | struct brw_cache_item **prev; | ||
547 | GLuint i; | ||
548 | |||
549 | if (BRW_DEBUG & DEBUG_STATE) | ||
550 | debug_printf("%s\n", __FUNCTION__); | ||
551 | |||
552 | for (i = 0; i < cache->size; i++) { | ||
553 | for (prev = &cache->items[i]; *prev;) { | ||
554 | struct brw_cache_item *c = *prev; | ||
555 | |||
556 | if (cache->sws->bo_references(c->bo, bo)) { | ||
557 | int j; | ||
558 | |||
559 | *prev = c->next; | ||
560 | |||
561 | for (j = 0; j < c->nr_relocs; j++) | ||
562 | bo_reference(&c->relocs[j].bo, NULL); | ||
563 | |||
564 | bo_reference(&c->bo, NULL); | ||
565 | |||
566 | FREE((void *)c->key); | ||
567 | FREE(c); | ||
568 | cache->n_items--; | ||
569 | } else { | ||
570 | prev = &c->next; | ||
571 | } | ||
572 | } | ||
573 | } | ||
574 | } | ||
575 | |||
576 | void | ||
577 | brw_state_cache_check_size(struct brw_context *brw) | ||
578 | { | ||
579 | if (BRW_DEBUG & DEBUG_STATE) | ||
580 | debug_printf("%s (n_items=%d)\n", __FUNCTION__, brw->cache.n_items); | ||
581 | |||
582 | /* un-tuned guess. We've got around 20 state objects for a total of around | ||
583 | * 32k, so 1000 of them is around 1.5MB. | ||
584 | */ | ||
585 | if (brw->cache.n_items > 1000) | ||
586 | brw_clear_cache(brw, &brw->cache); | ||
587 | |||
588 | if (brw->surface_cache.n_items > 1000) | ||
589 | brw_clear_cache(brw, &brw->surface_cache); | ||
590 | } | ||
591 | |||
592 | |||
593 | static void | ||
594 | brw_destroy_cache(struct brw_context *brw, struct brw_cache *cache) | ||
595 | { | ||
596 | GLuint i; | ||
597 | |||
598 | if (BRW_DEBUG & DEBUG_STATE) | ||
599 | debug_printf("%s\n", __FUNCTION__); | ||
600 | |||
601 | brw_clear_cache(brw, cache); | ||
602 | for (i = 0; i < BRW_MAX_CACHE; i++) { | ||
603 | bo_reference(&cache->last_bo[i], NULL); | ||
604 | FREE(cache->name[i]); | ||
605 | } | ||
606 | FREE(cache->items); | ||
607 | cache->items = NULL; | ||
608 | cache->size = 0; | ||
609 | } | ||
610 | |||
611 | |||
612 | void | ||
613 | brw_destroy_caches(struct brw_context *brw) | ||
614 | { | ||
615 | brw_destroy_cache(brw, &brw->cache); | ||
616 | brw_destroy_cache(brw, &brw->surface_cache); | ||
617 | } | ||
diff --git a/src/gallium/drivers/i965/brw_state_debug.c b/src/gallium/drivers/i965/brw_state_debug.c deleted file mode 100644 index 049c278c93e..00000000000 --- a/src/gallium/drivers/i965/brw_state_debug.c +++ /dev/null | |||
@@ -1,153 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | |||
28 | |||
29 | |||
30 | #include "brw_context.h" | ||
31 | #include "brw_state.h" | ||
32 | |||
33 | |||
34 | struct dirty_bit_map { | ||
35 | uint32_t bit; | ||
36 | char *name; | ||
37 | uint32_t count; | ||
38 | }; | ||
39 | |||
40 | #define DEFINE_BIT(name) {name, #name, 0} | ||
41 | |||
42 | static struct dirty_bit_map mesa_bits[] = { | ||
43 | DEFINE_BIT(PIPE_NEW_DEPTH_STENCIL_ALPHA), | ||
44 | DEFINE_BIT(PIPE_NEW_RAST), | ||
45 | DEFINE_BIT(PIPE_NEW_BLEND), | ||
46 | DEFINE_BIT(PIPE_NEW_VIEWPORT), | ||
47 | DEFINE_BIT(PIPE_NEW_SAMPLERS), | ||
48 | DEFINE_BIT(PIPE_NEW_VERTEX_BUFFER), | ||
49 | DEFINE_BIT(PIPE_NEW_VERTEX_ELEMENT), | ||
50 | DEFINE_BIT(PIPE_NEW_FRAGMENT_SHADER), | ||
51 | DEFINE_BIT(PIPE_NEW_VERTEX_SHADER), | ||
52 | DEFINE_BIT(PIPE_NEW_FRAGMENT_CONSTANTS), | ||
53 | DEFINE_BIT(PIPE_NEW_VERTEX_CONSTANTS), | ||
54 | DEFINE_BIT(PIPE_NEW_CLIP), | ||
55 | DEFINE_BIT(PIPE_NEW_INDEX_BUFFER), | ||
56 | DEFINE_BIT(PIPE_NEW_INDEX_RANGE), | ||
57 | DEFINE_BIT(PIPE_NEW_BLEND_COLOR), | ||
58 | DEFINE_BIT(PIPE_NEW_POLYGON_STIPPLE), | ||
59 | DEFINE_BIT(PIPE_NEW_FRAMEBUFFER_DIMENSIONS), | ||
60 | DEFINE_BIT(PIPE_NEW_DEPTH_BUFFER), | ||
61 | DEFINE_BIT(PIPE_NEW_COLOR_BUFFERS), | ||
62 | DEFINE_BIT(PIPE_NEW_QUERY), | ||
63 | DEFINE_BIT(PIPE_NEW_SCISSOR), | ||
64 | DEFINE_BIT(PIPE_NEW_BOUND_TEXTURES), | ||
65 | DEFINE_BIT(PIPE_NEW_NR_CBUFS), | ||
66 | {0, 0, 0} | ||
67 | }; | ||
68 | |||
69 | static struct dirty_bit_map brw_bits[] = { | ||
70 | DEFINE_BIT(BRW_NEW_URB_FENCE), | ||
71 | DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM), | ||
72 | DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM), | ||
73 | DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS), | ||
74 | DEFINE_BIT(BRW_NEW_CURBE_OFFSETS), | ||
75 | DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE), | ||
76 | DEFINE_BIT(BRW_NEW_PRIMITIVE), | ||
77 | DEFINE_BIT(BRW_NEW_CONTEXT), | ||
78 | DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS), | ||
79 | DEFINE_BIT(BRW_NEW_PSP), | ||
80 | DEFINE_BIT(BRW_NEW_WM_SURFACES), | ||
81 | DEFINE_BIT(BRW_NEW_xxx), | ||
82 | DEFINE_BIT(BRW_NEW_INDICES), | ||
83 | {0, 0, 0} | ||
84 | }; | ||
85 | |||
86 | static struct dirty_bit_map cache_bits[] = { | ||
87 | DEFINE_BIT(CACHE_NEW_CC_VP), | ||
88 | DEFINE_BIT(CACHE_NEW_CC_UNIT), | ||
89 | DEFINE_BIT(CACHE_NEW_WM_PROG), | ||
90 | DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR), | ||
91 | DEFINE_BIT(CACHE_NEW_SAMPLER), | ||
92 | DEFINE_BIT(CACHE_NEW_WM_UNIT), | ||
93 | DEFINE_BIT(CACHE_NEW_SF_PROG), | ||
94 | DEFINE_BIT(CACHE_NEW_SF_VP), | ||
95 | DEFINE_BIT(CACHE_NEW_SF_UNIT), | ||
96 | DEFINE_BIT(CACHE_NEW_VS_UNIT), | ||
97 | DEFINE_BIT(CACHE_NEW_VS_PROG), | ||
98 | DEFINE_BIT(CACHE_NEW_GS_UNIT), | ||
99 | DEFINE_BIT(CACHE_NEW_GS_PROG), | ||
100 | DEFINE_BIT(CACHE_NEW_CLIP_VP), | ||
101 | DEFINE_BIT(CACHE_NEW_CLIP_UNIT), | ||
102 | DEFINE_BIT(CACHE_NEW_CLIP_PROG), | ||
103 | DEFINE_BIT(CACHE_NEW_SURFACE), | ||
104 | DEFINE_BIT(CACHE_NEW_SURF_BIND), | ||
105 | {0, 0, 0} | ||
106 | }; | ||
107 | |||
108 | |||
109 | static void | ||
110 | brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) | ||
111 | { | ||
112 | int i; | ||
113 | |||
114 | for (i = 0; i < 32; i++) { | ||
115 | if (bit_map[i].bit == 0) | ||
116 | return; | ||
117 | |||
118 | if (bit_map[i].bit & bits) | ||
119 | bit_map[i].count++; | ||
120 | } | ||
121 | } | ||
122 | |||
123 | static void | ||
124 | brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) | ||
125 | { | ||
126 | int i; | ||
127 | |||
128 | for (i = 0; i < 32; i++) { | ||
129 | if (bit_map[i].bit == 0) | ||
130 | return; | ||
131 | |||
132 | debug_printf("0x%08x: %12d (%s)\n", | ||
133 | bit_map[i].bit, bit_map[i].count, bit_map[i].name); | ||
134 | } | ||
135 | } | ||
136 | |||
137 | void | ||
138 | brw_update_dirty_counts( unsigned mesa, | ||
139 | unsigned brw, | ||
140 | unsigned cache ) | ||
141 | { | ||
142 | static int dirty_count = 0; | ||
143 | |||
144 | brw_update_dirty_count(mesa_bits, mesa); | ||
145 | brw_update_dirty_count(brw_bits, brw); | ||
146 | brw_update_dirty_count(cache_bits, cache); | ||
147 | if (dirty_count++ % 1000 == 0) { | ||
148 | brw_print_dirty_count(mesa_bits, mesa); | ||
149 | brw_print_dirty_count(brw_bits, brw); | ||
150 | brw_print_dirty_count(cache_bits, cache); | ||
151 | debug_printf("\n"); | ||
152 | } | ||
153 | } | ||
diff --git a/src/gallium/drivers/i965/brw_state_upload.c b/src/gallium/drivers/i965/brw_state_upload.c deleted file mode 100644 index cdbf270e06a..00000000000 --- a/src/gallium/drivers/i965/brw_state_upload.c +++ /dev/null | |||
@@ -1,270 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_state.h" | ||
36 | #include "brw_batchbuffer.h" | ||
37 | #include "brw_debug.h" | ||
38 | |||
39 | const struct brw_tracked_state *atoms[] = | ||
40 | { | ||
41 | /* &brw_wm_input_sizes, */ | ||
42 | &brw_vs_prog, | ||
43 | &brw_gs_prog, | ||
44 | &brw_clip_prog, | ||
45 | &brw_sf_prog, | ||
46 | &brw_wm_prog, | ||
47 | |||
48 | /* Once all the programs are done, we know how large urb entry | ||
49 | * sizes need to be and can decide if we need to change the urb | ||
50 | * layout. | ||
51 | */ | ||
52 | &brw_curbe_offsets, | ||
53 | &brw_recalculate_urb_fence, | ||
54 | |||
55 | &brw_cc_vp, | ||
56 | &brw_cc_unit, | ||
57 | |||
58 | &brw_vs_surfaces, /* must do before unit */ | ||
59 | /*&brw_wm_constant_surface,*/ /* must do before wm surfaces/bind bo */ | ||
60 | &brw_wm_surfaces, /* must do before samplers and unit */ | ||
61 | &brw_wm_samplers, | ||
62 | |||
63 | &brw_wm_unit, | ||
64 | &brw_sf_vp, | ||
65 | &brw_sf_unit, | ||
66 | &brw_vs_unit, /* always required, enabled or not */ | ||
67 | &brw_clip_unit, | ||
68 | &brw_gs_unit, | ||
69 | |||
70 | /* Command packets: | ||
71 | */ | ||
72 | &brw_invariant_state, | ||
73 | &brw_state_base_address, | ||
74 | |||
75 | &brw_binding_table_pointers, | ||
76 | &brw_blend_constant_color, | ||
77 | |||
78 | &brw_depthbuffer, | ||
79 | &brw_polygon_stipple, | ||
80 | &brw_line_stipple, | ||
81 | |||
82 | &brw_psp_urb_cbs, | ||
83 | |||
84 | &brw_drawing_rect, | ||
85 | &brw_indices, | ||
86 | &brw_index_buffer, | ||
87 | &brw_vertices, | ||
88 | |||
89 | &brw_curbe_buffer | ||
90 | }; | ||
91 | |||
92 | |||
93 | void brw_init_state( struct brw_context *brw ) | ||
94 | { | ||
95 | brw_init_caches(brw); | ||
96 | } | ||
97 | |||
98 | |||
99 | void brw_destroy_state( struct brw_context *brw ) | ||
100 | { | ||
101 | brw_destroy_caches(brw); | ||
102 | brw_destroy_batch_cache(brw); | ||
103 | } | ||
104 | |||
105 | /*********************************************************************** | ||
106 | */ | ||
107 | |||
108 | static GLboolean check_state( const struct brw_state_flags *a, | ||
109 | const struct brw_state_flags *b ) | ||
110 | { | ||
111 | return ((a->mesa & b->mesa) || | ||
112 | (a->brw & b->brw) || | ||
113 | (a->cache & b->cache)); | ||
114 | } | ||
115 | |||
116 | static void accumulate_state( struct brw_state_flags *a, | ||
117 | const struct brw_state_flags *b ) | ||
118 | { | ||
119 | a->mesa |= b->mesa; | ||
120 | a->brw |= b->brw; | ||
121 | a->cache |= b->cache; | ||
122 | } | ||
123 | |||
124 | |||
125 | static void xor_states( struct brw_state_flags *result, | ||
126 | const struct brw_state_flags *a, | ||
127 | const struct brw_state_flags *b ) | ||
128 | { | ||
129 | result->mesa = a->mesa ^ b->mesa; | ||
130 | result->brw = a->brw ^ b->brw; | ||
131 | result->cache = a->cache ^ b->cache; | ||
132 | } | ||
133 | |||
134 | static void | ||
135 | brw_clear_validated_bos(struct brw_context *brw) | ||
136 | { | ||
137 | int i; | ||
138 | |||
139 | /* Clear the last round of validated bos */ | ||
140 | for (i = 0; i < brw->state.validated_bo_count; i++) { | ||
141 | bo_reference(&brw->state.validated_bos[i], NULL); | ||
142 | } | ||
143 | brw->state.validated_bo_count = 0; | ||
144 | } | ||
145 | |||
146 | |||
147 | /*********************************************************************** | ||
148 | * Emit all state: | ||
149 | */ | ||
150 | enum pipe_error brw_validate_state( struct brw_context *brw ) | ||
151 | { | ||
152 | struct brw_state_flags *state = &brw->state.dirty; | ||
153 | GLuint i; | ||
154 | int ret; | ||
155 | |||
156 | brw_clear_validated_bos(brw); | ||
157 | brw_add_validated_bo(brw, brw->batch->buf); | ||
158 | |||
159 | if (brw->flags.always_emit_state) { | ||
160 | state->mesa |= ~0; | ||
161 | state->brw |= ~0; | ||
162 | state->cache |= ~0; | ||
163 | } | ||
164 | |||
165 | if (state->mesa == 0 && | ||
166 | state->cache == 0 && | ||
167 | state->brw == 0) | ||
168 | return 0; | ||
169 | |||
170 | if (brw->state.dirty.brw & BRW_NEW_CONTEXT) | ||
171 | brw_clear_batch_cache(brw); | ||
172 | |||
173 | /* do prepare stage for all atoms */ | ||
174 | for (i = 0; i < Elements(atoms); i++) { | ||
175 | const struct brw_tracked_state *atom = atoms[i]; | ||
176 | |||
177 | if (check_state(state, &atom->dirty)) { | ||
178 | if (atom->prepare) { | ||
179 | ret = atom->prepare(brw); | ||
180 | if (ret) | ||
181 | return ret; | ||
182 | } | ||
183 | } | ||
184 | } | ||
185 | |||
186 | /* Make sure that the textures which are referenced by the current | ||
187 | * brw fragment program are actually present/valid. | ||
188 | * If this fails, we can experience GPU lock-ups. | ||
189 | */ | ||
190 | { | ||
191 | const struct brw_fragment_shader *fp = brw->curr.fragment_shader; | ||
192 | if (fp) { | ||
193 | assert(fp->info.file_max[TGSI_FILE_SAMPLER] < (int)brw->curr.num_samplers); | ||
194 | /*assert(fp->info.texture_max <= brw->curr.num_textures);*/ | ||
195 | } | ||
196 | } | ||
197 | |||
198 | return 0; | ||
199 | } | ||
200 | |||
201 | |||
202 | enum pipe_error brw_upload_state(struct brw_context *brw) | ||
203 | { | ||
204 | struct brw_state_flags *state = &brw->state.dirty; | ||
205 | int ret; | ||
206 | int i; | ||
207 | |||
208 | brw_clear_validated_bos(brw); | ||
209 | |||
210 | if (BRW_DEBUG) { | ||
211 | /* Debug version which enforces various sanity checks on the | ||
212 | * state flags which are generated and checked to help ensure | ||
213 | * state atoms are ordered correctly in the list. | ||
214 | */ | ||
215 | struct brw_state_flags examined, prev; | ||
216 | memset(&examined, 0, sizeof(examined)); | ||
217 | prev = *state; | ||
218 | |||
219 | for (i = 0; i < Elements(atoms); i++) { | ||
220 | const struct brw_tracked_state *atom = atoms[i]; | ||
221 | struct brw_state_flags generated; | ||
222 | |||
223 | assert(atom->dirty.mesa || | ||
224 | atom->dirty.brw || | ||
225 | atom->dirty.cache); | ||
226 | |||
227 | if (check_state(state, &atom->dirty)) { | ||
228 | if (atom->emit) { | ||
229 | ret = atom->emit( brw ); | ||
230 | if (ret) | ||
231 | return ret; | ||
232 | } | ||
233 | } | ||
234 | |||
235 | accumulate_state(&examined, &atom->dirty); | ||
236 | |||
237 | /* generated = (prev ^ state) | ||
238 | * if (examined & generated) | ||
239 | * fail; | ||
240 | */ | ||
241 | xor_states(&generated, &prev, state); | ||
242 | assert(!check_state(&examined, &generated)); | ||
243 | prev = *state; | ||
244 | } | ||
245 | } | ||
246 | else { | ||
247 | for (i = 0; i < Elements(atoms); i++) { | ||
248 | const struct brw_tracked_state *atom = atoms[i]; | ||
249 | |||
250 | if (check_state(state, &atom->dirty)) { | ||
251 | if (atom->emit) { | ||
252 | ret = atom->emit( brw ); | ||
253 | if (ret) | ||
254 | return ret; | ||
255 | } | ||
256 | } | ||
257 | } | ||
258 | } | ||
259 | |||
260 | if (BRW_DEBUG & DEBUG_STATE) { | ||
261 | brw_update_dirty_counts( state->mesa, | ||
262 | state->brw, | ||
263 | state->cache ); | ||
264 | } | ||
265 | |||
266 | /* Clear dirty flags: | ||
267 | */ | ||
268 | memset(state, 0, sizeof(*state)); | ||
269 | return 0; | ||
270 | } | ||
diff --git a/src/gallium/drivers/i965/brw_structs.h b/src/gallium/drivers/i965/brw_structs.h deleted file mode 100644 index b0d75b4f828..00000000000 --- a/src/gallium/drivers/i965/brw_structs.h +++ /dev/null | |||
@@ -1,1776 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_STRUCTS_H | ||
34 | #define BRW_STRUCTS_H | ||
35 | |||
36 | #include "brw_types.h" | ||
37 | |||
38 | /** Number of general purpose registers (VS, WM, etc) */ | ||
39 | #define BRW_MAX_GRF 128 | ||
40 | |||
41 | /** Number of message register file registers */ | ||
42 | #define BRW_MAX_MRF 16 | ||
43 | |||
44 | |||
45 | /* Command packets: | ||
46 | */ | ||
47 | struct header | ||
48 | { | ||
49 | GLuint length:16; | ||
50 | GLuint opcode:16; | ||
51 | }; | ||
52 | |||
53 | |||
54 | union header_union | ||
55 | { | ||
56 | struct header bits; | ||
57 | GLuint dword; | ||
58 | }; | ||
59 | |||
60 | struct brw_3d_control | ||
61 | { | ||
62 | struct | ||
63 | { | ||
64 | GLuint length:8; | ||
65 | GLuint notify_enable:1; | ||
66 | GLuint pad:3; | ||
67 | GLuint wc_flush_enable:1; | ||
68 | GLuint depth_stall_enable:1; | ||
69 | GLuint operation:2; | ||
70 | GLuint opcode:16; | ||
71 | } header; | ||
72 | |||
73 | struct | ||
74 | { | ||
75 | GLuint pad:2; | ||
76 | GLuint dest_addr_type:1; | ||
77 | GLuint dest_addr:29; | ||
78 | } dest; | ||
79 | |||
80 | GLuint dword2; | ||
81 | GLuint dword3; | ||
82 | }; | ||
83 | |||
84 | |||
85 | struct brw_3d_primitive | ||
86 | { | ||
87 | struct | ||
88 | { | ||
89 | GLuint length:8; | ||
90 | GLuint pad:2; | ||
91 | GLuint topology:5; | ||
92 | GLuint indexed:1; | ||
93 | GLuint opcode:16; | ||
94 | } header; | ||
95 | |||
96 | GLuint verts_per_instance; | ||
97 | GLuint start_vert_location; | ||
98 | GLuint instance_count; | ||
99 | GLuint start_instance_location; | ||
100 | GLuint base_vert_location; | ||
101 | }; | ||
102 | |||
103 | /* These seem to be passed around as function args, so it works out | ||
104 | * better to keep them as #defines: | ||
105 | */ | ||
106 | #define BRW_FLUSH_READ_CACHE 0x1 | ||
107 | #define BRW_FLUSH_STATE_CACHE 0x2 | ||
108 | #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 | ||
109 | #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 | ||
110 | |||
111 | struct brw_mi_flush | ||
112 | { | ||
113 | GLuint flags:4; | ||
114 | GLuint pad:12; | ||
115 | GLuint opcode:16; | ||
116 | }; | ||
117 | |||
118 | struct brw_vf_statistics | ||
119 | { | ||
120 | GLuint statistics_enable:1; | ||
121 | GLuint pad:15; | ||
122 | GLuint opcode:16; | ||
123 | }; | ||
124 | |||
125 | |||
126 | |||
127 | struct brw_binding_table_pointers | ||
128 | { | ||
129 | struct header header; | ||
130 | GLuint vs; | ||
131 | GLuint gs; | ||
132 | GLuint clp; | ||
133 | GLuint sf; | ||
134 | GLuint wm; | ||
135 | }; | ||
136 | |||
137 | |||
138 | struct brw_blend_constant_color | ||
139 | { | ||
140 | struct header header; | ||
141 | GLfloat blend_constant_color[4]; | ||
142 | }; | ||
143 | |||
144 | |||
145 | struct brw_depthbuffer | ||
146 | { | ||
147 | union header_union header; | ||
148 | |||
149 | union { | ||
150 | struct { | ||
151 | GLuint pitch:18; | ||
152 | GLuint format:3; | ||
153 | GLuint pad:2; | ||
154 | GLuint software_tiled_rendering_mode:2; | ||
155 | GLuint depth_offset_disable:1; | ||
156 | GLuint tile_walk:1; | ||
157 | GLuint tiled_surface:1; | ||
158 | GLuint pad2:1; | ||
159 | GLuint surface_type:3; | ||
160 | } bits; | ||
161 | GLuint dword; | ||
162 | } dword1; | ||
163 | |||
164 | GLuint dword2_base_addr; | ||
165 | |||
166 | union { | ||
167 | struct { | ||
168 | GLuint pad:1; | ||
169 | GLuint mipmap_layout:1; | ||
170 | GLuint lod:4; | ||
171 | GLuint width:13; | ||
172 | GLuint height:13; | ||
173 | } bits; | ||
174 | GLuint dword; | ||
175 | } dword3; | ||
176 | |||
177 | union { | ||
178 | struct { | ||
179 | GLuint pad:10; | ||
180 | GLuint min_array_element:11; | ||
181 | GLuint depth:11; | ||
182 | } bits; | ||
183 | GLuint dword; | ||
184 | } dword4; | ||
185 | }; | ||
186 | |||
187 | struct brw_depthbuffer_g4x | ||
188 | { | ||
189 | union header_union header; | ||
190 | |||
191 | union { | ||
192 | struct { | ||
193 | GLuint pitch:18; | ||
194 | GLuint format:3; | ||
195 | GLuint pad:2; | ||
196 | GLuint software_tiled_rendering_mode:2; | ||
197 | GLuint depth_offset_disable:1; | ||
198 | GLuint tile_walk:1; | ||
199 | GLuint tiled_surface:1; | ||
200 | GLuint pad2:1; | ||
201 | GLuint surface_type:3; | ||
202 | } bits; | ||
203 | GLuint dword; | ||
204 | } dword1; | ||
205 | |||
206 | GLuint dword2_base_addr; | ||
207 | |||
208 | union { | ||
209 | struct { | ||
210 | GLuint pad:1; | ||
211 | GLuint mipmap_layout:1; | ||
212 | GLuint lod:4; | ||
213 | GLuint width:13; | ||
214 | GLuint height:13; | ||
215 | } bits; | ||
216 | GLuint dword; | ||
217 | } dword3; | ||
218 | |||
219 | union { | ||
220 | struct { | ||
221 | GLuint pad:10; | ||
222 | GLuint min_array_element:11; | ||
223 | GLuint depth:11; | ||
224 | } bits; | ||
225 | GLuint dword; | ||
226 | } dword4; | ||
227 | |||
228 | union { | ||
229 | struct { | ||
230 | GLuint xoffset:16; | ||
231 | GLuint yoffset:16; | ||
232 | } bits; | ||
233 | GLuint dword; | ||
234 | } dword5; /* NEW in Integrated Graphics Device */ | ||
235 | }; | ||
236 | |||
237 | struct brw_drawrect | ||
238 | { | ||
239 | struct header header; | ||
240 | GLuint xmin:16; | ||
241 | GLuint ymin:16; | ||
242 | GLuint xmax:16; | ||
243 | GLuint ymax:16; | ||
244 | GLuint xorg:16; | ||
245 | GLuint yorg:16; | ||
246 | }; | ||
247 | |||
248 | |||
249 | |||
250 | |||
251 | struct brw_global_depth_offset_clamp | ||
252 | { | ||
253 | struct header header; | ||
254 | GLfloat depth_offset_clamp; | ||
255 | }; | ||
256 | |||
257 | struct brw_indexbuffer | ||
258 | { | ||
259 | union { | ||
260 | struct | ||
261 | { | ||
262 | GLuint length:8; | ||
263 | GLuint index_format:2; | ||
264 | GLuint cut_index_enable:1; | ||
265 | GLuint pad:5; | ||
266 | GLuint opcode:16; | ||
267 | } bits; | ||
268 | GLuint dword; | ||
269 | |||
270 | } header; | ||
271 | |||
272 | GLuint buffer_start; | ||
273 | GLuint buffer_end; | ||
274 | }; | ||
275 | |||
276 | /* NEW in Integrated Graphics Device */ | ||
277 | struct brw_aa_line_parameters | ||
278 | { | ||
279 | struct header header; | ||
280 | |||
281 | struct { | ||
282 | GLuint aa_coverage_slope:8; | ||
283 | GLuint pad0:8; | ||
284 | GLuint aa_coverage_bias:8; | ||
285 | GLuint pad1:8; | ||
286 | } bits0; | ||
287 | |||
288 | struct { | ||
289 | GLuint aa_coverage_endcap_slope:8; | ||
290 | GLuint pad0:8; | ||
291 | GLuint aa_coverage_endcap_bias:8; | ||
292 | GLuint pad1:8; | ||
293 | } bits1; | ||
294 | }; | ||
295 | |||
296 | struct brw_line_stipple | ||
297 | { | ||
298 | struct header header; | ||
299 | |||
300 | struct | ||
301 | { | ||
302 | GLuint pattern:16; | ||
303 | GLuint pad:16; | ||
304 | } bits0; | ||
305 | |||
306 | struct | ||
307 | { | ||
308 | GLuint repeat_count:9; | ||
309 | GLuint pad:7; | ||
310 | GLuint inverse_repeat_count:16; | ||
311 | } bits1; | ||
312 | }; | ||
313 | |||
314 | |||
315 | struct brw_pipelined_state_pointers | ||
316 | { | ||
317 | struct header header; | ||
318 | |||
319 | struct { | ||
320 | GLuint pad:5; | ||
321 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
322 | } vs; | ||
323 | |||
324 | struct | ||
325 | { | ||
326 | GLuint enable:1; | ||
327 | GLuint pad:4; | ||
328 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
329 | } gs; | ||
330 | |||
331 | struct | ||
332 | { | ||
333 | GLuint enable:1; | ||
334 | GLuint pad:4; | ||
335 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
336 | } clp; | ||
337 | |||
338 | struct | ||
339 | { | ||
340 | GLuint pad:5; | ||
341 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
342 | } sf; | ||
343 | |||
344 | struct | ||
345 | { | ||
346 | GLuint pad:5; | ||
347 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
348 | } wm; | ||
349 | |||
350 | struct | ||
351 | { | ||
352 | GLuint pad:5; | ||
353 | GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */ | ||
354 | } cc; | ||
355 | }; | ||
356 | |||
357 | |||
358 | struct brw_polygon_stipple_offset | ||
359 | { | ||
360 | struct header header; | ||
361 | |||
362 | struct { | ||
363 | GLuint y_offset:5; | ||
364 | GLuint pad:3; | ||
365 | GLuint x_offset:5; | ||
366 | GLuint pad0:19; | ||
367 | } bits0; | ||
368 | }; | ||
369 | |||
370 | |||
371 | |||
372 | struct brw_polygon_stipple | ||
373 | { | ||
374 | struct header header; | ||
375 | GLuint stipple[32]; | ||
376 | }; | ||
377 | |||
378 | |||
379 | |||
380 | struct brw_pipeline_select | ||
381 | { | ||
382 | struct | ||
383 | { | ||
384 | GLuint pipeline_select:1; | ||
385 | GLuint pad:15; | ||
386 | GLuint opcode:16; | ||
387 | } header; | ||
388 | }; | ||
389 | |||
390 | |||
391 | struct brw_pipe_control | ||
392 | { | ||
393 | struct | ||
394 | { | ||
395 | GLuint length:8; | ||
396 | GLuint notify_enable:1; | ||
397 | GLuint texture_cache_flush_enable:1; | ||
398 | GLuint indirect_state_pointers_disable:1; | ||
399 | GLuint instruction_state_cache_flush_enable:1; | ||
400 | GLuint write_cache_flush_enable:1; | ||
401 | GLuint depth_stall_enable:1; | ||
402 | GLuint post_sync_operation:2; | ||
403 | |||
404 | GLuint opcode:16; | ||
405 | } header; | ||
406 | |||
407 | struct | ||
408 | { | ||
409 | GLuint pad:2; | ||
410 | GLuint dest_addr_type:1; | ||
411 | GLuint dest_addr:29; | ||
412 | } bits1; | ||
413 | |||
414 | GLuint data0; | ||
415 | GLuint data1; | ||
416 | }; | ||
417 | |||
418 | |||
419 | struct brw_urb_fence | ||
420 | { | ||
421 | struct | ||
422 | { | ||
423 | GLuint length:8; | ||
424 | GLuint vs_realloc:1; | ||
425 | GLuint gs_realloc:1; | ||
426 | GLuint clp_realloc:1; | ||
427 | GLuint sf_realloc:1; | ||
428 | GLuint vfe_realloc:1; | ||
429 | GLuint cs_realloc:1; | ||
430 | GLuint pad:2; | ||
431 | GLuint opcode:16; | ||
432 | } header; | ||
433 | |||
434 | struct | ||
435 | { | ||
436 | GLuint vs_fence:10; | ||
437 | GLuint gs_fence:10; | ||
438 | GLuint clp_fence:10; | ||
439 | GLuint pad:2; | ||
440 | } bits0; | ||
441 | |||
442 | struct | ||
443 | { | ||
444 | GLuint sf_fence:10; | ||
445 | GLuint vf_fence:10; | ||
446 | GLuint cs_fence:11; | ||
447 | GLuint pad:1; | ||
448 | } bits1; | ||
449 | }; | ||
450 | |||
451 | struct brw_cs_urb_state | ||
452 | { | ||
453 | struct header header; | ||
454 | |||
455 | struct | ||
456 | { | ||
457 | GLuint nr_urb_entries:3; | ||
458 | GLuint pad:1; | ||
459 | GLuint urb_entry_size:5; | ||
460 | GLuint pad0:23; | ||
461 | } bits0; | ||
462 | }; | ||
463 | |||
464 | struct brw_constant_buffer | ||
465 | { | ||
466 | struct | ||
467 | { | ||
468 | GLuint length:8; | ||
469 | GLuint valid:1; | ||
470 | GLuint pad:7; | ||
471 | GLuint opcode:16; | ||
472 | } header; | ||
473 | |||
474 | struct | ||
475 | { | ||
476 | GLuint buffer_length:6; | ||
477 | GLuint buffer_address:26; | ||
478 | } bits0; | ||
479 | }; | ||
480 | |||
481 | struct brw_state_base_address | ||
482 | { | ||
483 | struct header header; | ||
484 | |||
485 | struct | ||
486 | { | ||
487 | GLuint modify_enable:1; | ||
488 | GLuint pad:4; | ||
489 | GLuint general_state_address:27; | ||
490 | } bits0; | ||
491 | |||
492 | struct | ||
493 | { | ||
494 | GLuint modify_enable:1; | ||
495 | GLuint pad:4; | ||
496 | GLuint surface_state_address:27; | ||
497 | } bits1; | ||
498 | |||
499 | struct | ||
500 | { | ||
501 | GLuint modify_enable:1; | ||
502 | GLuint pad:4; | ||
503 | GLuint indirect_object_state_address:27; | ||
504 | } bits2; | ||
505 | |||
506 | struct | ||
507 | { | ||
508 | GLuint modify_enable:1; | ||
509 | GLuint pad:11; | ||
510 | GLuint general_state_upper_bound:20; | ||
511 | } bits3; | ||
512 | |||
513 | struct | ||
514 | { | ||
515 | GLuint modify_enable:1; | ||
516 | GLuint pad:11; | ||
517 | GLuint indirect_object_state_upper_bound:20; | ||
518 | } bits4; | ||
519 | }; | ||
520 | |||
521 | struct brw_state_prefetch | ||
522 | { | ||
523 | struct header header; | ||
524 | |||
525 | struct | ||
526 | { | ||
527 | GLuint prefetch_count:3; | ||
528 | GLuint pad:3; | ||
529 | GLuint prefetch_pointer:26; | ||
530 | } bits0; | ||
531 | }; | ||
532 | |||
533 | struct brw_system_instruction_pointer | ||
534 | { | ||
535 | struct header header; | ||
536 | |||
537 | struct | ||
538 | { | ||
539 | GLuint pad:4; | ||
540 | GLuint system_instruction_pointer:28; | ||
541 | } bits0; | ||
542 | }; | ||
543 | |||
544 | |||
545 | |||
546 | |||
547 | /* State structs for the various fixed function units: | ||
548 | */ | ||
549 | |||
550 | |||
551 | struct thread0 | ||
552 | { | ||
553 | GLuint pad0:1; | ||
554 | GLuint grf_reg_count:3; | ||
555 | GLuint pad1:2; | ||
556 | GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */ | ||
557 | }; | ||
558 | |||
559 | struct thread1 | ||
560 | { | ||
561 | GLuint ext_halt_exception_enable:1; | ||
562 | GLuint sw_exception_enable:1; | ||
563 | GLuint mask_stack_exception_enable:1; | ||
564 | GLuint timeout_exception_enable:1; | ||
565 | GLuint illegal_op_exception_enable:1; | ||
566 | GLuint pad0:3; | ||
567 | GLuint depth_coef_urb_read_offset:6; /* WM only */ | ||
568 | GLuint pad1:2; | ||
569 | GLuint floating_point_mode:1; | ||
570 | GLuint thread_priority:1; | ||
571 | GLuint binding_table_entry_count:8; | ||
572 | GLuint pad3:5; | ||
573 | GLuint single_program_flow:1; | ||
574 | }; | ||
575 | |||
576 | struct thread2 | ||
577 | { | ||
578 | GLuint per_thread_scratch_space:4; | ||
579 | GLuint pad0:6; | ||
580 | GLuint scratch_space_base_pointer:22; | ||
581 | }; | ||
582 | |||
583 | |||
584 | struct thread3 | ||
585 | { | ||
586 | GLuint dispatch_grf_start_reg:4; | ||
587 | GLuint urb_entry_read_offset:6; | ||
588 | GLuint pad0:1; | ||
589 | GLuint urb_entry_read_length:6; | ||
590 | GLuint pad1:1; | ||
591 | GLuint const_urb_entry_read_offset:6; | ||
592 | GLuint pad2:1; | ||
593 | GLuint const_urb_entry_read_length:6; | ||
594 | GLuint pad3:1; | ||
595 | }; | ||
596 | |||
597 | |||
598 | |||
599 | struct brw_clip_unit_state | ||
600 | { | ||
601 | struct thread0 thread0; | ||
602 | struct | ||
603 | { | ||
604 | GLuint pad0:7; | ||
605 | GLuint sw_exception_enable:1; | ||
606 | GLuint pad1:3; | ||
607 | GLuint mask_stack_exception_enable:1; | ||
608 | GLuint pad2:1; | ||
609 | GLuint illegal_op_exception_enable:1; | ||
610 | GLuint pad3:2; | ||
611 | GLuint floating_point_mode:1; | ||
612 | GLuint thread_priority:1; | ||
613 | GLuint binding_table_entry_count:8; | ||
614 | GLuint pad4:5; | ||
615 | GLuint single_program_flow:1; | ||
616 | } thread1; | ||
617 | |||
618 | struct thread2 thread2; | ||
619 | struct thread3 thread3; | ||
620 | |||
621 | struct | ||
622 | { | ||
623 | GLuint pad0:9; | ||
624 | GLuint gs_output_stats:1; /* not always */ | ||
625 | GLuint stats_enable:1; | ||
626 | GLuint nr_urb_entries:7; | ||
627 | GLuint pad1:1; | ||
628 | GLuint urb_entry_allocation_size:5; | ||
629 | GLuint pad2:1; | ||
630 | GLuint max_threads:5; /* may be less */ | ||
631 | GLuint pad3:2; | ||
632 | } thread4; | ||
633 | |||
634 | struct | ||
635 | { | ||
636 | GLuint pad0:13; | ||
637 | GLuint clip_mode:3; | ||
638 | GLuint userclip_enable_flags:8; | ||
639 | GLuint userclip_must_clip:1; | ||
640 | GLuint negative_w_clip_test:1; | ||
641 | GLuint guard_band_enable:1; | ||
642 | GLuint viewport_z_clip_enable:1; | ||
643 | GLuint viewport_xy_clip_enable:1; | ||
644 | GLuint vertex_position_space:1; | ||
645 | GLuint api_mode:1; | ||
646 | GLuint pad2:1; | ||
647 | } clip5; | ||
648 | |||
649 | struct | ||
650 | { | ||
651 | GLuint pad0:5; | ||
652 | GLuint clipper_viewport_state_ptr:27; | ||
653 | } clip6; | ||
654 | |||
655 | |||
656 | GLfloat viewport_xmin; | ||
657 | GLfloat viewport_xmax; | ||
658 | GLfloat viewport_ymin; | ||
659 | GLfloat viewport_ymax; | ||
660 | }; | ||
661 | |||
662 | struct gen6_blend_state | ||
663 | { | ||
664 | struct { | ||
665 | GLuint dest_blend_factor:5; | ||
666 | GLuint source_blend_factor:5; | ||
667 | GLuint pad3:1; | ||
668 | GLuint blend_func:3; | ||
669 | GLuint pad2:1; | ||
670 | GLuint ia_dest_blend_factor:5; | ||
671 | GLuint ia_source_blend_factor:5; | ||
672 | GLuint pad1:1; | ||
673 | GLuint ia_blend_func:3; | ||
674 | GLuint pad0:1; | ||
675 | GLuint ia_blend_enable:1; | ||
676 | GLuint blend_enable:1; | ||
677 | } blend0; | ||
678 | |||
679 | struct { | ||
680 | GLuint post_blend_clamp_enable:1; | ||
681 | GLuint pre_blend_clamp_enable:1; | ||
682 | GLuint clamp_range:2; | ||
683 | GLuint pad0:4; | ||
684 | GLuint x_dither_offset:2; | ||
685 | GLuint y_dither_offset:2; | ||
686 | GLuint dither_enable:1; | ||
687 | GLuint alpha_test_func:3; | ||
688 | GLuint alpha_test_enable:1; | ||
689 | GLuint pad1:1; | ||
690 | GLuint logic_op_func:4; | ||
691 | GLuint logic_op_enable:1; | ||
692 | GLuint pad2:1; | ||
693 | GLuint write_disable_b:1; | ||
694 | GLuint write_disable_g:1; | ||
695 | GLuint write_disable_r:1; | ||
696 | GLuint write_disable_a:1; | ||
697 | GLuint pad3:1; | ||
698 | GLuint alpha_to_coverage_dither:1; | ||
699 | GLuint alpha_to_one:1; | ||
700 | GLuint alpha_to_coverage:1; | ||
701 | } blend1; | ||
702 | }; | ||
703 | |||
704 | struct gen6_color_calc_state | ||
705 | { | ||
706 | struct { | ||
707 | GLuint alpha_test_format:1; | ||
708 | GLuint pad0:14; | ||
709 | GLuint round_disable:1; | ||
710 | GLuint bf_stencil_ref:8; | ||
711 | GLuint stencil_ref:8; | ||
712 | } cc0; | ||
713 | |||
714 | union { | ||
715 | GLfloat alpha_ref_f; | ||
716 | struct { | ||
717 | GLuint ui:8; | ||
718 | GLuint pad0:24; | ||
719 | } alpha_ref_fi; | ||
720 | } cc1; | ||
721 | |||
722 | GLfloat constant_r; | ||
723 | GLfloat constant_g; | ||
724 | GLfloat constant_b; | ||
725 | GLfloat constant_a; | ||
726 | }; | ||
727 | |||
728 | struct gen6_depth_stencil_state | ||
729 | { | ||
730 | struct { | ||
731 | GLuint pad0:3; | ||
732 | GLuint bf_stencil_pass_depth_pass_op:3; | ||
733 | GLuint bf_stencil_pass_depth_fail_op:3; | ||
734 | GLuint bf_stencil_fail_op:3; | ||
735 | GLuint bf_stencil_func:3; | ||
736 | GLuint bf_stencil_enable:1; | ||
737 | GLuint pad1:2; | ||
738 | GLuint stencil_write_enable:1; | ||
739 | GLuint stencil_pass_depth_pass_op:3; | ||
740 | GLuint stencil_pass_depth_fail_op:3; | ||
741 | GLuint stencil_fail_op:3; | ||
742 | GLuint stencil_func:3; | ||
743 | GLuint stencil_enable:1; | ||
744 | } ds0; | ||
745 | |||
746 | struct { | ||
747 | GLuint bf_stencil_write_mask:8; | ||
748 | GLuint bf_stencil_test_mask:8; | ||
749 | GLuint stencil_write_mask:8; | ||
750 | GLuint stencil_test_mask:8; | ||
751 | } ds1; | ||
752 | |||
753 | struct { | ||
754 | GLuint pad0:26; | ||
755 | GLuint depth_write_enable:1; | ||
756 | GLuint depth_test_func:3; | ||
757 | GLuint pad1:1; | ||
758 | GLuint depth_test_enable:1; | ||
759 | } ds2; | ||
760 | }; | ||
761 | |||
762 | struct brw_cc_unit_state | ||
763 | { | ||
764 | struct brw_cc0 | ||
765 | { | ||
766 | GLuint pad0:3; | ||
767 | GLuint bf_stencil_pass_depth_pass_op:3; | ||
768 | GLuint bf_stencil_pass_depth_fail_op:3; | ||
769 | GLuint bf_stencil_fail_op:3; | ||
770 | GLuint bf_stencil_func:3; | ||
771 | GLuint bf_stencil_enable:1; | ||
772 | GLuint pad1:2; | ||
773 | GLuint stencil_write_enable:1; | ||
774 | GLuint stencil_pass_depth_pass_op:3; | ||
775 | GLuint stencil_pass_depth_fail_op:3; | ||
776 | GLuint stencil_fail_op:3; | ||
777 | GLuint stencil_func:3; | ||
778 | GLuint stencil_enable:1; | ||
779 | } cc0; | ||
780 | |||
781 | |||
782 | struct brw_cc1 | ||
783 | { | ||
784 | GLuint bf_stencil_ref:8; | ||
785 | GLuint stencil_write_mask:8; | ||
786 | GLuint stencil_test_mask:8; | ||
787 | GLuint stencil_ref:8; | ||
788 | } cc1; | ||
789 | |||
790 | |||
791 | struct brw_cc2 | ||
792 | { | ||
793 | GLuint logicop_enable:1; | ||
794 | GLuint pad0:10; | ||
795 | GLuint depth_write_enable:1; | ||
796 | GLuint depth_test_function:3; | ||
797 | GLuint depth_test:1; | ||
798 | GLuint bf_stencil_write_mask:8; | ||
799 | GLuint bf_stencil_test_mask:8; | ||
800 | } cc2; | ||
801 | |||
802 | |||
803 | struct brw_cc3 | ||
804 | { | ||
805 | GLuint pad0:8; | ||
806 | GLuint alpha_test_func:3; | ||
807 | GLuint alpha_test:1; | ||
808 | GLuint blend_enable:1; | ||
809 | GLuint ia_blend_enable:1; | ||
810 | GLuint pad1:1; | ||
811 | GLuint alpha_test_format:1; | ||
812 | GLuint pad2:16; | ||
813 | } cc3; | ||
814 | |||
815 | struct brw_cc4 | ||
816 | { | ||
817 | GLuint pad0:5; | ||
818 | GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
819 | } cc4; | ||
820 | |||
821 | struct brw_cc5 | ||
822 | { | ||
823 | GLuint pad0:2; | ||
824 | GLuint ia_dest_blend_factor:5; | ||
825 | GLuint ia_src_blend_factor:5; | ||
826 | GLuint ia_blend_function:3; | ||
827 | GLuint statistics_enable:1; | ||
828 | GLuint logicop_func:4; | ||
829 | GLuint pad1:11; | ||
830 | GLuint dither_enable:1; | ||
831 | } cc5; | ||
832 | |||
833 | struct brw_cc6 | ||
834 | { | ||
835 | GLuint clamp_post_alpha_blend:1; | ||
836 | GLuint clamp_pre_alpha_blend:1; | ||
837 | GLuint clamp_range:2; | ||
838 | GLuint pad0:11; | ||
839 | GLuint y_dither_offset:2; | ||
840 | GLuint x_dither_offset:2; | ||
841 | GLuint dest_blend_factor:5; | ||
842 | GLuint src_blend_factor:5; | ||
843 | GLuint blend_function:3; | ||
844 | } cc6; | ||
845 | |||
846 | struct brw_cc7 { | ||
847 | union { | ||
848 | GLfloat f; | ||
849 | GLubyte ub[4]; | ||
850 | } alpha_ref; | ||
851 | } cc7; | ||
852 | }; | ||
853 | |||
854 | |||
855 | |||
856 | struct brw_sf_unit_state | ||
857 | { | ||
858 | struct thread0 thread0; | ||
859 | struct thread1 thread1; | ||
860 | struct thread2 thread2; | ||
861 | struct thread3 thread3; | ||
862 | |||
863 | struct | ||
864 | { | ||
865 | GLuint pad0:10; | ||
866 | GLuint stats_enable:1; | ||
867 | GLuint nr_urb_entries:7; | ||
868 | GLuint pad1:1; | ||
869 | GLuint urb_entry_allocation_size:5; | ||
870 | GLuint pad2:1; | ||
871 | GLuint max_threads:6; | ||
872 | GLuint pad3:1; | ||
873 | } thread4; | ||
874 | |||
875 | struct | ||
876 | { | ||
877 | GLuint front_winding:1; | ||
878 | GLuint viewport_transform:1; | ||
879 | GLuint pad0:3; | ||
880 | GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ | ||
881 | } sf5; | ||
882 | |||
883 | struct | ||
884 | { | ||
885 | GLuint pad0:9; | ||
886 | GLuint dest_org_vbias:4; | ||
887 | GLuint dest_org_hbias:4; | ||
888 | GLuint scissor:1; | ||
889 | GLuint disable_2x2_trifilter:1; | ||
890 | GLuint disable_zero_pix_trifilter:1; | ||
891 | GLuint point_rast_rule:2; | ||
892 | GLuint line_endcap_aa_region_width:2; | ||
893 | GLuint line_width:4; | ||
894 | GLuint fast_scissor_disable:1; | ||
895 | GLuint cull_mode:2; | ||
896 | GLuint aa_enable:1; | ||
897 | } sf6; | ||
898 | |||
899 | struct | ||
900 | { | ||
901 | GLuint point_size:11; | ||
902 | GLuint use_point_size_state:1; | ||
903 | GLuint subpixel_precision:1; | ||
904 | GLuint sprite_point:1; | ||
905 | GLuint pad0:10; | ||
906 | GLuint aa_line_distance_mode:1; | ||
907 | GLuint trifan_pv:2; | ||
908 | GLuint linestrip_pv:2; | ||
909 | GLuint tristrip_pv:2; | ||
910 | GLuint line_last_pixel_enable:1; | ||
911 | } sf7; | ||
912 | |||
913 | }; | ||
914 | |||
915 | struct gen6_scissor_rect | ||
916 | { | ||
917 | GLuint xmin:16; | ||
918 | GLuint ymin:16; | ||
919 | GLuint xmax:16; | ||
920 | GLuint ymax:16; | ||
921 | }; | ||
922 | |||
923 | struct brw_gs_unit_state | ||
924 | { | ||
925 | struct thread0 thread0; | ||
926 | struct thread1 thread1; | ||
927 | struct thread2 thread2; | ||
928 | struct thread3 thread3; | ||
929 | |||
930 | struct | ||
931 | { | ||
932 | GLuint pad0:8; | ||
933 | GLuint rendering_enable:1; /* for Ironlake */ | ||
934 | GLuint pad4:1; | ||
935 | GLuint stats_enable:1; | ||
936 | GLuint nr_urb_entries:7; | ||
937 | GLuint pad1:1; | ||
938 | GLuint urb_entry_allocation_size:5; | ||
939 | GLuint pad2:1; | ||
940 | GLuint max_threads:5; | ||
941 | GLuint pad3:2; | ||
942 | } thread4; | ||
943 | |||
944 | struct | ||
945 | { | ||
946 | GLuint sampler_count:3; | ||
947 | GLuint pad0:2; | ||
948 | GLuint sampler_state_pointer:27; | ||
949 | } gs5; | ||
950 | |||
951 | |||
952 | struct | ||
953 | { | ||
954 | GLuint max_vp_index:4; | ||
955 | GLuint pad0:12; | ||
956 | GLuint svbi_post_inc_value:10; | ||
957 | GLuint pad1:1; | ||
958 | GLuint svbi_post_inc_enable:1; | ||
959 | GLuint svbi_payload:1; | ||
960 | GLuint discard_adjaceny:1; | ||
961 | GLuint reorder_enable:1; | ||
962 | GLuint pad2:1; | ||
963 | } gs6; | ||
964 | }; | ||
965 | |||
966 | |||
967 | struct brw_vs_unit_state | ||
968 | { | ||
969 | struct thread0 thread0; | ||
970 | struct thread1 thread1; | ||
971 | struct thread2 thread2; | ||
972 | struct thread3 thread3; | ||
973 | |||
974 | struct | ||
975 | { | ||
976 | GLuint pad0:10; | ||
977 | GLuint stats_enable:1; | ||
978 | GLuint nr_urb_entries:7; | ||
979 | GLuint pad1:1; | ||
980 | GLuint urb_entry_allocation_size:5; | ||
981 | GLuint pad2:1; | ||
982 | GLuint max_threads:6; | ||
983 | GLuint pad3:1; | ||
984 | } thread4; | ||
985 | |||
986 | struct | ||
987 | { | ||
988 | GLuint sampler_count:3; | ||
989 | GLuint pad0:2; | ||
990 | GLuint sampler_state_pointer:27; | ||
991 | } vs5; | ||
992 | |||
993 | struct | ||
994 | { | ||
995 | GLuint vs_enable:1; | ||
996 | GLuint vert_cache_disable:1; | ||
997 | GLuint pad0:30; | ||
998 | } vs6; | ||
999 | }; | ||
1000 | |||
1001 | |||
1002 | struct brw_wm_unit_state | ||
1003 | { | ||
1004 | struct thread0 thread0; | ||
1005 | struct thread1 thread1; | ||
1006 | struct thread2 thread2; | ||
1007 | struct thread3 thread3; | ||
1008 | |||
1009 | struct { | ||
1010 | GLuint stats_enable:1; | ||
1011 | GLuint depth_buffer_clear:1; | ||
1012 | GLuint sampler_count:3; | ||
1013 | GLuint sampler_state_pointer:27; | ||
1014 | } wm4; | ||
1015 | |||
1016 | struct | ||
1017 | { | ||
1018 | GLuint enable_8_pix:1; | ||
1019 | GLuint enable_16_pix:1; | ||
1020 | GLuint enable_32_pix:1; | ||
1021 | GLuint enable_con_32_pix:1; | ||
1022 | GLuint enable_con_64_pix:1; | ||
1023 | GLuint pad0:5; | ||
1024 | GLuint legacy_global_depth_bias:1; | ||
1025 | GLuint line_stipple:1; | ||
1026 | GLuint depth_offset:1; | ||
1027 | GLuint polygon_stipple:1; | ||
1028 | GLuint line_aa_region_width:2; | ||
1029 | GLuint line_endcap_aa_region_width:2; | ||
1030 | GLuint early_depth_test:1; | ||
1031 | GLuint thread_dispatch_enable:1; | ||
1032 | GLuint program_uses_depth:1; | ||
1033 | GLuint program_computes_depth:1; | ||
1034 | GLuint program_uses_killpixel:1; | ||
1035 | GLuint legacy_line_rast: 1; | ||
1036 | GLuint transposed_urb_read_enable:1; | ||
1037 | GLuint max_threads:7; | ||
1038 | } wm5; | ||
1039 | |||
1040 | GLfloat global_depth_offset_constant; | ||
1041 | GLfloat global_depth_offset_scale; | ||
1042 | |||
1043 | /* for Ironlake only */ | ||
1044 | struct { | ||
1045 | GLuint pad0:1; | ||
1046 | GLuint grf_reg_count_1:3; | ||
1047 | GLuint pad1:2; | ||
1048 | GLuint kernel_start_pointer_1:26; | ||
1049 | } wm8; | ||
1050 | |||
1051 | struct { | ||
1052 | GLuint pad0:1; | ||
1053 | GLuint grf_reg_count_2:3; | ||
1054 | GLuint pad1:2; | ||
1055 | GLuint kernel_start_pointer_2:26; | ||
1056 | } wm9; | ||
1057 | |||
1058 | struct { | ||
1059 | GLuint pad0:1; | ||
1060 | GLuint grf_reg_count_3:3; | ||
1061 | GLuint pad1:2; | ||
1062 | GLuint kernel_start_pointer_3:26; | ||
1063 | } wm10; | ||
1064 | }; | ||
1065 | |||
1066 | struct brw_sampler_default_color { | ||
1067 | GLfloat color[4]; | ||
1068 | }; | ||
1069 | |||
1070 | struct gen5_sampler_default_color { | ||
1071 | uint8_t ub[4]; | ||
1072 | float f[4]; | ||
1073 | uint16_t hf[4]; | ||
1074 | uint16_t us[4]; | ||
1075 | int16_t s[4]; | ||
1076 | uint8_t b[4]; | ||
1077 | }; | ||
1078 | |||
1079 | struct brw_sampler_state | ||
1080 | { | ||
1081 | |||
1082 | struct brw_ss0 | ||
1083 | { | ||
1084 | GLuint shadow_function:3; | ||
1085 | GLuint lod_bias:11; | ||
1086 | GLuint min_filter:3; | ||
1087 | GLuint mag_filter:3; | ||
1088 | GLuint mip_filter:2; | ||
1089 | GLuint base_level:5; | ||
1090 | GLuint min_mag_neq:1; | ||
1091 | GLuint lod_preclamp:1; | ||
1092 | GLuint default_color_mode:1; | ||
1093 | GLuint pad0:1; | ||
1094 | GLuint disable:1; | ||
1095 | } ss0; | ||
1096 | |||
1097 | struct brw_ss1 | ||
1098 | { | ||
1099 | GLuint r_wrap_mode:3; | ||
1100 | GLuint t_wrap_mode:3; | ||
1101 | GLuint s_wrap_mode:3; | ||
1102 | GLuint cube_control_mode:1; | ||
1103 | GLuint pad:2; | ||
1104 | GLuint max_lod:10; | ||
1105 | GLuint min_lod:10; | ||
1106 | } ss1; | ||
1107 | |||
1108 | |||
1109 | struct brw_ss2 | ||
1110 | { | ||
1111 | GLuint pad:5; | ||
1112 | GLuint default_color_pointer:27; | ||
1113 | } ss2; | ||
1114 | |||
1115 | struct brw_ss3 | ||
1116 | { | ||
1117 | GLuint non_normalized_coord:1; | ||
1118 | GLuint pad:12; | ||
1119 | GLuint address_round:6; | ||
1120 | GLuint max_aniso:3; | ||
1121 | GLuint chroma_key_mode:1; | ||
1122 | GLuint chroma_key_index:2; | ||
1123 | GLuint chroma_key_enable:1; | ||
1124 | GLuint monochrome_filter_width:3; | ||
1125 | GLuint monochrome_filter_height:3; | ||
1126 | } ss3; | ||
1127 | }; | ||
1128 | |||
1129 | |||
1130 | struct brw_clipper_viewport | ||
1131 | { | ||
1132 | GLfloat xmin; | ||
1133 | GLfloat xmax; | ||
1134 | GLfloat ymin; | ||
1135 | GLfloat ymax; | ||
1136 | }; | ||
1137 | |||
1138 | struct brw_cc_viewport | ||
1139 | { | ||
1140 | GLfloat min_depth; | ||
1141 | GLfloat max_depth; | ||
1142 | }; | ||
1143 | |||
1144 | struct brw_sf_viewport | ||
1145 | { | ||
1146 | struct { | ||
1147 | GLfloat m00; | ||
1148 | GLfloat m11; | ||
1149 | GLfloat m22; | ||
1150 | GLfloat m30; | ||
1151 | GLfloat m31; | ||
1152 | GLfloat m32; | ||
1153 | } viewport; | ||
1154 | |||
1155 | /* scissor coordinates are inclusive */ | ||
1156 | struct { | ||
1157 | GLshort xmin; | ||
1158 | GLshort ymin; | ||
1159 | GLshort xmax; | ||
1160 | GLshort ymax; | ||
1161 | } scissor; | ||
1162 | }; | ||
1163 | |||
1164 | struct gen6_sf_viewport { | ||
1165 | GLfloat m00; | ||
1166 | GLfloat m11; | ||
1167 | GLfloat m22; | ||
1168 | GLfloat m30; | ||
1169 | GLfloat m31; | ||
1170 | GLfloat m32; | ||
1171 | }; | ||
1172 | |||
1173 | /* Documented in the subsystem/shared-functions/sampler chapter... | ||
1174 | */ | ||
1175 | struct brw_surface_state | ||
1176 | { | ||
1177 | struct brw_surf_ss0 { | ||
1178 | GLuint cube_pos_z:1; | ||
1179 | GLuint cube_neg_z:1; | ||
1180 | GLuint cube_pos_y:1; | ||
1181 | GLuint cube_neg_y:1; | ||
1182 | GLuint cube_pos_x:1; | ||
1183 | GLuint cube_neg_x:1; | ||
1184 | GLuint pad:2; | ||
1185 | /* Required on gen6 for surfaces accessed through render cache messages. | ||
1186 | */ | ||
1187 | GLuint render_cache_read_write:1; | ||
1188 | /* Ironlake and newer: instead of replicating one of the texels */ | ||
1189 | GLuint cube_corner_average:1; | ||
1190 | GLuint mipmap_layout_mode:1; | ||
1191 | GLuint vert_line_stride_ofs:1; | ||
1192 | GLuint vert_line_stride:1; | ||
1193 | GLuint color_blend:1; | ||
1194 | GLuint writedisable_blue:1; | ||
1195 | GLuint writedisable_green:1; | ||
1196 | GLuint writedisable_red:1; | ||
1197 | GLuint writedisable_alpha:1; | ||
1198 | GLuint surface_format:9; /**< BRW_SURFACEFORMAT_x */ | ||
1199 | GLuint data_return_format:1; | ||
1200 | GLuint pad0:1; | ||
1201 | GLuint surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ | ||
1202 | } ss0; | ||
1203 | |||
1204 | struct brw_surf_ss1 { | ||
1205 | GLuint base_addr; | ||
1206 | } ss1; | ||
1207 | |||
1208 | struct brw_surf_ss2 { | ||
1209 | GLuint pad:2; | ||
1210 | GLuint mip_count:4; | ||
1211 | GLuint width:13; | ||
1212 | GLuint height:13; | ||
1213 | } ss2; | ||
1214 | |||
1215 | struct brw_surf_ss3 { | ||
1216 | GLuint tile_walk:1; | ||
1217 | GLuint tiled_surface:1; | ||
1218 | GLuint pad:1; | ||
1219 | GLuint pitch:18; | ||
1220 | GLuint depth:11; | ||
1221 | } ss3; | ||
1222 | |||
1223 | struct brw_surf_ss4 { | ||
1224 | GLuint multisample_position_palette_index:3; | ||
1225 | GLuint pad1:1; | ||
1226 | GLuint num_multisamples:3; | ||
1227 | GLuint pad0:1; | ||
1228 | GLuint render_target_view_extent:9; | ||
1229 | GLuint min_array_elt:11; | ||
1230 | GLuint min_lod:4; | ||
1231 | } ss4; | ||
1232 | |||
1233 | struct brw_surf_ss5 { | ||
1234 | GLuint pad1:16; | ||
1235 | GLuint llc_mapping:1; | ||
1236 | GLuint mlc_mapping:1; | ||
1237 | GLuint gfdt:1; | ||
1238 | GLuint gfdt_src:1; | ||
1239 | GLuint y_offset:4; | ||
1240 | GLuint pad0:1; | ||
1241 | GLuint x_offset:7; | ||
1242 | } ss5; /* New in G4X */ | ||
1243 | |||
1244 | }; | ||
1245 | |||
1246 | |||
1247 | |||
1248 | struct brw_vertex_buffer_state | ||
1249 | { | ||
1250 | struct { | ||
1251 | GLuint pitch:11; | ||
1252 | GLuint pad:15; | ||
1253 | GLuint access_type:1; | ||
1254 | GLuint vb_index:5; | ||
1255 | } vb0; | ||
1256 | |||
1257 | GLuint start_addr; | ||
1258 | GLuint max_index; | ||
1259 | #if 1 | ||
1260 | GLuint instance_data_step_rate; /* not included for sequential/random vertices? */ | ||
1261 | #endif | ||
1262 | }; | ||
1263 | |||
1264 | #define BRW_VBP_MAX 17 | ||
1265 | |||
1266 | struct brw_vb_array_state { | ||
1267 | struct header header; | ||
1268 | struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; | ||
1269 | }; | ||
1270 | |||
1271 | |||
1272 | struct brw_vertex_element_state | ||
1273 | { | ||
1274 | struct | ||
1275 | { | ||
1276 | GLuint src_offset:11; | ||
1277 | GLuint pad:5; | ||
1278 | GLuint src_format:9; | ||
1279 | GLuint pad0:1; | ||
1280 | GLuint valid:1; | ||
1281 | GLuint vertex_buffer_index:5; | ||
1282 | } ve0; | ||
1283 | |||
1284 | struct | ||
1285 | { | ||
1286 | GLuint dst_offset:8; | ||
1287 | GLuint pad:8; | ||
1288 | GLuint vfcomponent3:4; | ||
1289 | GLuint vfcomponent2:4; | ||
1290 | GLuint vfcomponent1:4; | ||
1291 | GLuint vfcomponent0:4; | ||
1292 | } ve1; | ||
1293 | }; | ||
1294 | |||
1295 | #define BRW_VEP_MAX 18 | ||
1296 | |||
1297 | struct brw_vertex_element_packet { | ||
1298 | struct header header; | ||
1299 | struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ | ||
1300 | }; | ||
1301 | |||
1302 | |||
1303 | struct brw_urb_immediate { | ||
1304 | GLuint opcode:4; | ||
1305 | GLuint offset:6; | ||
1306 | GLuint swizzle_control:2; | ||
1307 | GLuint pad:1; | ||
1308 | GLuint allocate:1; | ||
1309 | GLuint used:1; | ||
1310 | GLuint complete:1; | ||
1311 | GLuint response_length:4; | ||
1312 | GLuint msg_length:4; | ||
1313 | GLuint msg_target:4; | ||
1314 | GLuint pad1:3; | ||
1315 | GLuint end_of_thread:1; | ||
1316 | }; | ||
1317 | |||
1318 | /* Instruction format for the execution units: | ||
1319 | */ | ||
1320 | |||
1321 | struct brw_instruction | ||
1322 | { | ||
1323 | struct | ||
1324 | { | ||
1325 | GLuint opcode:7; | ||
1326 | GLuint pad:1; | ||
1327 | GLuint access_mode:1; | ||
1328 | GLuint mask_control:1; | ||
1329 | GLuint dependency_control:2; | ||
1330 | GLuint compression_control:2; | ||
1331 | GLuint thread_control:2; | ||
1332 | GLuint predicate_control:4; | ||
1333 | GLuint predicate_inverse:1; | ||
1334 | GLuint execution_size:3; | ||
1335 | GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */ | ||
1336 | GLuint acc_wr_control:1; | ||
1337 | GLuint cmpt_control:1; | ||
1338 | GLuint debug_control:1; | ||
1339 | GLuint saturate:1; | ||
1340 | } header; | ||
1341 | |||
1342 | union { | ||
1343 | struct | ||
1344 | { | ||
1345 | GLuint dest_reg_file:2; | ||
1346 | GLuint dest_reg_type:3; | ||
1347 | GLuint src0_reg_file:2; | ||
1348 | GLuint src0_reg_type:3; | ||
1349 | GLuint src1_reg_file:2; | ||
1350 | GLuint src1_reg_type:3; | ||
1351 | GLuint pad:1; | ||
1352 | GLuint dest_subreg_nr:5; | ||
1353 | GLuint dest_reg_nr:8; | ||
1354 | GLuint dest_horiz_stride:2; | ||
1355 | GLuint dest_address_mode:1; | ||
1356 | } da1; | ||
1357 | |||
1358 | struct | ||
1359 | { | ||
1360 | GLuint dest_reg_file:2; | ||
1361 | GLuint dest_reg_type:3; | ||
1362 | GLuint src0_reg_file:2; | ||
1363 | GLuint src0_reg_type:3; | ||
1364 | GLuint src1_reg_file:2; /* 0x00000c00 */ | ||
1365 | GLuint src1_reg_type:3; /* 0x00007000 */ | ||
1366 | GLuint pad:1; | ||
1367 | GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ | ||
1368 | GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ | ||
1369 | GLuint dest_horiz_stride:2; | ||
1370 | GLuint dest_address_mode:1; | ||
1371 | } ia1; | ||
1372 | |||
1373 | struct | ||
1374 | { | ||
1375 | GLuint dest_reg_file:2; | ||
1376 | GLuint dest_reg_type:3; | ||
1377 | GLuint src0_reg_file:2; | ||
1378 | GLuint src0_reg_type:3; | ||
1379 | GLuint src1_reg_file:2; | ||
1380 | GLuint src1_reg_type:3; | ||
1381 | GLuint pad:1; | ||
1382 | GLuint dest_writemask:4; | ||
1383 | GLuint dest_subreg_nr:1; | ||
1384 | GLuint dest_reg_nr:8; | ||
1385 | GLuint dest_horiz_stride:2; | ||
1386 | GLuint dest_address_mode:1; | ||
1387 | } da16; | ||
1388 | |||
1389 | struct | ||
1390 | { | ||
1391 | GLuint dest_reg_file:2; | ||
1392 | GLuint dest_reg_type:3; | ||
1393 | GLuint src0_reg_file:2; | ||
1394 | GLuint src0_reg_type:3; | ||
1395 | GLuint pad0:6; | ||
1396 | GLuint dest_writemask:4; | ||
1397 | GLint dest_indirect_offset:6; | ||
1398 | GLuint dest_subreg_nr:3; | ||
1399 | GLuint dest_horiz_stride:2; | ||
1400 | GLuint dest_address_mode:1; | ||
1401 | } ia16; | ||
1402 | |||
1403 | struct { | ||
1404 | GLuint dest_reg_file:2; | ||
1405 | GLuint dest_reg_type:3; | ||
1406 | GLuint src0_reg_file:2; | ||
1407 | GLuint src0_reg_type:3; | ||
1408 | GLuint src1_reg_file:2; | ||
1409 | GLuint src1_reg_type:3; | ||
1410 | GLuint pad:1; | ||
1411 | |||
1412 | GLint jump_count:16; | ||
1413 | } branch_gen6; | ||
1414 | } bits1; | ||
1415 | |||
1416 | |||
1417 | union { | ||
1418 | struct | ||
1419 | { | ||
1420 | GLuint src0_subreg_nr:5; | ||
1421 | GLuint src0_reg_nr:8; | ||
1422 | GLuint src0_abs:1; | ||
1423 | GLuint src0_negate:1; | ||
1424 | GLuint src0_address_mode:1; | ||
1425 | GLuint src0_horiz_stride:2; | ||
1426 | GLuint src0_width:3; | ||
1427 | GLuint src0_vert_stride:4; | ||
1428 | GLuint flag_reg_nr:1; | ||
1429 | GLuint pad:6; | ||
1430 | } da1; | ||
1431 | |||
1432 | struct | ||
1433 | { | ||
1434 | GLint src0_indirect_offset:10; | ||
1435 | GLuint src0_subreg_nr:3; | ||
1436 | GLuint src0_abs:1; | ||
1437 | GLuint src0_negate:1; | ||
1438 | GLuint src0_address_mode:1; | ||
1439 | GLuint src0_horiz_stride:2; | ||
1440 | GLuint src0_width:3; | ||
1441 | GLuint src0_vert_stride:4; | ||
1442 | GLuint flag_reg_nr:1; | ||
1443 | GLuint pad:6; | ||
1444 | } ia1; | ||
1445 | |||
1446 | struct | ||
1447 | { | ||
1448 | GLuint src0_swz_x:2; | ||
1449 | GLuint src0_swz_y:2; | ||
1450 | GLuint src0_subreg_nr:1; | ||
1451 | GLuint src0_reg_nr:8; | ||
1452 | GLuint src0_abs:1; | ||
1453 | GLuint src0_negate:1; | ||
1454 | GLuint src0_address_mode:1; | ||
1455 | GLuint src0_swz_z:2; | ||
1456 | GLuint src0_swz_w:2; | ||
1457 | GLuint pad0:1; | ||
1458 | GLuint src0_vert_stride:4; | ||
1459 | GLuint flag_reg_nr:1; | ||
1460 | GLuint pad1:6; | ||
1461 | } da16; | ||
1462 | |||
1463 | struct | ||
1464 | { | ||
1465 | GLuint src0_swz_x:2; | ||
1466 | GLuint src0_swz_y:2; | ||
1467 | GLint src0_indirect_offset:6; | ||
1468 | GLuint src0_subreg_nr:3; | ||
1469 | GLuint src0_abs:1; | ||
1470 | GLuint src0_negate:1; | ||
1471 | GLuint src0_address_mode:1; | ||
1472 | GLuint src0_swz_z:2; | ||
1473 | GLuint src0_swz_w:2; | ||
1474 | GLuint pad0:1; | ||
1475 | GLuint src0_vert_stride:4; | ||
1476 | GLuint flag_reg_nr:1; | ||
1477 | GLuint pad1:6; | ||
1478 | } ia16; | ||
1479 | |||
1480 | struct | ||
1481 | { | ||
1482 | GLuint pad:26; | ||
1483 | GLuint end_of_thread:1; | ||
1484 | GLuint pad1:1; | ||
1485 | GLuint sfid:4; | ||
1486 | } send_gen5; /* for Ironlake only */ | ||
1487 | |||
1488 | } bits2; | ||
1489 | |||
1490 | union | ||
1491 | { | ||
1492 | struct | ||
1493 | { | ||
1494 | GLuint src1_subreg_nr:5; | ||
1495 | GLuint src1_reg_nr:8; | ||
1496 | GLuint src1_abs:1; | ||
1497 | GLuint src1_negate:1; | ||
1498 | GLuint src1_address_mode:1; | ||
1499 | GLuint src1_horiz_stride:2; | ||
1500 | GLuint src1_width:3; | ||
1501 | GLuint src1_vert_stride:4; | ||
1502 | GLuint pad0:7; | ||
1503 | } da1; | ||
1504 | |||
1505 | struct | ||
1506 | { | ||
1507 | GLuint src1_swz_x:2; | ||
1508 | GLuint src1_swz_y:2; | ||
1509 | GLuint src1_subreg_nr:1; | ||
1510 | GLuint src1_reg_nr:8; | ||
1511 | GLuint src1_abs:1; | ||
1512 | GLuint src1_negate:1; | ||
1513 | GLuint src1_address_mode:1; | ||
1514 | GLuint src1_swz_z:2; | ||
1515 | GLuint src1_swz_w:2; | ||
1516 | GLuint pad1:1; | ||
1517 | GLuint src1_vert_stride:4; | ||
1518 | GLuint pad2:7; | ||
1519 | } da16; | ||
1520 | |||
1521 | struct | ||
1522 | { | ||
1523 | GLint src1_indirect_offset:10; | ||
1524 | GLuint src1_subreg_nr:3; | ||
1525 | GLuint src1_abs:1; | ||
1526 | GLuint src1_negate:1; | ||
1527 | GLuint src1_address_mode:1; | ||
1528 | GLuint src1_horiz_stride:2; | ||
1529 | GLuint src1_width:3; | ||
1530 | GLuint src1_vert_stride:4; | ||
1531 | GLuint flag_reg_nr:1; | ||
1532 | GLuint pad1:6; | ||
1533 | } ia1; | ||
1534 | |||
1535 | struct | ||
1536 | { | ||
1537 | GLuint src1_swz_x:2; | ||
1538 | GLuint src1_swz_y:2; | ||
1539 | GLint src1_indirect_offset:6; | ||
1540 | GLuint src1_subreg_nr:3; | ||
1541 | GLuint src1_abs:1; | ||
1542 | GLuint src1_negate:1; | ||
1543 | GLuint pad0:1; | ||
1544 | GLuint src1_swz_z:2; | ||
1545 | GLuint src1_swz_w:2; | ||
1546 | GLuint pad1:1; | ||
1547 | GLuint src1_vert_stride:4; | ||
1548 | GLuint flag_reg_nr:1; | ||
1549 | GLuint pad2:6; | ||
1550 | } ia16; | ||
1551 | |||
1552 | |||
1553 | struct | ||
1554 | { | ||
1555 | GLint jump_count:16; /* note: signed */ | ||
1556 | GLuint pop_count:4; | ||
1557 | GLuint pad0:12; | ||
1558 | } if_else; | ||
1559 | |||
1560 | struct | ||
1561 | { | ||
1562 | /* Signed jump distance to the ip to jump to if all channels | ||
1563 | * are disabled after the break or continue. It should point | ||
1564 | * to the end of the innermost control flow block, as that's | ||
1565 | * where some channel could get re-enabled. | ||
1566 | */ | ||
1567 | int jip:16; | ||
1568 | |||
1569 | /* Signed jump distance to the location to resume execution | ||
1570 | * of this channel if it's enabled for the break or continue. | ||
1571 | */ | ||
1572 | int uip:16; | ||
1573 | } break_cont; | ||
1574 | |||
1575 | struct { | ||
1576 | GLuint function:4; | ||
1577 | GLuint int_type:1; | ||
1578 | GLuint precision:1; | ||
1579 | GLuint saturate:1; | ||
1580 | GLuint data_type:1; | ||
1581 | GLuint pad0:8; | ||
1582 | GLuint response_length:4; | ||
1583 | GLuint msg_length:4; | ||
1584 | GLuint msg_target:4; | ||
1585 | GLuint pad1:3; | ||
1586 | GLuint end_of_thread:1; | ||
1587 | } math; | ||
1588 | |||
1589 | struct { | ||
1590 | GLuint function:4; | ||
1591 | GLuint int_type:1; | ||
1592 | GLuint precision:1; | ||
1593 | GLuint saturate:1; | ||
1594 | GLuint data_type:1; | ||
1595 | GLuint snapshot:1; | ||
1596 | GLuint pad0:10; | ||
1597 | GLuint header_present:1; | ||
1598 | GLuint response_length:5; | ||
1599 | GLuint msg_length:4; | ||
1600 | GLuint pad1:2; | ||
1601 | GLuint end_of_thread:1; | ||
1602 | } math_gen5; | ||
1603 | |||
1604 | struct { | ||
1605 | GLuint binding_table_index:8; | ||
1606 | GLuint sampler:4; | ||
1607 | GLuint return_format:2; | ||
1608 | GLuint msg_type:2; | ||
1609 | GLuint response_length:4; | ||
1610 | GLuint msg_length:4; | ||
1611 | GLuint msg_target:4; | ||
1612 | GLuint pad1:3; | ||
1613 | GLuint end_of_thread:1; | ||
1614 | } sampler; | ||
1615 | |||
1616 | struct { | ||
1617 | GLuint binding_table_index:8; | ||
1618 | GLuint sampler:4; | ||
1619 | GLuint msg_type:4; | ||
1620 | GLuint response_length:4; | ||
1621 | GLuint msg_length:4; | ||
1622 | GLuint msg_target:4; | ||
1623 | GLuint pad1:3; | ||
1624 | GLuint end_of_thread:1; | ||
1625 | } sampler_g4x; | ||
1626 | |||
1627 | struct { | ||
1628 | GLuint binding_table_index:8; | ||
1629 | GLuint sampler:4; | ||
1630 | GLuint msg_type:4; | ||
1631 | GLuint simd_mode:2; | ||
1632 | GLuint pad0:1; | ||
1633 | GLuint header_present:1; | ||
1634 | GLuint response_length:5; | ||
1635 | GLuint msg_length:4; | ||
1636 | GLuint pad1:2; | ||
1637 | GLuint end_of_thread:1; | ||
1638 | } sampler_gen5; | ||
1639 | |||
1640 | struct brw_urb_immediate urb; | ||
1641 | |||
1642 | struct { | ||
1643 | GLuint opcode:4; | ||
1644 | GLuint offset:6; | ||
1645 | GLuint swizzle_control:2; | ||
1646 | GLuint pad:1; | ||
1647 | GLuint allocate:1; | ||
1648 | GLuint used:1; | ||
1649 | GLuint complete:1; | ||
1650 | GLuint pad0:3; | ||
1651 | GLuint header_present:1; | ||
1652 | GLuint response_length:5; | ||
1653 | GLuint msg_length:4; | ||
1654 | GLuint pad1:2; | ||
1655 | GLuint end_of_thread:1; | ||
1656 | } urb_gen5; | ||
1657 | |||
1658 | struct { | ||
1659 | GLuint binding_table_index:8; | ||
1660 | GLuint msg_control:4; | ||
1661 | GLuint msg_type:2; | ||
1662 | GLuint target_cache:2; | ||
1663 | GLuint response_length:4; | ||
1664 | GLuint msg_length:4; | ||
1665 | GLuint msg_target:4; | ||
1666 | GLuint pad1:3; | ||
1667 | GLuint end_of_thread:1; | ||
1668 | } dp_read; | ||
1669 | |||
1670 | struct { | ||
1671 | GLuint binding_table_index:8; | ||
1672 | GLuint msg_control:3; | ||
1673 | GLuint msg_type:3; | ||
1674 | GLuint target_cache:2; | ||
1675 | GLuint response_length:4; | ||
1676 | GLuint msg_length:4; | ||
1677 | GLuint msg_target:4; | ||
1678 | GLuint pad1:3; | ||
1679 | GLuint end_of_thread:1; | ||
1680 | } dp_read_g4x; | ||
1681 | |||
1682 | struct { | ||
1683 | GLuint binding_table_index:8; | ||
1684 | GLuint msg_control:3; | ||
1685 | GLuint msg_type:3; | ||
1686 | GLuint target_cache:2; | ||
1687 | GLuint pad0:3; | ||
1688 | GLuint header_present:1; | ||
1689 | GLuint response_length:5; | ||
1690 | GLuint msg_length:4; | ||
1691 | GLuint pad1:2; | ||
1692 | GLuint end_of_thread:1; | ||
1693 | } dp_read_gen5; | ||
1694 | |||
1695 | struct { | ||
1696 | GLuint binding_table_index:8; | ||
1697 | GLuint msg_control:3; | ||
1698 | GLuint pixel_scoreboard_clear:1; | ||
1699 | GLuint msg_type:3; | ||
1700 | GLuint send_commit_msg:1; | ||
1701 | GLuint response_length:4; | ||
1702 | GLuint msg_length:4; | ||
1703 | GLuint msg_target:4; | ||
1704 | GLuint pad1:3; | ||
1705 | GLuint end_of_thread:1; | ||
1706 | } dp_write; | ||
1707 | |||
1708 | struct { | ||
1709 | GLuint binding_table_index:8; | ||
1710 | GLuint msg_control:3; | ||
1711 | GLuint pixel_scoreboard_clear:1; | ||
1712 | GLuint msg_type:3; | ||
1713 | GLuint send_commit_msg:1; | ||
1714 | GLuint pad0:3; | ||
1715 | GLuint header_present:1; | ||
1716 | GLuint response_length:5; | ||
1717 | GLuint msg_length:4; | ||
1718 | GLuint pad1:2; | ||
1719 | GLuint end_of_thread:1; | ||
1720 | } dp_write_gen5; | ||
1721 | |||
1722 | /* Sandybridge DP for sample cache, constant cache, render cache */ | ||
1723 | struct { | ||
1724 | GLuint binding_table_index:8; | ||
1725 | GLuint msg_control:5; | ||
1726 | GLuint msg_type:3; | ||
1727 | GLuint pad0:3; | ||
1728 | GLuint header_present:1; | ||
1729 | GLuint response_length:5; | ||
1730 | GLuint msg_length:4; | ||
1731 | GLuint pad1:2; | ||
1732 | GLuint end_of_thread:1; | ||
1733 | } dp_sampler_const_cache; | ||
1734 | |||
1735 | struct { | ||
1736 | GLuint binding_table_index:8; | ||
1737 | GLuint msg_control:3; | ||
1738 | GLuint slot_group_select:1; | ||
1739 | GLuint pixel_scoreboard_clear:1; | ||
1740 | GLuint msg_type:4; | ||
1741 | GLuint send_commit_msg:1; | ||
1742 | GLuint pad0:1; | ||
1743 | GLuint header_present:1; | ||
1744 | GLuint response_length:5; | ||
1745 | GLuint msg_length:4; | ||
1746 | GLuint pad1:2; | ||
1747 | GLuint end_of_thread:1; | ||
1748 | } dp_render_cache; | ||
1749 | |||
1750 | struct { | ||
1751 | GLuint function_control:16; | ||
1752 | GLuint response_length:4; | ||
1753 | GLuint msg_length:4; | ||
1754 | GLuint msg_target:4; | ||
1755 | GLuint pad1:3; | ||
1756 | GLuint end_of_thread:1; | ||
1757 | } generic; | ||
1758 | |||
1759 | /* Of this struct, only end_of_thread is not present for gen6. */ | ||
1760 | struct { | ||
1761 | GLuint function_control:19; | ||
1762 | GLuint header_present:1; | ||
1763 | GLuint response_length:5; | ||
1764 | GLuint msg_length:4; | ||
1765 | GLuint pad1:2; | ||
1766 | GLuint end_of_thread:1; | ||
1767 | } generic_gen5; | ||
1768 | |||
1769 | GLint d; | ||
1770 | GLuint ud; | ||
1771 | float f; | ||
1772 | } bits3; | ||
1773 | }; | ||
1774 | |||
1775 | |||
1776 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_structs_dump.c b/src/gallium/drivers/i965/brw_structs_dump.c deleted file mode 100644 index f3de2f995b3..00000000000 --- a/src/gallium/drivers/i965/brw_structs_dump.c +++ /dev/null | |||
@@ -1,1247 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2009 VMware, Inc. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
18 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
19 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
20 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * The above copyright notice and this permission notice (including the | ||
23 | * next paragraph) shall be included in all copies or substantial portions | ||
24 | * of the Software. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * Dump i965 data structures. | ||
31 | * | ||
32 | * Generated automatically from brw_structs.h by brw_structs_dump.py. | ||
33 | */ | ||
34 | |||
35 | #include "util/u_debug.h" | ||
36 | |||
37 | #include "brw_types.h" | ||
38 | #include "brw_structs.h" | ||
39 | #include "brw_structs_dump.h" | ||
40 | |||
41 | void | ||
42 | brw_dump_3d_control(const struct brw_3d_control *ptr) | ||
43 | { | ||
44 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
45 | debug_printf("\t\t.header.notify_enable = 0x%x\n", (*ptr).header.notify_enable); | ||
46 | debug_printf("\t\t.header.wc_flush_enable = 0x%x\n", (*ptr).header.wc_flush_enable); | ||
47 | debug_printf("\t\t.header.depth_stall_enable = 0x%x\n", (*ptr).header.depth_stall_enable); | ||
48 | debug_printf("\t\t.header.operation = 0x%x\n", (*ptr).header.operation); | ||
49 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
50 | debug_printf("\t\t.dest.dest_addr_type = 0x%x\n", (*ptr).dest.dest_addr_type); | ||
51 | debug_printf("\t\t.dest.dest_addr = 0x%x\n", (*ptr).dest.dest_addr); | ||
52 | debug_printf("\t\t.dword2 = 0x%x\n", (*ptr).dword2); | ||
53 | debug_printf("\t\t.dword3 = 0x%x\n", (*ptr).dword3); | ||
54 | } | ||
55 | |||
56 | void | ||
57 | brw_dump_3d_primitive(const struct brw_3d_primitive *ptr) | ||
58 | { | ||
59 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
60 | debug_printf("\t\t.header.topology = 0x%x\n", (*ptr).header.topology); | ||
61 | debug_printf("\t\t.header.indexed = 0x%x\n", (*ptr).header.indexed); | ||
62 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
63 | debug_printf("\t\t.verts_per_instance = 0x%x\n", (*ptr).verts_per_instance); | ||
64 | debug_printf("\t\t.start_vert_location = 0x%x\n", (*ptr).start_vert_location); | ||
65 | debug_printf("\t\t.instance_count = 0x%x\n", (*ptr).instance_count); | ||
66 | debug_printf("\t\t.start_instance_location = 0x%x\n", (*ptr).start_instance_location); | ||
67 | debug_printf("\t\t.base_vert_location = 0x%x\n", (*ptr).base_vert_location); | ||
68 | } | ||
69 | |||
70 | void | ||
71 | brw_dump_aa_line_parameters(const struct brw_aa_line_parameters *ptr) | ||
72 | { | ||
73 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
74 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
75 | debug_printf("\t\t.bits0.aa_coverage_scope = 0x%x\n", (*ptr).bits0.aa_coverage_slope); | ||
76 | debug_printf("\t\t.bits0.aa_coverage_bias = 0x%x\n", (*ptr).bits0.aa_coverage_bias); | ||
77 | debug_printf("\t\t.bits1.aa_coverage_endcap_slope = 0x%x\n", (*ptr).bits1.aa_coverage_endcap_slope); | ||
78 | debug_printf("\t\t.bits1.aa_coverage_endcap_bias = 0x%x\n", (*ptr).bits1.aa_coverage_endcap_bias); | ||
79 | } | ||
80 | |||
81 | void | ||
82 | brw_dump_binding_table_pointers(const struct brw_binding_table_pointers *ptr) | ||
83 | { | ||
84 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
85 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
86 | debug_printf("\t\t.vs = 0x%x\n", (*ptr).vs); | ||
87 | debug_printf("\t\t.gs = 0x%x\n", (*ptr).gs); | ||
88 | debug_printf("\t\t.clp = 0x%x\n", (*ptr).clp); | ||
89 | debug_printf("\t\t.sf = 0x%x\n", (*ptr).sf); | ||
90 | debug_printf("\t\t.wm = 0x%x\n", (*ptr).wm); | ||
91 | } | ||
92 | |||
93 | void | ||
94 | brw_dump_blend_constant_color(const struct brw_blend_constant_color *ptr) | ||
95 | { | ||
96 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
97 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
98 | debug_printf("\t\t.blend_constant_color[0] = %f\n", (*ptr).blend_constant_color[0]); | ||
99 | debug_printf("\t\t.blend_constant_color[1] = %f\n", (*ptr).blend_constant_color[1]); | ||
100 | debug_printf("\t\t.blend_constant_color[2] = %f\n", (*ptr).blend_constant_color[2]); | ||
101 | debug_printf("\t\t.blend_constant_color[3] = %f\n", (*ptr).blend_constant_color[3]); | ||
102 | } | ||
103 | |||
104 | void | ||
105 | brw_dump_cc0(const struct brw_cc0 *ptr) | ||
106 | { | ||
107 | debug_printf("\t\t.bf_stencil_pass_depth_pass_op = 0x%x\n", (*ptr).bf_stencil_pass_depth_pass_op); | ||
108 | debug_printf("\t\t.bf_stencil_pass_depth_fail_op = 0x%x\n", (*ptr).bf_stencil_pass_depth_fail_op); | ||
109 | debug_printf("\t\t.bf_stencil_fail_op = 0x%x\n", (*ptr).bf_stencil_fail_op); | ||
110 | debug_printf("\t\t.bf_stencil_func = 0x%x\n", (*ptr).bf_stencil_func); | ||
111 | debug_printf("\t\t.bf_stencil_enable = 0x%x\n", (*ptr).bf_stencil_enable); | ||
112 | debug_printf("\t\t.stencil_write_enable = 0x%x\n", (*ptr).stencil_write_enable); | ||
113 | debug_printf("\t\t.stencil_pass_depth_pass_op = 0x%x\n", (*ptr).stencil_pass_depth_pass_op); | ||
114 | debug_printf("\t\t.stencil_pass_depth_fail_op = 0x%x\n", (*ptr).stencil_pass_depth_fail_op); | ||
115 | debug_printf("\t\t.stencil_fail_op = 0x%x\n", (*ptr).stencil_fail_op); | ||
116 | debug_printf("\t\t.stencil_func = 0x%x\n", (*ptr).stencil_func); | ||
117 | debug_printf("\t\t.stencil_enable = 0x%x\n", (*ptr).stencil_enable); | ||
118 | } | ||
119 | |||
120 | void | ||
121 | brw_dump_cc1(const struct brw_cc1 *ptr) | ||
122 | { | ||
123 | debug_printf("\t\t.bf_stencil_ref = 0x%x\n", (*ptr).bf_stencil_ref); | ||
124 | debug_printf("\t\t.stencil_write_mask = 0x%x\n", (*ptr).stencil_write_mask); | ||
125 | debug_printf("\t\t.stencil_test_mask = 0x%x\n", (*ptr).stencil_test_mask); | ||
126 | debug_printf("\t\t.stencil_ref = 0x%x\n", (*ptr).stencil_ref); | ||
127 | } | ||
128 | |||
129 | void | ||
130 | brw_dump_cc2(const struct brw_cc2 *ptr) | ||
131 | { | ||
132 | debug_printf("\t\t.logicop_enable = 0x%x\n", (*ptr).logicop_enable); | ||
133 | debug_printf("\t\t.depth_write_enable = 0x%x\n", (*ptr).depth_write_enable); | ||
134 | debug_printf("\t\t.depth_test_function = 0x%x\n", (*ptr).depth_test_function); | ||
135 | debug_printf("\t\t.depth_test = 0x%x\n", (*ptr).depth_test); | ||
136 | debug_printf("\t\t.bf_stencil_write_mask = 0x%x\n", (*ptr).bf_stencil_write_mask); | ||
137 | debug_printf("\t\t.bf_stencil_test_mask = 0x%x\n", (*ptr).bf_stencil_test_mask); | ||
138 | } | ||
139 | |||
140 | void | ||
141 | brw_dump_cc3(const struct brw_cc3 *ptr) | ||
142 | { | ||
143 | debug_printf("\t\t.alpha_test_func = 0x%x\n", (*ptr).alpha_test_func); | ||
144 | debug_printf("\t\t.alpha_test = 0x%x\n", (*ptr).alpha_test); | ||
145 | debug_printf("\t\t.blend_enable = 0x%x\n", (*ptr).blend_enable); | ||
146 | debug_printf("\t\t.ia_blend_enable = 0x%x\n", (*ptr).ia_blend_enable); | ||
147 | debug_printf("\t\t.alpha_test_format = 0x%x\n", (*ptr).alpha_test_format); | ||
148 | } | ||
149 | |||
150 | void | ||
151 | brw_dump_cc4(const struct brw_cc4 *ptr) | ||
152 | { | ||
153 | debug_printf("\t\t.cc_viewport_state_offset = 0x%x\n", (*ptr).cc_viewport_state_offset); | ||
154 | } | ||
155 | |||
156 | void | ||
157 | brw_dump_cc5(const struct brw_cc5 *ptr) | ||
158 | { | ||
159 | debug_printf("\t\t.ia_dest_blend_factor = 0x%x\n", (*ptr).ia_dest_blend_factor); | ||
160 | debug_printf("\t\t.ia_src_blend_factor = 0x%x\n", (*ptr).ia_src_blend_factor); | ||
161 | debug_printf("\t\t.ia_blend_function = 0x%x\n", (*ptr).ia_blend_function); | ||
162 | debug_printf("\t\t.statistics_enable = 0x%x\n", (*ptr).statistics_enable); | ||
163 | debug_printf("\t\t.logicop_func = 0x%x\n", (*ptr).logicop_func); | ||
164 | debug_printf("\t\t.dither_enable = 0x%x\n", (*ptr).dither_enable); | ||
165 | } | ||
166 | |||
167 | void | ||
168 | brw_dump_cc6(const struct brw_cc6 *ptr) | ||
169 | { | ||
170 | debug_printf("\t\t.clamp_post_alpha_blend = 0x%x\n", (*ptr).clamp_post_alpha_blend); | ||
171 | debug_printf("\t\t.clamp_pre_alpha_blend = 0x%x\n", (*ptr).clamp_pre_alpha_blend); | ||
172 | debug_printf("\t\t.clamp_range = 0x%x\n", (*ptr).clamp_range); | ||
173 | debug_printf("\t\t.y_dither_offset = 0x%x\n", (*ptr).y_dither_offset); | ||
174 | debug_printf("\t\t.x_dither_offset = 0x%x\n", (*ptr).x_dither_offset); | ||
175 | debug_printf("\t\t.dest_blend_factor = 0x%x\n", (*ptr).dest_blend_factor); | ||
176 | debug_printf("\t\t.src_blend_factor = 0x%x\n", (*ptr).src_blend_factor); | ||
177 | debug_printf("\t\t.blend_function = 0x%x\n", (*ptr).blend_function); | ||
178 | } | ||
179 | |||
180 | void | ||
181 | brw_dump_cc7(const struct brw_cc7 *ptr) | ||
182 | { | ||
183 | debug_printf("\t\t.alpha_ref.f = %f\n", (*ptr).alpha_ref.f); | ||
184 | debug_printf("\t\t.alpha_ref.ub[0] = 0x%x\n", (*ptr).alpha_ref.ub[0]); | ||
185 | debug_printf("\t\t.alpha_ref.ub[1] = 0x%x\n", (*ptr).alpha_ref.ub[1]); | ||
186 | debug_printf("\t\t.alpha_ref.ub[2] = 0x%x\n", (*ptr).alpha_ref.ub[2]); | ||
187 | debug_printf("\t\t.alpha_ref.ub[3] = 0x%x\n", (*ptr).alpha_ref.ub[3]); | ||
188 | } | ||
189 | |||
190 | void | ||
191 | brw_dump_cc_unit_state(const struct brw_cc_unit_state *ptr) | ||
192 | { | ||
193 | debug_printf("\t\t.cc0.bf_stencil_pass_depth_pass_op = 0x%x\n", (*ptr).cc0.bf_stencil_pass_depth_pass_op); | ||
194 | debug_printf("\t\t.cc0.bf_stencil_pass_depth_fail_op = 0x%x\n", (*ptr).cc0.bf_stencil_pass_depth_fail_op); | ||
195 | debug_printf("\t\t.cc0.bf_stencil_fail_op = 0x%x\n", (*ptr).cc0.bf_stencil_fail_op); | ||
196 | debug_printf("\t\t.cc0.bf_stencil_func = 0x%x\n", (*ptr).cc0.bf_stencil_func); | ||
197 | debug_printf("\t\t.cc0.bf_stencil_enable = 0x%x\n", (*ptr).cc0.bf_stencil_enable); | ||
198 | debug_printf("\t\t.cc0.stencil_write_enable = 0x%x\n", (*ptr).cc0.stencil_write_enable); | ||
199 | debug_printf("\t\t.cc0.stencil_pass_depth_pass_op = 0x%x\n", (*ptr).cc0.stencil_pass_depth_pass_op); | ||
200 | debug_printf("\t\t.cc0.stencil_pass_depth_fail_op = 0x%x\n", (*ptr).cc0.stencil_pass_depth_fail_op); | ||
201 | debug_printf("\t\t.cc0.stencil_fail_op = 0x%x\n", (*ptr).cc0.stencil_fail_op); | ||
202 | debug_printf("\t\t.cc0.stencil_func = 0x%x\n", (*ptr).cc0.stencil_func); | ||
203 | debug_printf("\t\t.cc0.stencil_enable = 0x%x\n", (*ptr).cc0.stencil_enable); | ||
204 | debug_printf("\t\t.cc1.bf_stencil_ref = 0x%x\n", (*ptr).cc1.bf_stencil_ref); | ||
205 | debug_printf("\t\t.cc1.stencil_write_mask = 0x%x\n", (*ptr).cc1.stencil_write_mask); | ||
206 | debug_printf("\t\t.cc1.stencil_test_mask = 0x%x\n", (*ptr).cc1.stencil_test_mask); | ||
207 | debug_printf("\t\t.cc1.stencil_ref = 0x%x\n", (*ptr).cc1.stencil_ref); | ||
208 | debug_printf("\t\t.cc2.logicop_enable = 0x%x\n", (*ptr).cc2.logicop_enable); | ||
209 | debug_printf("\t\t.cc2.depth_write_enable = 0x%x\n", (*ptr).cc2.depth_write_enable); | ||
210 | debug_printf("\t\t.cc2.depth_test_function = 0x%x\n", (*ptr).cc2.depth_test_function); | ||
211 | debug_printf("\t\t.cc2.depth_test = 0x%x\n", (*ptr).cc2.depth_test); | ||
212 | debug_printf("\t\t.cc2.bf_stencil_write_mask = 0x%x\n", (*ptr).cc2.bf_stencil_write_mask); | ||
213 | debug_printf("\t\t.cc2.bf_stencil_test_mask = 0x%x\n", (*ptr).cc2.bf_stencil_test_mask); | ||
214 | debug_printf("\t\t.cc3.alpha_test_func = 0x%x\n", (*ptr).cc3.alpha_test_func); | ||
215 | debug_printf("\t\t.cc3.alpha_test = 0x%x\n", (*ptr).cc3.alpha_test); | ||
216 | debug_printf("\t\t.cc3.blend_enable = 0x%x\n", (*ptr).cc3.blend_enable); | ||
217 | debug_printf("\t\t.cc3.ia_blend_enable = 0x%x\n", (*ptr).cc3.ia_blend_enable); | ||
218 | debug_printf("\t\t.cc3.alpha_test_format = 0x%x\n", (*ptr).cc3.alpha_test_format); | ||
219 | debug_printf("\t\t.cc4.cc_viewport_state_offset = 0x%x\n", (*ptr).cc4.cc_viewport_state_offset); | ||
220 | debug_printf("\t\t.cc5.ia_dest_blend_factor = 0x%x\n", (*ptr).cc5.ia_dest_blend_factor); | ||
221 | debug_printf("\t\t.cc5.ia_src_blend_factor = 0x%x\n", (*ptr).cc5.ia_src_blend_factor); | ||
222 | debug_printf("\t\t.cc5.ia_blend_function = 0x%x\n", (*ptr).cc5.ia_blend_function); | ||
223 | debug_printf("\t\t.cc5.statistics_enable = 0x%x\n", (*ptr).cc5.statistics_enable); | ||
224 | debug_printf("\t\t.cc5.logicop_func = 0x%x\n", (*ptr).cc5.logicop_func); | ||
225 | debug_printf("\t\t.cc5.dither_enable = 0x%x\n", (*ptr).cc5.dither_enable); | ||
226 | debug_printf("\t\t.cc6.clamp_post_alpha_blend = 0x%x\n", (*ptr).cc6.clamp_post_alpha_blend); | ||
227 | debug_printf("\t\t.cc6.clamp_pre_alpha_blend = 0x%x\n", (*ptr).cc6.clamp_pre_alpha_blend); | ||
228 | debug_printf("\t\t.cc6.clamp_range = 0x%x\n", (*ptr).cc6.clamp_range); | ||
229 | debug_printf("\t\t.cc6.y_dither_offset = 0x%x\n", (*ptr).cc6.y_dither_offset); | ||
230 | debug_printf("\t\t.cc6.x_dither_offset = 0x%x\n", (*ptr).cc6.x_dither_offset); | ||
231 | debug_printf("\t\t.cc6.dest_blend_factor = 0x%x\n", (*ptr).cc6.dest_blend_factor); | ||
232 | debug_printf("\t\t.cc6.src_blend_factor = 0x%x\n", (*ptr).cc6.src_blend_factor); | ||
233 | debug_printf("\t\t.cc6.blend_function = 0x%x\n", (*ptr).cc6.blend_function); | ||
234 | debug_printf("\t\t.cc7.alpha_ref.f = %f\n", (*ptr).cc7.alpha_ref.f); | ||
235 | debug_printf("\t\t.cc7.alpha_ref.ub[0] = 0x%x\n", (*ptr).cc7.alpha_ref.ub[0]); | ||
236 | debug_printf("\t\t.cc7.alpha_ref.ub[1] = 0x%x\n", (*ptr).cc7.alpha_ref.ub[1]); | ||
237 | debug_printf("\t\t.cc7.alpha_ref.ub[2] = 0x%x\n", (*ptr).cc7.alpha_ref.ub[2]); | ||
238 | debug_printf("\t\t.cc7.alpha_ref.ub[3] = 0x%x\n", (*ptr).cc7.alpha_ref.ub[3]); | ||
239 | } | ||
240 | |||
241 | void | ||
242 | brw_dump_cc_viewport(const struct brw_cc_viewport *ptr) | ||
243 | { | ||
244 | debug_printf("\t\t.min_depth = %f\n", (*ptr).min_depth); | ||
245 | debug_printf("\t\t.max_depth = %f\n", (*ptr).max_depth); | ||
246 | } | ||
247 | |||
248 | void | ||
249 | brw_dump_clip_unit_state(const struct brw_clip_unit_state *ptr) | ||
250 | { | ||
251 | debug_printf("\t\t.thread0.grf_reg_count = 0x%x\n", (*ptr).thread0.grf_reg_count); | ||
252 | debug_printf("\t\t.thread0.kernel_start_pointer = 0x%x\n", (*ptr).thread0.kernel_start_pointer); | ||
253 | debug_printf("\t\t.thread1.sw_exception_enable = 0x%x\n", (*ptr).thread1.sw_exception_enable); | ||
254 | debug_printf("\t\t.thread1.mask_stack_exception_enable = 0x%x\n", (*ptr).thread1.mask_stack_exception_enable); | ||
255 | debug_printf("\t\t.thread1.illegal_op_exception_enable = 0x%x\n", (*ptr).thread1.illegal_op_exception_enable); | ||
256 | debug_printf("\t\t.thread1.floating_point_mode = 0x%x\n", (*ptr).thread1.floating_point_mode); | ||
257 | debug_printf("\t\t.thread1.thread_priority = 0x%x\n", (*ptr).thread1.thread_priority); | ||
258 | debug_printf("\t\t.thread1.binding_table_entry_count = 0x%x\n", (*ptr).thread1.binding_table_entry_count); | ||
259 | debug_printf("\t\t.thread1.single_program_flow = 0x%x\n", (*ptr).thread1.single_program_flow); | ||
260 | debug_printf("\t\t.thread2.per_thread_scratch_space = 0x%x\n", (*ptr).thread2.per_thread_scratch_space); | ||
261 | debug_printf("\t\t.thread2.scratch_space_base_pointer = 0x%x\n", (*ptr).thread2.scratch_space_base_pointer); | ||
262 | debug_printf("\t\t.thread3.dispatch_grf_start_reg = 0x%x\n", (*ptr).thread3.dispatch_grf_start_reg); | ||
263 | debug_printf("\t\t.thread3.urb_entry_read_offset = 0x%x\n", (*ptr).thread3.urb_entry_read_offset); | ||
264 | debug_printf("\t\t.thread3.urb_entry_read_length = 0x%x\n", (*ptr).thread3.urb_entry_read_length); | ||
265 | debug_printf("\t\t.thread3.const_urb_entry_read_offset = 0x%x\n", (*ptr).thread3.const_urb_entry_read_offset); | ||
266 | debug_printf("\t\t.thread3.const_urb_entry_read_length = 0x%x\n", (*ptr).thread3.const_urb_entry_read_length); | ||
267 | debug_printf("\t\t.thread4.gs_output_stats = 0x%x\n", (*ptr).thread4.gs_output_stats); | ||
268 | debug_printf("\t\t.thread4.stats_enable = 0x%x\n", (*ptr).thread4.stats_enable); | ||
269 | debug_printf("\t\t.thread4.nr_urb_entries = 0x%x\n", (*ptr).thread4.nr_urb_entries); | ||
270 | debug_printf("\t\t.thread4.urb_entry_allocation_size = 0x%x\n", (*ptr).thread4.urb_entry_allocation_size); | ||
271 | debug_printf("\t\t.thread4.max_threads = 0x%x\n", (*ptr).thread4.max_threads); | ||
272 | debug_printf("\t\t.clip5.clip_mode = 0x%x\n", (*ptr).clip5.clip_mode); | ||
273 | debug_printf("\t\t.clip5.userclip_enable_flags = 0x%x\n", (*ptr).clip5.userclip_enable_flags); | ||
274 | debug_printf("\t\t.clip5.userclip_must_clip = 0x%x\n", (*ptr).clip5.userclip_must_clip); | ||
275 | debug_printf("\t\t.clip5.negative_w_clip_test = 0x%x\n", (*ptr).clip5.negative_w_clip_test); | ||
276 | debug_printf("\t\t.clip5.guard_band_enable = 0x%x\n", (*ptr).clip5.guard_band_enable); | ||
277 | debug_printf("\t\t.clip5.viewport_z_clip_enable = 0x%x\n", (*ptr).clip5.viewport_z_clip_enable); | ||
278 | debug_printf("\t\t.clip5.viewport_xy_clip_enable = 0x%x\n", (*ptr).clip5.viewport_xy_clip_enable); | ||
279 | debug_printf("\t\t.clip5.vertex_position_space = 0x%x\n", (*ptr).clip5.vertex_position_space); | ||
280 | debug_printf("\t\t.clip5.api_mode = 0x%x\n", (*ptr).clip5.api_mode); | ||
281 | debug_printf("\t\t.clip6.clipper_viewport_state_ptr = 0x%x\n", (*ptr).clip6.clipper_viewport_state_ptr); | ||
282 | debug_printf("\t\t.viewport_xmin = %f\n", (*ptr).viewport_xmin); | ||
283 | debug_printf("\t\t.viewport_xmax = %f\n", (*ptr).viewport_xmax); | ||
284 | debug_printf("\t\t.viewport_ymin = %f\n", (*ptr).viewport_ymin); | ||
285 | debug_printf("\t\t.viewport_ymax = %f\n", (*ptr).viewport_ymax); | ||
286 | } | ||
287 | |||
288 | void | ||
289 | brw_dump_clipper_viewport(const struct brw_clipper_viewport *ptr) | ||
290 | { | ||
291 | debug_printf("\t\t.xmin = %f\n", (*ptr).xmin); | ||
292 | debug_printf("\t\t.xmax = %f\n", (*ptr).xmax); | ||
293 | debug_printf("\t\t.ymin = %f\n", (*ptr).ymin); | ||
294 | debug_printf("\t\t.ymax = %f\n", (*ptr).ymax); | ||
295 | } | ||
296 | |||
297 | void | ||
298 | brw_dump_constant_buffer(const struct brw_constant_buffer *ptr) | ||
299 | { | ||
300 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
301 | debug_printf("\t\t.header.valid = 0x%x\n", (*ptr).header.valid); | ||
302 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
303 | debug_printf("\t\t.bits0.buffer_length = 0x%x\n", (*ptr).bits0.buffer_length); | ||
304 | debug_printf("\t\t.bits0.buffer_address = 0x%x\n", (*ptr).bits0.buffer_address); | ||
305 | } | ||
306 | |||
307 | void | ||
308 | brw_dump_cs_urb_state(const struct brw_cs_urb_state *ptr) | ||
309 | { | ||
310 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
311 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
312 | debug_printf("\t\t.bits0.nr_urb_entries = 0x%x\n", (*ptr).bits0.nr_urb_entries); | ||
313 | debug_printf("\t\t.bits0.urb_entry_size = 0x%x\n", (*ptr).bits0.urb_entry_size); | ||
314 | } | ||
315 | |||
316 | void | ||
317 | brw_dump_depthbuffer(const struct brw_depthbuffer *ptr) | ||
318 | { | ||
319 | debug_printf("\t\t.header.bits.length = 0x%x\n", (*ptr).header.bits.length); | ||
320 | debug_printf("\t\t.header.bits.opcode = 0x%x\n", (*ptr).header.bits.opcode); | ||
321 | debug_printf("\t\t.dword1.bits.pitch = 0x%x\n", (*ptr).dword1.bits.pitch); | ||
322 | debug_printf("\t\t.dword1.bits.format = 0x%x\n", (*ptr).dword1.bits.format); | ||
323 | debug_printf("\t\t.dword1.bits.software_tiled_rendering_mode = 0x%x\n", (*ptr).dword1.bits.software_tiled_rendering_mode); | ||
324 | debug_printf("\t\t.dword1.bits.depth_offset_disable = 0x%x\n", (*ptr).dword1.bits.depth_offset_disable); | ||
325 | debug_printf("\t\t.dword1.bits.tile_walk = 0x%x\n", (*ptr).dword1.bits.tile_walk); | ||
326 | debug_printf("\t\t.dword1.bits.tiled_surface = 0x%x\n", (*ptr).dword1.bits.tiled_surface); | ||
327 | debug_printf("\t\t.dword1.bits.surface_type = 0x%x\n", (*ptr).dword1.bits.surface_type); | ||
328 | debug_printf("\t\t.dword2_base_addr = 0x%x\n", (*ptr).dword2_base_addr); | ||
329 | debug_printf("\t\t.dword3.bits.mipmap_layout = 0x%x\n", (*ptr).dword3.bits.mipmap_layout); | ||
330 | debug_printf("\t\t.dword3.bits.lod = 0x%x\n", (*ptr).dword3.bits.lod); | ||
331 | debug_printf("\t\t.dword3.bits.width = 0x%x\n", (*ptr).dword3.bits.width); | ||
332 | debug_printf("\t\t.dword3.bits.height = 0x%x\n", (*ptr).dword3.bits.height); | ||
333 | debug_printf("\t\t.dword4.bits.min_array_element = 0x%x\n", (*ptr).dword4.bits.min_array_element); | ||
334 | debug_printf("\t\t.dword4.bits.depth = 0x%x\n", (*ptr).dword4.bits.depth); | ||
335 | } | ||
336 | |||
337 | void | ||
338 | brw_dump_depthbuffer_g4x(const struct brw_depthbuffer_g4x *ptr) | ||
339 | { | ||
340 | debug_printf("\t\t.header.bits.length = 0x%x\n", (*ptr).header.bits.length); | ||
341 | debug_printf("\t\t.header.bits.opcode = 0x%x\n", (*ptr).header.bits.opcode); | ||
342 | debug_printf("\t\t.dword1.bits.pitch = 0x%x\n", (*ptr).dword1.bits.pitch); | ||
343 | debug_printf("\t\t.dword1.bits.format = 0x%x\n", (*ptr).dword1.bits.format); | ||
344 | debug_printf("\t\t.dword1.bits.software_tiled_rendering_mode = 0x%x\n", (*ptr).dword1.bits.software_tiled_rendering_mode); | ||
345 | debug_printf("\t\t.dword1.bits.depth_offset_disable = 0x%x\n", (*ptr).dword1.bits.depth_offset_disable); | ||
346 | debug_printf("\t\t.dword1.bits.tile_walk = 0x%x\n", (*ptr).dword1.bits.tile_walk); | ||
347 | debug_printf("\t\t.dword1.bits.tiled_surface = 0x%x\n", (*ptr).dword1.bits.tiled_surface); | ||
348 | debug_printf("\t\t.dword1.bits.surface_type = 0x%x\n", (*ptr).dword1.bits.surface_type); | ||
349 | debug_printf("\t\t.dword2_base_addr = 0x%x\n", (*ptr).dword2_base_addr); | ||
350 | debug_printf("\t\t.dword3.bits.mipmap_layout = 0x%x\n", (*ptr).dword3.bits.mipmap_layout); | ||
351 | debug_printf("\t\t.dword3.bits.lod = 0x%x\n", (*ptr).dword3.bits.lod); | ||
352 | debug_printf("\t\t.dword3.bits.width = 0x%x\n", (*ptr).dword3.bits.width); | ||
353 | debug_printf("\t\t.dword3.bits.height = 0x%x\n", (*ptr).dword3.bits.height); | ||
354 | debug_printf("\t\t.dword4.bits.min_array_element = 0x%x\n", (*ptr).dword4.bits.min_array_element); | ||
355 | debug_printf("\t\t.dword4.bits.depth = 0x%x\n", (*ptr).dword4.bits.depth); | ||
356 | debug_printf("\t\t.dword5.bits.xoffset = 0x%x\n", (*ptr).dword5.bits.xoffset); | ||
357 | debug_printf("\t\t.dword5.bits.yoffset = 0x%x\n", (*ptr).dword5.bits.yoffset); | ||
358 | } | ||
359 | |||
360 | void | ||
361 | brw_dump_drawrect(const struct brw_drawrect *ptr) | ||
362 | { | ||
363 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
364 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
365 | debug_printf("\t\t.xmin = 0x%x\n", (*ptr).xmin); | ||
366 | debug_printf("\t\t.ymin = 0x%x\n", (*ptr).ymin); | ||
367 | debug_printf("\t\t.xmax = 0x%x\n", (*ptr).xmax); | ||
368 | debug_printf("\t\t.ymax = 0x%x\n", (*ptr).ymax); | ||
369 | debug_printf("\t\t.xorg = 0x%x\n", (*ptr).xorg); | ||
370 | debug_printf("\t\t.yorg = 0x%x\n", (*ptr).yorg); | ||
371 | } | ||
372 | |||
373 | void | ||
374 | brw_dump_global_depth_offset_clamp(const struct brw_global_depth_offset_clamp *ptr) | ||
375 | { | ||
376 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
377 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
378 | debug_printf("\t\t.depth_offset_clamp = %f\n", (*ptr).depth_offset_clamp); | ||
379 | } | ||
380 | |||
381 | void | ||
382 | brw_dump_gs_unit_state(const struct brw_gs_unit_state *ptr) | ||
383 | { | ||
384 | debug_printf("\t\t.thread0.grf_reg_count = 0x%x\n", (*ptr).thread0.grf_reg_count); | ||
385 | debug_printf("\t\t.thread0.kernel_start_pointer = 0x%x\n", (*ptr).thread0.kernel_start_pointer); | ||
386 | debug_printf("\t\t.thread1.ext_halt_exception_enable = 0x%x\n", (*ptr).thread1.ext_halt_exception_enable); | ||
387 | debug_printf("\t\t.thread1.sw_exception_enable = 0x%x\n", (*ptr).thread1.sw_exception_enable); | ||
388 | debug_printf("\t\t.thread1.mask_stack_exception_enable = 0x%x\n", (*ptr).thread1.mask_stack_exception_enable); | ||
389 | debug_printf("\t\t.thread1.timeout_exception_enable = 0x%x\n", (*ptr).thread1.timeout_exception_enable); | ||
390 | debug_printf("\t\t.thread1.illegal_op_exception_enable = 0x%x\n", (*ptr).thread1.illegal_op_exception_enable); | ||
391 | debug_printf("\t\t.thread1.depth_coef_urb_read_offset = 0x%x\n", (*ptr).thread1.depth_coef_urb_read_offset); | ||
392 | debug_printf("\t\t.thread1.floating_point_mode = 0x%x\n", (*ptr).thread1.floating_point_mode); | ||
393 | debug_printf("\t\t.thread1.thread_priority = 0x%x\n", (*ptr).thread1.thread_priority); | ||
394 | debug_printf("\t\t.thread1.binding_table_entry_count = 0x%x\n", (*ptr).thread1.binding_table_entry_count); | ||
395 | debug_printf("\t\t.thread1.single_program_flow = 0x%x\n", (*ptr).thread1.single_program_flow); | ||
396 | debug_printf("\t\t.thread2.per_thread_scratch_space = 0x%x\n", (*ptr).thread2.per_thread_scratch_space); | ||
397 | debug_printf("\t\t.thread2.scratch_space_base_pointer = 0x%x\n", (*ptr).thread2.scratch_space_base_pointer); | ||
398 | debug_printf("\t\t.thread3.dispatch_grf_start_reg = 0x%x\n", (*ptr).thread3.dispatch_grf_start_reg); | ||
399 | debug_printf("\t\t.thread3.urb_entry_read_offset = 0x%x\n", (*ptr).thread3.urb_entry_read_offset); | ||
400 | debug_printf("\t\t.thread3.urb_entry_read_length = 0x%x\n", (*ptr).thread3.urb_entry_read_length); | ||
401 | debug_printf("\t\t.thread3.const_urb_entry_read_offset = 0x%x\n", (*ptr).thread3.const_urb_entry_read_offset); | ||
402 | debug_printf("\t\t.thread3.const_urb_entry_read_length = 0x%x\n", (*ptr).thread3.const_urb_entry_read_length); | ||
403 | debug_printf("\t\t.thread4.rendering_enable = 0x%x\n", (*ptr).thread4.rendering_enable); | ||
404 | debug_printf("\t\t.thread4.stats_enable = 0x%x\n", (*ptr).thread4.stats_enable); | ||
405 | debug_printf("\t\t.thread4.nr_urb_entries = 0x%x\n", (*ptr).thread4.nr_urb_entries); | ||
406 | debug_printf("\t\t.thread4.urb_entry_allocation_size = 0x%x\n", (*ptr).thread4.urb_entry_allocation_size); | ||
407 | debug_printf("\t\t.thread4.max_threads = 0x%x\n", (*ptr).thread4.max_threads); | ||
408 | debug_printf("\t\t.gs5.sampler_count = 0x%x\n", (*ptr).gs5.sampler_count); | ||
409 | debug_printf("\t\t.gs5.sampler_state_pointer = 0x%x\n", (*ptr).gs5.sampler_state_pointer); | ||
410 | debug_printf("\t\t.gs6.max_vp_index = 0x%x\n", (*ptr).gs6.max_vp_index); | ||
411 | debug_printf("\t\t.gs6.svbi_post_inc_value = 0x%x\n", (*ptr).gs6.svbi_post_inc_value); | ||
412 | debug_printf("\t\t.gs6.svbi_post_inc_enable = 0x%x\n", (*ptr).gs6.svbi_post_inc_enable); | ||
413 | debug_printf("\t\t.gs6.svbi_payload = 0x%x\n", (*ptr).gs6.svbi_payload); | ||
414 | debug_printf("\t\t.gs6.discard_adjaceny = 0x%x\n", (*ptr).gs6.discard_adjaceny); | ||
415 | debug_printf("\t\t.gs6.reorder_enable = 0x%x\n", (*ptr).gs6.reorder_enable); | ||
416 | } | ||
417 | |||
418 | void | ||
419 | brw_dump_indexbuffer(const struct brw_indexbuffer *ptr) | ||
420 | { | ||
421 | debug_printf("\t\t.header.bits.length = 0x%x\n", (*ptr).header.bits.length); | ||
422 | debug_printf("\t\t.header.bits.index_format = 0x%x\n", (*ptr).header.bits.index_format); | ||
423 | debug_printf("\t\t.header.bits.cut_index_enable = 0x%x\n", (*ptr).header.bits.cut_index_enable); | ||
424 | debug_printf("\t\t.header.bits.opcode = 0x%x\n", (*ptr).header.bits.opcode); | ||
425 | debug_printf("\t\t.buffer_start = 0x%x\n", (*ptr).buffer_start); | ||
426 | debug_printf("\t\t.buffer_end = 0x%x\n", (*ptr).buffer_end); | ||
427 | } | ||
428 | |||
429 | void | ||
430 | brw_dump_line_stipple(const struct brw_line_stipple *ptr) | ||
431 | { | ||
432 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
433 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
434 | debug_printf("\t\t.bits0.pattern = 0x%x\n", (*ptr).bits0.pattern); | ||
435 | debug_printf("\t\t.bits1.repeat_count = 0x%x\n", (*ptr).bits1.repeat_count); | ||
436 | debug_printf("\t\t.bits1.inverse_repeat_count = 0x%x\n", (*ptr).bits1.inverse_repeat_count); | ||
437 | } | ||
438 | |||
439 | void | ||
440 | brw_dump_mi_flush(const struct brw_mi_flush *ptr) | ||
441 | { | ||
442 | debug_printf("\t\t.flags = 0x%x\n", (*ptr).flags); | ||
443 | debug_printf("\t\t.opcode = 0x%x\n", (*ptr).opcode); | ||
444 | } | ||
445 | |||
446 | void | ||
447 | brw_dump_pipe_control(const struct brw_pipe_control *ptr) | ||
448 | { | ||
449 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
450 | debug_printf("\t\t.header.notify_enable = 0x%x\n", (*ptr).header.notify_enable); | ||
451 | debug_printf("\t\t.header.texture_cache_flush_enable = 0x%x\n", (*ptr).header.texture_cache_flush_enable); | ||
452 | debug_printf("\t\t.header.indirect_state_pointers_disable = 0x%x\n", (*ptr).header.indirect_state_pointers_disable); | ||
453 | debug_printf("\t\t.header.instruction_state_cache_flush_enable = 0x%x\n", (*ptr).header.instruction_state_cache_flush_enable); | ||
454 | debug_printf("\t\t.header.write_cache_flush_enable = 0x%x\n", (*ptr).header.write_cache_flush_enable); | ||
455 | debug_printf("\t\t.header.depth_stall_enable = 0x%x\n", (*ptr).header.depth_stall_enable); | ||
456 | debug_printf("\t\t.header.post_sync_operation = 0x%x\n", (*ptr).header.post_sync_operation); | ||
457 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
458 | debug_printf("\t\t.bits1.dest_addr_type = 0x%x\n", (*ptr).bits1.dest_addr_type); | ||
459 | debug_printf("\t\t.bits1.dest_addr = 0x%x\n", (*ptr).bits1.dest_addr); | ||
460 | debug_printf("\t\t.data0 = 0x%x\n", (*ptr).data0); | ||
461 | debug_printf("\t\t.data1 = 0x%x\n", (*ptr).data1); | ||
462 | } | ||
463 | |||
464 | void | ||
465 | brw_dump_pipeline_select(const struct brw_pipeline_select *ptr) | ||
466 | { | ||
467 | debug_printf("\t\t.header.pipeline_select = 0x%x\n", (*ptr).header.pipeline_select); | ||
468 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
469 | } | ||
470 | |||
471 | void | ||
472 | brw_dump_pipelined_state_pointers(const struct brw_pipelined_state_pointers *ptr) | ||
473 | { | ||
474 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
475 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
476 | debug_printf("\t\t.vs.offset = 0x%x\n", (*ptr).vs.offset); | ||
477 | debug_printf("\t\t.gs.enable = 0x%x\n", (*ptr).gs.enable); | ||
478 | debug_printf("\t\t.gs.offset = 0x%x\n", (*ptr).gs.offset); | ||
479 | debug_printf("\t\t.clp.enable = 0x%x\n", (*ptr).clp.enable); | ||
480 | debug_printf("\t\t.clp.offset = 0x%x\n", (*ptr).clp.offset); | ||
481 | debug_printf("\t\t.sf.offset = 0x%x\n", (*ptr).sf.offset); | ||
482 | debug_printf("\t\t.wm.offset = 0x%x\n", (*ptr).wm.offset); | ||
483 | debug_printf("\t\t.cc.offset = 0x%x\n", (*ptr).cc.offset); | ||
484 | } | ||
485 | |||
486 | void | ||
487 | brw_dump_polygon_stipple(const struct brw_polygon_stipple *ptr) | ||
488 | { | ||
489 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
490 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
491 | debug_printf("\t\t.stipple[0] = 0x%x\n", (*ptr).stipple[0]); | ||
492 | debug_printf("\t\t.stipple[1] = 0x%x\n", (*ptr).stipple[1]); | ||
493 | debug_printf("\t\t.stipple[2] = 0x%x\n", (*ptr).stipple[2]); | ||
494 | debug_printf("\t\t.stipple[3] = 0x%x\n", (*ptr).stipple[3]); | ||
495 | debug_printf("\t\t.stipple[4] = 0x%x\n", (*ptr).stipple[4]); | ||
496 | debug_printf("\t\t.stipple[5] = 0x%x\n", (*ptr).stipple[5]); | ||
497 | debug_printf("\t\t.stipple[6] = 0x%x\n", (*ptr).stipple[6]); | ||
498 | debug_printf("\t\t.stipple[7] = 0x%x\n", (*ptr).stipple[7]); | ||
499 | debug_printf("\t\t.stipple[8] = 0x%x\n", (*ptr).stipple[8]); | ||
500 | debug_printf("\t\t.stipple[9] = 0x%x\n", (*ptr).stipple[9]); | ||
501 | debug_printf("\t\t.stipple[10] = 0x%x\n", (*ptr).stipple[10]); | ||
502 | debug_printf("\t\t.stipple[11] = 0x%x\n", (*ptr).stipple[11]); | ||
503 | debug_printf("\t\t.stipple[12] = 0x%x\n", (*ptr).stipple[12]); | ||
504 | debug_printf("\t\t.stipple[13] = 0x%x\n", (*ptr).stipple[13]); | ||
505 | debug_printf("\t\t.stipple[14] = 0x%x\n", (*ptr).stipple[14]); | ||
506 | debug_printf("\t\t.stipple[15] = 0x%x\n", (*ptr).stipple[15]); | ||
507 | debug_printf("\t\t.stipple[16] = 0x%x\n", (*ptr).stipple[16]); | ||
508 | debug_printf("\t\t.stipple[17] = 0x%x\n", (*ptr).stipple[17]); | ||
509 | debug_printf("\t\t.stipple[18] = 0x%x\n", (*ptr).stipple[18]); | ||
510 | debug_printf("\t\t.stipple[19] = 0x%x\n", (*ptr).stipple[19]); | ||
511 | debug_printf("\t\t.stipple[20] = 0x%x\n", (*ptr).stipple[20]); | ||
512 | debug_printf("\t\t.stipple[21] = 0x%x\n", (*ptr).stipple[21]); | ||
513 | debug_printf("\t\t.stipple[22] = 0x%x\n", (*ptr).stipple[22]); | ||
514 | debug_printf("\t\t.stipple[23] = 0x%x\n", (*ptr).stipple[23]); | ||
515 | debug_printf("\t\t.stipple[24] = 0x%x\n", (*ptr).stipple[24]); | ||
516 | debug_printf("\t\t.stipple[25] = 0x%x\n", (*ptr).stipple[25]); | ||
517 | debug_printf("\t\t.stipple[26] = 0x%x\n", (*ptr).stipple[26]); | ||
518 | debug_printf("\t\t.stipple[27] = 0x%x\n", (*ptr).stipple[27]); | ||
519 | debug_printf("\t\t.stipple[28] = 0x%x\n", (*ptr).stipple[28]); | ||
520 | debug_printf("\t\t.stipple[29] = 0x%x\n", (*ptr).stipple[29]); | ||
521 | debug_printf("\t\t.stipple[30] = 0x%x\n", (*ptr).stipple[30]); | ||
522 | debug_printf("\t\t.stipple[31] = 0x%x\n", (*ptr).stipple[31]); | ||
523 | } | ||
524 | |||
525 | void | ||
526 | brw_dump_polygon_stipple_offset(const struct brw_polygon_stipple_offset *ptr) | ||
527 | { | ||
528 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
529 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
530 | debug_printf("\t\t.bits0.y_offset = 0x%x\n", (*ptr).bits0.y_offset); | ||
531 | debug_printf("\t\t.bits0.x_offset = 0x%x\n", (*ptr).bits0.x_offset); | ||
532 | } | ||
533 | |||
534 | void | ||
535 | brw_dump_sampler_default_color(const struct brw_sampler_default_color *ptr) | ||
536 | { | ||
537 | debug_printf("\t\t.color[0] = %f\n", (*ptr).color[0]); | ||
538 | debug_printf("\t\t.color[1] = %f\n", (*ptr).color[1]); | ||
539 | debug_printf("\t\t.color[2] = %f\n", (*ptr).color[2]); | ||
540 | debug_printf("\t\t.color[3] = %f\n", (*ptr).color[3]); | ||
541 | } | ||
542 | |||
543 | void | ||
544 | brw_dump_sampler_state(const struct brw_sampler_state *ptr) | ||
545 | { | ||
546 | debug_printf("\t\t.ss0.shadow_function = 0x%x\n", (*ptr).ss0.shadow_function); | ||
547 | debug_printf("\t\t.ss0.lod_bias = 0x%x\n", (*ptr).ss0.lod_bias); | ||
548 | debug_printf("\t\t.ss0.min_filter = 0x%x\n", (*ptr).ss0.min_filter); | ||
549 | debug_printf("\t\t.ss0.mag_filter = 0x%x\n", (*ptr).ss0.mag_filter); | ||
550 | debug_printf("\t\t.ss0.mip_filter = 0x%x\n", (*ptr).ss0.mip_filter); | ||
551 | debug_printf("\t\t.ss0.base_level = 0x%x\n", (*ptr).ss0.base_level); | ||
552 | debug_printf("\t\t.ss0.lod_preclamp = 0x%x\n", (*ptr).ss0.lod_preclamp); | ||
553 | debug_printf("\t\t.ss0.default_color_mode = 0x%x\n", (*ptr).ss0.default_color_mode); | ||
554 | debug_printf("\t\t.ss0.disable = 0x%x\n", (*ptr).ss0.disable); | ||
555 | debug_printf("\t\t.ss1.r_wrap_mode = 0x%x\n", (*ptr).ss1.r_wrap_mode); | ||
556 | debug_printf("\t\t.ss1.t_wrap_mode = 0x%x\n", (*ptr).ss1.t_wrap_mode); | ||
557 | debug_printf("\t\t.ss1.s_wrap_mode = 0x%x\n", (*ptr).ss1.s_wrap_mode); | ||
558 | debug_printf("\t\t.ss1.max_lod = 0x%x\n", (*ptr).ss1.max_lod); | ||
559 | debug_printf("\t\t.ss1.min_lod = 0x%x\n", (*ptr).ss1.min_lod); | ||
560 | debug_printf("\t\t.ss2.default_color_pointer = 0x%x\n", (*ptr).ss2.default_color_pointer); | ||
561 | debug_printf("\t\t.ss3.max_aniso = 0x%x\n", (*ptr).ss3.max_aniso); | ||
562 | debug_printf("\t\t.ss3.chroma_key_mode = 0x%x\n", (*ptr).ss3.chroma_key_mode); | ||
563 | debug_printf("\t\t.ss3.chroma_key_index = 0x%x\n", (*ptr).ss3.chroma_key_index); | ||
564 | debug_printf("\t\t.ss3.chroma_key_enable = 0x%x\n", (*ptr).ss3.chroma_key_enable); | ||
565 | debug_printf("\t\t.ss3.monochrome_filter_width = 0x%x\n", (*ptr).ss3.monochrome_filter_width); | ||
566 | debug_printf("\t\t.ss3.monochrome_filter_height = 0x%x\n", (*ptr).ss3.monochrome_filter_height); | ||
567 | } | ||
568 | |||
569 | void | ||
570 | brw_dump_sf_unit_state(const struct brw_sf_unit_state *ptr) | ||
571 | { | ||
572 | debug_printf("\t\t.thread0.grf_reg_count = 0x%x\n", (*ptr).thread0.grf_reg_count); | ||
573 | debug_printf("\t\t.thread0.kernel_start_pointer = 0x%x\n", (*ptr).thread0.kernel_start_pointer); | ||
574 | debug_printf("\t\t.thread1.ext_halt_exception_enable = 0x%x\n", (*ptr).thread1.ext_halt_exception_enable); | ||
575 | debug_printf("\t\t.thread1.sw_exception_enable = 0x%x\n", (*ptr).thread1.sw_exception_enable); | ||
576 | debug_printf("\t\t.thread1.mask_stack_exception_enable = 0x%x\n", (*ptr).thread1.mask_stack_exception_enable); | ||
577 | debug_printf("\t\t.thread1.timeout_exception_enable = 0x%x\n", (*ptr).thread1.timeout_exception_enable); | ||
578 | debug_printf("\t\t.thread1.illegal_op_exception_enable = 0x%x\n", (*ptr).thread1.illegal_op_exception_enable); | ||
579 | debug_printf("\t\t.thread1.depth_coef_urb_read_offset = 0x%x\n", (*ptr).thread1.depth_coef_urb_read_offset); | ||
580 | debug_printf("\t\t.thread1.floating_point_mode = 0x%x\n", (*ptr).thread1.floating_point_mode); | ||
581 | debug_printf("\t\t.thread1.thread_priority = 0x%x\n", (*ptr).thread1.thread_priority); | ||
582 | debug_printf("\t\t.thread1.binding_table_entry_count = 0x%x\n", (*ptr).thread1.binding_table_entry_count); | ||
583 | debug_printf("\t\t.thread1.single_program_flow = 0x%x\n", (*ptr).thread1.single_program_flow); | ||
584 | debug_printf("\t\t.thread2.per_thread_scratch_space = 0x%x\n", (*ptr).thread2.per_thread_scratch_space); | ||
585 | debug_printf("\t\t.thread2.scratch_space_base_pointer = 0x%x\n", (*ptr).thread2.scratch_space_base_pointer); | ||
586 | debug_printf("\t\t.thread3.dispatch_grf_start_reg = 0x%x\n", (*ptr).thread3.dispatch_grf_start_reg); | ||
587 | debug_printf("\t\t.thread3.urb_entry_read_offset = 0x%x\n", (*ptr).thread3.urb_entry_read_offset); | ||
588 | debug_printf("\t\t.thread3.urb_entry_read_length = 0x%x\n", (*ptr).thread3.urb_entry_read_length); | ||
589 | debug_printf("\t\t.thread3.const_urb_entry_read_offset = 0x%x\n", (*ptr).thread3.const_urb_entry_read_offset); | ||
590 | debug_printf("\t\t.thread3.const_urb_entry_read_length = 0x%x\n", (*ptr).thread3.const_urb_entry_read_length); | ||
591 | debug_printf("\t\t.thread4.stats_enable = 0x%x\n", (*ptr).thread4.stats_enable); | ||
592 | debug_printf("\t\t.thread4.nr_urb_entries = 0x%x\n", (*ptr).thread4.nr_urb_entries); | ||
593 | debug_printf("\t\t.thread4.urb_entry_allocation_size = 0x%x\n", (*ptr).thread4.urb_entry_allocation_size); | ||
594 | debug_printf("\t\t.thread4.max_threads = 0x%x\n", (*ptr).thread4.max_threads); | ||
595 | debug_printf("\t\t.sf5.front_winding = 0x%x\n", (*ptr).sf5.front_winding); | ||
596 | debug_printf("\t\t.sf5.viewport_transform = 0x%x\n", (*ptr).sf5.viewport_transform); | ||
597 | debug_printf("\t\t.sf5.sf_viewport_state_offset = 0x%x\n", (*ptr).sf5.sf_viewport_state_offset); | ||
598 | debug_printf("\t\t.sf6.dest_org_vbias = 0x%x\n", (*ptr).sf6.dest_org_vbias); | ||
599 | debug_printf("\t\t.sf6.dest_org_hbias = 0x%x\n", (*ptr).sf6.dest_org_hbias); | ||
600 | debug_printf("\t\t.sf6.scissor = 0x%x\n", (*ptr).sf6.scissor); | ||
601 | debug_printf("\t\t.sf6.disable_2x2_trifilter = 0x%x\n", (*ptr).sf6.disable_2x2_trifilter); | ||
602 | debug_printf("\t\t.sf6.disable_zero_pix_trifilter = 0x%x\n", (*ptr).sf6.disable_zero_pix_trifilter); | ||
603 | debug_printf("\t\t.sf6.point_rast_rule = 0x%x\n", (*ptr).sf6.point_rast_rule); | ||
604 | debug_printf("\t\t.sf6.line_endcap_aa_region_width = 0x%x\n", (*ptr).sf6.line_endcap_aa_region_width); | ||
605 | debug_printf("\t\t.sf6.line_width = 0x%x\n", (*ptr).sf6.line_width); | ||
606 | debug_printf("\t\t.sf6.fast_scissor_disable = 0x%x\n", (*ptr).sf6.fast_scissor_disable); | ||
607 | debug_printf("\t\t.sf6.cull_mode = 0x%x\n", (*ptr).sf6.cull_mode); | ||
608 | debug_printf("\t\t.sf6.aa_enable = 0x%x\n", (*ptr).sf6.aa_enable); | ||
609 | debug_printf("\t\t.sf7.point_size = 0x%x\n", (*ptr).sf7.point_size); | ||
610 | debug_printf("\t\t.sf7.use_point_size_state = 0x%x\n", (*ptr).sf7.use_point_size_state); | ||
611 | debug_printf("\t\t.sf7.subpixel_precision = 0x%x\n", (*ptr).sf7.subpixel_precision); | ||
612 | debug_printf("\t\t.sf7.sprite_point = 0x%x\n", (*ptr).sf7.sprite_point); | ||
613 | debug_printf("\t\t.sf7.aa_line_distance_mode = 0x%x\n", (*ptr).sf7.aa_line_distance_mode); | ||
614 | debug_printf("\t\t.sf7.trifan_pv = 0x%x\n", (*ptr).sf7.trifan_pv); | ||
615 | debug_printf("\t\t.sf7.linestrip_pv = 0x%x\n", (*ptr).sf7.linestrip_pv); | ||
616 | debug_printf("\t\t.sf7.tristrip_pv = 0x%x\n", (*ptr).sf7.tristrip_pv); | ||
617 | debug_printf("\t\t.sf7.line_last_pixel_enable = 0x%x\n", (*ptr).sf7.line_last_pixel_enable); | ||
618 | } | ||
619 | |||
620 | void | ||
621 | brw_dump_sf_viewport(const struct brw_sf_viewport *ptr) | ||
622 | { | ||
623 | debug_printf("\t\t.viewport.m00 = %f\n", (*ptr).viewport.m00); | ||
624 | debug_printf("\t\t.viewport.m11 = %f\n", (*ptr).viewport.m11); | ||
625 | debug_printf("\t\t.viewport.m22 = %f\n", (*ptr).viewport.m22); | ||
626 | debug_printf("\t\t.viewport.m30 = %f\n", (*ptr).viewport.m30); | ||
627 | debug_printf("\t\t.viewport.m31 = %f\n", (*ptr).viewport.m31); | ||
628 | debug_printf("\t\t.viewport.m32 = %f\n", (*ptr).viewport.m32); | ||
629 | debug_printf("\t\t.scissor.xmin = 0x%x\n", (*ptr).scissor.xmin); | ||
630 | debug_printf("\t\t.scissor.ymin = 0x%x\n", (*ptr).scissor.ymin); | ||
631 | debug_printf("\t\t.scissor.xmax = 0x%x\n", (*ptr).scissor.xmax); | ||
632 | debug_printf("\t\t.scissor.ymax = 0x%x\n", (*ptr).scissor.ymax); | ||
633 | } | ||
634 | |||
635 | void | ||
636 | brw_dump_ss0(const struct brw_ss0 *ptr) | ||
637 | { | ||
638 | debug_printf("\t\t.shadow_function = 0x%x\n", (*ptr).shadow_function); | ||
639 | debug_printf("\t\t.lod_bias = 0x%x\n", (*ptr).lod_bias); | ||
640 | debug_printf("\t\t.min_filter = 0x%x\n", (*ptr).min_filter); | ||
641 | debug_printf("\t\t.mag_filter = 0x%x\n", (*ptr).mag_filter); | ||
642 | debug_printf("\t\t.mip_filter = 0x%x\n", (*ptr).mip_filter); | ||
643 | debug_printf("\t\t.base_level = 0x%x\n", (*ptr).base_level); | ||
644 | debug_printf("\t\t.lod_preclamp = 0x%x\n", (*ptr).lod_preclamp); | ||
645 | debug_printf("\t\t.default_color_mode = 0x%x\n", (*ptr).default_color_mode); | ||
646 | debug_printf("\t\t.disable = 0x%x\n", (*ptr).disable); | ||
647 | } | ||
648 | |||
649 | void | ||
650 | brw_dump_ss1(const struct brw_ss1 *ptr) | ||
651 | { | ||
652 | debug_printf("\t\t.r_wrap_mode = 0x%x\n", (*ptr).r_wrap_mode); | ||
653 | debug_printf("\t\t.t_wrap_mode = 0x%x\n", (*ptr).t_wrap_mode); | ||
654 | debug_printf("\t\t.s_wrap_mode = 0x%x\n", (*ptr).s_wrap_mode); | ||
655 | debug_printf("\t\t.max_lod = 0x%x\n", (*ptr).max_lod); | ||
656 | debug_printf("\t\t.min_lod = 0x%x\n", (*ptr).min_lod); | ||
657 | } | ||
658 | |||
659 | void | ||
660 | brw_dump_ss2(const struct brw_ss2 *ptr) | ||
661 | { | ||
662 | debug_printf("\t\t.default_color_pointer = 0x%x\n", (*ptr).default_color_pointer); | ||
663 | } | ||
664 | |||
665 | void | ||
666 | brw_dump_ss3(const struct brw_ss3 *ptr) | ||
667 | { | ||
668 | debug_printf("\t\t.max_aniso = 0x%x\n", (*ptr).max_aniso); | ||
669 | debug_printf("\t\t.chroma_key_mode = 0x%x\n", (*ptr).chroma_key_mode); | ||
670 | debug_printf("\t\t.chroma_key_index = 0x%x\n", (*ptr).chroma_key_index); | ||
671 | debug_printf("\t\t.chroma_key_enable = 0x%x\n", (*ptr).chroma_key_enable); | ||
672 | debug_printf("\t\t.monochrome_filter_width = 0x%x\n", (*ptr).monochrome_filter_width); | ||
673 | debug_printf("\t\t.monochrome_filter_height = 0x%x\n", (*ptr).monochrome_filter_height); | ||
674 | } | ||
675 | |||
676 | void | ||
677 | brw_dump_state_base_address(const struct brw_state_base_address *ptr) | ||
678 | { | ||
679 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
680 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
681 | debug_printf("\t\t.bits0.modify_enable = 0x%x\n", (*ptr).bits0.modify_enable); | ||
682 | debug_printf("\t\t.bits0.general_state_address = 0x%x\n", (*ptr).bits0.general_state_address); | ||
683 | debug_printf("\t\t.bits1.modify_enable = 0x%x\n", (*ptr).bits1.modify_enable); | ||
684 | debug_printf("\t\t.bits1.surface_state_address = 0x%x\n", (*ptr).bits1.surface_state_address); | ||
685 | debug_printf("\t\t.bits2.modify_enable = 0x%x\n", (*ptr).bits2.modify_enable); | ||
686 | debug_printf("\t\t.bits2.indirect_object_state_address = 0x%x\n", (*ptr).bits2.indirect_object_state_address); | ||
687 | debug_printf("\t\t.bits3.modify_enable = 0x%x\n", (*ptr).bits3.modify_enable); | ||
688 | debug_printf("\t\t.bits3.general_state_upper_bound = 0x%x\n", (*ptr).bits3.general_state_upper_bound); | ||
689 | debug_printf("\t\t.bits4.modify_enable = 0x%x\n", (*ptr).bits4.modify_enable); | ||
690 | debug_printf("\t\t.bits4.indirect_object_state_upper_bound = 0x%x\n", (*ptr).bits4.indirect_object_state_upper_bound); | ||
691 | } | ||
692 | |||
693 | void | ||
694 | brw_dump_state_prefetch(const struct brw_state_prefetch *ptr) | ||
695 | { | ||
696 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
697 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
698 | debug_printf("\t\t.bits0.prefetch_count = 0x%x\n", (*ptr).bits0.prefetch_count); | ||
699 | debug_printf("\t\t.bits0.prefetch_pointer = 0x%x\n", (*ptr).bits0.prefetch_pointer); | ||
700 | } | ||
701 | |||
702 | void | ||
703 | brw_dump_surf_ss0(const struct brw_surf_ss0 *ptr) | ||
704 | { | ||
705 | debug_printf("\t\t.cube_pos_z = 0x%x\n", (*ptr).cube_pos_z); | ||
706 | debug_printf("\t\t.cube_neg_z = 0x%x\n", (*ptr).cube_neg_z); | ||
707 | debug_printf("\t\t.cube_pos_y = 0x%x\n", (*ptr).cube_pos_y); | ||
708 | debug_printf("\t\t.cube_neg_y = 0x%x\n", (*ptr).cube_neg_y); | ||
709 | debug_printf("\t\t.cube_pos_x = 0x%x\n", (*ptr).cube_pos_x); | ||
710 | debug_printf("\t\t.cube_neg_x = 0x%x\n", (*ptr).cube_neg_x); | ||
711 | debug_printf("\t\t.mipmap_layout_mode = 0x%x\n", (*ptr).mipmap_layout_mode); | ||
712 | debug_printf("\t\t.vert_line_stride_ofs = 0x%x\n", (*ptr).vert_line_stride_ofs); | ||
713 | debug_printf("\t\t.vert_line_stride = 0x%x\n", (*ptr).vert_line_stride); | ||
714 | debug_printf("\t\t.color_blend = 0x%x\n", (*ptr).color_blend); | ||
715 | debug_printf("\t\t.writedisable_blue = 0x%x\n", (*ptr).writedisable_blue); | ||
716 | debug_printf("\t\t.writedisable_green = 0x%x\n", (*ptr).writedisable_green); | ||
717 | debug_printf("\t\t.writedisable_red = 0x%x\n", (*ptr).writedisable_red); | ||
718 | debug_printf("\t\t.writedisable_alpha = 0x%x\n", (*ptr).writedisable_alpha); | ||
719 | debug_printf("\t\t.surface_format = 0x%x\n", (*ptr).surface_format); | ||
720 | debug_printf("\t\t.data_return_format = 0x%x\n", (*ptr).data_return_format); | ||
721 | debug_printf("\t\t.surface_type = 0x%x\n", (*ptr).surface_type); | ||
722 | } | ||
723 | |||
724 | void | ||
725 | brw_dump_surf_ss1(const struct brw_surf_ss1 *ptr) | ||
726 | { | ||
727 | debug_printf("\t\t.base_addr = 0x%x\n", (*ptr).base_addr); | ||
728 | } | ||
729 | |||
730 | void | ||
731 | brw_dump_surf_ss2(const struct brw_surf_ss2 *ptr) | ||
732 | { | ||
733 | debug_printf("\t\t.mip_count = 0x%x\n", (*ptr).mip_count); | ||
734 | debug_printf("\t\t.width = 0x%x\n", (*ptr).width); | ||
735 | debug_printf("\t\t.height = 0x%x\n", (*ptr).height); | ||
736 | } | ||
737 | |||
738 | void | ||
739 | brw_dump_surf_ss3(const struct brw_surf_ss3 *ptr) | ||
740 | { | ||
741 | debug_printf("\t\t.tile_walk = 0x%x\n", (*ptr).tile_walk); | ||
742 | debug_printf("\t\t.tiled_surface = 0x%x\n", (*ptr).tiled_surface); | ||
743 | debug_printf("\t\t.pitch = 0x%x\n", (*ptr).pitch); | ||
744 | debug_printf("\t\t.depth = 0x%x\n", (*ptr).depth); | ||
745 | } | ||
746 | |||
747 | void | ||
748 | brw_dump_surf_ss4(const struct brw_surf_ss4 *ptr) | ||
749 | { | ||
750 | debug_printf("\t\t.multisample_position_palette_index = 0x%x\n", (*ptr).multisample_position_palette_index); | ||
751 | debug_printf("\t\t.num_multisamples = 0x%x\n", (*ptr).num_multisamples); | ||
752 | debug_printf("\t\t.render_target_view_extent = 0x%x\n", (*ptr).render_target_view_extent); | ||
753 | debug_printf("\t\t.min_array_elt = 0x%x\n", (*ptr).min_array_elt); | ||
754 | debug_printf("\t\t.min_lod = 0x%x\n", (*ptr).min_lod); | ||
755 | } | ||
756 | |||
757 | void | ||
758 | brw_dump_surf_ss5(const struct brw_surf_ss5 *ptr) | ||
759 | { | ||
760 | debug_printf("\t\t.llc_mapping = 0x%x\n", (*ptr).llc_mapping); | ||
761 | debug_printf("\t\t.mlc_mapping = 0x%x\n", (*ptr).mlc_mapping); | ||
762 | debug_printf("\t\t.gfdt = 0x%x\n", (*ptr).gfdt); | ||
763 | debug_printf("\t\t.gfdt_src = 0x%x\n", (*ptr).gfdt_src); | ||
764 | debug_printf("\t\t.y_offset = 0x%x\n", (*ptr).y_offset); | ||
765 | debug_printf("\t\t.x_offset = 0x%x\n", (*ptr).x_offset); | ||
766 | } | ||
767 | |||
768 | void | ||
769 | brw_dump_surface_state(const struct brw_surface_state *ptr) | ||
770 | { | ||
771 | debug_printf("\t\t.ss0.cube_pos_z = 0x%x\n", (*ptr).ss0.cube_pos_z); | ||
772 | debug_printf("\t\t.ss0.cube_neg_z = 0x%x\n", (*ptr).ss0.cube_neg_z); | ||
773 | debug_printf("\t\t.ss0.cube_pos_y = 0x%x\n", (*ptr).ss0.cube_pos_y); | ||
774 | debug_printf("\t\t.ss0.cube_neg_y = 0x%x\n", (*ptr).ss0.cube_neg_y); | ||
775 | debug_printf("\t\t.ss0.cube_pos_x = 0x%x\n", (*ptr).ss0.cube_pos_x); | ||
776 | debug_printf("\t\t.ss0.cube_neg_x = 0x%x\n", (*ptr).ss0.cube_neg_x); | ||
777 | debug_printf("\t\t.ss0.mipmap_layout_mode = 0x%x\n", (*ptr).ss0.mipmap_layout_mode); | ||
778 | debug_printf("\t\t.ss0.vert_line_stride_ofs = 0x%x\n", (*ptr).ss0.vert_line_stride_ofs); | ||
779 | debug_printf("\t\t.ss0.vert_line_stride = 0x%x\n", (*ptr).ss0.vert_line_stride); | ||
780 | debug_printf("\t\t.ss0.color_blend = 0x%x\n", (*ptr).ss0.color_blend); | ||
781 | debug_printf("\t\t.ss0.writedisable_blue = 0x%x\n", (*ptr).ss0.writedisable_blue); | ||
782 | debug_printf("\t\t.ss0.writedisable_green = 0x%x\n", (*ptr).ss0.writedisable_green); | ||
783 | debug_printf("\t\t.ss0.writedisable_red = 0x%x\n", (*ptr).ss0.writedisable_red); | ||
784 | debug_printf("\t\t.ss0.writedisable_alpha = 0x%x\n", (*ptr).ss0.writedisable_alpha); | ||
785 | debug_printf("\t\t.ss0.surface_format = 0x%x\n", (*ptr).ss0.surface_format); | ||
786 | debug_printf("\t\t.ss0.data_return_format = 0x%x\n", (*ptr).ss0.data_return_format); | ||
787 | debug_printf("\t\t.ss0.surface_type = 0x%x\n", (*ptr).ss0.surface_type); | ||
788 | debug_printf("\t\t.ss1.base_addr = 0x%x\n", (*ptr).ss1.base_addr); | ||
789 | debug_printf("\t\t.ss2.mip_count = 0x%x\n", (*ptr).ss2.mip_count); | ||
790 | debug_printf("\t\t.ss2.width = 0x%x\n", (*ptr).ss2.width); | ||
791 | debug_printf("\t\t.ss2.height = 0x%x\n", (*ptr).ss2.height); | ||
792 | debug_printf("\t\t.ss3.tile_walk = 0x%x\n", (*ptr).ss3.tile_walk); | ||
793 | debug_printf("\t\t.ss3.tiled_surface = 0x%x\n", (*ptr).ss3.tiled_surface); | ||
794 | debug_printf("\t\t.ss3.pitch = 0x%x\n", (*ptr).ss3.pitch); | ||
795 | debug_printf("\t\t.ss3.depth = 0x%x\n", (*ptr).ss3.depth); | ||
796 | debug_printf("\t\t.ss4.multisample_position_palette_index = 0x%x\n", (*ptr).ss4.multisample_position_palette_index); | ||
797 | debug_printf("\t\t.ss4.num_multisamples = 0x%x\n", (*ptr).ss4.num_multisamples); | ||
798 | debug_printf("\t\t.ss4.render_target_view_extent = 0x%x\n", (*ptr).ss4.render_target_view_extent); | ||
799 | debug_printf("\t\t.ss4.min_array_elt = 0x%x\n", (*ptr).ss4.min_array_elt); | ||
800 | debug_printf("\t\t.ss4.min_lod = 0x%x\n", (*ptr).ss4.min_lod); | ||
801 | debug_printf("\t\t.ss5.llc_mapping = 0x%x\n", (*ptr).ss5.llc_mapping); | ||
802 | debug_printf("\t\t.ss5.mlc_mapping = 0x%x\n", (*ptr).ss5.mlc_mapping); | ||
803 | debug_printf("\t\t.ss5.gfdt = 0x%x\n", (*ptr).ss5.gfdt); | ||
804 | debug_printf("\t\t.ss5.gfdt_src = 0x%x\n", (*ptr).ss5.gfdt_src); | ||
805 | debug_printf("\t\t.ss5.y_offset = 0x%x\n", (*ptr).ss5.y_offset); | ||
806 | debug_printf("\t\t.ss5.x_offset = 0x%x\n", (*ptr).ss5.x_offset); | ||
807 | } | ||
808 | |||
809 | void | ||
810 | brw_dump_system_instruction_pointer(const struct brw_system_instruction_pointer *ptr) | ||
811 | { | ||
812 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
813 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
814 | debug_printf("\t\t.bits0.system_instruction_pointer = 0x%x\n", (*ptr).bits0.system_instruction_pointer); | ||
815 | } | ||
816 | |||
817 | void | ||
818 | brw_dump_urb_fence(const struct brw_urb_fence *ptr) | ||
819 | { | ||
820 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
821 | debug_printf("\t\t.header.vs_realloc = 0x%x\n", (*ptr).header.vs_realloc); | ||
822 | debug_printf("\t\t.header.gs_realloc = 0x%x\n", (*ptr).header.gs_realloc); | ||
823 | debug_printf("\t\t.header.clp_realloc = 0x%x\n", (*ptr).header.clp_realloc); | ||
824 | debug_printf("\t\t.header.sf_realloc = 0x%x\n", (*ptr).header.sf_realloc); | ||
825 | debug_printf("\t\t.header.vfe_realloc = 0x%x\n", (*ptr).header.vfe_realloc); | ||
826 | debug_printf("\t\t.header.cs_realloc = 0x%x\n", (*ptr).header.cs_realloc); | ||
827 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
828 | debug_printf("\t\t.bits0.vs_fence = 0x%x\n", (*ptr).bits0.vs_fence); | ||
829 | debug_printf("\t\t.bits0.gs_fence = 0x%x\n", (*ptr).bits0.gs_fence); | ||
830 | debug_printf("\t\t.bits0.clp_fence = 0x%x\n", (*ptr).bits0.clp_fence); | ||
831 | debug_printf("\t\t.bits1.sf_fence = 0x%x\n", (*ptr).bits1.sf_fence); | ||
832 | debug_printf("\t\t.bits1.vf_fence = 0x%x\n", (*ptr).bits1.vf_fence); | ||
833 | debug_printf("\t\t.bits1.cs_fence = 0x%x\n", (*ptr).bits1.cs_fence); | ||
834 | } | ||
835 | |||
836 | void | ||
837 | brw_dump_urb_immediate(const struct brw_urb_immediate *ptr) | ||
838 | { | ||
839 | debug_printf("\t\t.opcode = 0x%x\n", (*ptr).opcode); | ||
840 | debug_printf("\t\t.offset = 0x%x\n", (*ptr).offset); | ||
841 | debug_printf("\t\t.swizzle_control = 0x%x\n", (*ptr).swizzle_control); | ||
842 | debug_printf("\t\t.allocate = 0x%x\n", (*ptr).allocate); | ||
843 | debug_printf("\t\t.used = 0x%x\n", (*ptr).used); | ||
844 | debug_printf("\t\t.complete = 0x%x\n", (*ptr).complete); | ||
845 | debug_printf("\t\t.response_length = 0x%x\n", (*ptr).response_length); | ||
846 | debug_printf("\t\t.msg_length = 0x%x\n", (*ptr).msg_length); | ||
847 | debug_printf("\t\t.msg_target = 0x%x\n", (*ptr).msg_target); | ||
848 | debug_printf("\t\t.end_of_thread = 0x%x\n", (*ptr).end_of_thread); | ||
849 | } | ||
850 | |||
851 | void | ||
852 | brw_dump_vb_array_state(const struct brw_vb_array_state *ptr) | ||
853 | { | ||
854 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
855 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
856 | debug_printf("\t\t.vb[0].vb0.pitch = 0x%x\n", (*ptr).vb[0].vb0.pitch); | ||
857 | debug_printf("\t\t.vb[0].vb0.access_type = 0x%x\n", (*ptr).vb[0].vb0.access_type); | ||
858 | debug_printf("\t\t.vb[0].vb0.vb_index = 0x%x\n", (*ptr).vb[0].vb0.vb_index); | ||
859 | debug_printf("\t\t.vb[0].start_addr = 0x%x\n", (*ptr).vb[0].start_addr); | ||
860 | debug_printf("\t\t.vb[0].max_index = 0x%x\n", (*ptr).vb[0].max_index); | ||
861 | debug_printf("\t\t.vb[0].instance_data_step_rate = 0x%x\n", (*ptr).vb[0].instance_data_step_rate); | ||
862 | debug_printf("\t\t.vb[1].vb0.pitch = 0x%x\n", (*ptr).vb[1].vb0.pitch); | ||
863 | debug_printf("\t\t.vb[1].vb0.access_type = 0x%x\n", (*ptr).vb[1].vb0.access_type); | ||
864 | debug_printf("\t\t.vb[1].vb0.vb_index = 0x%x\n", (*ptr).vb[1].vb0.vb_index); | ||
865 | debug_printf("\t\t.vb[1].start_addr = 0x%x\n", (*ptr).vb[1].start_addr); | ||
866 | debug_printf("\t\t.vb[1].max_index = 0x%x\n", (*ptr).vb[1].max_index); | ||
867 | debug_printf("\t\t.vb[1].instance_data_step_rate = 0x%x\n", (*ptr).vb[1].instance_data_step_rate); | ||
868 | debug_printf("\t\t.vb[2].vb0.pitch = 0x%x\n", (*ptr).vb[2].vb0.pitch); | ||
869 | debug_printf("\t\t.vb[2].vb0.access_type = 0x%x\n", (*ptr).vb[2].vb0.access_type); | ||
870 | debug_printf("\t\t.vb[2].vb0.vb_index = 0x%x\n", (*ptr).vb[2].vb0.vb_index); | ||
871 | debug_printf("\t\t.vb[2].start_addr = 0x%x\n", (*ptr).vb[2].start_addr); | ||
872 | debug_printf("\t\t.vb[2].max_index = 0x%x\n", (*ptr).vb[2].max_index); | ||
873 | debug_printf("\t\t.vb[2].instance_data_step_rate = 0x%x\n", (*ptr).vb[2].instance_data_step_rate); | ||
874 | debug_printf("\t\t.vb[3].vb0.pitch = 0x%x\n", (*ptr).vb[3].vb0.pitch); | ||
875 | debug_printf("\t\t.vb[3].vb0.access_type = 0x%x\n", (*ptr).vb[3].vb0.access_type); | ||
876 | debug_printf("\t\t.vb[3].vb0.vb_index = 0x%x\n", (*ptr).vb[3].vb0.vb_index); | ||
877 | debug_printf("\t\t.vb[3].start_addr = 0x%x\n", (*ptr).vb[3].start_addr); | ||
878 | debug_printf("\t\t.vb[3].max_index = 0x%x\n", (*ptr).vb[3].max_index); | ||
879 | debug_printf("\t\t.vb[3].instance_data_step_rate = 0x%x\n", (*ptr).vb[3].instance_data_step_rate); | ||
880 | debug_printf("\t\t.vb[4].vb0.pitch = 0x%x\n", (*ptr).vb[4].vb0.pitch); | ||
881 | debug_printf("\t\t.vb[4].vb0.access_type = 0x%x\n", (*ptr).vb[4].vb0.access_type); | ||
882 | debug_printf("\t\t.vb[4].vb0.vb_index = 0x%x\n", (*ptr).vb[4].vb0.vb_index); | ||
883 | debug_printf("\t\t.vb[4].start_addr = 0x%x\n", (*ptr).vb[4].start_addr); | ||
884 | debug_printf("\t\t.vb[4].max_index = 0x%x\n", (*ptr).vb[4].max_index); | ||
885 | debug_printf("\t\t.vb[4].instance_data_step_rate = 0x%x\n", (*ptr).vb[4].instance_data_step_rate); | ||
886 | debug_printf("\t\t.vb[5].vb0.pitch = 0x%x\n", (*ptr).vb[5].vb0.pitch); | ||
887 | debug_printf("\t\t.vb[5].vb0.access_type = 0x%x\n", (*ptr).vb[5].vb0.access_type); | ||
888 | debug_printf("\t\t.vb[5].vb0.vb_index = 0x%x\n", (*ptr).vb[5].vb0.vb_index); | ||
889 | debug_printf("\t\t.vb[5].start_addr = 0x%x\n", (*ptr).vb[5].start_addr); | ||
890 | debug_printf("\t\t.vb[5].max_index = 0x%x\n", (*ptr).vb[5].max_index); | ||
891 | debug_printf("\t\t.vb[5].instance_data_step_rate = 0x%x\n", (*ptr).vb[5].instance_data_step_rate); | ||
892 | debug_printf("\t\t.vb[6].vb0.pitch = 0x%x\n", (*ptr).vb[6].vb0.pitch); | ||
893 | debug_printf("\t\t.vb[6].vb0.access_type = 0x%x\n", (*ptr).vb[6].vb0.access_type); | ||
894 | debug_printf("\t\t.vb[6].vb0.vb_index = 0x%x\n", (*ptr).vb[6].vb0.vb_index); | ||
895 | debug_printf("\t\t.vb[6].start_addr = 0x%x\n", (*ptr).vb[6].start_addr); | ||
896 | debug_printf("\t\t.vb[6].max_index = 0x%x\n", (*ptr).vb[6].max_index); | ||
897 | debug_printf("\t\t.vb[6].instance_data_step_rate = 0x%x\n", (*ptr).vb[6].instance_data_step_rate); | ||
898 | debug_printf("\t\t.vb[7].vb0.pitch = 0x%x\n", (*ptr).vb[7].vb0.pitch); | ||
899 | debug_printf("\t\t.vb[7].vb0.access_type = 0x%x\n", (*ptr).vb[7].vb0.access_type); | ||
900 | debug_printf("\t\t.vb[7].vb0.vb_index = 0x%x\n", (*ptr).vb[7].vb0.vb_index); | ||
901 | debug_printf("\t\t.vb[7].start_addr = 0x%x\n", (*ptr).vb[7].start_addr); | ||
902 | debug_printf("\t\t.vb[7].max_index = 0x%x\n", (*ptr).vb[7].max_index); | ||
903 | debug_printf("\t\t.vb[7].instance_data_step_rate = 0x%x\n", (*ptr).vb[7].instance_data_step_rate); | ||
904 | debug_printf("\t\t.vb[8].vb0.pitch = 0x%x\n", (*ptr).vb[8].vb0.pitch); | ||
905 | debug_printf("\t\t.vb[8].vb0.access_type = 0x%x\n", (*ptr).vb[8].vb0.access_type); | ||
906 | debug_printf("\t\t.vb[8].vb0.vb_index = 0x%x\n", (*ptr).vb[8].vb0.vb_index); | ||
907 | debug_printf("\t\t.vb[8].start_addr = 0x%x\n", (*ptr).vb[8].start_addr); | ||
908 | debug_printf("\t\t.vb[8].max_index = 0x%x\n", (*ptr).vb[8].max_index); | ||
909 | debug_printf("\t\t.vb[8].instance_data_step_rate = 0x%x\n", (*ptr).vb[8].instance_data_step_rate); | ||
910 | debug_printf("\t\t.vb[9].vb0.pitch = 0x%x\n", (*ptr).vb[9].vb0.pitch); | ||
911 | debug_printf("\t\t.vb[9].vb0.access_type = 0x%x\n", (*ptr).vb[9].vb0.access_type); | ||
912 | debug_printf("\t\t.vb[9].vb0.vb_index = 0x%x\n", (*ptr).vb[9].vb0.vb_index); | ||
913 | debug_printf("\t\t.vb[9].start_addr = 0x%x\n", (*ptr).vb[9].start_addr); | ||
914 | debug_printf("\t\t.vb[9].max_index = 0x%x\n", (*ptr).vb[9].max_index); | ||
915 | debug_printf("\t\t.vb[9].instance_data_step_rate = 0x%x\n", (*ptr).vb[9].instance_data_step_rate); | ||
916 | debug_printf("\t\t.vb[10].vb0.pitch = 0x%x\n", (*ptr).vb[10].vb0.pitch); | ||
917 | debug_printf("\t\t.vb[10].vb0.access_type = 0x%x\n", (*ptr).vb[10].vb0.access_type); | ||
918 | debug_printf("\t\t.vb[10].vb0.vb_index = 0x%x\n", (*ptr).vb[10].vb0.vb_index); | ||
919 | debug_printf("\t\t.vb[10].start_addr = 0x%x\n", (*ptr).vb[10].start_addr); | ||
920 | debug_printf("\t\t.vb[10].max_index = 0x%x\n", (*ptr).vb[10].max_index); | ||
921 | debug_printf("\t\t.vb[10].instance_data_step_rate = 0x%x\n", (*ptr).vb[10].instance_data_step_rate); | ||
922 | debug_printf("\t\t.vb[11].vb0.pitch = 0x%x\n", (*ptr).vb[11].vb0.pitch); | ||
923 | debug_printf("\t\t.vb[11].vb0.access_type = 0x%x\n", (*ptr).vb[11].vb0.access_type); | ||
924 | debug_printf("\t\t.vb[11].vb0.vb_index = 0x%x\n", (*ptr).vb[11].vb0.vb_index); | ||
925 | debug_printf("\t\t.vb[11].start_addr = 0x%x\n", (*ptr).vb[11].start_addr); | ||
926 | debug_printf("\t\t.vb[11].max_index = 0x%x\n", (*ptr).vb[11].max_index); | ||
927 | debug_printf("\t\t.vb[11].instance_data_step_rate = 0x%x\n", (*ptr).vb[11].instance_data_step_rate); | ||
928 | debug_printf("\t\t.vb[12].vb0.pitch = 0x%x\n", (*ptr).vb[12].vb0.pitch); | ||
929 | debug_printf("\t\t.vb[12].vb0.access_type = 0x%x\n", (*ptr).vb[12].vb0.access_type); | ||
930 | debug_printf("\t\t.vb[12].vb0.vb_index = 0x%x\n", (*ptr).vb[12].vb0.vb_index); | ||
931 | debug_printf("\t\t.vb[12].start_addr = 0x%x\n", (*ptr).vb[12].start_addr); | ||
932 | debug_printf("\t\t.vb[12].max_index = 0x%x\n", (*ptr).vb[12].max_index); | ||
933 | debug_printf("\t\t.vb[12].instance_data_step_rate = 0x%x\n", (*ptr).vb[12].instance_data_step_rate); | ||
934 | debug_printf("\t\t.vb[13].vb0.pitch = 0x%x\n", (*ptr).vb[13].vb0.pitch); | ||
935 | debug_printf("\t\t.vb[13].vb0.access_type = 0x%x\n", (*ptr).vb[13].vb0.access_type); | ||
936 | debug_printf("\t\t.vb[13].vb0.vb_index = 0x%x\n", (*ptr).vb[13].vb0.vb_index); | ||
937 | debug_printf("\t\t.vb[13].start_addr = 0x%x\n", (*ptr).vb[13].start_addr); | ||
938 | debug_printf("\t\t.vb[13].max_index = 0x%x\n", (*ptr).vb[13].max_index); | ||
939 | debug_printf("\t\t.vb[13].instance_data_step_rate = 0x%x\n", (*ptr).vb[13].instance_data_step_rate); | ||
940 | debug_printf("\t\t.vb[14].vb0.pitch = 0x%x\n", (*ptr).vb[14].vb0.pitch); | ||
941 | debug_printf("\t\t.vb[14].vb0.access_type = 0x%x\n", (*ptr).vb[14].vb0.access_type); | ||
942 | debug_printf("\t\t.vb[14].vb0.vb_index = 0x%x\n", (*ptr).vb[14].vb0.vb_index); | ||
943 | debug_printf("\t\t.vb[14].start_addr = 0x%x\n", (*ptr).vb[14].start_addr); | ||
944 | debug_printf("\t\t.vb[14].max_index = 0x%x\n", (*ptr).vb[14].max_index); | ||
945 | debug_printf("\t\t.vb[14].instance_data_step_rate = 0x%x\n", (*ptr).vb[14].instance_data_step_rate); | ||
946 | debug_printf("\t\t.vb[15].vb0.pitch = 0x%x\n", (*ptr).vb[15].vb0.pitch); | ||
947 | debug_printf("\t\t.vb[15].vb0.access_type = 0x%x\n", (*ptr).vb[15].vb0.access_type); | ||
948 | debug_printf("\t\t.vb[15].vb0.vb_index = 0x%x\n", (*ptr).vb[15].vb0.vb_index); | ||
949 | debug_printf("\t\t.vb[15].start_addr = 0x%x\n", (*ptr).vb[15].start_addr); | ||
950 | debug_printf("\t\t.vb[15].max_index = 0x%x\n", (*ptr).vb[15].max_index); | ||
951 | debug_printf("\t\t.vb[15].instance_data_step_rate = 0x%x\n", (*ptr).vb[15].instance_data_step_rate); | ||
952 | debug_printf("\t\t.vb[16].vb0.pitch = 0x%x\n", (*ptr).vb[16].vb0.pitch); | ||
953 | debug_printf("\t\t.vb[16].vb0.access_type = 0x%x\n", (*ptr).vb[16].vb0.access_type); | ||
954 | debug_printf("\t\t.vb[16].vb0.vb_index = 0x%x\n", (*ptr).vb[16].vb0.vb_index); | ||
955 | debug_printf("\t\t.vb[16].start_addr = 0x%x\n", (*ptr).vb[16].start_addr); | ||
956 | debug_printf("\t\t.vb[16].max_index = 0x%x\n", (*ptr).vb[16].max_index); | ||
957 | debug_printf("\t\t.vb[16].instance_data_step_rate = 0x%x\n", (*ptr).vb[16].instance_data_step_rate); | ||
958 | } | ||
959 | |||
960 | void | ||
961 | brw_dump_vertex_buffer_state(const struct brw_vertex_buffer_state *ptr) | ||
962 | { | ||
963 | debug_printf("\t\t.vb0.pitch = 0x%x\n", (*ptr).vb0.pitch); | ||
964 | debug_printf("\t\t.vb0.access_type = 0x%x\n", (*ptr).vb0.access_type); | ||
965 | debug_printf("\t\t.vb0.vb_index = 0x%x\n", (*ptr).vb0.vb_index); | ||
966 | debug_printf("\t\t.start_addr = 0x%x\n", (*ptr).start_addr); | ||
967 | debug_printf("\t\t.max_index = 0x%x\n", (*ptr).max_index); | ||
968 | debug_printf("\t\t.instance_data_step_rate = 0x%x\n", (*ptr).instance_data_step_rate); | ||
969 | } | ||
970 | |||
971 | void | ||
972 | brw_dump_vertex_element_packet(const struct brw_vertex_element_packet *ptr) | ||
973 | { | ||
974 | debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length); | ||
975 | debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode); | ||
976 | debug_printf("\t\t.ve[0].ve0.src_offset = 0x%x\n", (*ptr).ve[0].ve0.src_offset); | ||
977 | debug_printf("\t\t.ve[0].ve0.src_format = 0x%x\n", (*ptr).ve[0].ve0.src_format); | ||
978 | debug_printf("\t\t.ve[0].ve0.valid = 0x%x\n", (*ptr).ve[0].ve0.valid); | ||
979 | debug_printf("\t\t.ve[0].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[0].ve0.vertex_buffer_index); | ||
980 | debug_printf("\t\t.ve[0].ve1.dst_offset = 0x%x\n", (*ptr).ve[0].ve1.dst_offset); | ||
981 | debug_printf("\t\t.ve[0].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[0].ve1.vfcomponent3); | ||
982 | debug_printf("\t\t.ve[0].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[0].ve1.vfcomponent2); | ||
983 | debug_printf("\t\t.ve[0].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[0].ve1.vfcomponent1); | ||
984 | debug_printf("\t\t.ve[0].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[0].ve1.vfcomponent0); | ||
985 | debug_printf("\t\t.ve[1].ve0.src_offset = 0x%x\n", (*ptr).ve[1].ve0.src_offset); | ||
986 | debug_printf("\t\t.ve[1].ve0.src_format = 0x%x\n", (*ptr).ve[1].ve0.src_format); | ||
987 | debug_printf("\t\t.ve[1].ve0.valid = 0x%x\n", (*ptr).ve[1].ve0.valid); | ||
988 | debug_printf("\t\t.ve[1].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[1].ve0.vertex_buffer_index); | ||
989 | debug_printf("\t\t.ve[1].ve1.dst_offset = 0x%x\n", (*ptr).ve[1].ve1.dst_offset); | ||
990 | debug_printf("\t\t.ve[1].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[1].ve1.vfcomponent3); | ||
991 | debug_printf("\t\t.ve[1].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[1].ve1.vfcomponent2); | ||
992 | debug_printf("\t\t.ve[1].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[1].ve1.vfcomponent1); | ||
993 | debug_printf("\t\t.ve[1].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[1].ve1.vfcomponent0); | ||
994 | debug_printf("\t\t.ve[2].ve0.src_offset = 0x%x\n", (*ptr).ve[2].ve0.src_offset); | ||
995 | debug_printf("\t\t.ve[2].ve0.src_format = 0x%x\n", (*ptr).ve[2].ve0.src_format); | ||
996 | debug_printf("\t\t.ve[2].ve0.valid = 0x%x\n", (*ptr).ve[2].ve0.valid); | ||
997 | debug_printf("\t\t.ve[2].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[2].ve0.vertex_buffer_index); | ||
998 | debug_printf("\t\t.ve[2].ve1.dst_offset = 0x%x\n", (*ptr).ve[2].ve1.dst_offset); | ||
999 | debug_printf("\t\t.ve[2].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[2].ve1.vfcomponent3); | ||
1000 | debug_printf("\t\t.ve[2].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[2].ve1.vfcomponent2); | ||
1001 | debug_printf("\t\t.ve[2].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[2].ve1.vfcomponent1); | ||
1002 | debug_printf("\t\t.ve[2].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[2].ve1.vfcomponent0); | ||
1003 | debug_printf("\t\t.ve[3].ve0.src_offset = 0x%x\n", (*ptr).ve[3].ve0.src_offset); | ||
1004 | debug_printf("\t\t.ve[3].ve0.src_format = 0x%x\n", (*ptr).ve[3].ve0.src_format); | ||
1005 | debug_printf("\t\t.ve[3].ve0.valid = 0x%x\n", (*ptr).ve[3].ve0.valid); | ||
1006 | debug_printf("\t\t.ve[3].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[3].ve0.vertex_buffer_index); | ||
1007 | debug_printf("\t\t.ve[3].ve1.dst_offset = 0x%x\n", (*ptr).ve[3].ve1.dst_offset); | ||
1008 | debug_printf("\t\t.ve[3].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[3].ve1.vfcomponent3); | ||
1009 | debug_printf("\t\t.ve[3].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[3].ve1.vfcomponent2); | ||
1010 | debug_printf("\t\t.ve[3].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[3].ve1.vfcomponent1); | ||
1011 | debug_printf("\t\t.ve[3].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[3].ve1.vfcomponent0); | ||
1012 | debug_printf("\t\t.ve[4].ve0.src_offset = 0x%x\n", (*ptr).ve[4].ve0.src_offset); | ||
1013 | debug_printf("\t\t.ve[4].ve0.src_format = 0x%x\n", (*ptr).ve[4].ve0.src_format); | ||
1014 | debug_printf("\t\t.ve[4].ve0.valid = 0x%x\n", (*ptr).ve[4].ve0.valid); | ||
1015 | debug_printf("\t\t.ve[4].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[4].ve0.vertex_buffer_index); | ||
1016 | debug_printf("\t\t.ve[4].ve1.dst_offset = 0x%x\n", (*ptr).ve[4].ve1.dst_offset); | ||
1017 | debug_printf("\t\t.ve[4].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[4].ve1.vfcomponent3); | ||
1018 | debug_printf("\t\t.ve[4].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[4].ve1.vfcomponent2); | ||
1019 | debug_printf("\t\t.ve[4].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[4].ve1.vfcomponent1); | ||
1020 | debug_printf("\t\t.ve[4].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[4].ve1.vfcomponent0); | ||
1021 | debug_printf("\t\t.ve[5].ve0.src_offset = 0x%x\n", (*ptr).ve[5].ve0.src_offset); | ||
1022 | debug_printf("\t\t.ve[5].ve0.src_format = 0x%x\n", (*ptr).ve[5].ve0.src_format); | ||
1023 | debug_printf("\t\t.ve[5].ve0.valid = 0x%x\n", (*ptr).ve[5].ve0.valid); | ||
1024 | debug_printf("\t\t.ve[5].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[5].ve0.vertex_buffer_index); | ||
1025 | debug_printf("\t\t.ve[5].ve1.dst_offset = 0x%x\n", (*ptr).ve[5].ve1.dst_offset); | ||
1026 | debug_printf("\t\t.ve[5].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[5].ve1.vfcomponent3); | ||
1027 | debug_printf("\t\t.ve[5].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[5].ve1.vfcomponent2); | ||
1028 | debug_printf("\t\t.ve[5].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[5].ve1.vfcomponent1); | ||
1029 | debug_printf("\t\t.ve[5].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[5].ve1.vfcomponent0); | ||
1030 | debug_printf("\t\t.ve[6].ve0.src_offset = 0x%x\n", (*ptr).ve[6].ve0.src_offset); | ||
1031 | debug_printf("\t\t.ve[6].ve0.src_format = 0x%x\n", (*ptr).ve[6].ve0.src_format); | ||
1032 | debug_printf("\t\t.ve[6].ve0.valid = 0x%x\n", (*ptr).ve[6].ve0.valid); | ||
1033 | debug_printf("\t\t.ve[6].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[6].ve0.vertex_buffer_index); | ||
1034 | debug_printf("\t\t.ve[6].ve1.dst_offset = 0x%x\n", (*ptr).ve[6].ve1.dst_offset); | ||
1035 | debug_printf("\t\t.ve[6].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[6].ve1.vfcomponent3); | ||
1036 | debug_printf("\t\t.ve[6].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[6].ve1.vfcomponent2); | ||
1037 | debug_printf("\t\t.ve[6].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[6].ve1.vfcomponent1); | ||
1038 | debug_printf("\t\t.ve[6].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[6].ve1.vfcomponent0); | ||
1039 | debug_printf("\t\t.ve[7].ve0.src_offset = 0x%x\n", (*ptr).ve[7].ve0.src_offset); | ||
1040 | debug_printf("\t\t.ve[7].ve0.src_format = 0x%x\n", (*ptr).ve[7].ve0.src_format); | ||
1041 | debug_printf("\t\t.ve[7].ve0.valid = 0x%x\n", (*ptr).ve[7].ve0.valid); | ||
1042 | debug_printf("\t\t.ve[7].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[7].ve0.vertex_buffer_index); | ||
1043 | debug_printf("\t\t.ve[7].ve1.dst_offset = 0x%x\n", (*ptr).ve[7].ve1.dst_offset); | ||
1044 | debug_printf("\t\t.ve[7].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[7].ve1.vfcomponent3); | ||
1045 | debug_printf("\t\t.ve[7].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[7].ve1.vfcomponent2); | ||
1046 | debug_printf("\t\t.ve[7].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[7].ve1.vfcomponent1); | ||
1047 | debug_printf("\t\t.ve[7].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[7].ve1.vfcomponent0); | ||
1048 | debug_printf("\t\t.ve[8].ve0.src_offset = 0x%x\n", (*ptr).ve[8].ve0.src_offset); | ||
1049 | debug_printf("\t\t.ve[8].ve0.src_format = 0x%x\n", (*ptr).ve[8].ve0.src_format); | ||
1050 | debug_printf("\t\t.ve[8].ve0.valid = 0x%x\n", (*ptr).ve[8].ve0.valid); | ||
1051 | debug_printf("\t\t.ve[8].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[8].ve0.vertex_buffer_index); | ||
1052 | debug_printf("\t\t.ve[8].ve1.dst_offset = 0x%x\n", (*ptr).ve[8].ve1.dst_offset); | ||
1053 | debug_printf("\t\t.ve[8].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[8].ve1.vfcomponent3); | ||
1054 | debug_printf("\t\t.ve[8].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[8].ve1.vfcomponent2); | ||
1055 | debug_printf("\t\t.ve[8].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[8].ve1.vfcomponent1); | ||
1056 | debug_printf("\t\t.ve[8].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[8].ve1.vfcomponent0); | ||
1057 | debug_printf("\t\t.ve[9].ve0.src_offset = 0x%x\n", (*ptr).ve[9].ve0.src_offset); | ||
1058 | debug_printf("\t\t.ve[9].ve0.src_format = 0x%x\n", (*ptr).ve[9].ve0.src_format); | ||
1059 | debug_printf("\t\t.ve[9].ve0.valid = 0x%x\n", (*ptr).ve[9].ve0.valid); | ||
1060 | debug_printf("\t\t.ve[9].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[9].ve0.vertex_buffer_index); | ||
1061 | debug_printf("\t\t.ve[9].ve1.dst_offset = 0x%x\n", (*ptr).ve[9].ve1.dst_offset); | ||
1062 | debug_printf("\t\t.ve[9].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[9].ve1.vfcomponent3); | ||
1063 | debug_printf("\t\t.ve[9].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[9].ve1.vfcomponent2); | ||
1064 | debug_printf("\t\t.ve[9].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[9].ve1.vfcomponent1); | ||
1065 | debug_printf("\t\t.ve[9].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[9].ve1.vfcomponent0); | ||
1066 | debug_printf("\t\t.ve[10].ve0.src_offset = 0x%x\n", (*ptr).ve[10].ve0.src_offset); | ||
1067 | debug_printf("\t\t.ve[10].ve0.src_format = 0x%x\n", (*ptr).ve[10].ve0.src_format); | ||
1068 | debug_printf("\t\t.ve[10].ve0.valid = 0x%x\n", (*ptr).ve[10].ve0.valid); | ||
1069 | debug_printf("\t\t.ve[10].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[10].ve0.vertex_buffer_index); | ||
1070 | debug_printf("\t\t.ve[10].ve1.dst_offset = 0x%x\n", (*ptr).ve[10].ve1.dst_offset); | ||
1071 | debug_printf("\t\t.ve[10].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[10].ve1.vfcomponent3); | ||
1072 | debug_printf("\t\t.ve[10].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[10].ve1.vfcomponent2); | ||
1073 | debug_printf("\t\t.ve[10].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[10].ve1.vfcomponent1); | ||
1074 | debug_printf("\t\t.ve[10].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[10].ve1.vfcomponent0); | ||
1075 | debug_printf("\t\t.ve[11].ve0.src_offset = 0x%x\n", (*ptr).ve[11].ve0.src_offset); | ||
1076 | debug_printf("\t\t.ve[11].ve0.src_format = 0x%x\n", (*ptr).ve[11].ve0.src_format); | ||
1077 | debug_printf("\t\t.ve[11].ve0.valid = 0x%x\n", (*ptr).ve[11].ve0.valid); | ||
1078 | debug_printf("\t\t.ve[11].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[11].ve0.vertex_buffer_index); | ||
1079 | debug_printf("\t\t.ve[11].ve1.dst_offset = 0x%x\n", (*ptr).ve[11].ve1.dst_offset); | ||
1080 | debug_printf("\t\t.ve[11].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[11].ve1.vfcomponent3); | ||
1081 | debug_printf("\t\t.ve[11].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[11].ve1.vfcomponent2); | ||
1082 | debug_printf("\t\t.ve[11].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[11].ve1.vfcomponent1); | ||
1083 | debug_printf("\t\t.ve[11].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[11].ve1.vfcomponent0); | ||
1084 | debug_printf("\t\t.ve[12].ve0.src_offset = 0x%x\n", (*ptr).ve[12].ve0.src_offset); | ||
1085 | debug_printf("\t\t.ve[12].ve0.src_format = 0x%x\n", (*ptr).ve[12].ve0.src_format); | ||
1086 | debug_printf("\t\t.ve[12].ve0.valid = 0x%x\n", (*ptr).ve[12].ve0.valid); | ||
1087 | debug_printf("\t\t.ve[12].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[12].ve0.vertex_buffer_index); | ||
1088 | debug_printf("\t\t.ve[12].ve1.dst_offset = 0x%x\n", (*ptr).ve[12].ve1.dst_offset); | ||
1089 | debug_printf("\t\t.ve[12].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[12].ve1.vfcomponent3); | ||
1090 | debug_printf("\t\t.ve[12].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[12].ve1.vfcomponent2); | ||
1091 | debug_printf("\t\t.ve[12].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[12].ve1.vfcomponent1); | ||
1092 | debug_printf("\t\t.ve[12].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[12].ve1.vfcomponent0); | ||
1093 | debug_printf("\t\t.ve[13].ve0.src_offset = 0x%x\n", (*ptr).ve[13].ve0.src_offset); | ||
1094 | debug_printf("\t\t.ve[13].ve0.src_format = 0x%x\n", (*ptr).ve[13].ve0.src_format); | ||
1095 | debug_printf("\t\t.ve[13].ve0.valid = 0x%x\n", (*ptr).ve[13].ve0.valid); | ||
1096 | debug_printf("\t\t.ve[13].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[13].ve0.vertex_buffer_index); | ||
1097 | debug_printf("\t\t.ve[13].ve1.dst_offset = 0x%x\n", (*ptr).ve[13].ve1.dst_offset); | ||
1098 | debug_printf("\t\t.ve[13].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[13].ve1.vfcomponent3); | ||
1099 | debug_printf("\t\t.ve[13].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[13].ve1.vfcomponent2); | ||
1100 | debug_printf("\t\t.ve[13].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[13].ve1.vfcomponent1); | ||
1101 | debug_printf("\t\t.ve[13].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[13].ve1.vfcomponent0); | ||
1102 | debug_printf("\t\t.ve[14].ve0.src_offset = 0x%x\n", (*ptr).ve[14].ve0.src_offset); | ||
1103 | debug_printf("\t\t.ve[14].ve0.src_format = 0x%x\n", (*ptr).ve[14].ve0.src_format); | ||
1104 | debug_printf("\t\t.ve[14].ve0.valid = 0x%x\n", (*ptr).ve[14].ve0.valid); | ||
1105 | debug_printf("\t\t.ve[14].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[14].ve0.vertex_buffer_index); | ||
1106 | debug_printf("\t\t.ve[14].ve1.dst_offset = 0x%x\n", (*ptr).ve[14].ve1.dst_offset); | ||
1107 | debug_printf("\t\t.ve[14].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[14].ve1.vfcomponent3); | ||
1108 | debug_printf("\t\t.ve[14].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[14].ve1.vfcomponent2); | ||
1109 | debug_printf("\t\t.ve[14].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[14].ve1.vfcomponent1); | ||
1110 | debug_printf("\t\t.ve[14].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[14].ve1.vfcomponent0); | ||
1111 | debug_printf("\t\t.ve[15].ve0.src_offset = 0x%x\n", (*ptr).ve[15].ve0.src_offset); | ||
1112 | debug_printf("\t\t.ve[15].ve0.src_format = 0x%x\n", (*ptr).ve[15].ve0.src_format); | ||
1113 | debug_printf("\t\t.ve[15].ve0.valid = 0x%x\n", (*ptr).ve[15].ve0.valid); | ||
1114 | debug_printf("\t\t.ve[15].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[15].ve0.vertex_buffer_index); | ||
1115 | debug_printf("\t\t.ve[15].ve1.dst_offset = 0x%x\n", (*ptr).ve[15].ve1.dst_offset); | ||
1116 | debug_printf("\t\t.ve[15].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[15].ve1.vfcomponent3); | ||
1117 | debug_printf("\t\t.ve[15].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[15].ve1.vfcomponent2); | ||
1118 | debug_printf("\t\t.ve[15].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[15].ve1.vfcomponent1); | ||
1119 | debug_printf("\t\t.ve[15].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[15].ve1.vfcomponent0); | ||
1120 | debug_printf("\t\t.ve[16].ve0.src_offset = 0x%x\n", (*ptr).ve[16].ve0.src_offset); | ||
1121 | debug_printf("\t\t.ve[16].ve0.src_format = 0x%x\n", (*ptr).ve[16].ve0.src_format); | ||
1122 | debug_printf("\t\t.ve[16].ve0.valid = 0x%x\n", (*ptr).ve[16].ve0.valid); | ||
1123 | debug_printf("\t\t.ve[16].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[16].ve0.vertex_buffer_index); | ||
1124 | debug_printf("\t\t.ve[16].ve1.dst_offset = 0x%x\n", (*ptr).ve[16].ve1.dst_offset); | ||
1125 | debug_printf("\t\t.ve[16].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[16].ve1.vfcomponent3); | ||
1126 | debug_printf("\t\t.ve[16].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[16].ve1.vfcomponent2); | ||
1127 | debug_printf("\t\t.ve[16].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[16].ve1.vfcomponent1); | ||
1128 | debug_printf("\t\t.ve[16].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[16].ve1.vfcomponent0); | ||
1129 | debug_printf("\t\t.ve[17].ve0.src_offset = 0x%x\n", (*ptr).ve[17].ve0.src_offset); | ||
1130 | debug_printf("\t\t.ve[17].ve0.src_format = 0x%x\n", (*ptr).ve[17].ve0.src_format); | ||
1131 | debug_printf("\t\t.ve[17].ve0.valid = 0x%x\n", (*ptr).ve[17].ve0.valid); | ||
1132 | debug_printf("\t\t.ve[17].ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve[17].ve0.vertex_buffer_index); | ||
1133 | debug_printf("\t\t.ve[17].ve1.dst_offset = 0x%x\n", (*ptr).ve[17].ve1.dst_offset); | ||
1134 | debug_printf("\t\t.ve[17].ve1.vfcomponent3 = 0x%x\n", (*ptr).ve[17].ve1.vfcomponent3); | ||
1135 | debug_printf("\t\t.ve[17].ve1.vfcomponent2 = 0x%x\n", (*ptr).ve[17].ve1.vfcomponent2); | ||
1136 | debug_printf("\t\t.ve[17].ve1.vfcomponent1 = 0x%x\n", (*ptr).ve[17].ve1.vfcomponent1); | ||
1137 | debug_printf("\t\t.ve[17].ve1.vfcomponent0 = 0x%x\n", (*ptr).ve[17].ve1.vfcomponent0); | ||
1138 | } | ||
1139 | |||
1140 | void | ||
1141 | brw_dump_vertex_element_state(const struct brw_vertex_element_state *ptr) | ||
1142 | { | ||
1143 | debug_printf("\t\t.ve0.src_offset = 0x%x\n", (*ptr).ve0.src_offset); | ||
1144 | debug_printf("\t\t.ve0.src_format = 0x%x\n", (*ptr).ve0.src_format); | ||
1145 | debug_printf("\t\t.ve0.valid = 0x%x\n", (*ptr).ve0.valid); | ||
1146 | debug_printf("\t\t.ve0.vertex_buffer_index = 0x%x\n", (*ptr).ve0.vertex_buffer_index); | ||
1147 | debug_printf("\t\t.ve1.dst_offset = 0x%x\n", (*ptr).ve1.dst_offset); | ||
1148 | debug_printf("\t\t.ve1.vfcomponent3 = 0x%x\n", (*ptr).ve1.vfcomponent3); | ||
1149 | debug_printf("\t\t.ve1.vfcomponent2 = 0x%x\n", (*ptr).ve1.vfcomponent2); | ||
1150 | debug_printf("\t\t.ve1.vfcomponent1 = 0x%x\n", (*ptr).ve1.vfcomponent1); | ||
1151 | debug_printf("\t\t.ve1.vfcomponent0 = 0x%x\n", (*ptr).ve1.vfcomponent0); | ||
1152 | } | ||
1153 | |||
1154 | void | ||
1155 | brw_dump_vf_statistics(const struct brw_vf_statistics *ptr) | ||
1156 | { | ||
1157 | debug_printf("\t\t.statistics_enable = 0x%x\n", (*ptr).statistics_enable); | ||
1158 | debug_printf("\t\t.opcode = 0x%x\n", (*ptr).opcode); | ||
1159 | } | ||
1160 | |||
1161 | void | ||
1162 | brw_dump_vs_unit_state(const struct brw_vs_unit_state *ptr) | ||
1163 | { | ||
1164 | debug_printf("\t\t.thread0.grf_reg_count = 0x%x\n", (*ptr).thread0.grf_reg_count); | ||
1165 | debug_printf("\t\t.thread0.kernel_start_pointer = 0x%x\n", (*ptr).thread0.kernel_start_pointer); | ||
1166 | debug_printf("\t\t.thread1.ext_halt_exception_enable = 0x%x\n", (*ptr).thread1.ext_halt_exception_enable); | ||
1167 | debug_printf("\t\t.thread1.sw_exception_enable = 0x%x\n", (*ptr).thread1.sw_exception_enable); | ||
1168 | debug_printf("\t\t.thread1.mask_stack_exception_enable = 0x%x\n", (*ptr).thread1.mask_stack_exception_enable); | ||
1169 | debug_printf("\t\t.thread1.timeout_exception_enable = 0x%x\n", (*ptr).thread1.timeout_exception_enable); | ||
1170 | debug_printf("\t\t.thread1.illegal_op_exception_enable = 0x%x\n", (*ptr).thread1.illegal_op_exception_enable); | ||
1171 | debug_printf("\t\t.thread1.depth_coef_urb_read_offset = 0x%x\n", (*ptr).thread1.depth_coef_urb_read_offset); | ||
1172 | debug_printf("\t\t.thread1.floating_point_mode = 0x%x\n", (*ptr).thread1.floating_point_mode); | ||
1173 | debug_printf("\t\t.thread1.thread_priority = 0x%x\n", (*ptr).thread1.thread_priority); | ||
1174 | debug_printf("\t\t.thread1.binding_table_entry_count = 0x%x\n", (*ptr).thread1.binding_table_entry_count); | ||
1175 | debug_printf("\t\t.thread1.single_program_flow = 0x%x\n", (*ptr).thread1.single_program_flow); | ||
1176 | debug_printf("\t\t.thread2.per_thread_scratch_space = 0x%x\n", (*ptr).thread2.per_thread_scratch_space); | ||
1177 | debug_printf("\t\t.thread2.scratch_space_base_pointer = 0x%x\n", (*ptr).thread2.scratch_space_base_pointer); | ||
1178 | debug_printf("\t\t.thread3.dispatch_grf_start_reg = 0x%x\n", (*ptr).thread3.dispatch_grf_start_reg); | ||
1179 | debug_printf("\t\t.thread3.urb_entry_read_offset = 0x%x\n", (*ptr).thread3.urb_entry_read_offset); | ||
1180 | debug_printf("\t\t.thread3.urb_entry_read_length = 0x%x\n", (*ptr).thread3.urb_entry_read_length); | ||
1181 | debug_printf("\t\t.thread3.const_urb_entry_read_offset = 0x%x\n", (*ptr).thread3.const_urb_entry_read_offset); | ||
1182 | debug_printf("\t\t.thread3.const_urb_entry_read_length = 0x%x\n", (*ptr).thread3.const_urb_entry_read_length); | ||
1183 | debug_printf("\t\t.thread4.stats_enable = 0x%x\n", (*ptr).thread4.stats_enable); | ||
1184 | debug_printf("\t\t.thread4.nr_urb_entries = 0x%x\n", (*ptr).thread4.nr_urb_entries); | ||
1185 | debug_printf("\t\t.thread4.urb_entry_allocation_size = 0x%x\n", (*ptr).thread4.urb_entry_allocation_size); | ||
1186 | debug_printf("\t\t.thread4.max_threads = 0x%x\n", (*ptr).thread4.max_threads); | ||
1187 | debug_printf("\t\t.vs5.sampler_count = 0x%x\n", (*ptr).vs5.sampler_count); | ||
1188 | debug_printf("\t\t.vs5.sampler_state_pointer = 0x%x\n", (*ptr).vs5.sampler_state_pointer); | ||
1189 | debug_printf("\t\t.vs6.vs_enable = 0x%x\n", (*ptr).vs6.vs_enable); | ||
1190 | debug_printf("\t\t.vs6.vert_cache_disable = 0x%x\n", (*ptr).vs6.vert_cache_disable); | ||
1191 | } | ||
1192 | |||
1193 | void | ||
1194 | brw_dump_wm_unit_state(const struct brw_wm_unit_state *ptr) | ||
1195 | { | ||
1196 | debug_printf("\t\t.thread0.grf_reg_count = 0x%x\n", (*ptr).thread0.grf_reg_count); | ||
1197 | debug_printf("\t\t.thread0.kernel_start_pointer = 0x%x\n", (*ptr).thread0.kernel_start_pointer); | ||
1198 | debug_printf("\t\t.thread1.ext_halt_exception_enable = 0x%x\n", (*ptr).thread1.ext_halt_exception_enable); | ||
1199 | debug_printf("\t\t.thread1.sw_exception_enable = 0x%x\n", (*ptr).thread1.sw_exception_enable); | ||
1200 | debug_printf("\t\t.thread1.mask_stack_exception_enable = 0x%x\n", (*ptr).thread1.mask_stack_exception_enable); | ||
1201 | debug_printf("\t\t.thread1.timeout_exception_enable = 0x%x\n", (*ptr).thread1.timeout_exception_enable); | ||
1202 | debug_printf("\t\t.thread1.illegal_op_exception_enable = 0x%x\n", (*ptr).thread1.illegal_op_exception_enable); | ||
1203 | debug_printf("\t\t.thread1.depth_coef_urb_read_offset = 0x%x\n", (*ptr).thread1.depth_coef_urb_read_offset); | ||
1204 | debug_printf("\t\t.thread1.floating_point_mode = 0x%x\n", (*ptr).thread1.floating_point_mode); | ||
1205 | debug_printf("\t\t.thread1.thread_priority = 0x%x\n", (*ptr).thread1.thread_priority); | ||
1206 | debug_printf("\t\t.thread1.binding_table_entry_count = 0x%x\n", (*ptr).thread1.binding_table_entry_count); | ||
1207 | debug_printf("\t\t.thread1.single_program_flow = 0x%x\n", (*ptr).thread1.single_program_flow); | ||
1208 | debug_printf("\t\t.thread2.per_thread_scratch_space = 0x%x\n", (*ptr).thread2.per_thread_scratch_space); | ||
1209 | debug_printf("\t\t.thread2.scratch_space_base_pointer = 0x%x\n", (*ptr).thread2.scratch_space_base_pointer); | ||
1210 | debug_printf("\t\t.thread3.dispatch_grf_start_reg = 0x%x\n", (*ptr).thread3.dispatch_grf_start_reg); | ||
1211 | debug_printf("\t\t.thread3.urb_entry_read_offset = 0x%x\n", (*ptr).thread3.urb_entry_read_offset); | ||
1212 | debug_printf("\t\t.thread3.urb_entry_read_length = 0x%x\n", (*ptr).thread3.urb_entry_read_length); | ||
1213 | debug_printf("\t\t.thread3.const_urb_entry_read_offset = 0x%x\n", (*ptr).thread3.const_urb_entry_read_offset); | ||
1214 | debug_printf("\t\t.thread3.const_urb_entry_read_length = 0x%x\n", (*ptr).thread3.const_urb_entry_read_length); | ||
1215 | debug_printf("\t\t.wm4.stats_enable = 0x%x\n", (*ptr).wm4.stats_enable); | ||
1216 | debug_printf("\t\t.wm4.depth_buffer_clear = 0x%x\n", (*ptr).wm4.depth_buffer_clear); | ||
1217 | debug_printf("\t\t.wm4.sampler_count = 0x%x\n", (*ptr).wm4.sampler_count); | ||
1218 | debug_printf("\t\t.wm4.sampler_state_pointer = 0x%x\n", (*ptr).wm4.sampler_state_pointer); | ||
1219 | debug_printf("\t\t.wm5.enable_8_pix = 0x%x\n", (*ptr).wm5.enable_8_pix); | ||
1220 | debug_printf("\t\t.wm5.enable_16_pix = 0x%x\n", (*ptr).wm5.enable_16_pix); | ||
1221 | debug_printf("\t\t.wm5.enable_32_pix = 0x%x\n", (*ptr).wm5.enable_32_pix); | ||
1222 | debug_printf("\t\t.wm5.enable_con_32_pix = 0x%x\n", (*ptr).wm5.enable_con_32_pix); | ||
1223 | debug_printf("\t\t.wm5.enable_con_64_pix = 0x%x\n", (*ptr).wm5.enable_con_64_pix); | ||
1224 | debug_printf("\t\t.wm5.legacy_global_depth_bias = 0x%x\n", (*ptr).wm5.legacy_global_depth_bias); | ||
1225 | debug_printf("\t\t.wm5.line_stipple = 0x%x\n", (*ptr).wm5.line_stipple); | ||
1226 | debug_printf("\t\t.wm5.depth_offset = 0x%x\n", (*ptr).wm5.depth_offset); | ||
1227 | debug_printf("\t\t.wm5.polygon_stipple = 0x%x\n", (*ptr).wm5.polygon_stipple); | ||
1228 | debug_printf("\t\t.wm5.line_aa_region_width = 0x%x\n", (*ptr).wm5.line_aa_region_width); | ||
1229 | debug_printf("\t\t.wm5.line_endcap_aa_region_width = 0x%x\n", (*ptr).wm5.line_endcap_aa_region_width); | ||
1230 | debug_printf("\t\t.wm5.early_depth_test = 0x%x\n", (*ptr).wm5.early_depth_test); | ||
1231 | debug_printf("\t\t.wm5.thread_dispatch_enable = 0x%x\n", (*ptr).wm5.thread_dispatch_enable); | ||
1232 | debug_printf("\t\t.wm5.program_uses_depth = 0x%x\n", (*ptr).wm5.program_uses_depth); | ||
1233 | debug_printf("\t\t.wm5.program_computes_depth = 0x%x\n", (*ptr).wm5.program_computes_depth); | ||
1234 | debug_printf("\t\t.wm5.program_uses_killpixel = 0x%x\n", (*ptr).wm5.program_uses_killpixel); | ||
1235 | debug_printf("\t\t.wm5.legacy_line_rast = 0x%x\n", (*ptr).wm5.legacy_line_rast); | ||
1236 | debug_printf("\t\t.wm5.transposed_urb_read_enable = 0x%x\n", (*ptr).wm5.transposed_urb_read_enable); | ||
1237 | debug_printf("\t\t.wm5.max_threads = 0x%x\n", (*ptr).wm5.max_threads); | ||
1238 | debug_printf("\t\t.global_depth_offset_constant = %f\n", (*ptr).global_depth_offset_constant); | ||
1239 | debug_printf("\t\t.global_depth_offset_scale = %f\n", (*ptr).global_depth_offset_scale); | ||
1240 | debug_printf("\t\t.wm8.grf_reg_count_1 = 0x%x\n", (*ptr).wm8.grf_reg_count_1); | ||
1241 | debug_printf("\t\t.wm8.kernel_start_pointer_1 = 0x%x\n", (*ptr).wm8.kernel_start_pointer_1); | ||
1242 | debug_printf("\t\t.wm9.grf_reg_count_2 = 0x%x\n", (*ptr).wm9.grf_reg_count_2); | ||
1243 | debug_printf("\t\t.wm9.kernel_start_pointer_2 = 0x%x\n", (*ptr).wm9.kernel_start_pointer_2); | ||
1244 | debug_printf("\t\t.wm10.grf_reg_count_3 = 0x%x\n", (*ptr).wm10.grf_reg_count_3); | ||
1245 | debug_printf("\t\t.wm10.kernel_start_pointer_3 = 0x%x\n", (*ptr).wm10.kernel_start_pointer_3); | ||
1246 | } | ||
1247 | |||
diff --git a/src/gallium/drivers/i965/brw_structs_dump.h b/src/gallium/drivers/i965/brw_structs_dump.h deleted file mode 100644 index 7c02dbfe33f..00000000000 --- a/src/gallium/drivers/i965/brw_structs_dump.h +++ /dev/null | |||
@@ -1,276 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2009 VMware, Inc. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
18 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
19 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
20 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * The above copyright notice and this permission notice (including the | ||
23 | * next paragraph) shall be included in all copies or substantial portions | ||
24 | * of the Software. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | /** | ||
29 | * @file | ||
30 | * Dump i965 data structures. | ||
31 | * | ||
32 | * Generated automatically from brw_structs.h by brw_structs_dump.py. | ||
33 | */ | ||
34 | |||
35 | #ifndef BRW_STRUCTS_DUMP_H | ||
36 | #define BRW_STRUCTS_DUMP_H | ||
37 | |||
38 | struct brw_3d_control; | ||
39 | struct brw_3d_primitive; | ||
40 | struct brw_aa_line_parameters; | ||
41 | struct brw_binding_table_pointers; | ||
42 | struct brw_blend_constant_color; | ||
43 | struct brw_cc0; | ||
44 | struct brw_cc1; | ||
45 | struct brw_cc2; | ||
46 | struct brw_cc3; | ||
47 | struct brw_cc4; | ||
48 | struct brw_cc5; | ||
49 | struct brw_cc6; | ||
50 | struct brw_cc7; | ||
51 | struct brw_cc_unit_state; | ||
52 | struct brw_cc_viewport; | ||
53 | struct brw_clip_unit_state; | ||
54 | struct brw_clipper_viewport; | ||
55 | struct brw_constant_buffer; | ||
56 | struct brw_cs_urb_state; | ||
57 | struct brw_depthbuffer; | ||
58 | struct brw_depthbuffer_g4x; | ||
59 | struct brw_drawrect; | ||
60 | struct brw_global_depth_offset_clamp; | ||
61 | struct brw_gs_unit_state; | ||
62 | struct brw_indexbuffer; | ||
63 | struct brw_line_stipple; | ||
64 | struct brw_mi_flush; | ||
65 | struct brw_pipe_control; | ||
66 | struct brw_pipeline_select; | ||
67 | struct brw_pipelined_state_pointers; | ||
68 | struct brw_polygon_stipple; | ||
69 | struct brw_polygon_stipple_offset; | ||
70 | struct brw_sampler_default_color; | ||
71 | struct brw_sampler_state; | ||
72 | struct brw_sf_unit_state; | ||
73 | struct brw_sf_viewport; | ||
74 | struct brw_ss0; | ||
75 | struct brw_ss1; | ||
76 | struct brw_ss2; | ||
77 | struct brw_ss3; | ||
78 | struct brw_state_base_address; | ||
79 | struct brw_state_prefetch; | ||
80 | struct brw_surf_ss0; | ||
81 | struct brw_surf_ss1; | ||
82 | struct brw_surf_ss2; | ||
83 | struct brw_surf_ss3; | ||
84 | struct brw_surf_ss4; | ||
85 | struct brw_surf_ss5; | ||
86 | struct brw_surface_state; | ||
87 | struct brw_system_instruction_pointer; | ||
88 | struct brw_urb_fence; | ||
89 | struct brw_urb_immediate; | ||
90 | struct brw_vb_array_state; | ||
91 | struct brw_vertex_buffer_state; | ||
92 | struct brw_vertex_element_packet; | ||
93 | struct brw_vertex_element_state; | ||
94 | struct brw_vf_statistics; | ||
95 | struct brw_vs_unit_state; | ||
96 | struct brw_wm_unit_state; | ||
97 | |||
98 | void | ||
99 | brw_dump_3d_control(const struct brw_3d_control *ptr); | ||
100 | |||
101 | void | ||
102 | brw_dump_3d_primitive(const struct brw_3d_primitive *ptr); | ||
103 | |||
104 | void | ||
105 | brw_dump_aa_line_parameters(const struct brw_aa_line_parameters *ptr); | ||
106 | |||
107 | void | ||
108 | brw_dump_binding_table_pointers(const struct brw_binding_table_pointers *ptr); | ||
109 | |||
110 | void | ||
111 | brw_dump_blend_constant_color(const struct brw_blend_constant_color *ptr); | ||
112 | |||
113 | void | ||
114 | brw_dump_cc0(const struct brw_cc0 *ptr); | ||
115 | |||
116 | void | ||
117 | brw_dump_cc1(const struct brw_cc1 *ptr); | ||
118 | |||
119 | void | ||
120 | brw_dump_cc2(const struct brw_cc2 *ptr); | ||
121 | |||
122 | void | ||
123 | brw_dump_cc3(const struct brw_cc3 *ptr); | ||
124 | |||
125 | void | ||
126 | brw_dump_cc4(const struct brw_cc4 *ptr); | ||
127 | |||
128 | void | ||
129 | brw_dump_cc5(const struct brw_cc5 *ptr); | ||
130 | |||
131 | void | ||
132 | brw_dump_cc6(const struct brw_cc6 *ptr); | ||
133 | |||
134 | void | ||
135 | brw_dump_cc7(const struct brw_cc7 *ptr); | ||
136 | |||
137 | void | ||
138 | brw_dump_cc_unit_state(const struct brw_cc_unit_state *ptr); | ||
139 | |||
140 | void | ||
141 | brw_dump_cc_viewport(const struct brw_cc_viewport *ptr); | ||
142 | |||
143 | void | ||
144 | brw_dump_clip_unit_state(const struct brw_clip_unit_state *ptr); | ||
145 | |||
146 | void | ||
147 | brw_dump_clipper_viewport(const struct brw_clipper_viewport *ptr); | ||
148 | |||
149 | void | ||
150 | brw_dump_constant_buffer(const struct brw_constant_buffer *ptr); | ||
151 | |||
152 | void | ||
153 | brw_dump_cs_urb_state(const struct brw_cs_urb_state *ptr); | ||
154 | |||
155 | void | ||
156 | brw_dump_depthbuffer(const struct brw_depthbuffer *ptr); | ||
157 | |||
158 | void | ||
159 | brw_dump_depthbuffer_g4x(const struct brw_depthbuffer_g4x *ptr); | ||
160 | |||
161 | void | ||
162 | brw_dump_drawrect(const struct brw_drawrect *ptr); | ||
163 | |||
164 | void | ||
165 | brw_dump_global_depth_offset_clamp(const struct brw_global_depth_offset_clamp *ptr); | ||
166 | |||
167 | void | ||
168 | brw_dump_gs_unit_state(const struct brw_gs_unit_state *ptr); | ||
169 | |||
170 | void | ||
171 | brw_dump_indexbuffer(const struct brw_indexbuffer *ptr); | ||
172 | |||
173 | void | ||
174 | brw_dump_line_stipple(const struct brw_line_stipple *ptr); | ||
175 | |||
176 | void | ||
177 | brw_dump_mi_flush(const struct brw_mi_flush *ptr); | ||
178 | |||
179 | void | ||
180 | brw_dump_pipe_control(const struct brw_pipe_control *ptr); | ||
181 | |||
182 | void | ||
183 | brw_dump_pipeline_select(const struct brw_pipeline_select *ptr); | ||
184 | |||
185 | void | ||
186 | brw_dump_pipelined_state_pointers(const struct brw_pipelined_state_pointers *ptr); | ||
187 | |||
188 | void | ||
189 | brw_dump_polygon_stipple(const struct brw_polygon_stipple *ptr); | ||
190 | |||
191 | void | ||
192 | brw_dump_polygon_stipple_offset(const struct brw_polygon_stipple_offset *ptr); | ||
193 | |||
194 | void | ||
195 | brw_dump_sampler_default_color(const struct brw_sampler_default_color *ptr); | ||
196 | |||
197 | void | ||
198 | brw_dump_sampler_state(const struct brw_sampler_state *ptr); | ||
199 | |||
200 | void | ||
201 | brw_dump_sf_unit_state(const struct brw_sf_unit_state *ptr); | ||
202 | |||
203 | void | ||
204 | brw_dump_sf_viewport(const struct brw_sf_viewport *ptr); | ||
205 | |||
206 | void | ||
207 | brw_dump_ss0(const struct brw_ss0 *ptr); | ||
208 | |||
209 | void | ||
210 | brw_dump_ss1(const struct brw_ss1 *ptr); | ||
211 | |||
212 | void | ||
213 | brw_dump_ss2(const struct brw_ss2 *ptr); | ||
214 | |||
215 | void | ||
216 | brw_dump_ss3(const struct brw_ss3 *ptr); | ||
217 | |||
218 | void | ||
219 | brw_dump_state_base_address(const struct brw_state_base_address *ptr); | ||
220 | |||
221 | void | ||
222 | brw_dump_state_prefetch(const struct brw_state_prefetch *ptr); | ||
223 | |||
224 | void | ||
225 | brw_dump_surf_ss0(const struct brw_surf_ss0 *ptr); | ||
226 | |||
227 | void | ||
228 | brw_dump_surf_ss1(const struct brw_surf_ss1 *ptr); | ||
229 | |||
230 | void | ||
231 | brw_dump_surf_ss2(const struct brw_surf_ss2 *ptr); | ||
232 | |||
233 | void | ||
234 | brw_dump_surf_ss3(const struct brw_surf_ss3 *ptr); | ||
235 | |||
236 | void | ||
237 | brw_dump_surf_ss4(const struct brw_surf_ss4 *ptr); | ||
238 | |||
239 | void | ||
240 | brw_dump_surf_ss5(const struct brw_surf_ss5 *ptr); | ||
241 | |||
242 | void | ||
243 | brw_dump_surface_state(const struct brw_surface_state *ptr); | ||
244 | |||
245 | void | ||
246 | brw_dump_system_instruction_pointer(const struct brw_system_instruction_pointer *ptr); | ||
247 | |||
248 | void | ||
249 | brw_dump_urb_fence(const struct brw_urb_fence *ptr); | ||
250 | |||
251 | void | ||
252 | brw_dump_urb_immediate(const struct brw_urb_immediate *ptr); | ||
253 | |||
254 | void | ||
255 | brw_dump_vb_array_state(const struct brw_vb_array_state *ptr); | ||
256 | |||
257 | void | ||
258 | brw_dump_vertex_buffer_state(const struct brw_vertex_buffer_state *ptr); | ||
259 | |||
260 | void | ||
261 | brw_dump_vertex_element_packet(const struct brw_vertex_element_packet *ptr); | ||
262 | |||
263 | void | ||
264 | brw_dump_vertex_element_state(const struct brw_vertex_element_state *ptr); | ||
265 | |||
266 | void | ||
267 | brw_dump_vf_statistics(const struct brw_vf_statistics *ptr); | ||
268 | |||
269 | void | ||
270 | brw_dump_vs_unit_state(const struct brw_vs_unit_state *ptr); | ||
271 | |||
272 | void | ||
273 | brw_dump_wm_unit_state(const struct brw_wm_unit_state *ptr); | ||
274 | |||
275 | |||
276 | #endif /* BRW_STRUCTS_DUMP_H */ | ||
diff --git a/src/gallium/drivers/i965/brw_structs_dump.py b/src/gallium/drivers/i965/brw_structs_dump.py deleted file mode 100755 index 6dba49ad911..00000000000 --- a/src/gallium/drivers/i965/brw_structs_dump.py +++ /dev/null | |||
@@ -1,291 +0,0 @@ | |||
1 | #!/usr/bin/env python | ||
2 | ''' | ||
3 | Generates dumpers for the i965 state strucutures using pygccxml. | ||
4 | |||
5 | Run as | ||
6 | |||
7 | PYTHONPATH=/path/to/pygccxml-1.0.0 python brw_structs_dump.py | ||
8 | |||
9 | Jose Fonseca <jfonseca@vmware.com> | ||
10 | ''' | ||
11 | |||
12 | copyright = ''' | ||
13 | /************************************************************************** | ||
14 | * | ||
15 | * Copyright 2009 VMware, Inc. | ||
16 | * All Rights Reserved. | ||
17 | * | ||
18 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
19 | * copy of this software and associated documentation files (the | ||
20 | * "Software"), to deal in the Software without restriction, including | ||
21 | * without limitation the rights to use, copy, modify, merge, publish, | ||
22 | * distribute, sub license, and/or sell copies of the Software, and to | ||
23 | * permit persons to whom the Software is furnished to do so, subject to | ||
24 | * the following conditions: | ||
25 | * | ||
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
27 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
28 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
29 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
30 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
31 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
32 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
33 | * | ||
34 | * The above copyright notice and this permission notice (including the | ||
35 | * next paragraph) shall be included in all copies or substantial portions | ||
36 | * of the Software. | ||
37 | * | ||
38 | **************************************************************************/ | ||
39 | ''' | ||
40 | |||
41 | import os | ||
42 | import sys | ||
43 | import re | ||
44 | |||
45 | from pygccxml import parser | ||
46 | from pygccxml import declarations | ||
47 | |||
48 | from pygccxml.declarations import algorithm | ||
49 | from pygccxml.declarations import decl_visitor | ||
50 | from pygccxml.declarations import type_traits | ||
51 | from pygccxml.declarations import type_visitor | ||
52 | |||
53 | |||
54 | enums = True | ||
55 | |||
56 | |||
57 | def vars_filter(variable): | ||
58 | name = variable.name | ||
59 | return not re.match('^pad\d*', name) and name != 'dword' | ||
60 | |||
61 | |||
62 | class decl_dumper_t(decl_visitor.decl_visitor_t): | ||
63 | |||
64 | def __init__(self, stream, instance = '', decl = None): | ||
65 | decl_visitor.decl_visitor_t.__init__(self) | ||
66 | self.stream = stream | ||
67 | self._instance = instance | ||
68 | self.decl = decl | ||
69 | |||
70 | def clone(self): | ||
71 | return decl_dumper_t(self.stream, self._instance, self.decl) | ||
72 | |||
73 | def visit_class(self): | ||
74 | class_ = self.decl | ||
75 | assert self.decl.class_type in ('struct', 'union') | ||
76 | |||
77 | for variable in class_.variables(recursive = False): | ||
78 | if vars_filter(variable): | ||
79 | dump_type(self.stream, self._instance + '.' + variable.name, variable.type) | ||
80 | |||
81 | def visit_enumeration(self): | ||
82 | if enums: | ||
83 | self.stream.write(' switch(%s) {\n' % ("(*ptr)" + self._instance,)) | ||
84 | for name, value in self.decl.values: | ||
85 | self.stream.write(' case %s:\n' % (name,)) | ||
86 | self.stream.write(' debug_printf("\\t\\t%s = %s\\n");\n' % (self._instance, name)) | ||
87 | self.stream.write(' break;\n') | ||
88 | self.stream.write(' default:\n') | ||
89 | self.stream.write(' debug_printf("\\t\\t%s = %%i\\n", %s);\n' % (self._instance, "(*ptr)" + self._instance)) | ||
90 | self.stream.write(' break;\n') | ||
91 | self.stream.write(' }\n') | ||
92 | else: | ||
93 | self.stream.write(' debug_printf("\\t\\t%s = %%i\\n", %s);\n' % (self._instance, "(*ptr)" + self._instance)) | ||
94 | |||
95 | |||
96 | def dump_decl(stream, instance, decl): | ||
97 | dumper = decl_dumper_t(stream, instance, decl) | ||
98 | algorithm.apply_visitor(dumper, decl) | ||
99 | |||
100 | |||
101 | class type_dumper_t(type_visitor.type_visitor_t): | ||
102 | |||
103 | def __init__(self, stream, instance, type_): | ||
104 | type_visitor.type_visitor_t.__init__(self) | ||
105 | self.stream = stream | ||
106 | self.instance = instance | ||
107 | self.type = type_ | ||
108 | |||
109 | def clone(self): | ||
110 | return type_dumper_t(self.instance, self.type) | ||
111 | |||
112 | def visit_bool(self): | ||
113 | self.print_instance('%i') | ||
114 | |||
115 | def visit_char(self): | ||
116 | #self.print_instance('%i') | ||
117 | self.print_instance('0x%x') | ||
118 | |||
119 | def visit_unsigned_char(self): | ||
120 | #self.print_instance('%u') | ||
121 | self.print_instance('0x%x') | ||
122 | |||
123 | def visit_signed_char(self): | ||
124 | #self.print_instance('%i') | ||
125 | self.print_instance('0x%x') | ||
126 | |||
127 | def visit_wchar(self): | ||
128 | self.print_instance('0x%x') | ||
129 | |||
130 | def visit_short_int(self): | ||
131 | #self.print_instance('%i') | ||
132 | self.print_instance('0x%x') | ||
133 | |||
134 | def visit_short_unsigned_int(self): | ||
135 | #self.print_instance('%u') | ||
136 | self.print_instance('0x%x') | ||
137 | |||
138 | def visit_int(self): | ||
139 | #self.print_instance('%i') | ||
140 | self.print_instance('0x%x') | ||
141 | |||
142 | def visit_unsigned_int(self): | ||
143 | #self.print_instance('%u') | ||
144 | self.print_instance('0x%x') | ||
145 | |||
146 | def visit_long_int(self): | ||
147 | #self.print_instance('%li') | ||
148 | self.print_instance('0x%lx') | ||
149 | |||
150 | def visit_long_unsigned_int(self): | ||
151 | #self.print_instance('%lu') | ||
152 | self.print_instance('%0xlx') | ||
153 | |||
154 | def visit_long_long_int(self): | ||
155 | #self.print_instance('%lli') | ||
156 | self.print_instance('%0xllx') | ||
157 | |||
158 | def visit_long_long_unsigned_int(self): | ||
159 | #self.print_instance('%llu') | ||
160 | self.print_instance('0x%llx') | ||
161 | |||
162 | def visit_float(self): | ||
163 | self.print_instance('%f') | ||
164 | |||
165 | def visit_double(self): | ||
166 | self.print_instance('%f') | ||
167 | |||
168 | def visit_array(self): | ||
169 | for i in range(type_traits.array_size(self.type)): | ||
170 | dump_type(self.stream, self.instance + '[%i]' % i, type_traits.base_type(self.type)) | ||
171 | |||
172 | def visit_pointer(self): | ||
173 | self.print_instance('%p') | ||
174 | |||
175 | def visit_declarated(self): | ||
176 | #stream.write('decl = %r\n' % self.type.decl_string) | ||
177 | decl = type_traits.remove_declarated(self.type) | ||
178 | dump_decl(self.stream, self.instance, decl) | ||
179 | |||
180 | def print_instance(self, format): | ||
181 | self.stream.write(' debug_printf("\\t\\t%s = %s\\n", %s);\n' % (self.instance, format, "(*ptr)" + self.instance)) | ||
182 | |||
183 | |||
184 | |||
185 | def dump_type(stream, instance, type_): | ||
186 | type_ = type_traits.remove_alias(type_) | ||
187 | visitor = type_dumper_t(stream, instance, type_) | ||
188 | algorithm.apply_visitor(visitor, type_) | ||
189 | |||
190 | |||
191 | def dump_struct_interface(stream, class_, suffix = ';'): | ||
192 | name = class_.name | ||
193 | assert name.startswith('brw_'); | ||
194 | name = name[:4] + 'dump_' + name[4:] | ||
195 | stream.write('void\n') | ||
196 | stream.write('%s(const struct %s *ptr)%s\n' % (name, class_.name, suffix)) | ||
197 | |||
198 | |||
199 | def dump_struct_implementation(stream, decls, class_): | ||
200 | dump_struct_interface(stream, class_, suffix = '') | ||
201 | stream.write('{\n') | ||
202 | dump_decl(stream, '', class_) | ||
203 | stream.write('}\n') | ||
204 | stream.write('\n') | ||
205 | |||
206 | |||
207 | def dump_header(stream): | ||
208 | stream.write(copyright.strip() + '\n') | ||
209 | stream.write('\n') | ||
210 | stream.write('/**\n') | ||
211 | stream.write(' * @file\n') | ||
212 | stream.write(' * Dump i965 data structures.\n') | ||
213 | stream.write(' *\n') | ||
214 | stream.write(' * Generated automatically from brw_structs.h by brw_structs_dump.py.\n') | ||
215 | stream.write(' */\n') | ||
216 | stream.write('\n') | ||
217 | |||
218 | |||
219 | def dump_interfaces(decls, global_ns, names): | ||
220 | stream = open('brw_structs_dump.h', 'wt') | ||
221 | |||
222 | dump_header(stream) | ||
223 | |||
224 | stream.write('#ifndef BRW_STRUCTS_DUMP_H\n') | ||
225 | stream.write('#define BRW_STRUCTS_DUMP_H\n') | ||
226 | stream.write('\n') | ||
227 | |||
228 | for name in names: | ||
229 | stream.write('struct %s;\n' % (name,)) | ||
230 | stream.write('\n') | ||
231 | |||
232 | for name in names: | ||
233 | (class_,) = global_ns.classes(name = name) | ||
234 | dump_struct_interface(stream, class_) | ||
235 | stream.write('\n') | ||
236 | stream.write('\n') | ||
237 | |||
238 | stream.write('#endif /* BRW_STRUCTS_DUMP_H */\n') | ||
239 | |||
240 | |||
241 | def dump_implementations(decls, global_ns, names): | ||
242 | stream = open('brw_structs_dump.c', 'wt') | ||
243 | |||
244 | dump_header(stream) | ||
245 | |||
246 | stream.write('#include "util/u_debug.h"\n') | ||
247 | stream.write('\n') | ||
248 | stream.write('#include "brw_types.h"\n') | ||
249 | stream.write('#include "brw_structs.h"\n') | ||
250 | stream.write('#include "brw_structs_dump.h"\n') | ||
251 | stream.write('\n') | ||
252 | |||
253 | for name in names: | ||
254 | (class_,) = global_ns.classes(name = name) | ||
255 | dump_struct_implementation(stream, decls, class_) | ||
256 | |||
257 | |||
258 | def decl_filter(decl): | ||
259 | '''Filter the declarations we're interested in''' | ||
260 | name = decl.name | ||
261 | return name.startswith('brw_') and name not in ('brw_instruction',) | ||
262 | |||
263 | |||
264 | def main(): | ||
265 | |||
266 | config = parser.config_t( | ||
267 | include_paths = [ | ||
268 | '../../include', | ||
269 | ], | ||
270 | compiler = 'gcc', | ||
271 | ) | ||
272 | |||
273 | headers = [ | ||
274 | 'brw_types.h', | ||
275 | 'brw_structs.h', | ||
276 | ] | ||
277 | |||
278 | decls = parser.parse(headers, config, parser.COMPILATION_MODE.ALL_AT_ONCE) | ||
279 | global_ns = declarations.get_global_namespace(decls) | ||
280 | |||
281 | names = [] | ||
282 | for class_ in global_ns.classes(decl_filter): | ||
283 | names.append(class_.name) | ||
284 | names.sort() | ||
285 | |||
286 | dump_interfaces(decls, global_ns, names) | ||
287 | dump_implementations(decls, global_ns, names) | ||
288 | |||
289 | |||
290 | if __name__ == '__main__': | ||
291 | main() | ||
diff --git a/src/gallium/drivers/i965/brw_swtnl.c b/src/gallium/drivers/i965/brw_swtnl.c deleted file mode 100644 index f96301e99e6..00000000000 --- a/src/gallium/drivers/i965/brw_swtnl.c +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | |||
2 | #include "brw_context.h" | ||
3 | #include "brw_pipe_rast.h" | ||
4 | |||
5 | |||
6 | #if 0 | ||
7 | |||
8 | static GLboolean need_swtnl( struct brw_context *brw ) | ||
9 | { | ||
10 | const struct pipe_rasterizer_state *rast = &brw->curr.rast->templ; | ||
11 | |||
12 | /* If we don't require strict OpenGL conformance, never | ||
13 | * use fallbacks. If we're forcing fallbacks, always | ||
14 | * use fallfacks. | ||
15 | */ | ||
16 | if (brw->flags.no_swtnl) | ||
17 | return FALSE; | ||
18 | |||
19 | if (brw->flags.force_swtnl) | ||
20 | return TRUE; | ||
21 | |||
22 | /* Exceeding hw limits on number of VS inputs? | ||
23 | */ | ||
24 | if (brw->curr.num_vertex_elements == 0 || | ||
25 | brw->curr.num_vertex_elements >= BRW_VEP_MAX) { | ||
26 | return TRUE; | ||
27 | } | ||
28 | |||
29 | /* Position array with zero stride? | ||
30 | * | ||
31 | * XXX: position isn't always at zero... | ||
32 | * XXX: eliminate zero-stride arrays | ||
33 | */ | ||
34 | { | ||
35 | int ve0_vb = brw->curr.vertex_element[0].vertex_buffer_index; | ||
36 | |||
37 | if (brw->curr.vertex_buffer[ve0_vb].stride == 0) | ||
38 | return TRUE; | ||
39 | } | ||
40 | |||
41 | /* XXX: short-circuit | ||
42 | */ | ||
43 | return FALSE; | ||
44 | |||
45 | if (brw->reduced_primitive == PIPE_PRIM_TRIANGLES) { | ||
46 | if (rast->poly_smooth) | ||
47 | return TRUE; | ||
48 | |||
49 | } | ||
50 | |||
51 | if (brw->reduced_primitive == PIPE_PRIM_LINES || | ||
52 | (brw->reduced_primitive == PIPE_PRIM_TRIANGLES && | ||
53 | (rast->fill_cw == PIPE_POLYGON_MODE_LINE || | ||
54 | rast->fill_ccw == PIPE_POLYGON_MODE_LINE))) | ||
55 | { | ||
56 | /* BRW hardware will do AA lines, but they are non-conformant it | ||
57 | * seems. TBD whether we keep this fallback: | ||
58 | */ | ||
59 | if (rast->line_smooth) | ||
60 | return TRUE; | ||
61 | |||
62 | /* XXX: was a fallback in mesa (gs doesn't get enough | ||
63 | * information to know when to reset stipple counter), but there | ||
64 | * must be a way around it. | ||
65 | */ | ||
66 | if (rast->line_stipple_enable && | ||
67 | (brw->reduced_primitive == PIPE_PRIM_TRIANGLES || | ||
68 | brw->primitive == PIPE_PRIM_LINE_LOOP || | ||
69 | brw->primitive == PIPE_PRIM_LINE_STRIP)) | ||
70 | return TRUE; | ||
71 | } | ||
72 | |||
73 | |||
74 | if (brw->reduced_primitive == PIPE_PRIM_POINTS || | ||
75 | (brw->reduced_primitive == PIPE_PRIM_TRIANGLES && | ||
76 | (rast->fill_cw == PIPE_POLYGON_MODE_POINT || | ||
77 | rast->fill_ccw == PIPE_POLYGON_MODE_POINT))) | ||
78 | { | ||
79 | if (rast->point_smooth) | ||
80 | return TRUE; | ||
81 | } | ||
82 | |||
83 | /* BRW hardware doesn't handle CLAMP texturing correctly; | ||
84 | * brw_wm_sampler_state:translate_wrap_mode() treats CLAMP | ||
85 | * as CLAMP_TO_EDGE instead. If we're using CLAMP, and | ||
86 | * we want strict conformance, force the fallback. | ||
87 | * | ||
88 | * XXX: need a workaround for this. | ||
89 | */ | ||
90 | |||
91 | /* Nothing stopping us from the fast path now */ | ||
92 | return FALSE; | ||
93 | } | ||
94 | |||
95 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_types.h b/src/gallium/drivers/i965/brw_types.h deleted file mode 100644 index 89e08a5c804..00000000000 --- a/src/gallium/drivers/i965/brw_types.h +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | #ifndef BRW_TYPES_H | ||
2 | #define BRW_TYPES_H | ||
3 | |||
4 | #include "pipe/p_compiler.h" | ||
5 | |||
6 | typedef uint32_t GLuint; | ||
7 | typedef uint8_t GLubyte; | ||
8 | typedef uint16_t GLushort; | ||
9 | typedef int32_t GLint; | ||
10 | typedef int8_t GLbyte; | ||
11 | typedef int16_t GLshort; | ||
12 | typedef float GLfloat; | ||
13 | |||
14 | /* no GLenum, translate all away */ | ||
15 | |||
16 | typedef uint8_t GLboolean; | ||
17 | |||
18 | #define GL_FALSE FALSE | ||
19 | #define GL_TRUE TRUE | ||
20 | |||
21 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_urb.c b/src/gallium/drivers/i965/brw_urb.c deleted file mode 100644 index b630752809e..00000000000 --- a/src/gallium/drivers/i965/brw_urb.c +++ /dev/null | |||
@@ -1,263 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | |||
34 | #include "brw_batchbuffer.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_defines.h" | ||
38 | #include "brw_debug.h" | ||
39 | |||
40 | #define VS 0 | ||
41 | #define GS 1 | ||
42 | #define CLP 2 | ||
43 | #define SF 3 | ||
44 | #define CS 4 | ||
45 | |||
46 | /** @file brw_urb.c | ||
47 | * | ||
48 | * Manages the division of the URB space between the various fixed-function | ||
49 | * units. | ||
50 | * | ||
51 | * See the Thread Initiation Management section of the GEN4 B-Spec, and | ||
52 | * the individual *_STATE structures for restrictions on numbers of | ||
53 | * entries and threads. | ||
54 | */ | ||
55 | |||
56 | /* | ||
57 | * Generally, a unit requires a min_nr_entries based on how many entries | ||
58 | * it produces before the downstream unit gets unblocked and can use and | ||
59 | * dereference some of its handles. | ||
60 | * | ||
61 | * The SF unit preallocates a PUE at the start of thread dispatch, and only | ||
62 | * uses that one. So it requires one entry per thread. | ||
63 | * | ||
64 | * For CLIP, the SF unit will hold the previous primitive while the | ||
65 | * next is getting assembled, meaning that linestrips require 3 CLIP VUEs | ||
66 | * (vertices) to ensure continued processing, trifans require 4, and tristrips | ||
67 | * require 5. There can be 1 or 2 threads, and each has the same requirement. | ||
68 | * | ||
69 | * GS has the same requirement as CLIP, but it never handles tristrips, | ||
70 | * so we can lower the minimum to 4 for the POLYGONs (trifans) it produces. | ||
71 | * We only run it single-threaded. | ||
72 | * | ||
73 | * For VS, the number of entries may be 8, 12, 16, or 32 (or 64 on G4X). | ||
74 | * Each thread processes 2 preallocated VUEs (vertices) at a time, and they | ||
75 | * get streamed down as soon as threads processing earlier vertices get | ||
76 | * theirs accepted. | ||
77 | * | ||
78 | * Each unit will take the number of URB entries we give it (based on the | ||
79 | * entry size calculated in brw_vs_emit.c for VUEs, brw_sf_emit.c for PUEs, | ||
80 | * and brw_curbe.c for the CURBEs) and decide its maximum number of | ||
81 | * threads it can support based on that. in brw_*_state.c. | ||
82 | * | ||
83 | * XXX: Are the min_entry_size numbers useful? | ||
84 | * XXX: Verify min_nr_entries, esp for VS. | ||
85 | * XXX: Verify SF min_entry_size. | ||
86 | */ | ||
87 | static const struct urb_limits { | ||
88 | GLuint min_nr_entries; | ||
89 | GLuint preferred_nr_entries; | ||
90 | GLuint min_entry_size; | ||
91 | GLuint max_entry_size; | ||
92 | } limits[CS+1] = { | ||
93 | { 16, 32, 1, 5 }, /* vs */ | ||
94 | { 4, 8, 1, 5 }, /* gs */ | ||
95 | { 5, 10, 1, 5 }, /* clp */ | ||
96 | { 1, 8, 1, 12 }, /* sf */ | ||
97 | { 1, 4, 1, 32 } /* cs */ | ||
98 | }; | ||
99 | |||
100 | |||
101 | static GLboolean check_urb_layout( struct brw_context *brw ) | ||
102 | { | ||
103 | brw->urb.vs_start = 0; | ||
104 | brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize; | ||
105 | brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize; | ||
106 | brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize; | ||
107 | brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize; | ||
108 | |||
109 | return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw); | ||
110 | } | ||
111 | |||
112 | /* Most minimal update, forces re-emit of URB fence packet after GS | ||
113 | * unit turned on/off. | ||
114 | */ | ||
115 | static int recalculate_urb_fence( struct brw_context *brw ) | ||
116 | { | ||
117 | GLuint csize = brw->curbe.total_size; | ||
118 | GLuint vsize = brw->vs.prog_data->urb_entry_size; | ||
119 | GLuint sfsize = brw->sf.prog_data->urb_entry_size; | ||
120 | |||
121 | if (csize < limits[CS].min_entry_size) | ||
122 | csize = limits[CS].min_entry_size; | ||
123 | |||
124 | if (vsize < limits[VS].min_entry_size) | ||
125 | vsize = limits[VS].min_entry_size; | ||
126 | |||
127 | if (sfsize < limits[SF].min_entry_size) | ||
128 | sfsize = limits[SF].min_entry_size; | ||
129 | |||
130 | if (brw->urb.vsize < vsize || | ||
131 | brw->urb.sfsize < sfsize || | ||
132 | brw->urb.csize < csize || | ||
133 | (brw->urb.constrained && (brw->urb.vsize > vsize || | ||
134 | brw->urb.sfsize > sfsize || | ||
135 | brw->urb.csize > csize))) { | ||
136 | |||
137 | |||
138 | brw->urb.csize = csize; | ||
139 | brw->urb.sfsize = sfsize; | ||
140 | brw->urb.vsize = vsize; | ||
141 | |||
142 | brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; | ||
143 | brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries; | ||
144 | brw->urb.nr_clip_entries = limits[CLP].preferred_nr_entries; | ||
145 | brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; | ||
146 | brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries; | ||
147 | |||
148 | brw->urb.constrained = 0; | ||
149 | |||
150 | if (brw->gen == 5) { | ||
151 | brw->urb.nr_vs_entries = 128; | ||
152 | brw->urb.nr_sf_entries = 48; | ||
153 | if (check_urb_layout(brw)) { | ||
154 | goto done; | ||
155 | } else { | ||
156 | brw->urb.constrained = 1; | ||
157 | brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; | ||
158 | brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; | ||
159 | } | ||
160 | } else if (brw->is_g4x) { | ||
161 | brw->urb.nr_vs_entries = 64; | ||
162 | if (check_urb_layout(brw)) { | ||
163 | goto done; | ||
164 | } else { | ||
165 | brw->urb.constrained = 1; | ||
166 | brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; | ||
167 | } | ||
168 | } | ||
169 | |||
170 | if (BRW_DEBUG & DEBUG_MIN_URB) { | ||
171 | brw->urb.nr_vs_entries = limits[VS].min_nr_entries; | ||
172 | brw->urb.nr_gs_entries = limits[GS].min_nr_entries; | ||
173 | brw->urb.nr_clip_entries = limits[CLP].min_nr_entries; | ||
174 | brw->urb.nr_sf_entries = limits[SF].min_nr_entries; | ||
175 | brw->urb.nr_cs_entries = limits[CS].min_nr_entries; | ||
176 | brw->urb.constrained = 1; | ||
177 | } | ||
178 | |||
179 | if (!check_urb_layout(brw)) { | ||
180 | brw->urb.nr_vs_entries = limits[VS].min_nr_entries; | ||
181 | brw->urb.nr_gs_entries = limits[GS].min_nr_entries; | ||
182 | brw->urb.nr_clip_entries = limits[CLP].min_nr_entries; | ||
183 | brw->urb.nr_sf_entries = limits[SF].min_nr_entries; | ||
184 | brw->urb.nr_cs_entries = limits[CS].min_nr_entries; | ||
185 | |||
186 | /* Mark us as operating with constrained nr_entries, so that next | ||
187 | * time we recalculate we'll resize the fences in the hope of | ||
188 | * escaping constrained mode and getting back to normal performance. | ||
189 | */ | ||
190 | brw->urb.constrained = 1; | ||
191 | |||
192 | if (!check_urb_layout(brw)) { | ||
193 | /* This is impossible, given the maximal sizes of urb | ||
194 | * entries and the values for minimum nr of entries | ||
195 | * provided above. | ||
196 | */ | ||
197 | debug_printf("couldn't calculate URB layout!\n"); | ||
198 | exit(1); | ||
199 | } | ||
200 | |||
201 | if (BRW_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS)) | ||
202 | debug_printf("URB CONSTRAINED\n"); | ||
203 | } | ||
204 | |||
205 | done: | ||
206 | if (BRW_DEBUG & DEBUG_URB) | ||
207 | debug_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n", | ||
208 | brw->urb.vs_start, | ||
209 | brw->urb.gs_start, | ||
210 | brw->urb.clip_start, | ||
211 | brw->urb.sf_start, | ||
212 | brw->urb.cs_start, | ||
213 | URB_SIZES(brw)); | ||
214 | |||
215 | brw->state.dirty.brw |= BRW_NEW_URB_FENCE; | ||
216 | } | ||
217 | |||
218 | return 0; | ||
219 | } | ||
220 | |||
221 | |||
222 | const struct brw_tracked_state brw_recalculate_urb_fence = { | ||
223 | .dirty = { | ||
224 | .mesa = 0, | ||
225 | .brw = BRW_NEW_CURBE_OFFSETS, | ||
226 | .cache = (CACHE_NEW_VS_PROG | | ||
227 | CACHE_NEW_SF_PROG) | ||
228 | }, | ||
229 | .prepare = recalculate_urb_fence | ||
230 | }; | ||
231 | |||
232 | |||
233 | |||
234 | |||
235 | |||
236 | int brw_upload_urb_fence(struct brw_context *brw) | ||
237 | { | ||
238 | struct brw_urb_fence uf; | ||
239 | memset(&uf, 0, sizeof(uf)); | ||
240 | |||
241 | uf.header.opcode = CMD_URB_FENCE; | ||
242 | uf.header.length = sizeof(uf)/4-2; | ||
243 | uf.header.vs_realloc = 1; | ||
244 | uf.header.gs_realloc = 1; | ||
245 | uf.header.clp_realloc = 1; | ||
246 | uf.header.sf_realloc = 1; | ||
247 | uf.header.vfe_realloc = 1; | ||
248 | uf.header.cs_realloc = 1; | ||
249 | |||
250 | /* The ordering below is correct, not the layout in the | ||
251 | * instruction. | ||
252 | * | ||
253 | * There are 256/384 urb reg pairs in total. | ||
254 | */ | ||
255 | uf.bits0.vs_fence = brw->urb.gs_start; | ||
256 | uf.bits0.gs_fence = brw->urb.clip_start; | ||
257 | uf.bits0.clp_fence = brw->urb.sf_start; | ||
258 | uf.bits1.sf_fence = brw->urb.cs_start; | ||
259 | uf.bits1.cs_fence = URB_SIZES(brw); | ||
260 | |||
261 | BRW_BATCH_STRUCT(brw, &uf); | ||
262 | return 0; | ||
263 | } | ||
diff --git a/src/gallium/drivers/i965/brw_util.h b/src/gallium/drivers/i965/brw_util.h deleted file mode 100644 index b5f9a36e7bc..00000000000 --- a/src/gallium/drivers/i965/brw_util.h +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_UTIL_H | ||
34 | #define BRW_UTIL_H | ||
35 | |||
36 | #include "brw_types.h" | ||
37 | |||
38 | extern GLuint brw_count_bits( GLuint val ); | ||
39 | extern GLuint brw_translate_blend_factor( unsigned factor ); | ||
40 | extern GLuint brw_translate_blend_equation( unsigned mode ); | ||
41 | |||
42 | |||
43 | |||
44 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_vs.c b/src/gallium/drivers/i965/brw_vs.c deleted file mode 100644 index ca8ee79550d..00000000000 --- a/src/gallium/drivers/i965/brw_vs.c +++ /dev/null | |||
@@ -1,129 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "tgsi/tgsi_dump.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_vs.h" | ||
36 | #include "brw_state.h" | ||
37 | |||
38 | |||
39 | |||
40 | static enum pipe_error do_vs_prog( struct brw_context *brw, | ||
41 | struct brw_vertex_shader *vp, | ||
42 | struct brw_vs_prog_key *key, | ||
43 | struct brw_winsys_buffer **bo_out) | ||
44 | { | ||
45 | enum pipe_error ret; | ||
46 | GLuint program_size; | ||
47 | const GLuint *program; | ||
48 | struct brw_vs_compile c; | ||
49 | |||
50 | memset(&c, 0, sizeof(c)); | ||
51 | memcpy(&c.key, key, sizeof(*key)); | ||
52 | |||
53 | brw_init_compile(brw, &c.func); | ||
54 | c.vp = vp; | ||
55 | |||
56 | c.prog_data.nr_outputs = vp->info.num_outputs; | ||
57 | c.prog_data.nr_inputs = vp->info.num_inputs; | ||
58 | |||
59 | if (1) | ||
60 | tgsi_dump(c.vp->tokens, 0); | ||
61 | |||
62 | /* Emit GEN4 code. | ||
63 | */ | ||
64 | brw_vs_emit(&c); | ||
65 | |||
66 | /* get the program | ||
67 | */ | ||
68 | ret = brw_get_program(&c.func, &program, &program_size); | ||
69 | if (ret) | ||
70 | return ret; | ||
71 | |||
72 | ret = brw_upload_cache( &brw->cache, BRW_VS_PROG, | ||
73 | &c.key, brw_vs_prog_key_size(&c.key), | ||
74 | NULL, 0, | ||
75 | program, program_size, | ||
76 | &c.prog_data, | ||
77 | &brw->vs.prog_data, | ||
78 | bo_out); | ||
79 | if (ret) | ||
80 | return ret; | ||
81 | |||
82 | return PIPE_OK; | ||
83 | } | ||
84 | |||
85 | |||
86 | static enum pipe_error brw_upload_vs_prog(struct brw_context *brw) | ||
87 | { | ||
88 | struct brw_vs_prog_key key; | ||
89 | struct brw_vertex_shader *vp = brw->curr.vertex_shader; | ||
90 | struct brw_fs_signature *sig = &brw->curr.fragment_shader->signature; | ||
91 | enum pipe_error ret; | ||
92 | |||
93 | memset(&key, 0, sizeof(key)); | ||
94 | |||
95 | key.program_string_id = vp->id; | ||
96 | key.nr_userclip = brw->curr.ucp.nr; | ||
97 | |||
98 | memcpy(&key.fs_signature, sig, brw_fs_signature_size(sig)); | ||
99 | |||
100 | |||
101 | /* Make an early check for the key. | ||
102 | */ | ||
103 | if (brw_search_cache(&brw->cache, BRW_VS_PROG, | ||
104 | &key, brw_vs_prog_key_size(&key), | ||
105 | NULL, 0, | ||
106 | &brw->vs.prog_data, | ||
107 | &brw->vs.prog_bo)) | ||
108 | return PIPE_OK; | ||
109 | |||
110 | ret = do_vs_prog(brw, vp, &key, &brw->vs.prog_bo); | ||
111 | if (ret) | ||
112 | return ret; | ||
113 | |||
114 | return PIPE_OK; | ||
115 | } | ||
116 | |||
117 | |||
118 | /* See brw_vs.c: | ||
119 | */ | ||
120 | const struct brw_tracked_state brw_vs_prog = { | ||
121 | .dirty = { | ||
122 | .mesa = (PIPE_NEW_CLIP | | ||
123 | PIPE_NEW_RAST | | ||
124 | PIPE_NEW_FRAGMENT_SIGNATURE), | ||
125 | .brw = BRW_NEW_VERTEX_PROGRAM, | ||
126 | .cache = 0 | ||
127 | }, | ||
128 | .prepare = brw_upload_vs_prog | ||
129 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_vs.h b/src/gallium/drivers/i965/brw_vs.h deleted file mode 100644 index b6d1091618e..00000000000 --- a/src/gallium/drivers/i965/brw_vs.h +++ /dev/null | |||
@@ -1,105 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_VS_H | ||
34 | #define BRW_VS_H | ||
35 | |||
36 | |||
37 | #include "brw_context.h" | ||
38 | #include "brw_eu.h" | ||
39 | |||
40 | |||
41 | struct brw_vs_prog_key { | ||
42 | GLuint program_string_id; | ||
43 | GLuint nr_userclip:4; | ||
44 | GLuint pad:26; | ||
45 | struct brw_fs_signature fs_signature; | ||
46 | }; | ||
47 | |||
48 | #define brw_vs_prog_key_size(s) (offsetof(struct brw_vs_prog_key, fs_signature) + \ | ||
49 | brw_fs_signature_size(&(s)->fs_signature)) | ||
50 | |||
51 | |||
52 | #define MAX_IF_DEPTH 32 | ||
53 | #define MAX_LOOP_DEPTH 32 | ||
54 | |||
55 | struct brw_vs_compile { | ||
56 | struct brw_compile func; | ||
57 | struct brw_vs_prog_key key; | ||
58 | struct brw_vs_prog_data prog_data; | ||
59 | |||
60 | struct brw_vertex_shader *vp; | ||
61 | |||
62 | GLuint nr_inputs; | ||
63 | GLuint nr_outputs; | ||
64 | GLuint nr_immediates; | ||
65 | GLfloat immediate[128][4]; | ||
66 | |||
67 | GLuint overflow_grf_start; | ||
68 | GLuint overflow_count; | ||
69 | |||
70 | GLuint first_tmp; | ||
71 | GLuint last_tmp; | ||
72 | |||
73 | struct brw_reg r0; | ||
74 | struct brw_reg r1; | ||
75 | struct brw_reg regs[TGSI_FILE_COUNT][128]; | ||
76 | struct brw_reg tmp; | ||
77 | struct brw_reg stack; | ||
78 | |||
79 | struct { | ||
80 | GLboolean used_in_src; | ||
81 | struct brw_reg reg; | ||
82 | } output_regs[128]; | ||
83 | |||
84 | struct brw_reg userplane[6]; | ||
85 | |||
86 | /** we may need up to 3 constants per instruction (if use_const_buffer) */ | ||
87 | struct { | ||
88 | GLint index; | ||
89 | struct brw_reg reg; | ||
90 | } current_const[3]; | ||
91 | |||
92 | struct brw_instruction *if_inst[MAX_IF_DEPTH]; | ||
93 | struct brw_instruction *loop_inst[MAX_LOOP_DEPTH]; | ||
94 | GLuint insn; | ||
95 | GLuint if_depth; | ||
96 | GLuint loop_depth; | ||
97 | GLuint end_offset; | ||
98 | |||
99 | struct brw_indirect stack_index; | ||
100 | }; | ||
101 | |||
102 | |||
103 | void brw_vs_emit( struct brw_vs_compile *c ); | ||
104 | |||
105 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_vs_emit.c b/src/gallium/drivers/i965/brw_vs_emit.c deleted file mode 100644 index 559f0c61d8d..00000000000 --- a/src/gallium/drivers/i965/brw_vs_emit.c +++ /dev/null | |||
@@ -1,1660 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "pipe/p_shader_tokens.h" | ||
33 | |||
34 | #include "util/u_memory.h" | ||
35 | #include "util/u_math.h" | ||
36 | |||
37 | #include "tgsi/tgsi_parse.h" | ||
38 | #include "tgsi/tgsi_dump.h" | ||
39 | #include "tgsi/tgsi_info.h" | ||
40 | |||
41 | #include "brw_context.h" | ||
42 | #include "brw_vs.h" | ||
43 | #include "brw_debug.h" | ||
44 | #include "brw_disasm.h" | ||
45 | |||
46 | /* Choose one of the 4 vec4's which can be packed into each 16-wide reg. | ||
47 | */ | ||
48 | static INLINE struct brw_reg brw_vec4_grf_repeat( GLuint reg, GLuint slot ) | ||
49 | { | ||
50 | int nr = reg + slot/2; | ||
51 | int subnr = (slot%2) * 4; | ||
52 | |||
53 | return stride(brw_vec4_grf(nr, subnr), 0, 4, 1); | ||
54 | } | ||
55 | |||
56 | |||
57 | static struct brw_reg get_tmp( struct brw_vs_compile *c ) | ||
58 | { | ||
59 | struct brw_reg tmp = brw_vec8_grf(c->last_tmp, 0); | ||
60 | |||
61 | if (++c->last_tmp > c->prog_data.total_grf) | ||
62 | c->prog_data.total_grf = c->last_tmp; | ||
63 | |||
64 | return tmp; | ||
65 | } | ||
66 | |||
67 | static void release_tmp( struct brw_vs_compile *c, struct brw_reg tmp ) | ||
68 | { | ||
69 | if (tmp.nr == c->last_tmp-1) | ||
70 | c->last_tmp--; | ||
71 | } | ||
72 | |||
73 | static void release_tmps( struct brw_vs_compile *c ) | ||
74 | { | ||
75 | c->last_tmp = c->first_tmp; | ||
76 | } | ||
77 | |||
78 | |||
79 | static boolean is_position_output( struct brw_vs_compile *c, | ||
80 | unsigned vs_output ) | ||
81 | { | ||
82 | const struct brw_vertex_shader *vs = c->vp; | ||
83 | unsigned semantic = vs->info.output_semantic_name[vs_output]; | ||
84 | unsigned index = vs->info.output_semantic_index[vs_output]; | ||
85 | |||
86 | return (semantic == TGSI_SEMANTIC_POSITION && | ||
87 | index == 0); | ||
88 | } | ||
89 | |||
90 | |||
91 | static boolean find_output_slot( struct brw_vs_compile *c, | ||
92 | unsigned vs_output, | ||
93 | unsigned *fs_input_slot ) | ||
94 | { | ||
95 | const struct brw_vertex_shader *vs = c->vp; | ||
96 | unsigned semantic = vs->info.output_semantic_name[vs_output]; | ||
97 | unsigned index = vs->info.output_semantic_index[vs_output]; | ||
98 | unsigned i; | ||
99 | |||
100 | for (i = 0; i < c->key.fs_signature.nr_inputs; i++) { | ||
101 | if (c->key.fs_signature.input[i].semantic == semantic && | ||
102 | c->key.fs_signature.input[i].semantic_index == index) { | ||
103 | *fs_input_slot = i; | ||
104 | return TRUE; | ||
105 | } | ||
106 | } | ||
107 | |||
108 | return FALSE; | ||
109 | } | ||
110 | |||
111 | |||
112 | /** | ||
113 | * Preallocate GRF register before code emit. | ||
114 | * Do things as simply as possible. Allocate and populate all regs | ||
115 | * ahead of time. | ||
116 | */ | ||
117 | static void brw_vs_alloc_regs( struct brw_vs_compile *c ) | ||
118 | { | ||
119 | struct brw_context *brw = c->func.brw; | ||
120 | GLuint i, reg = 0, subreg = 0, mrf; | ||
121 | int attributes_in_vue; | ||
122 | |||
123 | /* Determine whether to use a real constant buffer or use a block | ||
124 | * of GRF registers for constants. The later is faster but only | ||
125 | * works if everything fits in the GRF. | ||
126 | * XXX this heuristic/check may need some fine tuning... | ||
127 | */ | ||
128 | if (c->vp->info.file_max[TGSI_FILE_CONSTANT] + 1 + | ||
129 | c->vp->info.file_max[TGSI_FILE_IMMEDIATE] + 1 + | ||
130 | c->vp->info.file_max[TGSI_FILE_TEMPORARY] + 1 + 21 > BRW_MAX_GRF) | ||
131 | c->vp->use_const_buffer = GL_TRUE; | ||
132 | else { | ||
133 | /* XXX: immediates can go elsewhere if necessary: | ||
134 | */ | ||
135 | assert(c->vp->info.file_max[TGSI_FILE_IMMEDIATE] + 1 + | ||
136 | c->vp->info.file_max[TGSI_FILE_TEMPORARY] + 1 + 21 <= BRW_MAX_GRF); | ||
137 | |||
138 | c->vp->use_const_buffer = GL_FALSE; | ||
139 | } | ||
140 | |||
141 | /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/ | ||
142 | |||
143 | /* r0 -- reserved as usual | ||
144 | */ | ||
145 | c->r0 = brw_vec8_grf(reg, 0); | ||
146 | reg++; | ||
147 | |||
148 | /* User clip planes from curbe: | ||
149 | */ | ||
150 | if (c->key.nr_userclip) { | ||
151 | /* Skip over fixed planes: Or never read them into vs unit? | ||
152 | */ | ||
153 | subreg += 6; | ||
154 | |||
155 | for (i = 0; i < c->key.nr_userclip; i++, subreg++) { | ||
156 | c->userplane[i] = | ||
157 | stride( brw_vec4_grf(reg+subreg/2, (subreg%2) * 4), 0, 4, 1); | ||
158 | } | ||
159 | |||
160 | /* Deal with curbe alignment: | ||
161 | */ | ||
162 | subreg = align(subreg, 2); | ||
163 | /*reg += ((6 + c->key.nr_userclip + 3) / 4) * 2;*/ | ||
164 | } | ||
165 | |||
166 | |||
167 | /* Immediates: always in the curbe. | ||
168 | * | ||
169 | * XXX: Can try to encode some immediates as brw immediates | ||
170 | * XXX: Make sure ureg sets minimal immediate size and respect it | ||
171 | * here. | ||
172 | */ | ||
173 | for (i = 0; i < c->vp->info.immediate_count; i++, subreg++) { | ||
174 | c->regs[TGSI_FILE_IMMEDIATE][i] = | ||
175 | stride( brw_vec4_grf(reg+subreg/2, (subreg%2) * 4), 0, 4, 1); | ||
176 | } | ||
177 | c->prog_data.nr_params = c->vp->info.immediate_count * 4; | ||
178 | |||
179 | |||
180 | /* Vertex constant buffer. | ||
181 | * | ||
182 | * Constants from the buffer can be either cached in the curbe or | ||
183 | * loaded as needed from the actual constant buffer. | ||
184 | */ | ||
185 | if (!c->vp->use_const_buffer) { | ||
186 | GLuint nr_params = c->vp->info.file_max[TGSI_FILE_CONSTANT] + 1; | ||
187 | |||
188 | for (i = 0; i < nr_params; i++, subreg++) { | ||
189 | c->regs[TGSI_FILE_CONSTANT][i] = | ||
190 | stride( brw_vec4_grf(reg+subreg/2, (subreg%2) * 4), 0, 4, 1); | ||
191 | } | ||
192 | |||
193 | c->prog_data.nr_params += nr_params * 4; | ||
194 | } | ||
195 | |||
196 | /* All regs allocated | ||
197 | */ | ||
198 | reg += (subreg + 1) / 2; | ||
199 | c->prog_data.curb_read_length = reg - 1; | ||
200 | |||
201 | |||
202 | /* Allocate input regs: | ||
203 | */ | ||
204 | c->nr_inputs = c->vp->info.num_inputs; | ||
205 | for (i = 0; i < c->nr_inputs; i++) { | ||
206 | c->regs[TGSI_FILE_INPUT][i] = brw_vec8_grf(reg, 0); | ||
207 | reg++; | ||
208 | } | ||
209 | |||
210 | /* If there are no inputs, we'll still be reading one attribute's worth | ||
211 | * because it's required -- see urb_read_length setting. | ||
212 | */ | ||
213 | if (c->nr_inputs == 0) | ||
214 | reg++; | ||
215 | |||
216 | |||
217 | |||
218 | /* Allocate outputs. The non-position outputs go straight into message regs. | ||
219 | */ | ||
220 | c->nr_outputs = c->prog_data.nr_outputs; | ||
221 | |||
222 | if (brw->gen == 5) | ||
223 | mrf = 8; | ||
224 | else | ||
225 | mrf = 4; | ||
226 | |||
227 | |||
228 | if (c->key.fs_signature.nr_inputs > BRW_MAX_MRF) { | ||
229 | c->overflow_grf_start = reg; | ||
230 | c->overflow_count = c->key.fs_signature.nr_inputs - BRW_MAX_MRF; | ||
231 | reg += c->overflow_count; | ||
232 | } | ||
233 | |||
234 | /* XXX: need to access vertex output semantics here: | ||
235 | */ | ||
236 | for (i = 0; i < c->nr_outputs; i++) { | ||
237 | unsigned slot; | ||
238 | |||
239 | /* XXX: Put output position in slot zero always. Clipper, etc, | ||
240 | * need access to this reg. | ||
241 | */ | ||
242 | if (is_position_output(c, i)) { | ||
243 | c->regs[TGSI_FILE_OUTPUT][i] = brw_vec8_grf(reg, 0); /* copy to mrf 0 */ | ||
244 | reg++; | ||
245 | } | ||
246 | else if (find_output_slot(c, i, &slot)) { | ||
247 | |||
248 | if (0 /* is_psize_output(c, i) */ ) { | ||
249 | /* c->psize_out.grf = reg; */ | ||
250 | /* c->psize_out.mrf = i; */ | ||
251 | } | ||
252 | |||
253 | /* The first (16-4) outputs can go straight into the message regs. | ||
254 | */ | ||
255 | if (slot + mrf < BRW_MAX_MRF) { | ||
256 | c->regs[TGSI_FILE_OUTPUT][i] = brw_message_reg(slot + mrf); | ||
257 | } | ||
258 | else { | ||
259 | int grf = c->overflow_grf_start + slot - BRW_MAX_MRF; | ||
260 | c->regs[TGSI_FILE_OUTPUT][i] = brw_vec8_grf(grf, 0); | ||
261 | } | ||
262 | } | ||
263 | else { | ||
264 | c->regs[TGSI_FILE_OUTPUT][i] = brw_null_reg(); | ||
265 | } | ||
266 | } | ||
267 | |||
268 | /* Allocate program temporaries: | ||
269 | */ | ||
270 | |||
271 | for (i = 0; i < c->vp->info.file_max[TGSI_FILE_TEMPORARY]+1; i++) { | ||
272 | c->regs[TGSI_FILE_TEMPORARY][i] = brw_vec8_grf(reg, 0); | ||
273 | reg++; | ||
274 | } | ||
275 | |||
276 | /* Address reg(s). Don't try to use the internal address reg until | ||
277 | * deref time. | ||
278 | */ | ||
279 | for (i = 0; i < c->vp->info.file_max[TGSI_FILE_ADDRESS]+1; i++) { | ||
280 | c->regs[TGSI_FILE_ADDRESS][i] = brw_reg(BRW_GENERAL_REGISTER_FILE, | ||
281 | reg, | ||
282 | 0, | ||
283 | BRW_REGISTER_TYPE_D, | ||
284 | BRW_VERTICAL_STRIDE_8, | ||
285 | BRW_WIDTH_8, | ||
286 | BRW_HORIZONTAL_STRIDE_1, | ||
287 | BRW_SWIZZLE_XXXX, | ||
288 | BRW_WRITEMASK_X); | ||
289 | reg++; | ||
290 | } | ||
291 | |||
292 | if (c->vp->use_const_buffer) { | ||
293 | for (i = 0; i < 3; i++) { | ||
294 | c->current_const[i].index = -1; | ||
295 | c->current_const[i].reg = brw_vec8_grf(reg, 0); | ||
296 | reg++; | ||
297 | } | ||
298 | } | ||
299 | |||
300 | #if 0 | ||
301 | for (i = 0; i < 128; i++) { | ||
302 | if (c->output_regs[i].used_in_src) { | ||
303 | c->output_regs[i].reg = brw_vec8_grf(reg, 0); | ||
304 | reg++; | ||
305 | } | ||
306 | } | ||
307 | #endif | ||
308 | |||
309 | if (c->vp->has_flow_control) { | ||
310 | c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0); | ||
311 | reg += 2; | ||
312 | } | ||
313 | |||
314 | /* Some opcodes need an internal temporary: | ||
315 | */ | ||
316 | c->first_tmp = reg; | ||
317 | c->last_tmp = reg; /* for allocation purposes */ | ||
318 | |||
319 | /* Each input reg holds data from two vertices. The | ||
320 | * urb_read_length is the number of registers read from *each* | ||
321 | * vertex urb, so is half the amount: | ||
322 | */ | ||
323 | c->prog_data.urb_read_length = (c->nr_inputs + 1) / 2; | ||
324 | |||
325 | /* Setting this field to 0 leads to undefined behavior according to the | ||
326 | * the VS_STATE docs. Our VUEs will always have at least one attribute | ||
327 | * sitting in them, even if it's padding. | ||
328 | */ | ||
329 | if (c->prog_data.urb_read_length == 0) | ||
330 | c->prog_data.urb_read_length = 1; | ||
331 | |||
332 | /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size | ||
333 | * them to fit the biggest thing they need to. | ||
334 | */ | ||
335 | attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs); | ||
336 | |||
337 | if (brw->gen == 5) | ||
338 | c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4; | ||
339 | else | ||
340 | c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4; | ||
341 | |||
342 | c->prog_data.total_grf = reg; | ||
343 | |||
344 | if (BRW_DEBUG & DEBUG_VS) { | ||
345 | debug_printf("%s NumAddrRegs %d\n", __FUNCTION__, | ||
346 | c->vp->info.file_max[TGSI_FILE_ADDRESS]+1); | ||
347 | debug_printf("%s NumTemps %d\n", __FUNCTION__, | ||
348 | c->vp->info.file_max[TGSI_FILE_TEMPORARY]+1); | ||
349 | debug_printf("%s reg = %d\n", __FUNCTION__, reg); | ||
350 | } | ||
351 | } | ||
352 | |||
353 | |||
354 | /** | ||
355 | * If an instruction uses a temp reg both as a src and the dest, we | ||
356 | * sometimes need to allocate an intermediate temporary. | ||
357 | */ | ||
358 | static void unalias1( struct brw_vs_compile *c, | ||
359 | struct brw_reg dst, | ||
360 | struct brw_reg arg0, | ||
361 | void (*func)( struct brw_vs_compile *, | ||
362 | struct brw_reg, | ||
363 | struct brw_reg )) | ||
364 | { | ||
365 | if (dst.file == arg0.file && dst.nr == arg0.nr) { | ||
366 | struct brw_compile *p = &c->func; | ||
367 | struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); | ||
368 | func(c, tmp, arg0); | ||
369 | brw_MOV(p, dst, tmp); | ||
370 | release_tmp(c, tmp); | ||
371 | } | ||
372 | else { | ||
373 | func(c, dst, arg0); | ||
374 | } | ||
375 | } | ||
376 | |||
377 | /** | ||
378 | * \sa unalias2 | ||
379 | * Checkes if 2-operand instruction needs an intermediate temporary. | ||
380 | */ | ||
381 | static void unalias2( struct brw_vs_compile *c, | ||
382 | struct brw_reg dst, | ||
383 | struct brw_reg arg0, | ||
384 | struct brw_reg arg1, | ||
385 | void (*func)( struct brw_vs_compile *, | ||
386 | struct brw_reg, | ||
387 | struct brw_reg, | ||
388 | struct brw_reg )) | ||
389 | { | ||
390 | if ((dst.file == arg0.file && dst.nr == arg0.nr) || | ||
391 | (dst.file == arg1.file && dst.nr == arg1.nr)) { | ||
392 | struct brw_compile *p = &c->func; | ||
393 | struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); | ||
394 | func(c, tmp, arg0, arg1); | ||
395 | brw_MOV(p, dst, tmp); | ||
396 | release_tmp(c, tmp); | ||
397 | } | ||
398 | else { | ||
399 | func(c, dst, arg0, arg1); | ||
400 | } | ||
401 | } | ||
402 | |||
403 | /** | ||
404 | * \sa unalias2 | ||
405 | * Checkes if 3-operand instruction needs an intermediate temporary. | ||
406 | */ | ||
407 | static void unalias3( struct brw_vs_compile *c, | ||
408 | struct brw_reg dst, | ||
409 | struct brw_reg arg0, | ||
410 | struct brw_reg arg1, | ||
411 | struct brw_reg arg2, | ||
412 | void (*func)( struct brw_vs_compile *, | ||
413 | struct brw_reg, | ||
414 | struct brw_reg, | ||
415 | struct brw_reg, | ||
416 | struct brw_reg )) | ||
417 | { | ||
418 | if ((dst.file == arg0.file && dst.nr == arg0.nr) || | ||
419 | (dst.file == arg1.file && dst.nr == arg1.nr) || | ||
420 | (dst.file == arg2.file && dst.nr == arg2.nr)) { | ||
421 | struct brw_compile *p = &c->func; | ||
422 | struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); | ||
423 | func(c, tmp, arg0, arg1, arg2); | ||
424 | brw_MOV(p, dst, tmp); | ||
425 | release_tmp(c, tmp); | ||
426 | } | ||
427 | else { | ||
428 | func(c, dst, arg0, arg1, arg2); | ||
429 | } | ||
430 | } | ||
431 | |||
432 | static void emit_sop( struct brw_compile *p, | ||
433 | struct brw_reg dst, | ||
434 | struct brw_reg arg0, | ||
435 | struct brw_reg arg1, | ||
436 | GLuint cond) | ||
437 | { | ||
438 | brw_MOV(p, dst, brw_imm_f(0.0f)); | ||
439 | brw_CMP(p, brw_null_reg(), cond, arg0, arg1); | ||
440 | brw_MOV(p, dst, brw_imm_f(1.0f)); | ||
441 | brw_set_predicate_control_flag_value(p, 0xff); | ||
442 | } | ||
443 | |||
444 | static void emit_seq( struct brw_compile *p, | ||
445 | struct brw_reg dst, | ||
446 | struct brw_reg arg0, | ||
447 | struct brw_reg arg1 ) | ||
448 | { | ||
449 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ); | ||
450 | } | ||
451 | |||
452 | static void emit_sne( struct brw_compile *p, | ||
453 | struct brw_reg dst, | ||
454 | struct brw_reg arg0, | ||
455 | struct brw_reg arg1 ) | ||
456 | { | ||
457 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); | ||
458 | } | ||
459 | static void emit_slt( struct brw_compile *p, | ||
460 | struct brw_reg dst, | ||
461 | struct brw_reg arg0, | ||
462 | struct brw_reg arg1 ) | ||
463 | { | ||
464 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L); | ||
465 | } | ||
466 | |||
467 | static void emit_sle( struct brw_compile *p, | ||
468 | struct brw_reg dst, | ||
469 | struct brw_reg arg0, | ||
470 | struct brw_reg arg1 ) | ||
471 | { | ||
472 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE); | ||
473 | } | ||
474 | |||
475 | static void emit_sgt( struct brw_compile *p, | ||
476 | struct brw_reg dst, | ||
477 | struct brw_reg arg0, | ||
478 | struct brw_reg arg1 ) | ||
479 | { | ||
480 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G); | ||
481 | } | ||
482 | |||
483 | static void emit_sge( struct brw_compile *p, | ||
484 | struct brw_reg dst, | ||
485 | struct brw_reg arg0, | ||
486 | struct brw_reg arg1 ) | ||
487 | { | ||
488 | emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE); | ||
489 | } | ||
490 | |||
491 | static void emit_max( struct brw_compile *p, | ||
492 | struct brw_reg dst, | ||
493 | struct brw_reg arg0, | ||
494 | struct brw_reg arg1 ) | ||
495 | { | ||
496 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1); | ||
497 | brw_SEL(p, dst, arg1, arg0); | ||
498 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
499 | } | ||
500 | |||
501 | static void emit_min( struct brw_compile *p, | ||
502 | struct brw_reg dst, | ||
503 | struct brw_reg arg0, | ||
504 | struct brw_reg arg1 ) | ||
505 | { | ||
506 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1); | ||
507 | brw_SEL(p, dst, arg0, arg1); | ||
508 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
509 | } | ||
510 | |||
511 | |||
512 | static void emit_math1( struct brw_vs_compile *c, | ||
513 | GLuint function, | ||
514 | struct brw_reg dst, | ||
515 | struct brw_reg arg0, | ||
516 | GLuint precision) | ||
517 | { | ||
518 | /* There are various odd behaviours with SEND on the simulator. In | ||
519 | * addition there are documented issues with the fact that the GEN4 | ||
520 | * processor doesn't do dependency control properly on SEND | ||
521 | * results. So, on balance, this kludge to get around failures | ||
522 | * with writemasked math results looks like it might be necessary | ||
523 | * whether that turns out to be a simulator bug or not: | ||
524 | */ | ||
525 | struct brw_compile *p = &c->func; | ||
526 | struct brw_reg tmp = dst; | ||
527 | GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf || | ||
528 | dst.file != BRW_GENERAL_REGISTER_FILE); | ||
529 | |||
530 | if (need_tmp) | ||
531 | tmp = get_tmp(c); | ||
532 | |||
533 | brw_math(p, | ||
534 | tmp, | ||
535 | function, | ||
536 | BRW_MATH_SATURATE_NONE, | ||
537 | 2, | ||
538 | arg0, | ||
539 | BRW_MATH_DATA_SCALAR, | ||
540 | precision); | ||
541 | |||
542 | if (need_tmp) { | ||
543 | brw_MOV(p, dst, tmp); | ||
544 | release_tmp(c, tmp); | ||
545 | } | ||
546 | } | ||
547 | |||
548 | |||
549 | static void emit_math2( struct brw_vs_compile *c, | ||
550 | GLuint function, | ||
551 | struct brw_reg dst, | ||
552 | struct brw_reg arg0, | ||
553 | struct brw_reg arg1, | ||
554 | GLuint precision) | ||
555 | { | ||
556 | struct brw_compile *p = &c->func; | ||
557 | struct brw_reg tmp = dst; | ||
558 | GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf || | ||
559 | dst.file != BRW_GENERAL_REGISTER_FILE); | ||
560 | |||
561 | if (need_tmp) | ||
562 | tmp = get_tmp(c); | ||
563 | |||
564 | brw_MOV(p, brw_message_reg(3), arg1); | ||
565 | |||
566 | brw_math(p, | ||
567 | tmp, | ||
568 | function, | ||
569 | BRW_MATH_SATURATE_NONE, | ||
570 | 2, | ||
571 | arg0, | ||
572 | BRW_MATH_DATA_SCALAR, | ||
573 | precision); | ||
574 | |||
575 | if (need_tmp) { | ||
576 | brw_MOV(p, dst, tmp); | ||
577 | release_tmp(c, tmp); | ||
578 | } | ||
579 | } | ||
580 | |||
581 | |||
582 | static void emit_exp_noalias( struct brw_vs_compile *c, | ||
583 | struct brw_reg dst, | ||
584 | struct brw_reg arg0 ) | ||
585 | { | ||
586 | struct brw_compile *p = &c->func; | ||
587 | |||
588 | |||
589 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_X) { | ||
590 | struct brw_reg tmp = get_tmp(c); | ||
591 | struct brw_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D); | ||
592 | |||
593 | /* tmp_d = floor(arg0.x) */ | ||
594 | brw_RNDD(p, tmp_d, brw_swizzle1(arg0, 0)); | ||
595 | |||
596 | /* result[0] = 2.0 ^ tmp */ | ||
597 | |||
598 | /* Adjust exponent for floating point: | ||
599 | * exp += 127 | ||
600 | */ | ||
601 | brw_ADD(p, brw_writemask(tmp_d, BRW_WRITEMASK_X), tmp_d, brw_imm_d(127)); | ||
602 | |||
603 | /* Install exponent and sign. | ||
604 | * Excess drops off the edge: | ||
605 | */ | ||
606 | brw_SHL(p, brw_writemask(retype(dst, BRW_REGISTER_TYPE_D), BRW_WRITEMASK_X), | ||
607 | tmp_d, brw_imm_d(23)); | ||
608 | |||
609 | release_tmp(c, tmp); | ||
610 | } | ||
611 | |||
612 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_Y) { | ||
613 | /* result[1] = arg0.x - floor(arg0.x) */ | ||
614 | brw_FRC(p, brw_writemask(dst, BRW_WRITEMASK_Y), brw_swizzle1(arg0, 0)); | ||
615 | } | ||
616 | |||
617 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_Z) { | ||
618 | /* As with the LOG instruction, we might be better off just | ||
619 | * doing a taylor expansion here, seeing as we have to do all | ||
620 | * the prep work. | ||
621 | * | ||
622 | * If mathbox partial precision is too low, consider also: | ||
623 | * result[3] = result[0] * EXP(result[1]) | ||
624 | */ | ||
625 | emit_math1(c, | ||
626 | BRW_MATH_FUNCTION_EXP, | ||
627 | brw_writemask(dst, BRW_WRITEMASK_Z), | ||
628 | brw_swizzle1(arg0, 0), | ||
629 | BRW_MATH_PRECISION_FULL); | ||
630 | } | ||
631 | |||
632 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_W) { | ||
633 | /* result[3] = 1.0; */ | ||
634 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_W), brw_imm_f(1)); | ||
635 | } | ||
636 | } | ||
637 | |||
638 | |||
639 | static void emit_log_noalias( struct brw_vs_compile *c, | ||
640 | struct brw_reg dst, | ||
641 | struct brw_reg arg0 ) | ||
642 | { | ||
643 | struct brw_compile *p = &c->func; | ||
644 | struct brw_reg tmp = dst; | ||
645 | struct brw_reg tmp_ud = retype(tmp, BRW_REGISTER_TYPE_UD); | ||
646 | struct brw_reg arg0_ud = retype(arg0, BRW_REGISTER_TYPE_UD); | ||
647 | GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf || | ||
648 | dst.file != BRW_GENERAL_REGISTER_FILE); | ||
649 | |||
650 | if (need_tmp) { | ||
651 | tmp = get_tmp(c); | ||
652 | tmp_ud = retype(tmp, BRW_REGISTER_TYPE_UD); | ||
653 | } | ||
654 | |||
655 | /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt | ||
656 | * according to spec: | ||
657 | * | ||
658 | * These almost look likey they could be joined up, but not really | ||
659 | * practical: | ||
660 | * | ||
661 | * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127 | ||
662 | * result[1].i = (x.i & ((1<<23)-1) + (127<<23) | ||
663 | */ | ||
664 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_XZ) { | ||
665 | brw_AND(p, | ||
666 | brw_writemask(tmp_ud, BRW_WRITEMASK_X), | ||
667 | brw_swizzle1(arg0_ud, 0), | ||
668 | brw_imm_ud((1U<<31)-1)); | ||
669 | |||
670 | brw_SHR(p, | ||
671 | brw_writemask(tmp_ud, BRW_WRITEMASK_X), | ||
672 | tmp_ud, | ||
673 | brw_imm_ud(23)); | ||
674 | |||
675 | brw_ADD(p, | ||
676 | brw_writemask(tmp, BRW_WRITEMASK_X), | ||
677 | retype(tmp_ud, BRW_REGISTER_TYPE_D), /* does it matter? */ | ||
678 | brw_imm_d(-127)); | ||
679 | } | ||
680 | |||
681 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_YZ) { | ||
682 | brw_AND(p, | ||
683 | brw_writemask(tmp_ud, BRW_WRITEMASK_Y), | ||
684 | brw_swizzle1(arg0_ud, 0), | ||
685 | brw_imm_ud((1<<23)-1)); | ||
686 | |||
687 | brw_OR(p, | ||
688 | brw_writemask(tmp_ud, BRW_WRITEMASK_Y), | ||
689 | tmp_ud, | ||
690 | brw_imm_ud(127<<23)); | ||
691 | } | ||
692 | |||
693 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_Z) { | ||
694 | /* result[2] = result[0] + LOG2(result[1]); */ | ||
695 | |||
696 | /* Why bother? The above is just a hint how to do this with a | ||
697 | * taylor series. Maybe we *should* use a taylor series as by | ||
698 | * the time all the above has been done it's almost certainly | ||
699 | * quicker than calling the mathbox, even with low precision. | ||
700 | * | ||
701 | * Options are: | ||
702 | * - result[0] + mathbox.LOG2(result[1]) | ||
703 | * - mathbox.LOG2(arg0.x) | ||
704 | * - result[0] + inline_taylor_approx(result[1]) | ||
705 | */ | ||
706 | emit_math1(c, | ||
707 | BRW_MATH_FUNCTION_LOG, | ||
708 | brw_writemask(tmp, BRW_WRITEMASK_Z), | ||
709 | brw_swizzle1(tmp, 1), | ||
710 | BRW_MATH_PRECISION_FULL); | ||
711 | |||
712 | brw_ADD(p, | ||
713 | brw_writemask(tmp, BRW_WRITEMASK_Z), | ||
714 | brw_swizzle1(tmp, 2), | ||
715 | brw_swizzle1(tmp, 0)); | ||
716 | } | ||
717 | |||
718 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_W) { | ||
719 | /* result[3] = 1.0; */ | ||
720 | brw_MOV(p, brw_writemask(tmp, BRW_WRITEMASK_W), brw_imm_f(1)); | ||
721 | } | ||
722 | |||
723 | if (need_tmp) { | ||
724 | brw_MOV(p, dst, tmp); | ||
725 | release_tmp(c, tmp); | ||
726 | } | ||
727 | } | ||
728 | |||
729 | |||
730 | /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1 | ||
731 | */ | ||
732 | static void emit_dst_noalias( struct brw_vs_compile *c, | ||
733 | struct brw_reg dst, | ||
734 | struct brw_reg arg0, | ||
735 | struct brw_reg arg1) | ||
736 | { | ||
737 | struct brw_compile *p = &c->func; | ||
738 | |||
739 | /* There must be a better way to do this: | ||
740 | */ | ||
741 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_X) | ||
742 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_X), brw_imm_f(1.0)); | ||
743 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_Y) | ||
744 | brw_MUL(p, brw_writemask(dst, BRW_WRITEMASK_Y), arg0, arg1); | ||
745 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_Z) | ||
746 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_Z), arg0); | ||
747 | if (dst.dw1.bits.writemask & BRW_WRITEMASK_W) | ||
748 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_W), arg1); | ||
749 | } | ||
750 | |||
751 | |||
752 | static void emit_xpd( struct brw_compile *p, | ||
753 | struct brw_reg dst, | ||
754 | struct brw_reg t, | ||
755 | struct brw_reg u) | ||
756 | { | ||
757 | brw_MUL(p, brw_null_reg(), brw_swizzle(t, 1,2,0,3), brw_swizzle(u,2,0,1,3)); | ||
758 | brw_MAC(p, dst, negate(brw_swizzle(t, 2,0,1,3)), brw_swizzle(u,1,2,0,3)); | ||
759 | } | ||
760 | |||
761 | |||
762 | static void emit_lit_noalias( struct brw_vs_compile *c, | ||
763 | struct brw_reg dst, | ||
764 | struct brw_reg arg0 ) | ||
765 | { | ||
766 | struct brw_compile *p = &c->func; | ||
767 | struct brw_instruction *if_insn; | ||
768 | struct brw_reg tmp = dst; | ||
769 | GLboolean need_tmp = (dst.file != BRW_GENERAL_REGISTER_FILE); | ||
770 | |||
771 | if (need_tmp) | ||
772 | tmp = get_tmp(c); | ||
773 | |||
774 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_YZ), brw_imm_f(0)); | ||
775 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_XW), brw_imm_f(1)); | ||
776 | |||
777 | /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order | ||
778 | * to get all channels active inside the IF. In the clipping code | ||
779 | * we run with NoMask, so it's not an option and we can use | ||
780 | * BRW_EXECUTE_1 for all comparisions. | ||
781 | */ | ||
782 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, brw_swizzle1(arg0,0), brw_imm_f(0)); | ||
783 | if_insn = brw_IF(p, BRW_EXECUTE_8); | ||
784 | { | ||
785 | brw_MOV(p, brw_writemask(dst, BRW_WRITEMASK_Y), brw_swizzle1(arg0,0)); | ||
786 | |||
787 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, brw_swizzle1(arg0,1), brw_imm_f(0)); | ||
788 | brw_MOV(p, brw_writemask(tmp, BRW_WRITEMASK_Z), brw_swizzle1(arg0,1)); | ||
789 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
790 | |||
791 | emit_math2(c, | ||
792 | BRW_MATH_FUNCTION_POW, | ||
793 | brw_writemask(dst, BRW_WRITEMASK_Z), | ||
794 | brw_swizzle1(tmp, 2), | ||
795 | brw_swizzle1(arg0, 3), | ||
796 | BRW_MATH_PRECISION_PARTIAL); | ||
797 | } | ||
798 | |||
799 | brw_ENDIF(p, if_insn); | ||
800 | |||
801 | release_tmp(c, tmp); | ||
802 | } | ||
803 | |||
804 | static void emit_lrp_noalias(struct brw_vs_compile *c, | ||
805 | struct brw_reg dst, | ||
806 | struct brw_reg arg0, | ||
807 | struct brw_reg arg1, | ||
808 | struct brw_reg arg2) | ||
809 | { | ||
810 | struct brw_compile *p = &c->func; | ||
811 | |||
812 | brw_ADD(p, dst, negate(arg0), brw_imm_f(1.0)); | ||
813 | brw_MUL(p, brw_null_reg(), dst, arg2); | ||
814 | brw_MAC(p, dst, arg0, arg1); | ||
815 | } | ||
816 | |||
817 | /** 3 or 4-component vector normalization */ | ||
818 | static void emit_nrm( struct brw_vs_compile *c, | ||
819 | struct brw_reg dst, | ||
820 | struct brw_reg arg0, | ||
821 | int num_comps) | ||
822 | { | ||
823 | struct brw_compile *p = &c->func; | ||
824 | struct brw_reg tmp = get_tmp(c); | ||
825 | |||
826 | /* tmp = dot(arg0, arg0) */ | ||
827 | if (num_comps == 3) | ||
828 | brw_DP3(p, tmp, arg0, arg0); | ||
829 | else | ||
830 | brw_DP4(p, tmp, arg0, arg0); | ||
831 | |||
832 | /* tmp = 1 / sqrt(tmp) */ | ||
833 | emit_math1(c, BRW_MATH_FUNCTION_RSQ, tmp, tmp, BRW_MATH_PRECISION_FULL); | ||
834 | |||
835 | /* dst = arg0 * tmp */ | ||
836 | brw_MUL(p, dst, arg0, tmp); | ||
837 | |||
838 | release_tmp(c, tmp); | ||
839 | } | ||
840 | |||
841 | |||
842 | static struct brw_reg | ||
843 | get_constant(struct brw_vs_compile *c, | ||
844 | GLuint argIndex, | ||
845 | GLuint index, | ||
846 | GLboolean relAddr) | ||
847 | { | ||
848 | struct brw_compile *p = &c->func; | ||
849 | struct brw_reg const_reg; | ||
850 | struct brw_reg const2_reg; | ||
851 | |||
852 | assert(argIndex < 3); | ||
853 | |||
854 | if (c->current_const[argIndex].index != index || relAddr) { | ||
855 | struct brw_reg addrReg = c->regs[TGSI_FILE_ADDRESS][0]; | ||
856 | |||
857 | c->current_const[argIndex].index = index; | ||
858 | |||
859 | #if 0 | ||
860 | printf(" fetch const[%d] for arg %d into reg %d\n", | ||
861 | src.Index, argIndex, c->current_const[argIndex].reg.nr); | ||
862 | #endif | ||
863 | /* need to fetch the constant now */ | ||
864 | brw_dp_READ_4_vs(p, | ||
865 | c->current_const[argIndex].reg,/* writeback dest */ | ||
866 | 0, /* oword */ | ||
867 | relAddr, /* relative indexing? */ | ||
868 | addrReg, /* address register */ | ||
869 | 16 * index, /* byte offset */ | ||
870 | SURF_INDEX_VERT_CONST_BUFFER /* binding table index */ | ||
871 | ); | ||
872 | |||
873 | if (relAddr) { | ||
874 | /* second read */ | ||
875 | const2_reg = get_tmp(c); | ||
876 | |||
877 | /* use upper half of address reg for second read */ | ||
878 | addrReg = stride(addrReg, 0, 4, 0); | ||
879 | addrReg.subnr = 16; | ||
880 | |||
881 | brw_dp_READ_4_vs(p, | ||
882 | const2_reg, /* writeback dest */ | ||
883 | 1, /* oword */ | ||
884 | relAddr, /* relative indexing? */ | ||
885 | addrReg, /* address register */ | ||
886 | 16 * index, /* byte offset */ | ||
887 | SURF_INDEX_VERT_CONST_BUFFER | ||
888 | ); | ||
889 | } | ||
890 | } | ||
891 | |||
892 | const_reg = c->current_const[argIndex].reg; | ||
893 | |||
894 | if (relAddr) { | ||
895 | /* merge the two Owords into the constant register */ | ||
896 | /* const_reg[7..4] = const2_reg[7..4] */ | ||
897 | brw_MOV(p, | ||
898 | suboffset(stride(const_reg, 0, 4, 1), 4), | ||
899 | suboffset(stride(const2_reg, 0, 4, 1), 4)); | ||
900 | release_tmp(c, const2_reg); | ||
901 | } | ||
902 | else { | ||
903 | /* replicate lower four floats into upper half (to get XYZWXYZW) */ | ||
904 | const_reg = stride(const_reg, 0, 4, 0); | ||
905 | const_reg.subnr = 0; | ||
906 | } | ||
907 | |||
908 | return const_reg; | ||
909 | } | ||
910 | |||
911 | |||
912 | #if 0 | ||
913 | |||
914 | /* TODO: relative addressing! | ||
915 | */ | ||
916 | static struct brw_reg get_reg( struct brw_vs_compile *c, | ||
917 | enum tgsi_file_type file, | ||
918 | GLuint index ) | ||
919 | { | ||
920 | switch (file) { | ||
921 | case TGSI_FILE_TEMPORARY: | ||
922 | case TGSI_FILE_INPUT: | ||
923 | case TGSI_FILE_OUTPUT: | ||
924 | case TGSI_FILE_CONSTANT: | ||
925 | assert(c->regs[file][index].nr != 0); | ||
926 | return c->regs[file][index]; | ||
927 | |||
928 | case TGSI_FILE_ADDRESS: | ||
929 | assert(index == 0); | ||
930 | return c->regs[file][index]; | ||
931 | |||
932 | case TGSI_FILE_NULL: /* undef values */ | ||
933 | return brw_null_reg(); | ||
934 | |||
935 | default: | ||
936 | assert(0); | ||
937 | return brw_null_reg(); | ||
938 | } | ||
939 | } | ||
940 | |||
941 | #endif | ||
942 | |||
943 | |||
944 | /** | ||
945 | * Indirect addressing: get reg[[arg] + offset]. | ||
946 | */ | ||
947 | static struct brw_reg deref( struct brw_vs_compile *c, | ||
948 | struct brw_reg arg, | ||
949 | GLint offset) | ||
950 | { | ||
951 | struct brw_compile *p = &c->func; | ||
952 | struct brw_reg tmp = vec4(get_tmp(c)); | ||
953 | struct brw_reg addr_reg = c->regs[TGSI_FILE_ADDRESS][0]; | ||
954 | struct brw_reg vp_address = retype(vec1(addr_reg), BRW_REGISTER_TYPE_UW); | ||
955 | GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * 16; | ||
956 | struct brw_reg indirect = brw_vec4_indirect(0,0); | ||
957 | |||
958 | { | ||
959 | brw_push_insn_state(p); | ||
960 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
961 | |||
962 | /* This is pretty clunky - load the address register twice and | ||
963 | * fetch each 4-dword value in turn. There must be a way to do | ||
964 | * this in a single pass, but I couldn't get it to work. | ||
965 | */ | ||
966 | brw_ADD(p, brw_address_reg(0), vp_address, brw_imm_d(byte_offset)); | ||
967 | brw_MOV(p, tmp, indirect); | ||
968 | |||
969 | brw_ADD(p, brw_address_reg(0), suboffset(vp_address, 8), brw_imm_d(byte_offset)); | ||
970 | brw_MOV(p, suboffset(tmp, 4), indirect); | ||
971 | |||
972 | brw_pop_insn_state(p); | ||
973 | } | ||
974 | |||
975 | /* NOTE: tmp not released */ | ||
976 | return vec8(tmp); | ||
977 | } | ||
978 | |||
979 | |||
980 | /** | ||
981 | * Get brw reg corresponding to the instruction's [argIndex] src reg. | ||
982 | * TODO: relative addressing! | ||
983 | */ | ||
984 | static struct brw_reg | ||
985 | get_src_reg( struct brw_vs_compile *c, | ||
986 | GLuint argIndex, | ||
987 | GLuint file, | ||
988 | GLint index, | ||
989 | GLboolean relAddr ) | ||
990 | { | ||
991 | |||
992 | switch (file) { | ||
993 | case TGSI_FILE_TEMPORARY: | ||
994 | case TGSI_FILE_INPUT: | ||
995 | case TGSI_FILE_OUTPUT: | ||
996 | if (relAddr) { | ||
997 | return deref(c, c->regs[file][0], index); | ||
998 | } | ||
999 | else { | ||
1000 | assert(c->regs[file][index].nr != 0); | ||
1001 | return c->regs[file][index]; | ||
1002 | } | ||
1003 | |||
1004 | case TGSI_FILE_IMMEDIATE: | ||
1005 | return c->regs[file][index]; | ||
1006 | |||
1007 | case TGSI_FILE_CONSTANT: | ||
1008 | if (c->vp->use_const_buffer) { | ||
1009 | return get_constant(c, argIndex, index, relAddr); | ||
1010 | } | ||
1011 | else if (relAddr) { | ||
1012 | return deref(c, c->regs[TGSI_FILE_CONSTANT][0], index); | ||
1013 | } | ||
1014 | else { | ||
1015 | assert(c->regs[TGSI_FILE_CONSTANT][index].nr != 0); | ||
1016 | return c->regs[TGSI_FILE_CONSTANT][index]; | ||
1017 | } | ||
1018 | case TGSI_FILE_ADDRESS: | ||
1019 | assert(index == 0); | ||
1020 | return c->regs[file][index]; | ||
1021 | |||
1022 | case TGSI_FILE_NULL: | ||
1023 | /* this is a normal case since we loop over all three src args */ | ||
1024 | return brw_null_reg(); | ||
1025 | |||
1026 | default: | ||
1027 | assert(0); | ||
1028 | return brw_null_reg(); | ||
1029 | } | ||
1030 | } | ||
1031 | |||
1032 | |||
1033 | static void emit_arl( struct brw_vs_compile *c, | ||
1034 | struct brw_reg dst, | ||
1035 | struct brw_reg arg0 ) | ||
1036 | { | ||
1037 | struct brw_compile *p = &c->func; | ||
1038 | struct brw_reg tmp = dst; | ||
1039 | GLboolean need_tmp = (dst.file != BRW_GENERAL_REGISTER_FILE); | ||
1040 | |||
1041 | if (need_tmp) | ||
1042 | tmp = get_tmp(c); | ||
1043 | |||
1044 | brw_RNDD(p, tmp, arg0); /* tmp = round(arg0) */ | ||
1045 | brw_MUL(p, dst, tmp, brw_imm_d(16)); /* dst = tmp * 16 */ | ||
1046 | |||
1047 | if (need_tmp) | ||
1048 | release_tmp(c, tmp); | ||
1049 | } | ||
1050 | |||
1051 | |||
1052 | /** | ||
1053 | * Return the brw reg for the given instruction's src argument. | ||
1054 | */ | ||
1055 | static struct brw_reg get_arg( struct brw_vs_compile *c, | ||
1056 | const struct tgsi_full_src_register *src, | ||
1057 | GLuint argIndex ) | ||
1058 | { | ||
1059 | struct brw_reg reg; | ||
1060 | |||
1061 | if (src->Register.File == TGSI_FILE_NULL) | ||
1062 | return brw_null_reg(); | ||
1063 | |||
1064 | reg = get_src_reg(c, argIndex, | ||
1065 | src->Register.File, | ||
1066 | src->Register.Index, | ||
1067 | src->Register.Indirect); | ||
1068 | |||
1069 | /* Convert 3-bit swizzle to 2-bit. | ||
1070 | */ | ||
1071 | reg.dw1.bits.swizzle = BRW_SWIZZLE4(src->Register.SwizzleX, | ||
1072 | src->Register.SwizzleY, | ||
1073 | src->Register.SwizzleZ, | ||
1074 | src->Register.SwizzleW); | ||
1075 | |||
1076 | reg.negate = src->Register.Negate ? 1 : 0; | ||
1077 | |||
1078 | /* XXX: abs, absneg | ||
1079 | */ | ||
1080 | |||
1081 | return reg; | ||
1082 | } | ||
1083 | |||
1084 | |||
1085 | /** | ||
1086 | * Get brw register for the given program dest register. | ||
1087 | */ | ||
1088 | static struct brw_reg get_dst( struct brw_vs_compile *c, | ||
1089 | unsigned file, | ||
1090 | unsigned index, | ||
1091 | unsigned writemask ) | ||
1092 | { | ||
1093 | struct brw_reg reg; | ||
1094 | |||
1095 | switch (file) { | ||
1096 | case TGSI_FILE_TEMPORARY: | ||
1097 | case TGSI_FILE_OUTPUT: | ||
1098 | assert(c->regs[file][index].nr != 0); | ||
1099 | reg = c->regs[file][index]; | ||
1100 | break; | ||
1101 | case TGSI_FILE_ADDRESS: | ||
1102 | assert(index == 0); | ||
1103 | reg = c->regs[file][index]; | ||
1104 | break; | ||
1105 | case TGSI_FILE_NULL: | ||
1106 | /* we may hit this for OPCODE_END, OPCODE_KIL, etc */ | ||
1107 | reg = brw_null_reg(); | ||
1108 | break; | ||
1109 | default: | ||
1110 | assert(0); | ||
1111 | reg = brw_null_reg(); | ||
1112 | } | ||
1113 | |||
1114 | reg.dw1.bits.writemask = writemask; | ||
1115 | |||
1116 | return reg; | ||
1117 | } | ||
1118 | |||
1119 | |||
1120 | |||
1121 | |||
1122 | /** | ||
1123 | * Post-vertex-program processing. Send the results to the URB. | ||
1124 | */ | ||
1125 | static void emit_vertex_write( struct brw_vs_compile *c) | ||
1126 | { | ||
1127 | struct brw_compile *p = &c->func; | ||
1128 | struct brw_context *brw = p->brw; | ||
1129 | struct brw_reg m0 = brw_message_reg(0); | ||
1130 | struct brw_reg pos = c->regs[TGSI_FILE_OUTPUT][VERT_RESULT_HPOS]; | ||
1131 | struct brw_reg ndc; | ||
1132 | int eot; | ||
1133 | int i; | ||
1134 | GLuint len_vertext_header = 2; | ||
1135 | |||
1136 | /* Build ndc coords */ | ||
1137 | ndc = get_tmp(c); | ||
1138 | /* ndc = 1.0 / pos.w */ | ||
1139 | emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL); | ||
1140 | /* ndc.xyz = pos * ndc */ | ||
1141 | brw_MUL(p, brw_writemask(ndc, BRW_WRITEMASK_XYZ), pos, ndc); | ||
1142 | |||
1143 | /* Update the header for point size, user clipping flags, and -ve rhw | ||
1144 | * workaround. | ||
1145 | */ | ||
1146 | if (c->prog_data.writes_psiz || | ||
1147 | c->key.nr_userclip || | ||
1148 | brw->has_negative_rhw_bug) | ||
1149 | { | ||
1150 | struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); | ||
1151 | GLuint i; | ||
1152 | |||
1153 | brw_MOV(p, header1, brw_imm_ud(0)); | ||
1154 | |||
1155 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1156 | |||
1157 | if (c->prog_data.writes_psiz) { | ||
1158 | struct brw_reg psiz = c->regs[TGSI_FILE_OUTPUT][VERT_RESULT_PSIZ]; | ||
1159 | brw_MUL(p, brw_writemask(header1, BRW_WRITEMASK_W), brw_swizzle1(psiz, 0), brw_imm_f(1<<11)); | ||
1160 | brw_AND(p, brw_writemask(header1, BRW_WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8)); | ||
1161 | } | ||
1162 | |||
1163 | for (i = 0; i < c->key.nr_userclip; i++) { | ||
1164 | brw_set_conditionalmod(p, BRW_CONDITIONAL_L); | ||
1165 | brw_DP4(p, brw_null_reg(), pos, c->userplane[i]); | ||
1166 | brw_OR(p, brw_writemask(header1, BRW_WRITEMASK_W), header1, brw_imm_ud(1<<i)); | ||
1167 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1168 | } | ||
1169 | |||
1170 | /* i965 clipping workaround: | ||
1171 | * 1) Test for -ve rhw | ||
1172 | * 2) If set, | ||
1173 | * set ndc = (0,0,0,0) | ||
1174 | * set ucp[6] = 1 | ||
1175 | * | ||
1176 | * Later, clipping will detect ucp[6] and ensure the primitive is | ||
1177 | * clipped against all fixed planes. | ||
1178 | */ | ||
1179 | if (brw->has_negative_rhw_bug) { | ||
1180 | brw_CMP(p, | ||
1181 | vec8(brw_null_reg()), | ||
1182 | BRW_CONDITIONAL_L, | ||
1183 | brw_swizzle1(ndc, 3), | ||
1184 | brw_imm_f(0)); | ||
1185 | |||
1186 | brw_OR(p, brw_writemask(header1, BRW_WRITEMASK_W), header1, brw_imm_ud(1<<6)); | ||
1187 | brw_MOV(p, ndc, brw_imm_f(0)); | ||
1188 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1189 | } | ||
1190 | |||
1191 | brw_set_access_mode(p, BRW_ALIGN_1); /* why? */ | ||
1192 | brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), header1); | ||
1193 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1194 | |||
1195 | release_tmp(c, header1); | ||
1196 | } | ||
1197 | else { | ||
1198 | brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), brw_imm_ud(0)); | ||
1199 | } | ||
1200 | |||
1201 | /* Emit the (interleaved) headers for the two vertices - an 8-reg | ||
1202 | * of zeros followed by two sets of NDC coordinates: | ||
1203 | */ | ||
1204 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
1205 | brw_MOV(p, offset(m0, 2), ndc); | ||
1206 | |||
1207 | if (brw->gen == 5) { | ||
1208 | /* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */ | ||
1209 | brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */ | ||
1210 | /* m4, m5 contain the distances from vertex to the user clip planeXXX. | ||
1211 | * Seems it is useless for us. | ||
1212 | * m6 is used for aligning, so that the remainder of vertex element is | ||
1213 | * reg-aligned. | ||
1214 | */ | ||
1215 | brw_MOV(p, offset(m0, 7), pos); /* the remainder of vertex element */ | ||
1216 | len_vertext_header = 6; | ||
1217 | } else { | ||
1218 | brw_MOV(p, offset(m0, 3), pos); | ||
1219 | len_vertext_header = 2; | ||
1220 | } | ||
1221 | |||
1222 | eot = (c->overflow_count == 0); | ||
1223 | |||
1224 | brw_urb_WRITE(p, | ||
1225 | brw_null_reg(), /* dest */ | ||
1226 | 0, /* starting mrf reg nr */ | ||
1227 | c->r0, /* src */ | ||
1228 | 0, /* allocate */ | ||
1229 | 1, /* used */ | ||
1230 | MIN2(c->nr_outputs + 1 + len_vertext_header, (BRW_MAX_MRF-1)), /* msg len */ | ||
1231 | 0, /* response len */ | ||
1232 | eot, /* eot */ | ||
1233 | eot, /* writes complete */ | ||
1234 | 0, /* urb destination offset */ | ||
1235 | BRW_URB_SWIZZLE_INTERLEAVE); | ||
1236 | |||
1237 | /* Not all of the vertex outputs/results fit into the MRF. | ||
1238 | * Move the overflowed attributes from the GRF to the MRF and | ||
1239 | * issue another brw_urb_WRITE(). | ||
1240 | */ | ||
1241 | for (i = 0; i < c->overflow_count; i += BRW_MAX_MRF) { | ||
1242 | unsigned nr = MIN2(c->overflow_count - i, BRW_MAX_MRF); | ||
1243 | GLuint j; | ||
1244 | |||
1245 | eot = (i + nr >= c->overflow_count); | ||
1246 | |||
1247 | /* XXX I'm not 100% sure about which MRF regs to use here. Starting | ||
1248 | * at mrf[4] atm... | ||
1249 | */ | ||
1250 | for (j = 0; j < nr; j++) { | ||
1251 | brw_MOV(p, brw_message_reg(4+j), | ||
1252 | brw_vec8_grf(c->overflow_grf_start + i + j, 0)); | ||
1253 | } | ||
1254 | |||
1255 | brw_urb_WRITE(p, | ||
1256 | brw_null_reg(), /* dest */ | ||
1257 | 4, /* starting mrf reg nr */ | ||
1258 | c->r0, /* src */ | ||
1259 | 0, /* allocate */ | ||
1260 | 1, /* used */ | ||
1261 | nr+1, /* msg len */ | ||
1262 | 0, /* response len */ | ||
1263 | eot, /* eot */ | ||
1264 | eot, /* writes complete */ | ||
1265 | i-1, /* urb destination offset */ | ||
1266 | BRW_URB_SWIZZLE_INTERLEAVE); | ||
1267 | } | ||
1268 | } | ||
1269 | |||
1270 | |||
1271 | /** | ||
1272 | * Called after code generation to resolve subroutine calls and the | ||
1273 | * END instruction. | ||
1274 | * \param end_inst points to brw code for END instruction | ||
1275 | * \param last_inst points to last instruction emitted before vertex write | ||
1276 | */ | ||
1277 | static void | ||
1278 | post_vs_emit( struct brw_vs_compile *c, | ||
1279 | struct brw_instruction *end_inst, | ||
1280 | struct brw_instruction *last_inst ) | ||
1281 | { | ||
1282 | GLint offset; | ||
1283 | |||
1284 | brw_resolve_cals(&c->func); | ||
1285 | |||
1286 | /* patch up the END code to jump past subroutines, etc */ | ||
1287 | offset = last_inst - end_inst; | ||
1288 | if (offset > 1) { | ||
1289 | brw_set_src1(end_inst, brw_imm_d(offset * 16)); | ||
1290 | } else { | ||
1291 | end_inst->header.opcode = BRW_OPCODE_NOP; | ||
1292 | } | ||
1293 | } | ||
1294 | |||
1295 | static uint32_t | ||
1296 | get_predicate(const struct tgsi_full_instruction *inst) | ||
1297 | { | ||
1298 | /* XXX: disabling for now | ||
1299 | */ | ||
1300 | #if 0 | ||
1301 | if (inst->dst.CondMask == COND_TR) | ||
1302 | return BRW_PREDICATE_NONE; | ||
1303 | |||
1304 | /* All of GLSL only produces predicates for COND_NE and one channel per | ||
1305 | * vector. Fail badly if someone starts doing something else, as it might | ||
1306 | * mean infinite looping or something. | ||
1307 | * | ||
1308 | * We'd like to support all the condition codes, but our hardware doesn't | ||
1309 | * quite match the Mesa IR, which is modeled after the NV extensions. For | ||
1310 | * those, the instruction may update the condition codes or not, then any | ||
1311 | * later instruction may use one of those condition codes. For gen4, the | ||
1312 | * instruction may update the flags register based on one of the condition | ||
1313 | * codes output by the instruction, and then further instructions may | ||
1314 | * predicate on that. We can probably support this, but it won't | ||
1315 | * necessarily be easy. | ||
1316 | */ | ||
1317 | /* assert(inst->dst.CondMask == COND_NE); */ | ||
1318 | |||
1319 | switch (inst->dst.CondSwizzle) { | ||
1320 | case SWIZZLE_XXXX: | ||
1321 | return BRW_PREDICATE_ALIGN16_REPLICATE_X; | ||
1322 | case SWIZZLE_YYYY: | ||
1323 | return BRW_PREDICATE_ALIGN16_REPLICATE_Y; | ||
1324 | case SWIZZLE_ZZZZ: | ||
1325 | return BRW_PREDICATE_ALIGN16_REPLICATE_Z; | ||
1326 | case SWIZZLE_WWWW: | ||
1327 | return BRW_PREDICATE_ALIGN16_REPLICATE_W; | ||
1328 | default: | ||
1329 | debug_printf("Unexpected predicate: 0x%08x\n", | ||
1330 | inst->dst.CondMask); | ||
1331 | return BRW_PREDICATE_NORMAL; | ||
1332 | } | ||
1333 | #else | ||
1334 | return BRW_PREDICATE_NORMAL; | ||
1335 | #endif | ||
1336 | } | ||
1337 | |||
1338 | static void emit_insn(struct brw_vs_compile *c, | ||
1339 | const struct tgsi_full_instruction *inst) | ||
1340 | { | ||
1341 | unsigned opcode = inst->Instruction.Opcode; | ||
1342 | unsigned label = inst->Label.Label; | ||
1343 | struct brw_compile *p = &c->func; | ||
1344 | struct brw_context *brw = p->brw; | ||
1345 | struct brw_reg args[3], dst; | ||
1346 | GLuint i; | ||
1347 | |||
1348 | #if 0 | ||
1349 | printf("%d: ", insn); | ||
1350 | _mesa_print_instruction(inst); | ||
1351 | #endif | ||
1352 | |||
1353 | /* Get argument regs. | ||
1354 | */ | ||
1355 | for (i = 0; i < 3; i++) { | ||
1356 | args[i] = get_arg(c, &inst->Src[i], i); | ||
1357 | } | ||
1358 | |||
1359 | /* Get dest regs. Note that it is possible for a reg to be both | ||
1360 | * dst and arg, given the static allocation of registers. So | ||
1361 | * care needs to be taken emitting multi-operation instructions. | ||
1362 | */ | ||
1363 | dst = get_dst(c, | ||
1364 | inst->Dst[0].Register.File, | ||
1365 | inst->Dst[0].Register.Index, | ||
1366 | inst->Dst[0].Register.WriteMask); | ||
1367 | |||
1368 | /* XXX: saturate | ||
1369 | */ | ||
1370 | if (inst->Instruction.Saturate != TGSI_SAT_NONE) { | ||
1371 | debug_printf("Unsupported saturate in vertex shader"); | ||
1372 | } | ||
1373 | |||
1374 | switch (opcode) { | ||
1375 | case TGSI_OPCODE_ABS: | ||
1376 | brw_MOV(p, dst, brw_abs(args[0])); | ||
1377 | break; | ||
1378 | case TGSI_OPCODE_ADD: | ||
1379 | brw_ADD(p, dst, args[0], args[1]); | ||
1380 | break; | ||
1381 | case TGSI_OPCODE_COS: | ||
1382 | emit_math1(c, BRW_MATH_FUNCTION_COS, dst, args[0], BRW_MATH_PRECISION_FULL); | ||
1383 | break; | ||
1384 | case TGSI_OPCODE_DP3: | ||
1385 | brw_DP3(p, dst, args[0], args[1]); | ||
1386 | break; | ||
1387 | case TGSI_OPCODE_DP4: | ||
1388 | brw_DP4(p, dst, args[0], args[1]); | ||
1389 | break; | ||
1390 | case TGSI_OPCODE_DPH: | ||
1391 | brw_DPH(p, dst, args[0], args[1]); | ||
1392 | break; | ||
1393 | case TGSI_OPCODE_NRM: | ||
1394 | emit_nrm(c, dst, args[0], 3); | ||
1395 | break; | ||
1396 | case TGSI_OPCODE_NRM4: | ||
1397 | emit_nrm(c, dst, args[0], 4); | ||
1398 | break; | ||
1399 | case TGSI_OPCODE_DST: | ||
1400 | unalias2(c, dst, args[0], args[1], emit_dst_noalias); | ||
1401 | break; | ||
1402 | case TGSI_OPCODE_EXP: | ||
1403 | unalias1(c, dst, args[0], emit_exp_noalias); | ||
1404 | break; | ||
1405 | case TGSI_OPCODE_EX2: | ||
1406 | emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, args[0], BRW_MATH_PRECISION_FULL); | ||
1407 | break; | ||
1408 | case TGSI_OPCODE_ARL: | ||
1409 | emit_arl(c, dst, args[0]); | ||
1410 | break; | ||
1411 | case TGSI_OPCODE_FLR: | ||
1412 | brw_RNDD(p, dst, args[0]); | ||
1413 | break; | ||
1414 | case TGSI_OPCODE_FRC: | ||
1415 | brw_FRC(p, dst, args[0]); | ||
1416 | break; | ||
1417 | case TGSI_OPCODE_LOG: | ||
1418 | unalias1(c, dst, args[0], emit_log_noalias); | ||
1419 | break; | ||
1420 | case TGSI_OPCODE_LG2: | ||
1421 | emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, args[0], BRW_MATH_PRECISION_FULL); | ||
1422 | break; | ||
1423 | case TGSI_OPCODE_LIT: | ||
1424 | unalias1(c, dst, args[0], emit_lit_noalias); | ||
1425 | break; | ||
1426 | case TGSI_OPCODE_LRP: | ||
1427 | unalias3(c, dst, args[0], args[1], args[2], emit_lrp_noalias); | ||
1428 | break; | ||
1429 | case TGSI_OPCODE_MAD: | ||
1430 | brw_MOV(p, brw_acc_reg(), args[2]); | ||
1431 | brw_MAC(p, dst, args[0], args[1]); | ||
1432 | break; | ||
1433 | case TGSI_OPCODE_MAX: | ||
1434 | emit_max(p, dst, args[0], args[1]); | ||
1435 | break; | ||
1436 | case TGSI_OPCODE_MIN: | ||
1437 | emit_min(p, dst, args[0], args[1]); | ||
1438 | break; | ||
1439 | case TGSI_OPCODE_MOV: | ||
1440 | brw_MOV(p, dst, args[0]); | ||
1441 | break; | ||
1442 | case TGSI_OPCODE_MUL: | ||
1443 | brw_MUL(p, dst, args[0], args[1]); | ||
1444 | break; | ||
1445 | case TGSI_OPCODE_POW: | ||
1446 | emit_math2(c, BRW_MATH_FUNCTION_POW, dst, args[0], args[1], BRW_MATH_PRECISION_FULL); | ||
1447 | break; | ||
1448 | case TGSI_OPCODE_RCP: | ||
1449 | emit_math1(c, BRW_MATH_FUNCTION_INV, dst, args[0], BRW_MATH_PRECISION_FULL); | ||
1450 | break; | ||
1451 | case TGSI_OPCODE_RSQ: | ||
1452 | emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, | ||
1453 | brw_swizzle(args[0], 0,0,0,0), BRW_MATH_PRECISION_FULL); | ||
1454 | break; | ||
1455 | case TGSI_OPCODE_SEQ: | ||
1456 | emit_seq(p, dst, args[0], args[1]); | ||
1457 | break; | ||
1458 | case TGSI_OPCODE_SIN: | ||
1459 | emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, args[0], BRW_MATH_PRECISION_FULL); | ||
1460 | break; | ||
1461 | case TGSI_OPCODE_SNE: | ||
1462 | emit_sne(p, dst, args[0], args[1]); | ||
1463 | break; | ||
1464 | case TGSI_OPCODE_SGE: | ||
1465 | emit_sge(p, dst, args[0], args[1]); | ||
1466 | break; | ||
1467 | case TGSI_OPCODE_SGT: | ||
1468 | emit_sgt(p, dst, args[0], args[1]); | ||
1469 | break; | ||
1470 | case TGSI_OPCODE_SLT: | ||
1471 | emit_slt(p, dst, args[0], args[1]); | ||
1472 | break; | ||
1473 | case TGSI_OPCODE_SLE: | ||
1474 | emit_sle(p, dst, args[0], args[1]); | ||
1475 | break; | ||
1476 | case TGSI_OPCODE_SUB: | ||
1477 | brw_ADD(p, dst, args[0], negate(args[1])); | ||
1478 | break; | ||
1479 | case TGSI_OPCODE_TRUNC: | ||
1480 | /* round toward zero */ | ||
1481 | brw_RNDZ(p, dst, args[0]); | ||
1482 | break; | ||
1483 | case TGSI_OPCODE_XPD: | ||
1484 | emit_xpd(p, dst, args[0], args[1]); | ||
1485 | break; | ||
1486 | case TGSI_OPCODE_IF: | ||
1487 | assert(c->if_depth < MAX_IF_DEPTH); | ||
1488 | c->if_inst[c->if_depth] = brw_IF(p, BRW_EXECUTE_8); | ||
1489 | /* Note that brw_IF smashes the predicate_control field. */ | ||
1490 | c->if_inst[c->if_depth]->header.predicate_control = get_predicate(inst); | ||
1491 | c->if_depth++; | ||
1492 | break; | ||
1493 | case TGSI_OPCODE_ELSE: | ||
1494 | c->if_inst[c->if_depth-1] = brw_ELSE(p, c->if_inst[c->if_depth-1]); | ||
1495 | break; | ||
1496 | case TGSI_OPCODE_ENDIF: | ||
1497 | assert(c->if_depth > 0); | ||
1498 | brw_ENDIF(p, c->if_inst[--c->if_depth]); | ||
1499 | break; | ||
1500 | case TGSI_OPCODE_BGNLOOP: | ||
1501 | c->loop_inst[c->loop_depth++] = brw_DO(p, BRW_EXECUTE_8); | ||
1502 | break; | ||
1503 | case TGSI_OPCODE_BRK: | ||
1504 | brw_set_predicate_control(p, get_predicate(inst)); | ||
1505 | brw_BREAK(p); | ||
1506 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1507 | break; | ||
1508 | case TGSI_OPCODE_CONT: | ||
1509 | brw_set_predicate_control(p, get_predicate(inst)); | ||
1510 | brw_CONT(p); | ||
1511 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1512 | break; | ||
1513 | case TGSI_OPCODE_ENDLOOP: | ||
1514 | { | ||
1515 | struct brw_instruction *inst0, *inst1; | ||
1516 | GLuint br = 1; | ||
1517 | |||
1518 | c->loop_depth--; | ||
1519 | |||
1520 | if (brw->gen == 5) | ||
1521 | br = 2; | ||
1522 | |||
1523 | inst0 = inst1 = brw_WHILE(p, c->loop_inst[c->loop_depth]); | ||
1524 | /* patch all the BREAK/CONT instructions from last BEGINLOOP */ | ||
1525 | while (inst0 > c->loop_inst[c->loop_depth]) { | ||
1526 | inst0--; | ||
1527 | if (inst0->header.opcode == TGSI_OPCODE_BRK) { | ||
1528 | inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); | ||
1529 | inst0->bits3.if_else.pop_count = 0; | ||
1530 | } | ||
1531 | else if (inst0->header.opcode == TGSI_OPCODE_CONT) { | ||
1532 | inst0->bits3.if_else.jump_count = br * (inst1 - inst0); | ||
1533 | inst0->bits3.if_else.pop_count = 0; | ||
1534 | } | ||
1535 | } | ||
1536 | } | ||
1537 | break; | ||
1538 | case TGSI_OPCODE_BRA: | ||
1539 | brw_set_predicate_control(p, get_predicate(inst)); | ||
1540 | brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); | ||
1541 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1542 | break; | ||
1543 | case TGSI_OPCODE_CAL: | ||
1544 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
1545 | brw_ADD(p, deref_1d(c->stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); | ||
1546 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1547 | brw_ADD(p, get_addr_reg(c->stack_index), | ||
1548 | get_addr_reg(c->stack_index), brw_imm_d(4)); | ||
1549 | brw_save_call(p, label, p->nr_insn); | ||
1550 | brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); | ||
1551 | break; | ||
1552 | case TGSI_OPCODE_RET: | ||
1553 | brw_ADD(p, get_addr_reg(c->stack_index), | ||
1554 | get_addr_reg(c->stack_index), brw_imm_d(-4)); | ||
1555 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
1556 | brw_MOV(p, brw_ip_reg(), deref_1d(c->stack_index, 0)); | ||
1557 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1558 | break; | ||
1559 | case TGSI_OPCODE_END: | ||
1560 | c->end_offset = p->nr_insn; | ||
1561 | /* this instruction will get patched later to jump past subroutine | ||
1562 | * code, etc. | ||
1563 | */ | ||
1564 | brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); | ||
1565 | break; | ||
1566 | case TGSI_OPCODE_BGNSUB: | ||
1567 | brw_save_label(p, p->nr_insn, p->nr_insn); | ||
1568 | break; | ||
1569 | case TGSI_OPCODE_ENDSUB: | ||
1570 | /* no-op */ | ||
1571 | break; | ||
1572 | default: | ||
1573 | debug_printf("Unsupported opcode %i (%s) in vertex shader", | ||
1574 | opcode, | ||
1575 | tgsi_get_opcode_name(opcode)); | ||
1576 | } | ||
1577 | |||
1578 | /* Set the predication update on the last instruction of the native | ||
1579 | * instruction sequence. | ||
1580 | * | ||
1581 | * This would be problematic if it was set on a math instruction, | ||
1582 | * but that shouldn't be the case with the current GLSL compiler. | ||
1583 | */ | ||
1584 | #if 0 | ||
1585 | /* XXX: disabled | ||
1586 | */ | ||
1587 | if (inst->CondUpdate) { | ||
1588 | struct brw_instruction *hw_insn = &p->store[p->nr_insn - 1]; | ||
1589 | |||
1590 | assert(hw_insn->header.destreg__conditionalmod == 0); | ||
1591 | hw_insn->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; | ||
1592 | } | ||
1593 | #endif | ||
1594 | |||
1595 | release_tmps(c); | ||
1596 | } | ||
1597 | |||
1598 | |||
1599 | /* Emit the vertex program instructions here. | ||
1600 | */ | ||
1601 | void brw_vs_emit(struct brw_vs_compile *c) | ||
1602 | { | ||
1603 | struct brw_compile *p = &c->func; | ||
1604 | const struct tgsi_token *tokens = c->vp->tokens; | ||
1605 | struct brw_instruction *end_inst, *last_inst; | ||
1606 | struct tgsi_parse_context parse; | ||
1607 | struct tgsi_full_instruction *inst; | ||
1608 | |||
1609 | if (BRW_DEBUG & DEBUG_VS) | ||
1610 | tgsi_dump(c->vp->tokens, 0); | ||
1611 | |||
1612 | c->stack_index = brw_indirect(0, 0); | ||
1613 | |||
1614 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1615 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1616 | |||
1617 | |||
1618 | /* Static register allocation | ||
1619 | */ | ||
1620 | brw_vs_alloc_regs(c); | ||
1621 | |||
1622 | if (c->vp->has_flow_control) { | ||
1623 | brw_MOV(p, get_addr_reg(c->stack_index), brw_address(c->stack)); | ||
1624 | } | ||
1625 | |||
1626 | /* Instructions | ||
1627 | */ | ||
1628 | tgsi_parse_init( &parse, tokens ); | ||
1629 | while( !tgsi_parse_end_of_tokens( &parse ) ) { | ||
1630 | tgsi_parse_token( &parse ); | ||
1631 | |||
1632 | switch( parse.FullToken.Token.Type ) { | ||
1633 | case TGSI_TOKEN_TYPE_DECLARATION: | ||
1634 | case TGSI_TOKEN_TYPE_IMMEDIATE: | ||
1635 | break; | ||
1636 | |||
1637 | case TGSI_TOKEN_TYPE_INSTRUCTION: | ||
1638 | inst = &parse.FullToken.FullInstruction; | ||
1639 | emit_insn( c, inst ); | ||
1640 | break; | ||
1641 | |||
1642 | default: | ||
1643 | assert( 0 ); | ||
1644 | } | ||
1645 | } | ||
1646 | tgsi_parse_free( &parse ); | ||
1647 | |||
1648 | end_inst = &p->store[c->end_offset]; | ||
1649 | last_inst = &p->store[p->nr_insn]; | ||
1650 | |||
1651 | /* The END instruction will be patched to jump to this code */ | ||
1652 | emit_vertex_write(c); | ||
1653 | |||
1654 | post_vs_emit(c, end_inst, last_inst); | ||
1655 | |||
1656 | if (BRW_DEBUG & DEBUG_VS) { | ||
1657 | debug_printf("vs-native:\n"); | ||
1658 | brw_disasm(stderr, p->store, p->nr_insn, p->brw->gen); | ||
1659 | } | ||
1660 | } | ||
diff --git a/src/gallium/drivers/i965/brw_vs_state.c b/src/gallium/drivers/i965/brw_vs_state.c deleted file mode 100644 index 6d2ccfd6d98..00000000000 --- a/src/gallium/drivers/i965/brw_vs_state.c +++ /dev/null | |||
@@ -1,201 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | |||
34 | |||
35 | #include "brw_debug.h" | ||
36 | #include "brw_context.h" | ||
37 | #include "brw_state.h" | ||
38 | #include "brw_defines.h" | ||
39 | |||
40 | struct brw_vs_unit_key { | ||
41 | unsigned int total_grf; | ||
42 | unsigned int urb_entry_read_length; | ||
43 | unsigned int curb_entry_read_length; | ||
44 | |||
45 | unsigned int curbe_offset; | ||
46 | |||
47 | unsigned int nr_urb_entries, urb_size; | ||
48 | |||
49 | unsigned int nr_surfaces; | ||
50 | }; | ||
51 | |||
52 | static void | ||
53 | vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key) | ||
54 | { | ||
55 | memset(key, 0, sizeof(*key)); | ||
56 | |||
57 | /* CACHE_NEW_VS_PROG */ | ||
58 | key->total_grf = brw->vs.prog_data->total_grf; | ||
59 | key->urb_entry_read_length = brw->vs.prog_data->urb_read_length; | ||
60 | key->curb_entry_read_length = brw->vs.prog_data->curb_read_length; | ||
61 | |||
62 | /* BRW_NEW_URB_FENCE */ | ||
63 | key->nr_urb_entries = brw->urb.nr_vs_entries; | ||
64 | key->urb_size = brw->urb.vsize; | ||
65 | |||
66 | /* BRW_NEW_NR_VS_SURFACES */ | ||
67 | key->nr_surfaces = brw->vs.nr_surfaces; | ||
68 | |||
69 | /* PIPE_NEW_CLIP */ | ||
70 | if (brw->curr.ucp.nr) { | ||
71 | /* Note that we read in the userclip planes as well, hence | ||
72 | * clip_start: | ||
73 | */ | ||
74 | key->curbe_offset = brw->curbe.clip_start; | ||
75 | } | ||
76 | else { | ||
77 | key->curbe_offset = brw->curbe.vs_start; | ||
78 | } | ||
79 | } | ||
80 | |||
81 | static enum pipe_error | ||
82 | vs_unit_create_from_key(struct brw_context *brw, | ||
83 | struct brw_vs_unit_key *key, | ||
84 | struct brw_winsys_reloc *reloc, | ||
85 | struct brw_winsys_buffer **bo_out) | ||
86 | { | ||
87 | enum pipe_error ret; | ||
88 | struct brw_vs_unit_state vs; | ||
89 | int chipset_max_threads; | ||
90 | |||
91 | memset(&vs, 0, sizeof(vs)); | ||
92 | |||
93 | vs.thread0.kernel_start_pointer = 0; /* reloc */ | ||
94 | vs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1; | ||
95 | vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; | ||
96 | /* Choosing multiple program flow means that we may get 2-vertex threads, | ||
97 | * which will have the channel mask for dwords 4-7 enabled in the thread, | ||
98 | * and those dwords will be written to the second URB handle when we | ||
99 | * brw_urb_WRITE() results. | ||
100 | */ | ||
101 | vs.thread1.single_program_flow = 0; | ||
102 | |||
103 | if (brw->gen == 5) | ||
104 | vs.thread1.binding_table_entry_count = 0; /* hardware requirement */ | ||
105 | else | ||
106 | vs.thread1.binding_table_entry_count = key->nr_surfaces; | ||
107 | |||
108 | vs.thread3.urb_entry_read_length = key->urb_entry_read_length; | ||
109 | vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length; | ||
110 | vs.thread3.dispatch_grf_start_reg = 1; | ||
111 | vs.thread3.urb_entry_read_offset = 0; | ||
112 | vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; | ||
113 | |||
114 | if (brw->gen == 5) | ||
115 | vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2; | ||
116 | else | ||
117 | vs.thread4.nr_urb_entries = key->nr_urb_entries; | ||
118 | |||
119 | vs.thread4.urb_entry_allocation_size = key->urb_size - 1; | ||
120 | |||
121 | if (brw->gen == 5) | ||
122 | chipset_max_threads = 72; | ||
123 | else if (brw->is_g4x) | ||
124 | chipset_max_threads = 32; | ||
125 | else | ||
126 | chipset_max_threads = 16; | ||
127 | |||
128 | vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2, | ||
129 | 1, chipset_max_threads) - 1; | ||
130 | |||
131 | if (BRW_DEBUG & DEBUG_SINGLE_THREAD) | ||
132 | vs.thread4.max_threads = 0; | ||
133 | |||
134 | /* No samplers for ARB_vp programs: | ||
135 | */ | ||
136 | /* It has to be set to 0 for IGDNG | ||
137 | */ | ||
138 | vs.vs5.sampler_count = 0; | ||
139 | |||
140 | if (BRW_DEBUG & DEBUG_STATS) | ||
141 | vs.thread4.stats_enable = 1; | ||
142 | |||
143 | /* Vertex program always enabled: | ||
144 | */ | ||
145 | vs.vs6.vs_enable = 1; | ||
146 | |||
147 | ret = brw_upload_cache(&brw->cache, BRW_VS_UNIT, | ||
148 | key, sizeof(*key), | ||
149 | reloc, 1, | ||
150 | &vs, sizeof(vs), | ||
151 | NULL, NULL, | ||
152 | bo_out); | ||
153 | if (ret) | ||
154 | return ret; | ||
155 | |||
156 | return PIPE_OK; | ||
157 | } | ||
158 | |||
159 | static int prepare_vs_unit(struct brw_context *brw) | ||
160 | { | ||
161 | struct brw_vs_unit_key key; | ||
162 | enum pipe_error ret; | ||
163 | struct brw_winsys_reloc reloc[1]; | ||
164 | unsigned grf_reg_count; | ||
165 | |||
166 | vs_unit_populate_key(brw, &key); | ||
167 | |||
168 | grf_reg_count = (align(key.total_grf, 16) / 16 - 1); | ||
169 | |||
170 | /* Emit VS program relocation */ | ||
171 | make_reloc(&reloc[0], | ||
172 | BRW_USAGE_STATE, | ||
173 | grf_reg_count << 1, | ||
174 | offsetof(struct brw_vs_unit_state, thread0), | ||
175 | brw->vs.prog_bo); | ||
176 | |||
177 | |||
178 | if (brw_search_cache(&brw->cache, BRW_VS_UNIT, | ||
179 | &key, sizeof(key), | ||
180 | reloc, 1, | ||
181 | NULL, | ||
182 | &brw->vs.state_bo)) | ||
183 | return PIPE_OK; | ||
184 | |||
185 | ret = vs_unit_create_from_key(brw, &key, reloc, &brw->vs.state_bo); | ||
186 | if (ret) | ||
187 | return ret; | ||
188 | |||
189 | return PIPE_OK; | ||
190 | } | ||
191 | |||
192 | const struct brw_tracked_state brw_vs_unit = { | ||
193 | .dirty = { | ||
194 | .mesa = (PIPE_NEW_CLIP), | ||
195 | .brw = (BRW_NEW_CURBE_OFFSETS | | ||
196 | BRW_NEW_NR_VS_SURFACES | | ||
197 | BRW_NEW_URB_FENCE), | ||
198 | .cache = CACHE_NEW_VS_PROG | ||
199 | }, | ||
200 | .prepare = prepare_vs_unit, | ||
201 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_vs_surface_state.c b/src/gallium/drivers/i965/brw_vs_surface_state.c deleted file mode 100644 index 424bb0d0dfb..00000000000 --- a/src/gallium/drivers/i965/brw_vs_surface_state.c +++ /dev/null | |||
@@ -1,231 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "brw_context.h" | ||
33 | #include "brw_state.h" | ||
34 | #include "brw_winsys.h" | ||
35 | |||
36 | /* XXX: disabled true constant buffer functionality | ||
37 | */ | ||
38 | |||
39 | |||
40 | /* Creates a new VS constant buffer reflecting the current VS program's | ||
41 | * constants, if needed by the VS program. | ||
42 | * | ||
43 | * Otherwise, constants go through the CURBEs using the brw_constant_buffer | ||
44 | * state atom. | ||
45 | */ | ||
46 | #if 0 | ||
47 | static struct brw_winsys_buffer * | ||
48 | brw_vs_update_constant_buffer(struct brw_context *brw) | ||
49 | { | ||
50 | /* XXX: true constant buffers | ||
51 | */ | ||
52 | struct brw_vertex_program *vp = | ||
53 | (struct brw_vertex_program *) brw->vertex_program; | ||
54 | const struct gl_program_parameter_list *params = vp->program.Base.Parameters; | ||
55 | const int size = params->NumParameters * 4 * sizeof(GLfloat); | ||
56 | drm_intel_bo *const_buffer; | ||
57 | |||
58 | /* BRW_NEW_VERTEX_PROGRAM */ | ||
59 | if (!vp->use_const_buffer) | ||
60 | return NULL; | ||
61 | |||
62 | const_buffer = brw->sws->bo_alloc(brw->sws, | ||
63 | BRW_BUFFER_TYPE_SHADER_CONSTANTS, | ||
64 | size, 64); | ||
65 | |||
66 | /* _NEW_PROGRAM_CONSTANTS */ | ||
67 | brw->sws->bo_subdata(const_buffer, 0, size, params->ParameterValues, | ||
68 | NULL, 0); | ||
69 | |||
70 | return const_buffer; | ||
71 | } | ||
72 | #endif | ||
73 | |||
74 | /** | ||
75 | * Update the surface state for a VS constant buffer. | ||
76 | * | ||
77 | * Sets brw->vs.surf_bo[surf] and brw->vp->const_buffer. | ||
78 | */ | ||
79 | #if 0 | ||
80 | static void | ||
81 | brw_update_vs_constant_surface( struct brw_context *brw, | ||
82 | GLuint surf) | ||
83 | { | ||
84 | struct brw_surface_key key; | ||
85 | struct pipe_resource *cb = brw->curr.vs_constants; | ||
86 | enum pipe_error ret; | ||
87 | |||
88 | assert(surf == 0); | ||
89 | |||
90 | /* If we're in this state update atom, we need to update VS constants, so | ||
91 | * free the old buffer and create a new one for the new contents. | ||
92 | */ | ||
93 | ret = brw_vs_update_constant_buffer(brw, &vp->const_buffer); | ||
94 | if (ret) | ||
95 | return ret; | ||
96 | |||
97 | /* If there's no constant buffer, then no surface BO is needed to point at | ||
98 | * it. | ||
99 | */ | ||
100 | if (vp->const_buffer == NULL) { | ||
101 | bo_reference(brw->vs.surf_bo[surf], NULL); | ||
102 | return PIPE_OK; | ||
103 | } | ||
104 | |||
105 | memset(&key, 0, sizeof(key)); | ||
106 | |||
107 | key.format = PIPE_FORMAT_R32G32B32A32_FLOAT; | ||
108 | key.bo = vp->const_buffer; | ||
109 | key.depthmode = GL_NONE; | ||
110 | key.pitch = params->NumParameters; | ||
111 | key.width = params->NumParameters; | ||
112 | key.height = 1; | ||
113 | key.depth = 1; | ||
114 | key.cpp = 16; | ||
115 | |||
116 | /* | ||
117 | printf("%s:\n", __FUNCTION__); | ||
118 | printf(" width %d height %d depth %d cpp %d pitch %d\n", | ||
119 | key.width, key.height, key.depth, key.cpp, key.pitch); | ||
120 | */ | ||
121 | |||
122 | if (brw_search_cache(&brw->surface_cache, | ||
123 | BRW_SS_SURFACE, | ||
124 | &key, sizeof(key), | ||
125 | &key.bo, key.bo ? 1 : 0, | ||
126 | NULL, | ||
127 | &brw->vs.surf_bo[surf])) | ||
128 | return PIPE_OK; | ||
129 | |||
130 | ret = brw_create_constant_surface(brw, &key | ||
131 | &brw->vs.surf_bo[surf]); | ||
132 | if (ret) | ||
133 | return ret; | ||
134 | |||
135 | return PIPE_OK; | ||
136 | } | ||
137 | #endif | ||
138 | |||
139 | |||
140 | /** | ||
141 | * Constructs the binding table for the VS surface state. | ||
142 | */ | ||
143 | static enum pipe_error | ||
144 | brw_vs_get_binding_table(struct brw_context *brw, | ||
145 | struct brw_winsys_buffer **bo_out) | ||
146 | { | ||
147 | #if 0 | ||
148 | static GLuint data[BRW_VS_MAX_SURF]; /* always zero */ | ||
149 | struct brw_winsys_reloc reloc[BRW_VS_MAX_SURF]; | ||
150 | int i; | ||
151 | |||
152 | /* Emit binding table relocations to surface state */ | ||
153 | for (i = 0; i < BRW_VS_MAX_SURF; i++) { | ||
154 | make_reloc(&reloc[i], | ||
155 | BRW_USAGE_STATE, | ||
156 | 0, | ||
157 | i * 4, | ||
158 | brw->vs.surf_bo[i]); | ||
159 | } | ||
160 | |||
161 | ret = brw_cache_data( &brw->surface_cache, | ||
162 | BRW_SS_SURF_BIND, | ||
163 | NULL, 0, | ||
164 | reloc, nr_reloc, | ||
165 | data, sizeof data, | ||
166 | NULL, NULL, | ||
167 | bo_out); | ||
168 | if (ret) | ||
169 | return ret; | ||
170 | |||
171 | FREE(data); | ||
172 | return PIPE_OK; | ||
173 | #else | ||
174 | return PIPE_OK; | ||
175 | #endif | ||
176 | } | ||
177 | |||
178 | /** | ||
179 | * Vertex shader surfaces (constant buffer). | ||
180 | * | ||
181 | * This consumes the state updates for the constant buffer needing | ||
182 | * to be updated, and produces BRW_NEW_NR_VS_SURFACES for the VS unit and | ||
183 | * CACHE_NEW_SURF_BIND for the binding table upload. | ||
184 | */ | ||
185 | static enum pipe_error prepare_vs_surfaces(struct brw_context *brw ) | ||
186 | { | ||
187 | enum pipe_error ret; | ||
188 | |||
189 | #if 0 | ||
190 | int i; | ||
191 | int nr_surfaces = 0; | ||
192 | |||
193 | brw_update_vs_constant_surface(ctx, SURF_INDEX_VERT_CONST_BUFFER); | ||
194 | |||
195 | for (i = 0; i < BRW_VS_MAX_SURF; i++) { | ||
196 | if (brw->vs.surf_bo[i] != NULL) { | ||
197 | nr_surfaces = i + 1; | ||
198 | } | ||
199 | } | ||
200 | |||
201 | if (brw->vs.nr_surfaces != nr_surfaces) { | ||
202 | brw->state.dirty.brw |= BRW_NEW_NR_VS_SURFACES; | ||
203 | brw->vs.nr_surfaces = nr_surfaces; | ||
204 | } | ||
205 | #endif | ||
206 | |||
207 | /* Note that we don't end up updating the bind_bo if we don't have a | ||
208 | * surface to be pointing at. This should be relatively harmless, as it | ||
209 | * just slightly increases our working set size. | ||
210 | */ | ||
211 | if (brw->vs.nr_surfaces != 0) { | ||
212 | ret = brw_vs_get_binding_table(brw, &brw->vs.bind_bo); | ||
213 | if (ret) | ||
214 | return ret; | ||
215 | } | ||
216 | |||
217 | return PIPE_OK; | ||
218 | } | ||
219 | |||
220 | const struct brw_tracked_state brw_vs_surfaces = { | ||
221 | .dirty = { | ||
222 | .mesa = (PIPE_NEW_VERTEX_CONSTANTS | | ||
223 | PIPE_NEW_VERTEX_SHADER), | ||
224 | .brw = 0, | ||
225 | .cache = 0 | ||
226 | }, | ||
227 | .prepare = prepare_vs_surfaces, | ||
228 | }; | ||
229 | |||
230 | |||
231 | |||
diff --git a/src/gallium/drivers/i965/brw_winsys.h b/src/gallium/drivers/i965/brw_winsys.h deleted file mode 100644 index 038f6f788a0..00000000000 --- a/src/gallium/drivers/i965/brw_winsys.h +++ /dev/null | |||
@@ -1,288 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright © 2009 Jakob Bornecrantz | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the "Software"), | ||
7 | * to deal in the Software without restriction, including without limitation | ||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
9 | * and/or sell copies of the Software, and to permit persons to whom the | ||
10 | * Software is furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice (including the next | ||
13 | * paragraph) shall be included in all copies or substantial portions of the | ||
14 | * Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | **************************************************************************/ | ||
25 | |||
26 | #ifndef BRW_WINSYS_H | ||
27 | #define BRW_WINSYS_H | ||
28 | |||
29 | #include "pipe/p_compiler.h" | ||
30 | #include "pipe/p_defines.h" | ||
31 | #include "util/u_inlines.h" | ||
32 | |||
33 | struct brw_winsys; | ||
34 | struct pipe_fence_handle; | ||
35 | |||
36 | /* Not sure why the winsys needs this: | ||
37 | */ | ||
38 | #define BRW_BATCH_SIZE (32*1024) | ||
39 | |||
40 | struct brw_winsys_screen; | ||
41 | |||
42 | /* Need a tiny bit of information inside the abstract buffer struct: | ||
43 | */ | ||
44 | struct brw_winsys_buffer { | ||
45 | struct pipe_reference reference; | ||
46 | struct brw_winsys_screen *sws; | ||
47 | unsigned size; | ||
48 | }; | ||
49 | |||
50 | |||
51 | /* Should be possible to validate usages above against buffer creation | ||
52 | * types, below: | ||
53 | */ | ||
54 | enum brw_buffer_type | ||
55 | { | ||
56 | BRW_BUFFER_TYPE_TEXTURE, | ||
57 | BRW_BUFFER_TYPE_SCANOUT, /**< a texture used for scanning out from */ | ||
58 | BRW_BUFFER_TYPE_VERTEX, | ||
59 | BRW_BUFFER_TYPE_CURBE, | ||
60 | BRW_BUFFER_TYPE_QUERY, | ||
61 | BRW_BUFFER_TYPE_SHADER_CONSTANTS, | ||
62 | BRW_BUFFER_TYPE_SHADER_SCRATCH, | ||
63 | BRW_BUFFER_TYPE_BATCH, | ||
64 | BRW_BUFFER_TYPE_GENERAL_STATE, | ||
65 | BRW_BUFFER_TYPE_SURFACE_STATE, | ||
66 | BRW_BUFFER_TYPE_PIXEL, /* image uploads, pbo's, etc */ | ||
67 | BRW_BUFFER_TYPE_GENERIC, /* unknown */ | ||
68 | BRW_BUFFER_TYPE_MAX /* Count of possible values */ | ||
69 | }; | ||
70 | |||
71 | |||
72 | /* Describe the usage of a particular buffer in a relocation. The DRM | ||
73 | * winsys will translate these back to GEM read/write domain flags. | ||
74 | */ | ||
75 | enum brw_buffer_usage { | ||
76 | BRW_USAGE_STATE, /* INSTRUCTION, 0 */ | ||
77 | BRW_USAGE_QUERY_RESULT, /* INSTRUCTION, INSTRUCTION */ | ||
78 | BRW_USAGE_RENDER_TARGET, /* RENDER, 0 */ | ||
79 | BRW_USAGE_DEPTH_BUFFER, /* RENDER, RENDER */ | ||
80 | BRW_USAGE_BLIT_SOURCE, /* RENDER, 0 */ | ||
81 | BRW_USAGE_BLIT_DEST, /* RENDER, RENDER */ | ||
82 | BRW_USAGE_SAMPLER, /* SAMPLER, 0 */ | ||
83 | BRW_USAGE_VERTEX, /* VERTEX, 0 */ | ||
84 | BRW_USAGE_SCRATCH, /* 0, 0 */ | ||
85 | BRW_USAGE_MAX | ||
86 | }; | ||
87 | |||
88 | enum brw_buffer_data_type { | ||
89 | BRW_DATA_GS_CC_VP, | ||
90 | BRW_DATA_GS_CC_UNIT, | ||
91 | BRW_DATA_GS_WM_PROG, | ||
92 | BRW_DATA_GS_SAMPLER_DEFAULT_COLOR, | ||
93 | BRW_DATA_GS_SAMPLER, | ||
94 | BRW_DATA_GS_WM_UNIT, | ||
95 | BRW_DATA_GS_SF_PROG, | ||
96 | BRW_DATA_GS_SF_VP, | ||
97 | BRW_DATA_GS_SF_UNIT, | ||
98 | BRW_DATA_GS_VS_UNIT, | ||
99 | BRW_DATA_GS_VS_PROG, | ||
100 | BRW_DATA_GS_GS_UNIT, | ||
101 | BRW_DATA_GS_GS_PROG, | ||
102 | BRW_DATA_GS_CLIP_VP, | ||
103 | BRW_DATA_GS_CLIP_UNIT, | ||
104 | BRW_DATA_GS_CLIP_PROG, | ||
105 | BRW_DATA_SS_SURFACE, | ||
106 | BRW_DATA_SS_SURF_BIND, | ||
107 | BRW_DATA_CONSTANT_BUFFER, | ||
108 | BRW_DATA_BATCH_BUFFER, | ||
109 | BRW_DATA_OTHER, | ||
110 | BRW_DATA_MAX | ||
111 | }; | ||
112 | |||
113 | |||
114 | /* Matches the i915_drm definitions: | ||
115 | */ | ||
116 | #define BRW_TILING_NONE 0 | ||
117 | #define BRW_TILING_X 1 | ||
118 | #define BRW_TILING_Y 2 | ||
119 | |||
120 | |||
121 | /* Relocations to be applied with subdata in a call to sws->bo_subdata, below. | ||
122 | * | ||
123 | * Effectively this encodes: | ||
124 | * | ||
125 | * (unsigned *)(subdata + offset) = bo->offset + delta | ||
126 | */ | ||
127 | struct brw_winsys_reloc { | ||
128 | enum brw_buffer_usage usage; /* debug only */ | ||
129 | unsigned delta; | ||
130 | unsigned offset; | ||
131 | struct brw_winsys_buffer *bo; | ||
132 | }; | ||
133 | |||
134 | static INLINE void make_reloc(struct brw_winsys_reloc *reloc, | ||
135 | enum brw_buffer_usage usage, | ||
136 | unsigned delta, | ||
137 | unsigned offset, | ||
138 | struct brw_winsys_buffer *bo) | ||
139 | { | ||
140 | reloc->usage = usage; | ||
141 | reloc->delta = delta; | ||
142 | reloc->offset = offset; | ||
143 | reloc->bo = bo; /* Note - note taking a reference yet */ | ||
144 | } | ||
145 | |||
146 | |||
147 | |||
148 | struct brw_winsys_screen { | ||
149 | |||
150 | unsigned pci_id; | ||
151 | int gen; | ||
152 | /** | ||
153 | * Buffer functions. | ||
154 | */ | ||
155 | |||
156 | /*@{*/ | ||
157 | /** | ||
158 | * Create a buffer. | ||
159 | */ | ||
160 | enum pipe_error (*bo_alloc)(struct brw_winsys_screen *sws, | ||
161 | enum brw_buffer_type type, | ||
162 | unsigned size, | ||
163 | unsigned alignment, | ||
164 | struct brw_winsys_buffer **bo_out); | ||
165 | |||
166 | enum pipe_error (*bo_from_handle)(struct brw_winsys_screen *sws, | ||
167 | struct winsys_handle *whandle, | ||
168 | unsigned *stride, | ||
169 | unsigned *tiling, | ||
170 | struct brw_winsys_buffer **bo_out); | ||
171 | |||
172 | enum pipe_error (*bo_get_handle)(struct brw_winsys_buffer *buffer, | ||
173 | struct winsys_handle *whandle, | ||
174 | unsigned stride); | ||
175 | |||
176 | /* Destroy a buffer when our refcount goes to zero: | ||
177 | */ | ||
178 | void (*bo_destroy)(struct brw_winsys_buffer *buffer); | ||
179 | |||
180 | /* delta -- added to b2->offset, and written into buffer | ||
181 | * offset -- location above value is written to within buffer | ||
182 | */ | ||
183 | enum pipe_error (*bo_emit_reloc)(struct brw_winsys_buffer *buffer, | ||
184 | enum brw_buffer_usage usage, | ||
185 | unsigned delta, | ||
186 | unsigned offset, | ||
187 | struct brw_winsys_buffer *b2); | ||
188 | |||
189 | enum pipe_error (*bo_exec)(struct brw_winsys_buffer *buffer, | ||
190 | unsigned bytes_used); | ||
191 | |||
192 | enum pipe_error (*bo_subdata)(struct brw_winsys_buffer *buffer, | ||
193 | enum brw_buffer_data_type data_type, | ||
194 | size_t offset, | ||
195 | size_t size, | ||
196 | const void *data, | ||
197 | const struct brw_winsys_reloc *reloc, | ||
198 | unsigned nr_reloc ); | ||
199 | |||
200 | boolean (*bo_is_busy)(struct brw_winsys_buffer *buffer); | ||
201 | boolean (*bo_references)(struct brw_winsys_buffer *a, | ||
202 | struct brw_winsys_buffer *b); | ||
203 | |||
204 | /* XXX: couldn't this be handled by returning true/false on | ||
205 | * bo_emit_reloc? | ||
206 | */ | ||
207 | enum pipe_error (*check_aperture_space)(struct brw_winsys_screen *iws, | ||
208 | struct brw_winsys_buffer **buffers, | ||
209 | unsigned count); | ||
210 | |||
211 | /** | ||
212 | * Map a buffer. | ||
213 | */ | ||
214 | void *(*bo_map)(struct brw_winsys_buffer *buffer, | ||
215 | enum brw_buffer_data_type data_type, | ||
216 | unsigned offset, | ||
217 | unsigned length, | ||
218 | boolean write, | ||
219 | boolean discard, | ||
220 | boolean flush_explicit); | ||
221 | |||
222 | void (*bo_flush_range)(struct brw_winsys_buffer *buffer, | ||
223 | unsigned offset, | ||
224 | unsigned length); | ||
225 | |||
226 | /** | ||
227 | * Unmap a buffer. | ||
228 | */ | ||
229 | void (*bo_unmap)(struct brw_winsys_buffer *buffer); | ||
230 | /*@}*/ | ||
231 | |||
232 | |||
233 | /* Wait for buffer to go idle. Similar to map+unmap, but doesn't | ||
234 | * mark buffer contents as dirty. | ||
235 | */ | ||
236 | void (*bo_wait_idle)(struct brw_winsys_buffer *buffer); | ||
237 | |||
238 | /** | ||
239 | * Destroy the winsys. | ||
240 | */ | ||
241 | void (*destroy)(struct brw_winsys_screen *iws); | ||
242 | }; | ||
243 | |||
244 | static INLINE void * | ||
245 | bo_map_read(struct brw_winsys_screen *sws, struct brw_winsys_buffer *buf) | ||
246 | { | ||
247 | return sws->bo_map( buf, | ||
248 | BRW_DATA_OTHER, | ||
249 | 0, buf->size, | ||
250 | FALSE, FALSE, FALSE ); | ||
251 | } | ||
252 | |||
253 | static INLINE void | ||
254 | bo_reference(struct brw_winsys_buffer **ptr, struct brw_winsys_buffer *buf) | ||
255 | { | ||
256 | struct brw_winsys_buffer *old_buf = *ptr; | ||
257 | |||
258 | if (pipe_reference(&(*ptr)->reference, &buf->reference)) | ||
259 | old_buf->sws->bo_destroy(old_buf); | ||
260 | |||
261 | *ptr = buf; | ||
262 | } | ||
263 | |||
264 | |||
265 | |||
266 | /************************************************************************* | ||
267 | * Cooperative dumping between winsys and driver. TODO: make this | ||
268 | * driver-only by wrapping calls to winsys->bo_subdata(). | ||
269 | */ | ||
270 | |||
271 | #ifdef DEBUG | ||
272 | extern int BRW_DUMP; | ||
273 | #else | ||
274 | #define BRW_DUMP 0 | ||
275 | #endif | ||
276 | |||
277 | #define DUMP_ASM 0x1 | ||
278 | #define DUMP_STATE 0x2 | ||
279 | #define DUMP_BATCH 0x4 | ||
280 | |||
281 | void brw_dump_data( unsigned pci_id, | ||
282 | enum brw_buffer_data_type data_type, | ||
283 | unsigned offset, | ||
284 | const void *data, | ||
285 | size_t size, int gen ); | ||
286 | |||
287 | |||
288 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_winsys_debug.c b/src/gallium/drivers/i965/brw_winsys_debug.c deleted file mode 100644 index b66b1cfccb6..00000000000 --- a/src/gallium/drivers/i965/brw_winsys_debug.c +++ /dev/null | |||
@@ -1,87 +0,0 @@ | |||
1 | #include "brw_winsys.h" | ||
2 | #include "brw_disasm.h" | ||
3 | #include "brw_structs_dump.h" | ||
4 | #include "brw_structs.h" | ||
5 | #include "intel_decode.h" | ||
6 | |||
7 | |||
8 | void brw_dump_data( unsigned pci_id, | ||
9 | enum brw_buffer_data_type data_type, | ||
10 | unsigned offset, | ||
11 | const void *data, | ||
12 | size_t size, int gen ) | ||
13 | { | ||
14 | if (BRW_DUMP & DUMP_ASM) { | ||
15 | switch (data_type) { | ||
16 | case BRW_DATA_GS_WM_PROG: | ||
17 | case BRW_DATA_GS_SF_PROG: | ||
18 | case BRW_DATA_GS_VS_PROG: | ||
19 | case BRW_DATA_GS_GS_PROG: | ||
20 | case BRW_DATA_GS_CLIP_PROG: | ||
21 | brw_disasm( stderr, (struct brw_instruction *)data, size / sizeof(struct brw_instruction), gen ); | ||
22 | break; | ||
23 | default: | ||
24 | break; | ||
25 | } | ||
26 | } | ||
27 | |||
28 | if (BRW_DUMP & DUMP_STATE) { | ||
29 | switch (data_type) { | ||
30 | case BRW_DATA_GS_CC_VP: | ||
31 | brw_dump_cc_viewport( data ); | ||
32 | break; | ||
33 | case BRW_DATA_GS_CC_UNIT: | ||
34 | brw_dump_cc_unit_state( data ); | ||
35 | break; | ||
36 | case BRW_DATA_GS_SAMPLER_DEFAULT_COLOR: | ||
37 | brw_dump_sampler_default_color( data ); | ||
38 | break; | ||
39 | case BRW_DATA_GS_SAMPLER: | ||
40 | brw_dump_sampler_state( data ); | ||
41 | break; | ||
42 | case BRW_DATA_GS_WM_UNIT: | ||
43 | brw_dump_wm_unit_state( data ); | ||
44 | break; | ||
45 | case BRW_DATA_GS_SF_VP: | ||
46 | brw_dump_sf_viewport( data ); | ||
47 | break; | ||
48 | case BRW_DATA_GS_SF_UNIT: | ||
49 | brw_dump_sf_unit_state( data ); | ||
50 | break; | ||
51 | case BRW_DATA_GS_VS_UNIT: | ||
52 | brw_dump_vs_unit_state( data ); | ||
53 | break; | ||
54 | case BRW_DATA_GS_GS_UNIT: | ||
55 | brw_dump_gs_unit_state( data ); | ||
56 | break; | ||
57 | case BRW_DATA_GS_CLIP_VP: | ||
58 | brw_dump_clipper_viewport( data ); | ||
59 | break; | ||
60 | case BRW_DATA_GS_CLIP_UNIT: | ||
61 | brw_dump_clip_unit_state( data ); | ||
62 | break; | ||
63 | case BRW_DATA_SS_SURFACE: | ||
64 | brw_dump_surface_state( data ); | ||
65 | break; | ||
66 | case BRW_DATA_SS_SURF_BIND: | ||
67 | break; | ||
68 | case BRW_DATA_OTHER: | ||
69 | break; | ||
70 | case BRW_DATA_CONSTANT_BUFFER: | ||
71 | break; | ||
72 | default: | ||
73 | break; | ||
74 | } | ||
75 | } | ||
76 | |||
77 | if (BRW_DUMP & DUMP_BATCH) { | ||
78 | switch (data_type) { | ||
79 | case BRW_DATA_BATCH_BUFFER: | ||
80 | intel_decode(data, size / 4, offset, pci_id, 0); | ||
81 | break; | ||
82 | default: | ||
83 | break; | ||
84 | } | ||
85 | } | ||
86 | } | ||
87 | |||
diff --git a/src/gallium/drivers/i965/brw_wm.c b/src/gallium/drivers/i965/brw_wm.c deleted file mode 100644 index 5d66e61fbc1..00000000000 --- a/src/gallium/drivers/i965/brw_wm.c +++ /dev/null | |||
@@ -1,319 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | #include "tgsi/tgsi_info.h" | ||
32 | |||
33 | #include "brw_context.h" | ||
34 | #include "brw_screen.h" | ||
35 | #include "brw_wm.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_debug.h" | ||
38 | #include "brw_resource.h" | ||
39 | #include "brw_pipe_rast.h" | ||
40 | |||
41 | |||
42 | /** Return number of src args for given instruction */ | ||
43 | GLuint brw_wm_nr_args( GLuint opcode ) | ||
44 | { | ||
45 | switch (opcode) { | ||
46 | case WM_FRONTFACING: | ||
47 | case WM_PIXELXY: | ||
48 | return 0; | ||
49 | case WM_CINTERP: | ||
50 | case WM_WPOSXY: | ||
51 | case WM_DELTAXY: | ||
52 | return 1; | ||
53 | case WM_LINTERP: | ||
54 | case WM_PIXELW: | ||
55 | return 2; | ||
56 | case WM_FB_WRITE: | ||
57 | case WM_PINTERP: | ||
58 | return 3; | ||
59 | case TGSI_OPCODE_TEX: | ||
60 | case TGSI_OPCODE_TXP: | ||
61 | case TGSI_OPCODE_TXB: | ||
62 | case TGSI_OPCODE_TXD: | ||
63 | /* sampler arg is held as a field in the instruction, not in an | ||
64 | * actual register: | ||
65 | */ | ||
66 | return tgsi_get_opcode_info(opcode)->num_src - 1; | ||
67 | |||
68 | default: | ||
69 | assert(opcode < MAX_OPCODE); | ||
70 | return tgsi_get_opcode_info(opcode)->num_src; | ||
71 | } | ||
72 | } | ||
73 | |||
74 | |||
75 | GLuint brw_wm_is_scalar_result( GLuint opcode ) | ||
76 | { | ||
77 | switch (opcode) { | ||
78 | case TGSI_OPCODE_COS: | ||
79 | case TGSI_OPCODE_EX2: | ||
80 | case TGSI_OPCODE_LG2: | ||
81 | case TGSI_OPCODE_POW: | ||
82 | case TGSI_OPCODE_RCP: | ||
83 | case TGSI_OPCODE_RSQ: | ||
84 | case TGSI_OPCODE_SIN: | ||
85 | case TGSI_OPCODE_DP3: | ||
86 | case TGSI_OPCODE_DP4: | ||
87 | case TGSI_OPCODE_DPH: | ||
88 | case TGSI_OPCODE_DST: | ||
89 | return 1; | ||
90 | |||
91 | default: | ||
92 | return 0; | ||
93 | } | ||
94 | } | ||
95 | |||
96 | |||
97 | /** | ||
98 | * Do GPU code generation for shaders without flow control. Shaders | ||
99 | * without flow control instructions can more readily be analysed for | ||
100 | * SSA-style optimizations. | ||
101 | */ | ||
102 | static void | ||
103 | brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c) | ||
104 | { | ||
105 | /* Augment fragment program. Add instructions for pre- and | ||
106 | * post-fragment-program tasks such as interpolation and fogging. | ||
107 | */ | ||
108 | brw_wm_pass_fp(c); | ||
109 | |||
110 | /* Translate to intermediate representation. Build register usage | ||
111 | * chains. | ||
112 | */ | ||
113 | brw_wm_pass0(c); | ||
114 | |||
115 | /* Dead code removal. | ||
116 | */ | ||
117 | brw_wm_pass1(c); | ||
118 | |||
119 | /* Register allocation. | ||
120 | * Divide by two because we operate on 16 pixels at a time and require | ||
121 | * two GRF entries for each logical shader register. | ||
122 | */ | ||
123 | c->grf_limit = BRW_WM_MAX_GRF / 2; | ||
124 | |||
125 | brw_wm_pass2(c); | ||
126 | |||
127 | /* how many general-purpose registers are used */ | ||
128 | c->prog_data.total_grf = c->max_wm_grf; | ||
129 | |||
130 | /* Scratch space is used for register spilling */ | ||
131 | if (c->last_scratch) { | ||
132 | c->prog_data.total_scratch = c->last_scratch + 0x40; | ||
133 | } | ||
134 | else { | ||
135 | c->prog_data.total_scratch = 0; | ||
136 | } | ||
137 | |||
138 | /* Emit GEN4 code. | ||
139 | */ | ||
140 | brw_wm_emit(c); | ||
141 | } | ||
142 | |||
143 | |||
144 | /** | ||
145 | * All Mesa program -> GPU code generation goes through this function. | ||
146 | * Depending on the instructions used (i.e. flow control instructions) | ||
147 | * we'll use one of two code generators. | ||
148 | */ | ||
149 | static enum pipe_error do_wm_prog( struct brw_context *brw, | ||
150 | struct brw_fragment_shader *fp, | ||
151 | struct brw_wm_prog_key *key, | ||
152 | struct brw_winsys_buffer **bo_out) | ||
153 | { | ||
154 | enum pipe_error ret; | ||
155 | struct brw_wm_compile *c; | ||
156 | const GLuint *program; | ||
157 | GLuint program_size; | ||
158 | |||
159 | if (brw->wm.compile_data == NULL) { | ||
160 | brw->wm.compile_data = MALLOC(sizeof(*brw->wm.compile_data)); | ||
161 | if (!brw->wm.compile_data) | ||
162 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
163 | } | ||
164 | |||
165 | c = brw->wm.compile_data; | ||
166 | memset(c, 0, sizeof *c); | ||
167 | |||
168 | c->key = *key; | ||
169 | c->fp = fp; | ||
170 | c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/ | ||
171 | |||
172 | brw_init_compile(brw, &c->func); | ||
173 | |||
174 | /* | ||
175 | * Shader which use GLSL features such as flow control are handled | ||
176 | * differently from "simple" shaders. | ||
177 | */ | ||
178 | if (fp->has_flow_control) { | ||
179 | c->dispatch_width = 8; | ||
180 | /* XXX: GLSL support | ||
181 | */ | ||
182 | exit(1); | ||
183 | /* brw_wm_branching_shader_emit(brw, c); */ | ||
184 | } | ||
185 | else { | ||
186 | c->dispatch_width = 16; | ||
187 | brw_wm_linear_shader_emit(brw, c); | ||
188 | } | ||
189 | |||
190 | if (BRW_DEBUG & DEBUG_WM) | ||
191 | debug_printf("\n"); | ||
192 | |||
193 | /* get the program | ||
194 | */ | ||
195 | ret = brw_get_program(&c->func, &program, &program_size); | ||
196 | if (ret) | ||
197 | return ret; | ||
198 | |||
199 | ret = brw_upload_cache( &brw->cache, BRW_WM_PROG, | ||
200 | &c->key, sizeof(c->key), | ||
201 | NULL, 0, | ||
202 | program, program_size, | ||
203 | &c->prog_data, | ||
204 | &brw->wm.prog_data, | ||
205 | bo_out ); | ||
206 | if (ret) | ||
207 | return ret; | ||
208 | |||
209 | return PIPE_OK; | ||
210 | } | ||
211 | |||
212 | |||
213 | |||
214 | static void brw_wm_populate_key( struct brw_context *brw, | ||
215 | struct brw_wm_prog_key *key ) | ||
216 | { | ||
217 | unsigned lookup, line_aa; | ||
218 | unsigned i; | ||
219 | |||
220 | memset(key, 0, sizeof(*key)); | ||
221 | |||
222 | /* PIPE_NEW_FRAGMENT_SHADER | ||
223 | * PIPE_NEW_DEPTH_STENCIL_ALPHA | ||
224 | */ | ||
225 | lookup = (brw->curr.zstencil->iz_lookup | | ||
226 | brw->curr.fragment_shader->iz_lookup); | ||
227 | |||
228 | |||
229 | /* PIPE_NEW_RAST | ||
230 | * BRW_NEW_REDUCED_PRIMITIVE | ||
231 | */ | ||
232 | switch (brw->reduced_primitive) { | ||
233 | case PIPE_PRIM_POINTS: | ||
234 | line_aa = AA_NEVER; | ||
235 | break; | ||
236 | case PIPE_PRIM_LINES: | ||
237 | line_aa = (brw->curr.rast->templ.line_smooth ? | ||
238 | AA_ALWAYS : AA_NEVER); | ||
239 | break; | ||
240 | default: | ||
241 | line_aa = brw->curr.rast->unfilled_aa_line; | ||
242 | break; | ||
243 | } | ||
244 | |||
245 | brw_wm_lookup_iz(line_aa, | ||
246 | lookup, | ||
247 | brw->curr.fragment_shader->uses_depth, | ||
248 | key); | ||
249 | |||
250 | /* PIPE_NEW_RAST */ | ||
251 | key->flat_shade = brw->curr.rast->templ.flatshade; | ||
252 | |||
253 | |||
254 | /* PIPE_NEW_BOUND_TEXTURES */ | ||
255 | for (i = 0; i < brw->curr.num_fragment_sampler_views; i++) { | ||
256 | const struct brw_texture *tex = brw_texture(brw->curr.fragment_sampler_views[i]->texture); | ||
257 | |||
258 | if (tex->b.b.format == PIPE_FORMAT_UYVY) | ||
259 | key->yuvtex_mask |= 1 << i; | ||
260 | |||
261 | if (tex->b.b.format == PIPE_FORMAT_YUYV) | ||
262 | key->yuvtex_swap_mask |= 1 << i; | ||
263 | |||
264 | /* XXX: shadow texture | ||
265 | */ | ||
266 | /* key->shadowtex_mask |= 1<<i; */ | ||
267 | } | ||
268 | |||
269 | /* CACHE_NEW_VS_PROG */ | ||
270 | key->vp_nr_outputs = brw->vs.prog_data->nr_outputs; | ||
271 | |||
272 | key->nr_cbufs = brw->curr.fb.nr_cbufs; | ||
273 | |||
274 | key->nr_inputs = brw->curr.fragment_shader->info.num_inputs; | ||
275 | |||
276 | /* The unique fragment program ID */ | ||
277 | key->program_string_id = brw->curr.fragment_shader->id; | ||
278 | } | ||
279 | |||
280 | |||
281 | static enum pipe_error brw_prepare_wm_prog(struct brw_context *brw) | ||
282 | { | ||
283 | struct brw_wm_prog_key key; | ||
284 | struct brw_fragment_shader *fs = brw->curr.fragment_shader; | ||
285 | enum pipe_error ret; | ||
286 | |||
287 | brw_wm_populate_key(brw, &key); | ||
288 | |||
289 | /* Make an early check for the key. | ||
290 | */ | ||
291 | if (brw_search_cache(&brw->cache, BRW_WM_PROG, | ||
292 | &key, sizeof(key), | ||
293 | NULL, 0, | ||
294 | &brw->wm.prog_data, | ||
295 | &brw->wm.prog_bo)) | ||
296 | return PIPE_OK; | ||
297 | |||
298 | ret = do_wm_prog(brw, fs, &key, &brw->wm.prog_bo); | ||
299 | if (ret) | ||
300 | return ret; | ||
301 | |||
302 | return PIPE_OK; | ||
303 | } | ||
304 | |||
305 | |||
306 | const struct brw_tracked_state brw_wm_prog = { | ||
307 | .dirty = { | ||
308 | .mesa = (PIPE_NEW_FRAGMENT_SHADER | | ||
309 | PIPE_NEW_DEPTH_STENCIL_ALPHA | | ||
310 | PIPE_NEW_RAST | | ||
311 | PIPE_NEW_NR_CBUFS | | ||
312 | PIPE_NEW_BOUND_TEXTURES), | ||
313 | .brw = (BRW_NEW_WM_INPUT_DIMENSIONS | | ||
314 | BRW_NEW_REDUCED_PRIMITIVE), | ||
315 | .cache = CACHE_NEW_VS_PROG, | ||
316 | }, | ||
317 | .prepare = brw_prepare_wm_prog | ||
318 | }; | ||
319 | |||
diff --git a/src/gallium/drivers/i965/brw_wm.h b/src/gallium/drivers/i965/brw_wm.h deleted file mode 100644 index f1ca9f63696..00000000000 --- a/src/gallium/drivers/i965/brw_wm.h +++ /dev/null | |||
@@ -1,344 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #ifndef BRW_WM_H | ||
34 | #define BRW_WM_H | ||
35 | |||
36 | #include "brw_context.h" | ||
37 | #include "brw_eu.h" | ||
38 | |||
39 | #define SATURATE (1<<5) | ||
40 | |||
41 | /* A big lookup table is used to figure out which and how many | ||
42 | * additional regs will inserted before the main payload in the WM | ||
43 | * program execution. These mainly relate to depth and stencil | ||
44 | * processing and the early-depth-test optimization. | ||
45 | */ | ||
46 | #define IZ_PS_KILL_ALPHATEST_BIT 0x1 | ||
47 | #define IZ_PS_COMPUTES_DEPTH_BIT 0x2 | ||
48 | #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4 | ||
49 | #define IZ_DEPTH_TEST_ENABLE_BIT 0x8 | ||
50 | #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10 | ||
51 | #define IZ_STENCIL_TEST_ENABLE_BIT 0x20 | ||
52 | #define IZ_BIT_MAX 0x40 | ||
53 | |||
54 | #define AA_NEVER 0 | ||
55 | #define AA_SOMETIMES 1 | ||
56 | #define AA_ALWAYS 2 | ||
57 | |||
58 | struct brw_wm_prog_key { | ||
59 | GLuint source_depth_reg:3; | ||
60 | GLuint aa_dest_stencil_reg:3; | ||
61 | GLuint dest_depth_reg:3; | ||
62 | GLuint nr_depth_regs:3; | ||
63 | GLuint computes_depth:1; | ||
64 | GLuint source_depth_to_render_target:1; | ||
65 | GLuint flat_shade:1; | ||
66 | GLuint runtime_check_aads_emit:1; | ||
67 | |||
68 | GLuint shadowtex_mask:16; | ||
69 | GLuint yuvtex_mask:16; | ||
70 | GLuint yuvtex_swap_mask:16; /* UV swaped */ | ||
71 | |||
72 | GLuint vp_nr_outputs:6; | ||
73 | GLuint nr_inputs:6; | ||
74 | GLuint nr_cbufs:3; | ||
75 | GLuint has_flow_control:1; | ||
76 | |||
77 | GLuint program_string_id; | ||
78 | }; | ||
79 | |||
80 | |||
81 | /* A bit of a glossary: | ||
82 | * | ||
83 | * brw_wm_value: A computed value or program input. Values are | ||
84 | * constant, they are created once and are never modified. When a | ||
85 | * fragment program register is written or overwritten, new values are | ||
86 | * created fresh, preserving the rule that values are constant. | ||
87 | * | ||
88 | * brw_wm_ref: A reference to a value. Wherever a value used is by an | ||
89 | * instruction or as a program output, that is tracked with an | ||
90 | * instance of this struct. All references to a value occur after it | ||
91 | * is created. After the last reference, a value is dead and can be | ||
92 | * discarded. | ||
93 | * | ||
94 | * brw_wm_grf: Represents a physical hardware register. May be either | ||
95 | * empty or hold a value. Register allocation is the process of | ||
96 | * assigning values to grf registers. This occurs in pass2 and the | ||
97 | * brw_wm_grf struct is not used before that. | ||
98 | * | ||
99 | * Fragment program registers: These are time-varying constructs that | ||
100 | * are hard to reason about and which we translate away in pass0. A | ||
101 | * single fragment program register element (eg. temp[0].x) will be | ||
102 | * translated to one or more brw_wm_value structs, one for each time | ||
103 | * that temp[0].x is written to during the program. | ||
104 | */ | ||
105 | |||
106 | |||
107 | |||
108 | /* Used in pass2 to track register allocation. | ||
109 | */ | ||
110 | struct brw_wm_grf { | ||
111 | struct brw_wm_value *value; | ||
112 | GLuint nextuse; | ||
113 | }; | ||
114 | |||
115 | struct brw_wm_value { | ||
116 | struct brw_reg hw_reg; /* emitted to this reg, may not always be there */ | ||
117 | struct brw_wm_ref *lastuse; | ||
118 | struct brw_wm_grf *resident; | ||
119 | GLuint contributes_to_output:1; | ||
120 | GLuint spill_slot:16; /* if non-zero, spill immediately after calculation */ | ||
121 | }; | ||
122 | |||
123 | struct brw_wm_ref { | ||
124 | struct brw_reg hw_reg; /* nr filled in in pass2, everything else, pass0 */ | ||
125 | struct brw_wm_value *value; | ||
126 | struct brw_wm_ref *prevuse; | ||
127 | GLuint unspill_reg:7; /* unspill to reg */ | ||
128 | GLuint emitted:1; | ||
129 | GLuint insn:24; | ||
130 | }; | ||
131 | |||
132 | struct brw_wm_instruction { | ||
133 | struct brw_wm_value *dst[4]; | ||
134 | struct brw_wm_ref *src[3][4]; | ||
135 | GLuint opcode:8; | ||
136 | GLuint saturate:1; | ||
137 | GLuint writemask:4; | ||
138 | GLuint sampler:4; | ||
139 | GLuint tex_unit:4; /* texture/sampler unit for texture instructions */ | ||
140 | GLuint target:4; /* TGSI_TEXTURE_x for texture instructions, | ||
141 | * target binding table index for FB_WRITE | ||
142 | */ | ||
143 | GLuint eot:1; /* End of thread indicator for FB_WRITE*/ | ||
144 | }; | ||
145 | |||
146 | |||
147 | #define BRW_WM_MAX_INSN 2048 | ||
148 | #define BRW_WM_MAX_GRF 128 /* hardware limit */ | ||
149 | #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4) | ||
150 | #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12) | ||
151 | #define BRW_WM_MAX_PARAM 256 | ||
152 | #define BRW_WM_MAX_CONST 256 | ||
153 | #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS | ||
154 | #define BRW_WM_MAX_SUBROUTINE 16 | ||
155 | |||
156 | |||
157 | /* New opcodes to track internal operations required for WM unit. | ||
158 | * These are added early so that the registers used can be tracked, | ||
159 | * freed and reused like those of other instructions. | ||
160 | */ | ||
161 | #define MAX_OPCODE TGSI_OPCODE_LAST | ||
162 | #define WM_PIXELXY (MAX_OPCODE) | ||
163 | #define WM_DELTAXY (MAX_OPCODE + 1) | ||
164 | #define WM_PIXELW (MAX_OPCODE + 2) | ||
165 | #define WM_LINTERP (MAX_OPCODE + 3) | ||
166 | #define WM_PINTERP (MAX_OPCODE + 4) | ||
167 | #define WM_CINTERP (MAX_OPCODE + 5) | ||
168 | #define WM_WPOSXY (MAX_OPCODE + 6) | ||
169 | #define WM_FB_WRITE (MAX_OPCODE + 7) | ||
170 | #define WM_FRONTFACING (MAX_OPCODE + 8) | ||
171 | #define MAX_WM_OPCODE (MAX_OPCODE + 9) | ||
172 | |||
173 | #define BRW_FILE_PAYLOAD (TGSI_FILE_COUNT) | ||
174 | #define PAYLOAD_DEPTH (PIPE_MAX_SHADER_INPUTS) /* ?? */ | ||
175 | |||
176 | #define X 0 | ||
177 | #define Y 1 | ||
178 | #define Z 2 | ||
179 | #define W 3 | ||
180 | |||
181 | |||
182 | struct brw_fp_src { | ||
183 | unsigned file:4; | ||
184 | unsigned index:16; | ||
185 | unsigned swizzle:8; | ||
186 | unsigned indirect:1; | ||
187 | unsigned negate:1; | ||
188 | unsigned abs:1; | ||
189 | }; | ||
190 | |||
191 | struct brw_fp_dst { | ||
192 | unsigned file:4; | ||
193 | unsigned index:16; | ||
194 | unsigned writemask:4; | ||
195 | unsigned indirect:1; | ||
196 | unsigned saturate:1; | ||
197 | }; | ||
198 | |||
199 | struct brw_fp_instruction { | ||
200 | struct brw_fp_dst dst; | ||
201 | struct brw_fp_src src[3]; | ||
202 | unsigned opcode:8; | ||
203 | unsigned target:8; /* XXX: special usage for FB_WRITE */ | ||
204 | unsigned tex_unit:4; | ||
205 | unsigned sampler:4; | ||
206 | unsigned pad:8; | ||
207 | }; | ||
208 | |||
209 | |||
210 | struct brw_wm_compile { | ||
211 | struct brw_compile func; | ||
212 | struct brw_wm_prog_key key; | ||
213 | struct brw_wm_prog_data prog_data; | ||
214 | |||
215 | struct brw_fragment_shader *fp; | ||
216 | |||
217 | GLfloat (*env_param)[4]; | ||
218 | |||
219 | enum { | ||
220 | START, | ||
221 | PASS2_DONE | ||
222 | } state; | ||
223 | |||
224 | /* Initial pass - translate fp instructions to fp instructions, | ||
225 | * simplifying and adding instructions for interpolation and | ||
226 | * framebuffer writes. | ||
227 | */ | ||
228 | struct { | ||
229 | GLfloat v[4]; | ||
230 | unsigned nr; | ||
231 | } immediate[BRW_WM_MAX_CONST+3]; | ||
232 | GLuint nr_immediates; | ||
233 | |||
234 | struct brw_fp_instruction fp_instructions[BRW_WM_MAX_INSN]; | ||
235 | GLuint nr_fp_insns; | ||
236 | GLuint fp_temp; | ||
237 | GLuint fp_interp_emitted; | ||
238 | GLuint fp_fragcolor_emitted; | ||
239 | GLuint fp_first_internal_temp; | ||
240 | |||
241 | struct brw_fp_src fp_pixel_xy; | ||
242 | struct brw_fp_src fp_delta_xy; | ||
243 | struct brw_fp_src fp_pixel_w; | ||
244 | |||
245 | |||
246 | /* Subsequent passes using SSA representation: | ||
247 | */ | ||
248 | struct brw_wm_value vreg[BRW_WM_MAX_VREG]; | ||
249 | GLuint nr_vreg; | ||
250 | |||
251 | struct brw_wm_value creg[BRW_WM_MAX_PARAM]; | ||
252 | GLuint nr_creg; | ||
253 | |||
254 | struct { | ||
255 | struct brw_wm_value depth[4]; /* includes r0/r1 */ | ||
256 | struct brw_wm_value input_interp[PIPE_MAX_SHADER_INPUTS]; | ||
257 | } payload; | ||
258 | |||
259 | |||
260 | const struct brw_wm_ref *pass0_fp_reg[BRW_FILE_PAYLOAD+1][256][4]; | ||
261 | |||
262 | struct brw_wm_ref undef_ref; | ||
263 | struct brw_wm_value undef_value; | ||
264 | |||
265 | struct brw_wm_ref refs[BRW_WM_MAX_REF]; | ||
266 | GLuint nr_refs; | ||
267 | |||
268 | struct brw_wm_instruction instruction[BRW_WM_MAX_INSN]; | ||
269 | GLuint nr_insns; | ||
270 | |||
271 | struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2]; | ||
272 | |||
273 | GLuint grf_limit; | ||
274 | GLuint max_wm_grf; | ||
275 | GLuint last_scratch; | ||
276 | |||
277 | GLuint cur_inst; /**< index of current instruction */ | ||
278 | |||
279 | GLboolean out_of_regs; /**< ran out of GRF registers? */ | ||
280 | |||
281 | /** Mapping from Mesa registers to hardware registers */ | ||
282 | struct { | ||
283 | GLboolean inited; | ||
284 | struct brw_reg reg; | ||
285 | } wm_regs[BRW_FILE_PAYLOAD+1][256][4]; | ||
286 | |||
287 | GLboolean used_grf[BRW_WM_MAX_GRF]; | ||
288 | GLuint first_free_grf; | ||
289 | struct brw_reg stack; | ||
290 | struct brw_reg emit_mask_reg; | ||
291 | GLuint tmp_regs[BRW_WM_MAX_GRF]; | ||
292 | GLuint tmp_index; | ||
293 | GLuint tmp_max; | ||
294 | GLuint subroutines[BRW_WM_MAX_SUBROUTINE]; | ||
295 | GLuint dispatch_width; | ||
296 | |||
297 | /** we may need up to 3 constants per instruction (if use_const_buffer) */ | ||
298 | struct { | ||
299 | GLint index; | ||
300 | struct brw_reg reg; | ||
301 | } current_const[3]; | ||
302 | |||
303 | GLuint error; | ||
304 | }; | ||
305 | |||
306 | |||
307 | GLuint brw_wm_nr_args( GLuint opcode ); | ||
308 | GLuint brw_wm_is_scalar_result( GLuint opcode ); | ||
309 | |||
310 | int brw_wm_pass_fp( struct brw_wm_compile *c ); | ||
311 | void brw_wm_pass0( struct brw_wm_compile *c ); | ||
312 | void brw_wm_pass1( struct brw_wm_compile *c ); | ||
313 | void brw_wm_pass2( struct brw_wm_compile *c ); | ||
314 | void brw_wm_emit( struct brw_wm_compile *c ); | ||
315 | |||
316 | void brw_wm_print_value( struct brw_wm_compile *c, | ||
317 | struct brw_wm_value *value ); | ||
318 | |||
319 | void brw_wm_print_ref( struct brw_wm_compile *c, | ||
320 | struct brw_wm_ref *ref ); | ||
321 | |||
322 | void brw_wm_print_insn( struct brw_wm_compile *c, | ||
323 | struct brw_wm_instruction *inst ); | ||
324 | |||
325 | void brw_wm_print_program( struct brw_wm_compile *c, | ||
326 | const char *stage ); | ||
327 | |||
328 | void brw_wm_print_fp_program( struct brw_wm_compile *c, | ||
329 | const char *stage ); | ||
330 | |||
331 | void brw_wm_lookup_iz( GLuint line_aa, | ||
332 | GLuint lookup, | ||
333 | GLboolean ps_uses_depth, | ||
334 | struct brw_wm_prog_key *key ); | ||
335 | |||
336 | void brw_wm_branching_shader_emit(struct brw_context *brw, struct brw_wm_compile *c); | ||
337 | |||
338 | void emit_ddxy(struct brw_compile *p, | ||
339 | const struct brw_reg *dst, | ||
340 | GLuint mask, | ||
341 | GLboolean is_ddx, | ||
342 | const struct brw_reg *arg0); | ||
343 | |||
344 | #endif | ||
diff --git a/src/gallium/drivers/i965/brw_wm_constant_buffer.c b/src/gallium/drivers/i965/brw_wm_constant_buffer.c deleted file mode 100644 index df5cd0398c9..00000000000 --- a/src/gallium/drivers/i965/brw_wm_constant_buffer.c +++ /dev/null | |||
@@ -1,165 +0,0 @@ | |||
1 | /* XXX: Constant buffers disabled | ||
2 | */ | ||
3 | |||
4 | |||
5 | /** | ||
6 | * Create the constant buffer surface. Vertex/fragment shader constants will be | ||
7 | * read from this buffer with Data Port Read instructions/messages. | ||
8 | */ | ||
9 | enum pipe_error | ||
10 | brw_create_constant_surface( struct brw_context *brw, | ||
11 | struct brw_surface_key *key, | ||
12 | struct brw_winsys_buffer **bo_out ) | ||
13 | { | ||
14 | const GLint w = key->width - 1; | ||
15 | struct brw_winsys_buffer *bo; | ||
16 | struct brw_winsys_reloc reloc[1]; | ||
17 | enum pipe_error ret; | ||
18 | |||
19 | /* Emit relocation to surface contents */ | ||
20 | make_reloc(&reloc[0], | ||
21 | BRW_USAGE_SAMPLER, | ||
22 | 0, | ||
23 | offsetof(struct brw_surface_state, ss1), | ||
24 | key->bo); | ||
25 | |||
26 | |||
27 | memset(&surf, 0, sizeof(surf)); | ||
28 | |||
29 | surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; | ||
30 | surf.ss0.surface_type = BRW_SURFACE_BUFFER; | ||
31 | surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; | ||
32 | |||
33 | surf.ss1.base_addr = 0; /* reloc */ | ||
34 | |||
35 | surf.ss2.width = w & 0x7f; /* bits 6:0 of size or width */ | ||
36 | surf.ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */ | ||
37 | surf.ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */ | ||
38 | surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */ | ||
39 | brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */ | ||
40 | |||
41 | ret = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE, | ||
42 | key, sizeof(*key), | ||
43 | reloc, Elements(reloc), | ||
44 | &surf, sizeof(surf), | ||
45 | NULL, NULL, | ||
46 | &bo_out); | ||
47 | if (ret) | ||
48 | return ret; | ||
49 | |||
50 | return PIPE_OK; | ||
51 | } | ||
52 | |||
53 | |||
54 | |||
55 | /** | ||
56 | * Update the surface state for a WM constant buffer. | ||
57 | * The constant buffer will be (re)allocated here if needed. | ||
58 | */ | ||
59 | static enum pipe_error | ||
60 | brw_update_wm_constant_surface( struct brw_context *brw, | ||
61 | GLuint surf) | ||
62 | { | ||
63 | struct brw_surface_key key; | ||
64 | struct brw_fragment_shader *fp = brw->curr.fragment_shader; | ||
65 | struct pipe_resource *cbuf = brw->curr.fragment_constants; | ||
66 | int pitch = cbuf->size / (4 * sizeof(float)); | ||
67 | enum pipe_error ret; | ||
68 | |||
69 | /* If we're in this state update atom, we need to update WM constants, so | ||
70 | * free the old buffer and create a new one for the new contents. | ||
71 | */ | ||
72 | ret = brw_wm_update_constant_buffer(brw, &fp->const_buffer); | ||
73 | if (ret) | ||
74 | return ret; | ||
75 | |||
76 | /* If there's no constant buffer, then no surface BO is needed to point at | ||
77 | * it. | ||
78 | */ | ||
79 | if (cbuf == NULL) { | ||
80 | bo_reference(&brw->wm.surf_bo[surf], NULL); | ||
81 | return PIPE_OK; | ||
82 | } | ||
83 | |||
84 | memset(&key, 0, sizeof(key)); | ||
85 | |||
86 | key.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; | ||
87 | key.ss0.surface_type = BRW_SURFACE_BUFFER; | ||
88 | key.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; | ||
89 | |||
90 | key.bo = brw_buffer(cbuf)->bo; | ||
91 | |||
92 | key.ss2.width = (pitch-1) & 0x7f; /* bits 6:0 of size or width */ | ||
93 | key.ss2.height = ((pitch-1) >> 7) & 0x1fff; /* bits 19:7 of size or width */ | ||
94 | key.ss3.depth = ((pitch-1) >> 20) & 0x7f; /* bits 26:20 of size or width */ | ||
95 | key.ss3.pitch = (pitch * 4 * sizeof(float)) - 1; /* ignored?? */ | ||
96 | brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */ | ||
97 | |||
98 | |||
99 | /* | ||
100 | printf("%s:\n", __FUNCTION__); | ||
101 | printf(" width %d height %d depth %d cpp %d pitch %d\n", | ||
102 | key.width, key.height, key.depth, key.cpp, key.pitch); | ||
103 | */ | ||
104 | |||
105 | if (brw_search_cache(&brw->surface_cache, | ||
106 | BRW_SS_SURFACE, | ||
107 | &key, sizeof(key), | ||
108 | &key.bo, 1, | ||
109 | NULL, | ||
110 | &brw->wm.surf_bo[surf])) | ||
111 | return PIPE_OK; | ||
112 | |||
113 | ret = brw_create_constant_surface(brw, &key, &brw->wm.surf_bo[surf]); | ||
114 | if (ret) | ||
115 | return ret; | ||
116 | |||
117 | brw->state.dirty.brw |= BRW_NEW_WM_SURFACES; | ||
118 | return PIPE_OK; | ||
119 | } | ||
120 | |||
121 | /** | ||
122 | * Updates surface / buffer for fragment shader constant buffer, if | ||
123 | * one is required. | ||
124 | * | ||
125 | * This consumes the state updates for the constant buffer, and produces | ||
126 | * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for | ||
127 | * inclusion in the binding table. | ||
128 | */ | ||
129 | static enum pipe_error prepare_wm_constant_surface(struct brw_context *brw ) | ||
130 | { | ||
131 | struct brw_fragment_program *fp = | ||
132 | (struct brw_fragment_program *) brw->fragment_program; | ||
133 | GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER; | ||
134 | |||
135 | ret = brw_wm_update_constant_buffer(brw, | ||
136 | &fp->const_buffer); | ||
137 | if (ret) | ||
138 | return ret; | ||
139 | |||
140 | /* If there's no constant buffer, then no surface BO is needed to point at | ||
141 | * it. | ||
142 | */ | ||
143 | if (fp->const_buffer == 0) { | ||
144 | if (brw->wm.surf_bo[surf] != NULL) { | ||
145 | bo_reference(&brw->wm.surf_bo[surf], NULL); | ||
146 | brw->state.dirty.brw |= BRW_NEW_WM_SURFACES; | ||
147 | } | ||
148 | return PIPE_OK; | ||
149 | } | ||
150 | |||
151 | ret = brw_update_wm_constant_surface(ctx, surf); | ||
152 | if (ret) | ||
153 | return ret; | ||
154 | |||
155 | return PIPE_OK | ||
156 | } | ||
157 | |||
158 | const struct brw_tracked_state brw_wm_constant_surface = { | ||
159 | .dirty = { | ||
160 | .mesa = (_NEW_PROGRAM_CONSTANTS), | ||
161 | .brw = (BRW_NEW_FRAGMENT_PROGRAM), | ||
162 | .cache = 0 | ||
163 | }, | ||
164 | .prepare = prepare_wm_constant_surface, | ||
165 | }; | ||
diff --git a/src/gallium/drivers/i965/brw_wm_debug.c b/src/gallium/drivers/i965/brw_wm_debug.c deleted file mode 100644 index 1b2aa93befc..00000000000 --- a/src/gallium/drivers/i965/brw_wm_debug.c +++ /dev/null | |||
@@ -1,257 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "tgsi/tgsi_info.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_wm.h" | ||
36 | |||
37 | static void print_writemask( unsigned writemask ) | ||
38 | { | ||
39 | if (writemask != BRW_WRITEMASK_XYZW) | ||
40 | debug_printf(".%s%s%s%s", | ||
41 | (writemask & BRW_WRITEMASK_X) ? "x" : "", | ||
42 | (writemask & BRW_WRITEMASK_Y) ? "y" : "", | ||
43 | (writemask & BRW_WRITEMASK_Z) ? "z" : "", | ||
44 | (writemask & BRW_WRITEMASK_W) ? "w" : ""); | ||
45 | } | ||
46 | |||
47 | static void print_swizzle( unsigned swizzle ) | ||
48 | { | ||
49 | char *swz = "xyzw"; | ||
50 | if (swizzle != BRW_SWIZZLE_XYZW) | ||
51 | debug_printf(".%c%c%c%c", | ||
52 | swz[BRW_GET_SWZ(swizzle, X)], | ||
53 | swz[BRW_GET_SWZ(swizzle, Y)], | ||
54 | swz[BRW_GET_SWZ(swizzle, Z)], | ||
55 | swz[BRW_GET_SWZ(swizzle, W)]); | ||
56 | } | ||
57 | |||
58 | static void print_opcode( unsigned opcode ) | ||
59 | { | ||
60 | switch (opcode) { | ||
61 | case WM_PIXELXY: | ||
62 | debug_printf("PIXELXY"); | ||
63 | break; | ||
64 | case WM_DELTAXY: | ||
65 | debug_printf("DELTAXY"); | ||
66 | break; | ||
67 | case WM_PIXELW: | ||
68 | debug_printf("PIXELW"); | ||
69 | break; | ||
70 | case WM_WPOSXY: | ||
71 | debug_printf("WPOSXY"); | ||
72 | break; | ||
73 | case WM_PINTERP: | ||
74 | debug_printf("PINTERP"); | ||
75 | break; | ||
76 | case WM_LINTERP: | ||
77 | debug_printf("LINTERP"); | ||
78 | break; | ||
79 | case WM_CINTERP: | ||
80 | debug_printf("CINTERP"); | ||
81 | break; | ||
82 | case WM_FB_WRITE: | ||
83 | debug_printf("FB_WRITE"); | ||
84 | break; | ||
85 | case WM_FRONTFACING: | ||
86 | debug_printf("FRONTFACING"); | ||
87 | break; | ||
88 | default: | ||
89 | debug_printf("%s", tgsi_get_opcode_info(opcode)->mnemonic); | ||
90 | break; | ||
91 | } | ||
92 | } | ||
93 | |||
94 | void brw_wm_print_value( struct brw_wm_compile *c, | ||
95 | struct brw_wm_value *value ) | ||
96 | { | ||
97 | assert(value); | ||
98 | if (c->state >= PASS2_DONE) | ||
99 | brw_print_reg(value->hw_reg); | ||
100 | else if( value == &c->undef_value ) | ||
101 | debug_printf("undef"); | ||
102 | else if( value - c->vreg >= 0 && | ||
103 | value - c->vreg < BRW_WM_MAX_VREG) | ||
104 | debug_printf("r%ld", (long) (value - c->vreg)); | ||
105 | else if (value - c->creg >= 0 && | ||
106 | value - c->creg < BRW_WM_MAX_PARAM) | ||
107 | debug_printf("c%ld", (long) (value - c->creg)); | ||
108 | else if (value - c->payload.input_interp >= 0 && | ||
109 | value - c->payload.input_interp < PIPE_MAX_SHADER_INPUTS) | ||
110 | debug_printf("i%ld", (long) (value - c->payload.input_interp)); | ||
111 | else if (value - c->payload.depth >= 0 && | ||
112 | value - c->payload.depth < PIPE_MAX_SHADER_INPUTS) | ||
113 | debug_printf("d%ld", (long) (value - c->payload.depth)); | ||
114 | else | ||
115 | debug_printf("?"); | ||
116 | } | ||
117 | |||
118 | void brw_wm_print_ref( struct brw_wm_compile *c, | ||
119 | struct brw_wm_ref *ref ) | ||
120 | { | ||
121 | struct brw_reg hw_reg = ref->hw_reg; | ||
122 | |||
123 | if (ref->unspill_reg) | ||
124 | debug_printf("UNSPILL(%x)/", ref->value->spill_slot); | ||
125 | |||
126 | if (c->state >= PASS2_DONE) | ||
127 | brw_print_reg(ref->hw_reg); | ||
128 | else { | ||
129 | debug_printf("%s", hw_reg.negate ? "-" : ""); | ||
130 | debug_printf("%s", hw_reg.abs ? "abs/" : ""); | ||
131 | brw_wm_print_value(c, ref->value); | ||
132 | if ((hw_reg.nr&1) || hw_reg.subnr) { | ||
133 | debug_printf("->%d.%d", (hw_reg.nr&1), hw_reg.subnr); | ||
134 | } | ||
135 | } | ||
136 | } | ||
137 | |||
138 | void brw_wm_print_insn( struct brw_wm_compile *c, | ||
139 | struct brw_wm_instruction *inst ) | ||
140 | { | ||
141 | GLuint i, arg; | ||
142 | GLuint nr_args = brw_wm_nr_args(inst->opcode); | ||
143 | |||
144 | debug_printf("["); | ||
145 | for (i = 0; i < 4; i++) { | ||
146 | if (inst->dst[i]) { | ||
147 | brw_wm_print_value(c, inst->dst[i]); | ||
148 | if (inst->dst[i]->spill_slot) | ||
149 | debug_printf("/SPILL(%x)",inst->dst[i]->spill_slot); | ||
150 | } | ||
151 | else | ||
152 | debug_printf("#"); | ||
153 | if (i < 3) | ||
154 | debug_printf(","); | ||
155 | } | ||
156 | debug_printf("]"); | ||
157 | print_writemask(inst->writemask); | ||
158 | |||
159 | debug_printf(" = "); | ||
160 | print_opcode(inst->opcode); | ||
161 | |||
162 | if (inst->saturate) | ||
163 | debug_printf("_SAT"); | ||
164 | |||
165 | for (arg = 0; arg < nr_args; arg++) { | ||
166 | |||
167 | debug_printf(" ["); | ||
168 | |||
169 | for (i = 0; i < 4; i++) { | ||
170 | if (inst->src[arg][i]) { | ||
171 | brw_wm_print_ref(c, inst->src[arg][i]); | ||
172 | } | ||
173 | else | ||
174 | debug_printf("%%"); | ||
175 | |||
176 | if (i < 3) | ||
177 | debug_printf(","); | ||
178 | else | ||
179 | debug_printf("]"); | ||
180 | } | ||
181 | } | ||
182 | debug_printf("\n"); | ||
183 | } | ||
184 | |||
185 | void brw_wm_print_program( struct brw_wm_compile *c, | ||
186 | const char *stage ) | ||
187 | { | ||
188 | GLuint insn; | ||
189 | |||
190 | debug_printf("%s:\n", stage); | ||
191 | for (insn = 0; insn < c->nr_insns; insn++) | ||
192 | brw_wm_print_insn(c, &c->instruction[insn]); | ||
193 | debug_printf("\n"); | ||
194 | } | ||
195 | |||
196 | static const char *file_strings[TGSI_FILE_COUNT+1] = { | ||
197 | "NULL", | ||
198 | "CONST", | ||
199 | "IN", | ||
200 | "OUT", | ||
201 | "TEMP", | ||
202 | "SAMPLER", | ||
203 | "ADDR", | ||
204 | "IMM", | ||
205 | "PRED", | ||
206 | "SV", | ||
207 | "PAYLOAD" | ||
208 | }; | ||
209 | |||
210 | static void brw_wm_print_fp_insn( struct brw_wm_compile *c, | ||
211 | struct brw_fp_instruction *inst ) | ||
212 | { | ||
213 | GLuint i; | ||
214 | GLuint nr_args = brw_wm_nr_args(inst->opcode); | ||
215 | |||
216 | print_opcode(inst->opcode); | ||
217 | if (inst->dst.saturate) | ||
218 | debug_printf("_SAT"); | ||
219 | debug_printf(" "); | ||
220 | |||
221 | if (inst->dst.indirect) | ||
222 | debug_printf("["); | ||
223 | |||
224 | debug_printf("%s[%d]", | ||
225 | file_strings[inst->dst.file], | ||
226 | inst->dst.index ); | ||
227 | print_writemask(inst->dst.writemask); | ||
228 | |||
229 | if (inst->dst.indirect) | ||
230 | debug_printf("]"); | ||
231 | |||
232 | debug_printf(nr_args ? ", " : "\n"); | ||
233 | |||
234 | for (i = 0; i < nr_args; i++) { | ||
235 | debug_printf("%s%s%s[%d]%s", | ||
236 | inst->src[i].negate ? "-" : "", | ||
237 | inst->src[i].abs ? "ABS(" : "", | ||
238 | file_strings[inst->src[i].file], | ||
239 | inst->src[i].index, | ||
240 | inst->src[i].abs ? ")" : ""); | ||
241 | print_swizzle(inst->src[i].swizzle); | ||
242 | debug_printf("%s", i == nr_args - 1 ? "\n" : ", "); | ||
243 | } | ||
244 | } | ||
245 | |||
246 | |||
247 | void brw_wm_print_fp_program( struct brw_wm_compile *c, | ||
248 | const char *stage ) | ||
249 | { | ||
250 | GLuint insn; | ||
251 | |||
252 | debug_printf("%s:\n", stage); | ||
253 | for (insn = 0; insn < c->nr_fp_insns; insn++) | ||
254 | brw_wm_print_fp_insn(c, &c->fp_instructions[insn]); | ||
255 | debug_printf("\n"); | ||
256 | } | ||
257 | |||
diff --git a/src/gallium/drivers/i965/brw_wm_emit.c b/src/gallium/drivers/i965/brw_wm_emit.c deleted file mode 100644 index 6301062fd79..00000000000 --- a/src/gallium/drivers/i965/brw_wm_emit.c +++ /dev/null | |||
@@ -1,1521 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | #include "tgsi/tgsi_info.h" | ||
34 | |||
35 | #include "brw_context.h" | ||
36 | #include "brw_wm.h" | ||
37 | #include "brw_debug.h" | ||
38 | #include "brw_disasm.h" | ||
39 | |||
40 | /* Not quite sure how correct this is - need to understand horiz | ||
41 | * vs. vertical strides a little better. | ||
42 | */ | ||
43 | static INLINE struct brw_reg sechalf( struct brw_reg reg ) | ||
44 | { | ||
45 | if (reg.vstride) | ||
46 | reg.nr++; | ||
47 | return reg; | ||
48 | } | ||
49 | |||
50 | /* Payload R0: | ||
51 | * | ||
52 | * R0.0 -- pixel mask, one bit for each of 4 pixels in 4 quads, | ||
53 | * corresponding to each of the 16 execution channels. | ||
54 | * R0.1..8 -- ? | ||
55 | * R1.0 -- triangle vertex 0.X | ||
56 | * R1.1 -- triangle vertex 0.Y | ||
57 | * R1.2 -- quad 0 x,y coords (2 packed uwords) | ||
58 | * R1.3 -- quad 1 x,y coords (2 packed uwords) | ||
59 | * R1.4 -- quad 2 x,y coords (2 packed uwords) | ||
60 | * R1.5 -- quad 3 x,y coords (2 packed uwords) | ||
61 | * R1.6 -- ? | ||
62 | * R1.7 -- ? | ||
63 | * R1.8 -- ? | ||
64 | */ | ||
65 | |||
66 | |||
67 | static void emit_pixel_xy(struct brw_compile *p, | ||
68 | const struct brw_reg *dst, | ||
69 | GLuint mask) | ||
70 | { | ||
71 | struct brw_reg r1 = brw_vec1_grf(1, 0); | ||
72 | struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); | ||
73 | |||
74 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
75 | |||
76 | /* Calculate pixel centers by adding 1 or 0 to each of the | ||
77 | * micro-tile coordinates passed in r1. | ||
78 | */ | ||
79 | if (mask & BRW_WRITEMASK_X) { | ||
80 | brw_ADD(p, | ||
81 | vec16(retype(dst[0], BRW_REGISTER_TYPE_UW)), | ||
82 | stride(suboffset(r1_uw, 4), 2, 4, 0), | ||
83 | brw_imm_v(0x10101010)); | ||
84 | } | ||
85 | |||
86 | if (mask & BRW_WRITEMASK_Y) { | ||
87 | brw_ADD(p, | ||
88 | vec16(retype(dst[1], BRW_REGISTER_TYPE_UW)), | ||
89 | stride(suboffset(r1_uw,5), 2, 4, 0), | ||
90 | brw_imm_v(0x11001100)); | ||
91 | } | ||
92 | |||
93 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); | ||
94 | } | ||
95 | |||
96 | |||
97 | |||
98 | static void emit_delta_xy(struct brw_compile *p, | ||
99 | const struct brw_reg *dst, | ||
100 | GLuint mask, | ||
101 | const struct brw_reg *arg0) | ||
102 | { | ||
103 | struct brw_reg r1 = brw_vec1_grf(1, 0); | ||
104 | |||
105 | /* Calc delta X,Y by subtracting origin in r1 from the pixel | ||
106 | * centers. | ||
107 | */ | ||
108 | if (mask & BRW_WRITEMASK_X) { | ||
109 | brw_ADD(p, | ||
110 | dst[0], | ||
111 | retype(arg0[0], BRW_REGISTER_TYPE_UW), | ||
112 | negate(r1)); | ||
113 | } | ||
114 | |||
115 | if (mask & BRW_WRITEMASK_Y) { | ||
116 | brw_ADD(p, | ||
117 | dst[1], | ||
118 | retype(arg0[1], BRW_REGISTER_TYPE_UW), | ||
119 | negate(suboffset(r1,1))); | ||
120 | |||
121 | } | ||
122 | } | ||
123 | |||
124 | static void emit_wpos_xy(struct brw_wm_compile *c, | ||
125 | const struct brw_reg *dst, | ||
126 | GLuint mask, | ||
127 | const struct brw_reg *arg0) | ||
128 | { | ||
129 | struct brw_compile *p = &c->func; | ||
130 | |||
131 | if (mask & BRW_WRITEMASK_X) { | ||
132 | /* X' = X */ | ||
133 | brw_MOV(p, | ||
134 | dst[0], | ||
135 | retype(arg0[0], BRW_REGISTER_TYPE_W)); | ||
136 | } | ||
137 | |||
138 | /* XXX: is this needed any more, or is this a NOOP? | ||
139 | */ | ||
140 | if (mask & BRW_WRITEMASK_Y) { | ||
141 | #if 0 | ||
142 | /* Y' = height - 1 - Y */ | ||
143 | brw_ADD(p, | ||
144 | dst[1], | ||
145 | negate(retype(arg0[1], BRW_REGISTER_TYPE_W)), | ||
146 | brw_imm_d(c->key.drawable_height - 1)); | ||
147 | #else | ||
148 | brw_MOV(p, | ||
149 | dst[0], | ||
150 | retype(arg0[0], BRW_REGISTER_TYPE_W)); | ||
151 | #endif | ||
152 | } | ||
153 | } | ||
154 | |||
155 | |||
156 | static void emit_pixel_w( struct brw_compile *p, | ||
157 | const struct brw_reg *dst, | ||
158 | GLuint mask, | ||
159 | const struct brw_reg *arg0, | ||
160 | const struct brw_reg *deltas) | ||
161 | { | ||
162 | /* Don't need this if all you are doing is interpolating color, for | ||
163 | * instance. | ||
164 | */ | ||
165 | if (mask & BRW_WRITEMASK_W) { | ||
166 | struct brw_reg interp3 = brw_vec1_grf(arg0[0].nr+1, 4); | ||
167 | |||
168 | /* Calc 1/w - just linterp wpos[3] optimized by putting the | ||
169 | * result straight into a message reg. | ||
170 | */ | ||
171 | brw_LINE(p, brw_null_reg(), interp3, deltas[0]); | ||
172 | brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]); | ||
173 | |||
174 | /* Calc w */ | ||
175 | brw_math_16( p, dst[3], | ||
176 | BRW_MATH_FUNCTION_INV, | ||
177 | BRW_MATH_SATURATE_NONE, | ||
178 | 2, brw_null_reg(), | ||
179 | BRW_MATH_PRECISION_FULL); | ||
180 | } | ||
181 | } | ||
182 | |||
183 | |||
184 | |||
185 | static void emit_linterp( struct brw_compile *p, | ||
186 | const struct brw_reg *dst, | ||
187 | GLuint mask, | ||
188 | const struct brw_reg *arg0, | ||
189 | const struct brw_reg *deltas ) | ||
190 | { | ||
191 | struct brw_reg interp[4]; | ||
192 | GLuint nr = arg0[0].nr; | ||
193 | GLuint i; | ||
194 | |||
195 | interp[0] = brw_vec1_grf(nr, 0); | ||
196 | interp[1] = brw_vec1_grf(nr, 4); | ||
197 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
198 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
199 | |||
200 | for (i = 0; i < 4; i++) { | ||
201 | if (mask & (1<<i)) { | ||
202 | brw_LINE(p, brw_null_reg(), interp[i], deltas[0]); | ||
203 | brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]); | ||
204 | } | ||
205 | } | ||
206 | } | ||
207 | |||
208 | |||
209 | static void emit_pinterp( struct brw_compile *p, | ||
210 | const struct brw_reg *dst, | ||
211 | GLuint mask, | ||
212 | const struct brw_reg *arg0, | ||
213 | const struct brw_reg *deltas, | ||
214 | const struct brw_reg *w) | ||
215 | { | ||
216 | struct brw_reg interp[4]; | ||
217 | GLuint nr = arg0[0].nr; | ||
218 | GLuint i; | ||
219 | |||
220 | interp[0] = brw_vec1_grf(nr, 0); | ||
221 | interp[1] = brw_vec1_grf(nr, 4); | ||
222 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
223 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
224 | |||
225 | for (i = 0; i < 4; i++) { | ||
226 | if (mask & (1<<i)) { | ||
227 | brw_LINE(p, brw_null_reg(), interp[i], deltas[0]); | ||
228 | brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]); | ||
229 | } | ||
230 | } | ||
231 | for (i = 0; i < 4; i++) { | ||
232 | if (mask & (1<<i)) { | ||
233 | brw_MUL(p, dst[i], dst[i], w[3]); | ||
234 | } | ||
235 | } | ||
236 | } | ||
237 | |||
238 | |||
239 | static void emit_cinterp( struct brw_compile *p, | ||
240 | const struct brw_reg *dst, | ||
241 | GLuint mask, | ||
242 | const struct brw_reg *arg0 ) | ||
243 | { | ||
244 | struct brw_reg interp[4]; | ||
245 | GLuint nr = arg0[0].nr; | ||
246 | GLuint i; | ||
247 | |||
248 | interp[0] = brw_vec1_grf(nr, 0); | ||
249 | interp[1] = brw_vec1_grf(nr, 4); | ||
250 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
251 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
252 | |||
253 | for (i = 0; i < 4; i++) { | ||
254 | if (mask & (1<<i)) { | ||
255 | brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */ | ||
256 | } | ||
257 | } | ||
258 | } | ||
259 | |||
260 | /* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ | ||
261 | static void emit_frontfacing( struct brw_compile *p, | ||
262 | const struct brw_reg *dst, | ||
263 | GLuint mask ) | ||
264 | { | ||
265 | struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); | ||
266 | GLuint i; | ||
267 | |||
268 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
269 | return; | ||
270 | |||
271 | for (i = 0; i < 4; i++) { | ||
272 | if (mask & (1<<i)) { | ||
273 | brw_MOV(p, dst[i], brw_imm_f(0.0)); | ||
274 | } | ||
275 | } | ||
276 | |||
277 | /* bit 31 is "primitive is back face", so checking < (1 << 31) gives | ||
278 | * us front face | ||
279 | */ | ||
280 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, r1_6ud, brw_imm_ud(1 << 31)); | ||
281 | for (i = 0; i < 4; i++) { | ||
282 | if (mask & (1<<i)) { | ||
283 | brw_MOV(p, dst[i], brw_imm_f(1.0)); | ||
284 | } | ||
285 | } | ||
286 | brw_set_predicate_control_flag_value(p, 0xff); | ||
287 | } | ||
288 | |||
289 | /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input | ||
290 | * looking like: | ||
291 | * | ||
292 | * arg0: q0.tl q0.tr q0.bl q0.br q1.tl q1.tr q1.bl q1.br | ||
293 | * | ||
294 | * and we're trying to produce: | ||
295 | * | ||
296 | * DDX DDY | ||
297 | * dst: (q0.tr - q0.tl) (q0.tl - q0.bl) | ||
298 | * (q0.tr - q0.tl) (q0.tr - q0.br) | ||
299 | * (q0.br - q0.bl) (q0.tl - q0.bl) | ||
300 | * (q0.br - q0.bl) (q0.tr - q0.br) | ||
301 | * (q1.tr - q1.tl) (q1.tl - q1.bl) | ||
302 | * (q1.tr - q1.tl) (q1.tr - q1.br) | ||
303 | * (q1.br - q1.bl) (q1.tl - q1.bl) | ||
304 | * (q1.br - q1.bl) (q1.tr - q1.br) | ||
305 | * | ||
306 | * and add two more quads if in 16-pixel dispatch mode. | ||
307 | * | ||
308 | * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result | ||
309 | * for each pair, and vertstride = 2 jumps us 2 elements after processing a | ||
310 | * pair. But for DDY, it's harder, as we want to produce the pairs swizzled | ||
311 | * between each other. We could probably do it like ddx and swizzle the right | ||
312 | * order later, but bail for now and just produce | ||
313 | * ((q0.tl - q0.bl)x4 (q1.tl - q1.bl)x4) | ||
314 | */ | ||
315 | void emit_ddxy(struct brw_compile *p, | ||
316 | const struct brw_reg *dst, | ||
317 | GLuint mask, | ||
318 | GLboolean is_ddx, | ||
319 | const struct brw_reg *arg0) | ||
320 | { | ||
321 | int i; | ||
322 | struct brw_reg src0, src1; | ||
323 | |||
324 | if (mask & SATURATE) | ||
325 | brw_set_saturate(p, 1); | ||
326 | for (i = 0; i < 4; i++ ) { | ||
327 | if (mask & (1<<i)) { | ||
328 | if (is_ddx) { | ||
329 | src0 = brw_reg(arg0[i].file, arg0[i].nr, 1, | ||
330 | BRW_REGISTER_TYPE_F, | ||
331 | BRW_VERTICAL_STRIDE_2, | ||
332 | BRW_WIDTH_2, | ||
333 | BRW_HORIZONTAL_STRIDE_0, | ||
334 | BRW_SWIZZLE_XYZW, BRW_WRITEMASK_XYZW); | ||
335 | src1 = brw_reg(arg0[i].file, arg0[i].nr, 0, | ||
336 | BRW_REGISTER_TYPE_F, | ||
337 | BRW_VERTICAL_STRIDE_2, | ||
338 | BRW_WIDTH_2, | ||
339 | BRW_HORIZONTAL_STRIDE_0, | ||
340 | BRW_SWIZZLE_XYZW, BRW_WRITEMASK_XYZW); | ||
341 | } else { | ||
342 | src0 = brw_reg(arg0[i].file, arg0[i].nr, 0, | ||
343 | BRW_REGISTER_TYPE_F, | ||
344 | BRW_VERTICAL_STRIDE_4, | ||
345 | BRW_WIDTH_4, | ||
346 | BRW_HORIZONTAL_STRIDE_0, | ||
347 | BRW_SWIZZLE_XYZW, BRW_WRITEMASK_XYZW); | ||
348 | src1 = brw_reg(arg0[i].file, arg0[i].nr, 2, | ||
349 | BRW_REGISTER_TYPE_F, | ||
350 | BRW_VERTICAL_STRIDE_4, | ||
351 | BRW_WIDTH_4, | ||
352 | BRW_HORIZONTAL_STRIDE_0, | ||
353 | BRW_SWIZZLE_XYZW, BRW_WRITEMASK_XYZW); | ||
354 | } | ||
355 | brw_ADD(p, dst[i], src0, negate(src1)); | ||
356 | } | ||
357 | } | ||
358 | if (mask & SATURATE) | ||
359 | brw_set_saturate(p, 0); | ||
360 | } | ||
361 | |||
362 | static void emit_alu1( struct brw_compile *p, | ||
363 | struct brw_instruction *(*func)(struct brw_compile *, | ||
364 | struct brw_reg, | ||
365 | struct brw_reg), | ||
366 | const struct brw_reg *dst, | ||
367 | GLuint mask, | ||
368 | const struct brw_reg *arg0 ) | ||
369 | { | ||
370 | GLuint i; | ||
371 | |||
372 | if (mask & SATURATE) | ||
373 | brw_set_saturate(p, 1); | ||
374 | |||
375 | for (i = 0; i < 4; i++) { | ||
376 | if (mask & (1<<i)) { | ||
377 | func(p, dst[i], arg0[i]); | ||
378 | } | ||
379 | } | ||
380 | |||
381 | if (mask & SATURATE) | ||
382 | brw_set_saturate(p, 0); | ||
383 | } | ||
384 | |||
385 | |||
386 | static void emit_alu2( struct brw_compile *p, | ||
387 | struct brw_instruction *(*func)(struct brw_compile *, | ||
388 | struct brw_reg, | ||
389 | struct brw_reg, | ||
390 | struct brw_reg), | ||
391 | const struct brw_reg *dst, | ||
392 | GLuint mask, | ||
393 | const struct brw_reg *arg0, | ||
394 | const struct brw_reg *arg1 ) | ||
395 | { | ||
396 | GLuint i; | ||
397 | |||
398 | if (mask & SATURATE) | ||
399 | brw_set_saturate(p, 1); | ||
400 | |||
401 | for (i = 0; i < 4; i++) { | ||
402 | if (mask & (1<<i)) { | ||
403 | func(p, dst[i], arg0[i], arg1[i]); | ||
404 | } | ||
405 | } | ||
406 | |||
407 | if (mask & SATURATE) | ||
408 | brw_set_saturate(p, 0); | ||
409 | } | ||
410 | |||
411 | |||
412 | static void emit_mad( struct brw_compile *p, | ||
413 | const struct brw_reg *dst, | ||
414 | GLuint mask, | ||
415 | const struct brw_reg *arg0, | ||
416 | const struct brw_reg *arg1, | ||
417 | const struct brw_reg *arg2 ) | ||
418 | { | ||
419 | GLuint i; | ||
420 | |||
421 | for (i = 0; i < 4; i++) { | ||
422 | if (mask & (1<<i)) { | ||
423 | brw_MUL(p, dst[i], arg0[i], arg1[i]); | ||
424 | |||
425 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
426 | brw_ADD(p, dst[i], dst[i], arg2[i]); | ||
427 | brw_set_saturate(p, 0); | ||
428 | } | ||
429 | } | ||
430 | } | ||
431 | |||
432 | static void emit_trunc( struct brw_compile *p, | ||
433 | const struct brw_reg *dst, | ||
434 | GLuint mask, | ||
435 | const struct brw_reg *arg0) | ||
436 | { | ||
437 | GLuint i; | ||
438 | |||
439 | for (i = 0; i < 4; i++) { | ||
440 | if (mask & (1<<i)) { | ||
441 | brw_RNDZ(p, dst[i], arg0[i]); | ||
442 | } | ||
443 | } | ||
444 | } | ||
445 | |||
446 | static void emit_lrp( struct brw_compile *p, | ||
447 | const struct brw_reg *dst, | ||
448 | GLuint mask, | ||
449 | const struct brw_reg *arg0, | ||
450 | const struct brw_reg *arg1, | ||
451 | const struct brw_reg *arg2 ) | ||
452 | { | ||
453 | GLuint i; | ||
454 | |||
455 | /* Uses dst as a temporary: | ||
456 | */ | ||
457 | for (i = 0; i < 4; i++) { | ||
458 | if (mask & (1<<i)) { | ||
459 | /* Can I use the LINE instruction for this? | ||
460 | */ | ||
461 | brw_ADD(p, dst[i], negate(arg0[i]), brw_imm_f(1.0)); | ||
462 | brw_MUL(p, brw_null_reg(), dst[i], arg2[i]); | ||
463 | |||
464 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
465 | brw_MAC(p, dst[i], arg0[i], arg1[i]); | ||
466 | brw_set_saturate(p, 0); | ||
467 | } | ||
468 | } | ||
469 | } | ||
470 | |||
471 | static void emit_sop( struct brw_compile *p, | ||
472 | const struct brw_reg *dst, | ||
473 | GLuint mask, | ||
474 | GLuint cond, | ||
475 | const struct brw_reg *arg0, | ||
476 | const struct brw_reg *arg1 ) | ||
477 | { | ||
478 | GLuint i; | ||
479 | |||
480 | for (i = 0; i < 4; i++) { | ||
481 | if (mask & (1<<i)) { | ||
482 | brw_MOV(p, dst[i], brw_imm_f(0)); | ||
483 | brw_CMP(p, brw_null_reg(), cond, arg0[i], arg1[i]); | ||
484 | brw_MOV(p, dst[i], brw_imm_f(1.0)); | ||
485 | brw_set_predicate_control_flag_value(p, 0xff); | ||
486 | } | ||
487 | } | ||
488 | } | ||
489 | |||
490 | static void emit_slt( struct brw_compile *p, | ||
491 | const struct brw_reg *dst, | ||
492 | GLuint mask, | ||
493 | const struct brw_reg *arg0, | ||
494 | const struct brw_reg *arg1 ) | ||
495 | { | ||
496 | emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1); | ||
497 | } | ||
498 | |||
499 | static void emit_sle( struct brw_compile *p, | ||
500 | const struct brw_reg *dst, | ||
501 | GLuint mask, | ||
502 | const struct brw_reg *arg0, | ||
503 | const struct brw_reg *arg1 ) | ||
504 | { | ||
505 | emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1); | ||
506 | } | ||
507 | |||
508 | static void emit_sgt( struct brw_compile *p, | ||
509 | const struct brw_reg *dst, | ||
510 | GLuint mask, | ||
511 | const struct brw_reg *arg0, | ||
512 | const struct brw_reg *arg1 ) | ||
513 | { | ||
514 | emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1); | ||
515 | } | ||
516 | |||
517 | static void emit_sge( struct brw_compile *p, | ||
518 | const struct brw_reg *dst, | ||
519 | GLuint mask, | ||
520 | const struct brw_reg *arg0, | ||
521 | const struct brw_reg *arg1 ) | ||
522 | { | ||
523 | emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1); | ||
524 | } | ||
525 | |||
526 | static void emit_seq( struct brw_compile *p, | ||
527 | const struct brw_reg *dst, | ||
528 | GLuint mask, | ||
529 | const struct brw_reg *arg0, | ||
530 | const struct brw_reg *arg1 ) | ||
531 | { | ||
532 | emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1); | ||
533 | } | ||
534 | |||
535 | static void emit_sne( struct brw_compile *p, | ||
536 | const struct brw_reg *dst, | ||
537 | GLuint mask, | ||
538 | const struct brw_reg *arg0, | ||
539 | const struct brw_reg *arg1 ) | ||
540 | { | ||
541 | emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1); | ||
542 | } | ||
543 | |||
544 | static void emit_cmp( struct brw_compile *p, | ||
545 | const struct brw_reg *dst, | ||
546 | GLuint mask, | ||
547 | const struct brw_reg *arg0, | ||
548 | const struct brw_reg *arg1, | ||
549 | const struct brw_reg *arg2 ) | ||
550 | { | ||
551 | GLuint i; | ||
552 | |||
553 | for (i = 0; i < 4; i++) { | ||
554 | if (mask & (1<<i)) { | ||
555 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
556 | brw_MOV(p, dst[i], arg2[i]); | ||
557 | brw_set_saturate(p, 0); | ||
558 | |||
559 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], brw_imm_f(0)); | ||
560 | |||
561 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
562 | brw_MOV(p, dst[i], arg1[i]); | ||
563 | brw_set_saturate(p, 0); | ||
564 | brw_set_predicate_control_flag_value(p, 0xff); | ||
565 | } | ||
566 | } | ||
567 | } | ||
568 | |||
569 | static void emit_max( struct brw_compile *p, | ||
570 | const struct brw_reg *dst, | ||
571 | GLuint mask, | ||
572 | const struct brw_reg *arg0, | ||
573 | const struct brw_reg *arg1 ) | ||
574 | { | ||
575 | GLuint i; | ||
576 | |||
577 | for (i = 0; i < 4; i++) { | ||
578 | if (mask & (1<<i)) { | ||
579 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
580 | brw_MOV(p, dst[i], arg0[i]); | ||
581 | brw_set_saturate(p, 0); | ||
582 | |||
583 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]); | ||
584 | |||
585 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
586 | brw_MOV(p, dst[i], arg1[i]); | ||
587 | brw_set_saturate(p, 0); | ||
588 | brw_set_predicate_control_flag_value(p, 0xff); | ||
589 | } | ||
590 | } | ||
591 | } | ||
592 | |||
593 | static void emit_min( struct brw_compile *p, | ||
594 | const struct brw_reg *dst, | ||
595 | GLuint mask, | ||
596 | const struct brw_reg *arg0, | ||
597 | const struct brw_reg *arg1 ) | ||
598 | { | ||
599 | GLuint i; | ||
600 | |||
601 | for (i = 0; i < 4; i++) { | ||
602 | if (mask & (1<<i)) { | ||
603 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
604 | brw_MOV(p, dst[i], arg1[i]); | ||
605 | brw_set_saturate(p, 0); | ||
606 | |||
607 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]); | ||
608 | |||
609 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
610 | brw_MOV(p, dst[i], arg0[i]); | ||
611 | brw_set_saturate(p, 0); | ||
612 | brw_set_predicate_control_flag_value(p, 0xff); | ||
613 | } | ||
614 | } | ||
615 | } | ||
616 | |||
617 | |||
618 | static void emit_dp3( struct brw_compile *p, | ||
619 | const struct brw_reg *dst, | ||
620 | GLuint mask, | ||
621 | const struct brw_reg *arg0, | ||
622 | const struct brw_reg *arg1 ) | ||
623 | { | ||
624 | int dst_chan = ffs(mask & BRW_WRITEMASK_XYZW) - 1; | ||
625 | |||
626 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
627 | return; /* Do not emit dead code */ | ||
628 | |||
629 | assert(util_is_power_of_two(mask & BRW_WRITEMASK_XYZW)); | ||
630 | |||
631 | brw_MUL(p, brw_null_reg(), arg0[0], arg1[0]); | ||
632 | brw_MAC(p, brw_null_reg(), arg0[1], arg1[1]); | ||
633 | |||
634 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
635 | brw_MAC(p, dst[dst_chan], arg0[2], arg1[2]); | ||
636 | brw_set_saturate(p, 0); | ||
637 | } | ||
638 | |||
639 | |||
640 | static void emit_dp4( struct brw_compile *p, | ||
641 | const struct brw_reg *dst, | ||
642 | GLuint mask, | ||
643 | const struct brw_reg *arg0, | ||
644 | const struct brw_reg *arg1 ) | ||
645 | { | ||
646 | int dst_chan = ffs(mask & BRW_WRITEMASK_XYZW) - 1; | ||
647 | |||
648 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
649 | return; /* Do not emit dead code */ | ||
650 | |||
651 | assert(util_is_power_of_two(mask & BRW_WRITEMASK_XYZW)); | ||
652 | |||
653 | brw_MUL(p, brw_null_reg(), arg0[0], arg1[0]); | ||
654 | brw_MAC(p, brw_null_reg(), arg0[1], arg1[1]); | ||
655 | brw_MAC(p, brw_null_reg(), arg0[2], arg1[2]); | ||
656 | |||
657 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
658 | brw_MAC(p, dst[dst_chan], arg0[3], arg1[3]); | ||
659 | brw_set_saturate(p, 0); | ||
660 | } | ||
661 | |||
662 | |||
663 | static void emit_dph( struct brw_compile *p, | ||
664 | const struct brw_reg *dst, | ||
665 | GLuint mask, | ||
666 | const struct brw_reg *arg0, | ||
667 | const struct brw_reg *arg1 ) | ||
668 | { | ||
669 | const int dst_chan = ffs(mask & BRW_WRITEMASK_XYZW) - 1; | ||
670 | |||
671 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
672 | return; /* Do not emit dead code */ | ||
673 | |||
674 | assert(util_is_power_of_two(mask & BRW_WRITEMASK_XYZW)); | ||
675 | |||
676 | brw_MUL(p, brw_null_reg(), arg0[0], arg1[0]); | ||
677 | brw_MAC(p, brw_null_reg(), arg0[1], arg1[1]); | ||
678 | brw_MAC(p, dst[dst_chan], arg0[2], arg1[2]); | ||
679 | |||
680 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
681 | brw_ADD(p, dst[dst_chan], dst[dst_chan], arg1[3]); | ||
682 | brw_set_saturate(p, 0); | ||
683 | } | ||
684 | |||
685 | |||
686 | static void emit_xpd( struct brw_compile *p, | ||
687 | const struct brw_reg *dst, | ||
688 | GLuint mask, | ||
689 | const struct brw_reg *arg0, | ||
690 | const struct brw_reg *arg1 ) | ||
691 | { | ||
692 | GLuint i; | ||
693 | |||
694 | assert((mask & BRW_WRITEMASK_W) != BRW_WRITEMASK_W); | ||
695 | |||
696 | for (i = 0 ; i < 3; i++) { | ||
697 | if (mask & (1<<i)) { | ||
698 | GLuint i2 = (i+2)%3; | ||
699 | GLuint i1 = (i+1)%3; | ||
700 | |||
701 | brw_MUL(p, brw_null_reg(), negate(arg0[i2]), arg1[i1]); | ||
702 | |||
703 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
704 | brw_MAC(p, dst[i], arg0[i1], arg1[i2]); | ||
705 | brw_set_saturate(p, 0); | ||
706 | } | ||
707 | } | ||
708 | } | ||
709 | |||
710 | |||
711 | static void emit_math1( struct brw_compile *p, | ||
712 | GLuint function, | ||
713 | const struct brw_reg *dst, | ||
714 | GLuint mask, | ||
715 | const struct brw_reg *arg0 ) | ||
716 | { | ||
717 | int dst_chan = ffs(mask & BRW_WRITEMASK_XYZW) - 1; | ||
718 | |||
719 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
720 | return; /* Do not emit dead code */ | ||
721 | |||
722 | assert(util_is_power_of_two(mask & BRW_WRITEMASK_XYZW)); | ||
723 | |||
724 | brw_MOV(p, brw_message_reg(2), arg0[0]); | ||
725 | |||
726 | /* Send two messages to perform all 16 operations: | ||
727 | */ | ||
728 | brw_math_16(p, | ||
729 | dst[dst_chan], | ||
730 | function, | ||
731 | (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, | ||
732 | 2, | ||
733 | brw_null_reg(), | ||
734 | BRW_MATH_PRECISION_FULL); | ||
735 | } | ||
736 | |||
737 | |||
738 | static void emit_math2( struct brw_compile *p, | ||
739 | GLuint function, | ||
740 | const struct brw_reg *dst, | ||
741 | GLuint mask, | ||
742 | const struct brw_reg *arg0, | ||
743 | const struct brw_reg *arg1) | ||
744 | { | ||
745 | int dst_chan = ffs(mask & BRW_WRITEMASK_XYZW) - 1; | ||
746 | |||
747 | if (!(mask & BRW_WRITEMASK_XYZW)) | ||
748 | return; /* Do not emit dead code */ | ||
749 | |||
750 | assert(util_is_power_of_two(mask & BRW_WRITEMASK_XYZW)); | ||
751 | |||
752 | brw_push_insn_state(p); | ||
753 | |||
754 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
755 | brw_MOV(p, brw_message_reg(2), arg0[0]); | ||
756 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); | ||
757 | brw_MOV(p, brw_message_reg(4), sechalf(arg0[0])); | ||
758 | |||
759 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
760 | brw_MOV(p, brw_message_reg(3), arg1[0]); | ||
761 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); | ||
762 | brw_MOV(p, brw_message_reg(5), sechalf(arg1[0])); | ||
763 | |||
764 | |||
765 | /* Send two messages to perform all 16 operations: | ||
766 | */ | ||
767 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
768 | brw_math(p, | ||
769 | dst[dst_chan], | ||
770 | function, | ||
771 | (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, | ||
772 | 2, | ||
773 | brw_null_reg(), | ||
774 | BRW_MATH_DATA_VECTOR, | ||
775 | BRW_MATH_PRECISION_FULL); | ||
776 | |||
777 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); | ||
778 | brw_math(p, | ||
779 | offset(dst[dst_chan],1), | ||
780 | function, | ||
781 | (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, | ||
782 | 4, | ||
783 | brw_null_reg(), | ||
784 | BRW_MATH_DATA_VECTOR, | ||
785 | BRW_MATH_PRECISION_FULL); | ||
786 | |||
787 | brw_pop_insn_state(p); | ||
788 | } | ||
789 | |||
790 | |||
791 | |||
792 | static void emit_tex( struct brw_wm_compile *c, | ||
793 | const struct brw_wm_instruction *inst, | ||
794 | struct brw_reg *dst, | ||
795 | GLuint dst_flags, | ||
796 | struct brw_reg *coord, | ||
797 | GLuint sampler) | ||
798 | { | ||
799 | struct brw_compile *p = &c->func; | ||
800 | GLuint msgLength, responseLength; | ||
801 | GLuint i, nr; | ||
802 | GLuint emit; | ||
803 | GLuint msg_type; | ||
804 | GLboolean shadow = FALSE; | ||
805 | |||
806 | /* How many input regs are there? | ||
807 | */ | ||
808 | switch (inst->target) { | ||
809 | case TGSI_TEXTURE_1D: | ||
810 | emit = BRW_WRITEMASK_X; | ||
811 | nr = 1; | ||
812 | break; | ||
813 | case TGSI_TEXTURE_SHADOW1D: | ||
814 | emit = BRW_WRITEMASK_XW; | ||
815 | nr = 4; | ||
816 | shadow = TRUE; | ||
817 | break; | ||
818 | case TGSI_TEXTURE_2D: | ||
819 | emit = BRW_WRITEMASK_XY; | ||
820 | nr = 2; | ||
821 | break; | ||
822 | case TGSI_TEXTURE_SHADOW2D: | ||
823 | case TGSI_TEXTURE_SHADOWRECT: | ||
824 | emit = BRW_WRITEMASK_XYW; | ||
825 | nr = 4; | ||
826 | shadow = TRUE; | ||
827 | break; | ||
828 | case TGSI_TEXTURE_3D: | ||
829 | case TGSI_TEXTURE_CUBE: | ||
830 | emit = BRW_WRITEMASK_XYZ; | ||
831 | nr = 3; | ||
832 | break; | ||
833 | default: | ||
834 | /* unexpected target */ | ||
835 | abort(); | ||
836 | } | ||
837 | |||
838 | msgLength = 1; | ||
839 | |||
840 | for (i = 0; i < nr; i++) { | ||
841 | static const GLuint swz[4] = {0,1,2,2}; | ||
842 | if (emit & (1<<i)) | ||
843 | brw_MOV(p, brw_message_reg(msgLength+1), coord[swz[i]]); | ||
844 | else | ||
845 | brw_MOV(p, brw_message_reg(msgLength+1), brw_imm_f(0)); | ||
846 | msgLength += 2; | ||
847 | } | ||
848 | |||
849 | responseLength = 8; /* always */ | ||
850 | |||
851 | if (p->brw->gen == 5) { | ||
852 | if (shadow) | ||
853 | msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; | ||
854 | else | ||
855 | msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; | ||
856 | } else { | ||
857 | if (shadow) | ||
858 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; | ||
859 | else | ||
860 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; | ||
861 | } | ||
862 | |||
863 | brw_SAMPLE(p, | ||
864 | retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), | ||
865 | 1, | ||
866 | retype(c->payload.depth[0].hw_reg, BRW_REGISTER_TYPE_UW), | ||
867 | BTI_TEXTURE(inst->tex_unit), | ||
868 | sampler, /* sampler index */ | ||
869 | inst->writemask, | ||
870 | msg_type, | ||
871 | responseLength, | ||
872 | msgLength, | ||
873 | 0, | ||
874 | 1, | ||
875 | BRW_SAMPLER_SIMD_MODE_SIMD16); | ||
876 | } | ||
877 | |||
878 | |||
879 | static void emit_txb( struct brw_wm_compile *c, | ||
880 | const struct brw_wm_instruction *inst, | ||
881 | struct brw_reg *dst, | ||
882 | GLuint dst_flags, | ||
883 | struct brw_reg *coord, | ||
884 | GLuint sampler ) | ||
885 | { | ||
886 | struct brw_compile *p = &c->func; | ||
887 | GLuint msgLength; | ||
888 | GLuint msg_type; | ||
889 | /* Shadow ignored for txb. | ||
890 | */ | ||
891 | switch (inst->target) { | ||
892 | case TGSI_TEXTURE_1D: | ||
893 | case TGSI_TEXTURE_SHADOW1D: | ||
894 | brw_MOV(p, brw_message_reg(2), coord[0]); | ||
895 | brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); | ||
896 | brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); | ||
897 | break; | ||
898 | case TGSI_TEXTURE_2D: | ||
899 | case TGSI_TEXTURE_RECT: | ||
900 | case TGSI_TEXTURE_SHADOW2D: | ||
901 | case TGSI_TEXTURE_SHADOWRECT: | ||
902 | brw_MOV(p, brw_message_reg(2), coord[0]); | ||
903 | brw_MOV(p, brw_message_reg(4), coord[1]); | ||
904 | brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); | ||
905 | break; | ||
906 | case TGSI_TEXTURE_3D: | ||
907 | case TGSI_TEXTURE_CUBE: | ||
908 | brw_MOV(p, brw_message_reg(2), coord[0]); | ||
909 | brw_MOV(p, brw_message_reg(4), coord[1]); | ||
910 | brw_MOV(p, brw_message_reg(6), coord[2]); | ||
911 | break; | ||
912 | default: | ||
913 | /* unexpected target */ | ||
914 | abort(); | ||
915 | } | ||
916 | |||
917 | brw_MOV(p, brw_message_reg(8), coord[3]); | ||
918 | msgLength = 9; | ||
919 | |||
920 | if (p->brw->gen == 5) | ||
921 | msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; | ||
922 | else | ||
923 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; | ||
924 | |||
925 | brw_SAMPLE(p, | ||
926 | retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), | ||
927 | 1, | ||
928 | retype(c->payload.depth[0].hw_reg, BRW_REGISTER_TYPE_UW), | ||
929 | BTI_TEXTURE(inst->tex_unit), | ||
930 | sampler, /* sampler index */ | ||
931 | inst->writemask, | ||
932 | msg_type, | ||
933 | 8, /* responseLength */ | ||
934 | msgLength, | ||
935 | 0, | ||
936 | 1, | ||
937 | BRW_SAMPLER_SIMD_MODE_SIMD16); | ||
938 | } | ||
939 | |||
940 | |||
941 | static void emit_lit( struct brw_compile *p, | ||
942 | const struct brw_reg *dst, | ||
943 | GLuint mask, | ||
944 | const struct brw_reg *arg0 ) | ||
945 | { | ||
946 | assert((mask & BRW_WRITEMASK_XW) == 0); | ||
947 | |||
948 | if (mask & BRW_WRITEMASK_Y) { | ||
949 | brw_set_saturate(p, (mask & SATURATE) ? 1 : 0); | ||
950 | brw_MOV(p, dst[1], arg0[0]); | ||
951 | brw_set_saturate(p, 0); | ||
952 | } | ||
953 | |||
954 | if (mask & BRW_WRITEMASK_Z) { | ||
955 | emit_math2(p, BRW_MATH_FUNCTION_POW, | ||
956 | &dst[2], | ||
957 | BRW_WRITEMASK_X | (mask & SATURATE), | ||
958 | &arg0[1], | ||
959 | &arg0[3]); | ||
960 | } | ||
961 | |||
962 | /* Ordinarily you'd use an iff statement to skip or shortcircuit | ||
963 | * some of the POW calculations above, but 16-wide iff statements | ||
964 | * seem to lock c1 hardware, so this is a nasty workaround: | ||
965 | */ | ||
966 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_LE, arg0[0], brw_imm_f(0)); | ||
967 | { | ||
968 | if (mask & BRW_WRITEMASK_Y) | ||
969 | brw_MOV(p, dst[1], brw_imm_f(0)); | ||
970 | |||
971 | if (mask & BRW_WRITEMASK_Z) | ||
972 | brw_MOV(p, dst[2], brw_imm_f(0)); | ||
973 | } | ||
974 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
975 | } | ||
976 | |||
977 | |||
978 | /* Kill pixel - set execution mask to zero for those pixels which | ||
979 | * fail. | ||
980 | */ | ||
981 | static void emit_kil( struct brw_wm_compile *c, | ||
982 | struct brw_reg *arg0) | ||
983 | { | ||
984 | struct brw_compile *p = &c->func; | ||
985 | struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); | ||
986 | GLuint i; | ||
987 | |||
988 | /* XXX - usually won't need 4 compares! | ||
989 | */ | ||
990 | for (i = 0; i < 4; i++) { | ||
991 | brw_push_insn_state(p); | ||
992 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0)); | ||
993 | brw_set_predicate_control_flag_value(p, 0xff); | ||
994 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
995 | brw_AND(p, r0uw, brw_flag_reg(), r0uw); | ||
996 | brw_pop_insn_state(p); | ||
997 | } | ||
998 | } | ||
999 | |||
1000 | /* KILLP kills the pixels that are currently executing, not based on a test | ||
1001 | * of the arguments. | ||
1002 | */ | ||
1003 | static void emit_killp( struct brw_wm_compile *c ) | ||
1004 | { | ||
1005 | struct brw_compile *p = &c->func; | ||
1006 | struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); | ||
1007 | |||
1008 | brw_push_insn_state(p); | ||
1009 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1010 | brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ | ||
1011 | brw_AND(p, r0uw, c->emit_mask_reg, r0uw); | ||
1012 | brw_pop_insn_state(p); | ||
1013 | } | ||
1014 | |||
1015 | static void fire_fb_write( struct brw_wm_compile *c, | ||
1016 | GLuint base_reg, | ||
1017 | GLuint nr, | ||
1018 | GLuint target, | ||
1019 | GLuint eot ) | ||
1020 | { | ||
1021 | struct brw_compile *p = &c->func; | ||
1022 | |||
1023 | /* Pass through control information: | ||
1024 | */ | ||
1025 | /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ | ||
1026 | { | ||
1027 | brw_push_insn_state(p); | ||
1028 | brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */ | ||
1029 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1030 | brw_MOV(p, | ||
1031 | brw_message_reg(base_reg + 1), | ||
1032 | brw_vec8_grf(1, 0)); | ||
1033 | brw_pop_insn_state(p); | ||
1034 | } | ||
1035 | |||
1036 | /* Send framebuffer write message: */ | ||
1037 | /* send (16) null.0<1>:uw m0 r0.0<8;8,1>:uw 0x85a04000:ud { Align1 EOT } */ | ||
1038 | brw_fb_WRITE(p, | ||
1039 | retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW), | ||
1040 | base_reg, | ||
1041 | retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), | ||
1042 | target, | ||
1043 | nr, | ||
1044 | 0, | ||
1045 | eot); | ||
1046 | } | ||
1047 | |||
1048 | |||
1049 | static void emit_aa( struct brw_wm_compile *c, | ||
1050 | struct brw_reg *arg1, | ||
1051 | GLuint reg ) | ||
1052 | { | ||
1053 | struct brw_compile *p = &c->func; | ||
1054 | GLuint comp = c->key.aa_dest_stencil_reg / 2; | ||
1055 | GLuint off = c->key.aa_dest_stencil_reg % 2; | ||
1056 | struct brw_reg aa = offset(arg1[comp], off); | ||
1057 | |||
1058 | brw_push_insn_state(p); | ||
1059 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); /* ?? */ | ||
1060 | brw_MOV(p, brw_message_reg(reg), aa); | ||
1061 | brw_pop_insn_state(p); | ||
1062 | } | ||
1063 | |||
1064 | |||
1065 | /* Post-fragment-program processing. Send the results to the | ||
1066 | * framebuffer. | ||
1067 | * \param arg0 the fragment color | ||
1068 | * \param arg1 the pass-through depth value | ||
1069 | * \param arg2 the shader-computed depth value | ||
1070 | */ | ||
1071 | static void emit_fb_write( struct brw_wm_compile *c, | ||
1072 | struct brw_reg *arg0, | ||
1073 | struct brw_reg *arg1, | ||
1074 | struct brw_reg *arg2, | ||
1075 | GLuint target, | ||
1076 | GLuint eot) | ||
1077 | { | ||
1078 | struct brw_compile *p = &c->func; | ||
1079 | GLuint nr = 2; | ||
1080 | GLuint channel; | ||
1081 | |||
1082 | /* Reserve a space for AA - may not be needed: | ||
1083 | */ | ||
1084 | if (c->key.aa_dest_stencil_reg) | ||
1085 | nr += 1; | ||
1086 | |||
1087 | /* I don't really understand how this achieves the color interleave | ||
1088 | * (ie RGBARGBA) in the result: [Do the saturation here] | ||
1089 | */ | ||
1090 | { | ||
1091 | brw_push_insn_state(p); | ||
1092 | |||
1093 | for (channel = 0; channel < 4; channel++) { | ||
1094 | /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ | ||
1095 | /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ | ||
1096 | |||
1097 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1098 | brw_MOV(p, | ||
1099 | brw_message_reg(nr + channel), | ||
1100 | arg0[channel]); | ||
1101 | |||
1102 | brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); | ||
1103 | brw_MOV(p, | ||
1104 | brw_message_reg(nr + channel + 4), | ||
1105 | sechalf(arg0[channel])); | ||
1106 | } | ||
1107 | |||
1108 | /* skip over the regs populated above: | ||
1109 | */ | ||
1110 | nr += 8; | ||
1111 | |||
1112 | brw_pop_insn_state(p); | ||
1113 | } | ||
1114 | |||
1115 | if (c->key.source_depth_to_render_target) | ||
1116 | { | ||
1117 | if (c->key.computes_depth) | ||
1118 | brw_MOV(p, brw_message_reg(nr), arg2[2]); | ||
1119 | else | ||
1120 | brw_MOV(p, brw_message_reg(nr), arg1[1]); /* ? */ | ||
1121 | |||
1122 | nr += 2; | ||
1123 | } | ||
1124 | |||
1125 | if (c->key.dest_depth_reg) | ||
1126 | { | ||
1127 | GLuint comp = c->key.dest_depth_reg / 2; | ||
1128 | GLuint off = c->key.dest_depth_reg % 2; | ||
1129 | |||
1130 | if (off != 0) { | ||
1131 | brw_push_insn_state(p); | ||
1132 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1133 | |||
1134 | brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1)); | ||
1135 | /* 2nd half? */ | ||
1136 | brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]); | ||
1137 | brw_pop_insn_state(p); | ||
1138 | } | ||
1139 | else { | ||
1140 | brw_MOV(p, brw_message_reg(nr), arg1[comp]); | ||
1141 | } | ||
1142 | nr += 2; | ||
1143 | } | ||
1144 | |||
1145 | if (!c->key.runtime_check_aads_emit) { | ||
1146 | if (c->key.aa_dest_stencil_reg) | ||
1147 | emit_aa(c, arg1, 2); | ||
1148 | |||
1149 | fire_fb_write(c, 0, nr, target, eot); | ||
1150 | } | ||
1151 | else { | ||
1152 | struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); | ||
1153 | struct brw_reg ip = brw_ip_reg(); | ||
1154 | struct brw_instruction *jmp; | ||
1155 | |||
1156 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1157 | brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); | ||
1158 | brw_AND(p, | ||
1159 | v1_null_ud, | ||
1160 | get_element_ud(brw_vec8_grf(1,0), 6), | ||
1161 | brw_imm_ud(1<<26)); | ||
1162 | |||
1163 | jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)); | ||
1164 | { | ||
1165 | emit_aa(c, arg1, 2); | ||
1166 | fire_fb_write(c, 0, nr, target, eot); | ||
1167 | /* note - thread killed in subroutine */ | ||
1168 | } | ||
1169 | brw_land_fwd_jump(p, jmp); | ||
1170 | |||
1171 | /* ELSE: Shuffle up one register to fill in the hole left for AA: | ||
1172 | */ | ||
1173 | fire_fb_write(c, 1, nr-1, target, eot); | ||
1174 | } | ||
1175 | } | ||
1176 | |||
1177 | |||
1178 | /** | ||
1179 | * Move a GPR to scratch memory. | ||
1180 | */ | ||
1181 | static void emit_spill( struct brw_wm_compile *c, | ||
1182 | struct brw_reg reg, | ||
1183 | GLuint slot ) | ||
1184 | { | ||
1185 | struct brw_compile *p = &c->func; | ||
1186 | |||
1187 | /* | ||
1188 | mov (16) m2.0<1>:ud r2.0<8;8,1>:ud { Align1 Compr } | ||
1189 | */ | ||
1190 | brw_MOV(p, brw_message_reg(2), reg); | ||
1191 | |||
1192 | /* | ||
1193 | mov (1) r0.2<1>:d 0x00000080:d { Align1 NoMask } | ||
1194 | send (16) null.0<1>:uw m1 r0.0<8;8,1>:uw 0x053003ff:ud { Align1 } | ||
1195 | */ | ||
1196 | brw_dp_WRITE_16(p, | ||
1197 | retype(vec16(brw_vec8_grf(0, 0)), BRW_REGISTER_TYPE_UW), | ||
1198 | slot); | ||
1199 | } | ||
1200 | |||
1201 | |||
1202 | /** | ||
1203 | * Load a GPR from scratch memory. | ||
1204 | */ | ||
1205 | static void emit_unspill( struct brw_wm_compile *c, | ||
1206 | struct brw_reg reg, | ||
1207 | GLuint slot ) | ||
1208 | { | ||
1209 | struct brw_compile *p = &c->func; | ||
1210 | |||
1211 | /* Slot 0 is the undef value. | ||
1212 | */ | ||
1213 | if (slot == 0) { | ||
1214 | brw_MOV(p, reg, brw_imm_f(0)); | ||
1215 | return; | ||
1216 | } | ||
1217 | |||
1218 | /* | ||
1219 | mov (1) r0.2<1>:d 0x000000c0:d { Align1 NoMask } | ||
1220 | send (16) r110.0<1>:uw m1 r0.0<8;8,1>:uw 0x041243ff:ud { Align1 } | ||
1221 | */ | ||
1222 | |||
1223 | brw_dp_READ_16(p, | ||
1224 | retype(vec16(reg), BRW_REGISTER_TYPE_UW), | ||
1225 | slot); | ||
1226 | } | ||
1227 | |||
1228 | |||
1229 | /** | ||
1230 | * Retrieve up to 4 GEN4 register pairs for the given wm reg: | ||
1231 | * Args with unspill_reg != 0 will be loaded from scratch memory. | ||
1232 | */ | ||
1233 | static void get_argument_regs( struct brw_wm_compile *c, | ||
1234 | struct brw_wm_ref *arg[], | ||
1235 | struct brw_reg *regs ) | ||
1236 | { | ||
1237 | GLuint i; | ||
1238 | |||
1239 | for (i = 0; i < 4; i++) { | ||
1240 | if (arg[i]) { | ||
1241 | if (arg[i]->unspill_reg) | ||
1242 | emit_unspill(c, | ||
1243 | brw_vec8_grf(arg[i]->unspill_reg, 0), | ||
1244 | arg[i]->value->spill_slot); | ||
1245 | |||
1246 | regs[i] = arg[i]->hw_reg; | ||
1247 | } | ||
1248 | else { | ||
1249 | regs[i] = brw_null_reg(); | ||
1250 | } | ||
1251 | } | ||
1252 | } | ||
1253 | |||
1254 | |||
1255 | /** | ||
1256 | * For values that have a spill_slot!=0, write those regs to scratch memory. | ||
1257 | */ | ||
1258 | static void spill_values( struct brw_wm_compile *c, | ||
1259 | struct brw_wm_value *values, | ||
1260 | GLuint nr ) | ||
1261 | { | ||
1262 | GLuint i; | ||
1263 | |||
1264 | for (i = 0; i < nr; i++) | ||
1265 | if (values[i].spill_slot) | ||
1266 | emit_spill(c, values[i].hw_reg, values[i].spill_slot); | ||
1267 | } | ||
1268 | |||
1269 | |||
1270 | /* Emit the fragment program instructions here. | ||
1271 | */ | ||
1272 | void brw_wm_emit( struct brw_wm_compile *c ) | ||
1273 | { | ||
1274 | struct brw_compile *p = &c->func; | ||
1275 | GLuint insn; | ||
1276 | |||
1277 | brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); | ||
1278 | |||
1279 | /* Check if any of the payload regs need to be spilled: | ||
1280 | */ | ||
1281 | spill_values(c, c->payload.depth, 4); | ||
1282 | spill_values(c, c->creg, c->nr_creg); | ||
1283 | spill_values(c, c->payload.input_interp, PIPE_MAX_SHADER_INPUTS); | ||
1284 | |||
1285 | |||
1286 | for (insn = 0; insn < c->nr_insns; insn++) { | ||
1287 | |||
1288 | struct brw_wm_instruction *inst = &c->instruction[insn]; | ||
1289 | struct brw_reg args[3][4], dst[4]; | ||
1290 | GLuint i, dst_flags; | ||
1291 | |||
1292 | /* Get argument regs: | ||
1293 | */ | ||
1294 | for (i = 0; i < 3; i++) | ||
1295 | get_argument_regs(c, inst->src[i], args[i]); | ||
1296 | |||
1297 | /* Get dest regs: | ||
1298 | */ | ||
1299 | for (i = 0; i < 4; i++) | ||
1300 | if (inst->dst[i]) | ||
1301 | dst[i] = inst->dst[i]->hw_reg; | ||
1302 | else | ||
1303 | dst[i] = brw_null_reg(); | ||
1304 | |||
1305 | /* Flags | ||
1306 | */ | ||
1307 | dst_flags = inst->writemask; | ||
1308 | if (inst->saturate) | ||
1309 | dst_flags |= SATURATE; | ||
1310 | |||
1311 | switch (inst->opcode) { | ||
1312 | /* Generated instructions for calculating triangle interpolants: | ||
1313 | */ | ||
1314 | case WM_PIXELXY: | ||
1315 | emit_pixel_xy(p, dst, dst_flags); | ||
1316 | break; | ||
1317 | |||
1318 | case WM_DELTAXY: | ||
1319 | emit_delta_xy(p, dst, dst_flags, args[0]); | ||
1320 | break; | ||
1321 | |||
1322 | case WM_WPOSXY: | ||
1323 | emit_wpos_xy(c, dst, dst_flags, args[0]); | ||
1324 | break; | ||
1325 | |||
1326 | case WM_PIXELW: | ||
1327 | emit_pixel_w(p, dst, dst_flags, args[0], args[1]); | ||
1328 | break; | ||
1329 | |||
1330 | case WM_LINTERP: | ||
1331 | emit_linterp(p, dst, dst_flags, args[0], args[1]); | ||
1332 | break; | ||
1333 | |||
1334 | case WM_PINTERP: | ||
1335 | emit_pinterp(p, dst, dst_flags, args[0], args[1], args[2]); | ||
1336 | break; | ||
1337 | |||
1338 | case WM_CINTERP: | ||
1339 | emit_cinterp(p, dst, dst_flags, args[0]); | ||
1340 | break; | ||
1341 | |||
1342 | case WM_FB_WRITE: | ||
1343 | emit_fb_write(c, args[0], args[1], args[2], inst->target, inst->eot); | ||
1344 | break; | ||
1345 | |||
1346 | case WM_FRONTFACING: | ||
1347 | emit_frontfacing(p, dst, dst_flags); | ||
1348 | break; | ||
1349 | |||
1350 | /* Straightforward arithmetic: | ||
1351 | */ | ||
1352 | case TGSI_OPCODE_ADD: | ||
1353 | emit_alu2(p, brw_ADD, dst, dst_flags, args[0], args[1]); | ||
1354 | break; | ||
1355 | |||
1356 | case TGSI_OPCODE_FRC: | ||
1357 | emit_alu1(p, brw_FRC, dst, dst_flags, args[0]); | ||
1358 | break; | ||
1359 | |||
1360 | case TGSI_OPCODE_FLR: | ||
1361 | emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]); | ||
1362 | break; | ||
1363 | |||
1364 | case TGSI_OPCODE_DDX: | ||
1365 | emit_ddxy(p, dst, dst_flags, GL_TRUE, args[0]); | ||
1366 | break; | ||
1367 | |||
1368 | case TGSI_OPCODE_DDY: | ||
1369 | emit_ddxy(p, dst, dst_flags, GL_FALSE, args[0]); | ||
1370 | break; | ||
1371 | |||
1372 | case TGSI_OPCODE_DP3: | ||
1373 | emit_dp3(p, dst, dst_flags, args[0], args[1]); | ||
1374 | break; | ||
1375 | |||
1376 | case TGSI_OPCODE_DP4: | ||
1377 | emit_dp4(p, dst, dst_flags, args[0], args[1]); | ||
1378 | break; | ||
1379 | |||
1380 | case TGSI_OPCODE_DPH: | ||
1381 | emit_dph(p, dst, dst_flags, args[0], args[1]); | ||
1382 | break; | ||
1383 | |||
1384 | case TGSI_OPCODE_TRUNC: | ||
1385 | emit_trunc(p, dst, dst_flags, args[0]); | ||
1386 | break; | ||
1387 | |||
1388 | case TGSI_OPCODE_LRP: | ||
1389 | emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]); | ||
1390 | break; | ||
1391 | |||
1392 | case TGSI_OPCODE_MAD: | ||
1393 | emit_mad(p, dst, dst_flags, args[0], args[1], args[2]); | ||
1394 | break; | ||
1395 | |||
1396 | case TGSI_OPCODE_MOV: | ||
1397 | emit_alu1(p, brw_MOV, dst, dst_flags, args[0]); | ||
1398 | break; | ||
1399 | |||
1400 | case TGSI_OPCODE_MUL: | ||
1401 | emit_alu2(p, brw_MUL, dst, dst_flags, args[0], args[1]); | ||
1402 | break; | ||
1403 | |||
1404 | case TGSI_OPCODE_XPD: | ||
1405 | emit_xpd(p, dst, dst_flags, args[0], args[1]); | ||
1406 | break; | ||
1407 | |||
1408 | /* Higher math functions: | ||
1409 | */ | ||
1410 | case TGSI_OPCODE_RCP: | ||
1411 | emit_math1(p, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]); | ||
1412 | break; | ||
1413 | |||
1414 | case TGSI_OPCODE_RSQ: | ||
1415 | emit_math1(p, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]); | ||
1416 | break; | ||
1417 | |||
1418 | case TGSI_OPCODE_SIN: | ||
1419 | emit_math1(p, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]); | ||
1420 | break; | ||
1421 | |||
1422 | case TGSI_OPCODE_COS: | ||
1423 | emit_math1(p, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]); | ||
1424 | break; | ||
1425 | |||
1426 | case TGSI_OPCODE_EX2: | ||
1427 | emit_math1(p, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]); | ||
1428 | break; | ||
1429 | |||
1430 | case TGSI_OPCODE_LG2: | ||
1431 | emit_math1(p, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]); | ||
1432 | break; | ||
1433 | |||
1434 | case TGSI_OPCODE_SCS: | ||
1435 | /* There is an scs math function, but it would need some | ||
1436 | * fixup for 16-element execution. | ||
1437 | */ | ||
1438 | if (dst_flags & BRW_WRITEMASK_X) | ||
1439 | emit_math1(p, BRW_MATH_FUNCTION_COS, dst, (dst_flags&SATURATE)|BRW_WRITEMASK_X, args[0]); | ||
1440 | if (dst_flags & BRW_WRITEMASK_Y) | ||
1441 | emit_math1(p, BRW_MATH_FUNCTION_SIN, dst+1, (dst_flags&SATURATE)|BRW_WRITEMASK_X, args[0]); | ||
1442 | break; | ||
1443 | |||
1444 | case TGSI_OPCODE_POW: | ||
1445 | emit_math2(p, BRW_MATH_FUNCTION_POW, dst, dst_flags, args[0], args[1]); | ||
1446 | break; | ||
1447 | |||
1448 | /* Comparisons: | ||
1449 | */ | ||
1450 | case TGSI_OPCODE_CMP: | ||
1451 | emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]); | ||
1452 | break; | ||
1453 | |||
1454 | case TGSI_OPCODE_MAX: | ||
1455 | emit_max(p, dst, dst_flags, args[0], args[1]); | ||
1456 | break; | ||
1457 | |||
1458 | case TGSI_OPCODE_MIN: | ||
1459 | emit_min(p, dst, dst_flags, args[0], args[1]); | ||
1460 | break; | ||
1461 | |||
1462 | case TGSI_OPCODE_SLT: | ||
1463 | emit_slt(p, dst, dst_flags, args[0], args[1]); | ||
1464 | break; | ||
1465 | |||
1466 | case TGSI_OPCODE_SLE: | ||
1467 | emit_sle(p, dst, dst_flags, args[0], args[1]); | ||
1468 | break; | ||
1469 | case TGSI_OPCODE_SGT: | ||
1470 | emit_sgt(p, dst, dst_flags, args[0], args[1]); | ||
1471 | break; | ||
1472 | case TGSI_OPCODE_SGE: | ||
1473 | emit_sge(p, dst, dst_flags, args[0], args[1]); | ||
1474 | break; | ||
1475 | case TGSI_OPCODE_SEQ: | ||
1476 | emit_seq(p, dst, dst_flags, args[0], args[1]); | ||
1477 | break; | ||
1478 | case TGSI_OPCODE_SNE: | ||
1479 | emit_sne(p, dst, dst_flags, args[0], args[1]); | ||
1480 | break; | ||
1481 | |||
1482 | case TGSI_OPCODE_LIT: | ||
1483 | emit_lit(p, dst, dst_flags, args[0]); | ||
1484 | break; | ||
1485 | |||
1486 | /* Texturing operations: | ||
1487 | */ | ||
1488 | case TGSI_OPCODE_TEX: | ||
1489 | emit_tex(c, inst, dst, dst_flags, args[0], inst->sampler); | ||
1490 | break; | ||
1491 | |||
1492 | case TGSI_OPCODE_TXB: | ||
1493 | emit_txb(c, inst, dst, dst_flags, args[0], inst->sampler); | ||
1494 | break; | ||
1495 | |||
1496 | case TGSI_OPCODE_KIL: | ||
1497 | emit_kil(c, args[0]); | ||
1498 | break; | ||
1499 | |||
1500 | case TGSI_OPCODE_KILP: | ||
1501 | emit_killp(c); | ||
1502 | break; | ||
1503 | |||
1504 | default: | ||
1505 | debug_printf("Unsupported opcode %i (%s) in fragment shader\n", | ||
1506 | inst->opcode, | ||
1507 | tgsi_get_opcode_info(inst->opcode)->mnemonic); | ||
1508 | } | ||
1509 | |||
1510 | for (i = 0; i < 4; i++) | ||
1511 | if (inst->dst[i] && inst->dst[i]->spill_slot) | ||
1512 | emit_spill(c, | ||
1513 | inst->dst[i]->hw_reg, | ||
1514 | inst->dst[i]->spill_slot); | ||
1515 | } | ||
1516 | |||
1517 | if (BRW_DEBUG & DEBUG_WM) { | ||
1518 | debug_printf("wm-native:\n"); | ||
1519 | brw_disasm(stderr, p->store, p->nr_insn, p->brw->gen); | ||
1520 | } | ||
1521 | } | ||
diff --git a/src/gallium/drivers/i965/brw_wm_fp.c b/src/gallium/drivers/i965/brw_wm_fp.c deleted file mode 100644 index a65e16edec0..00000000000 --- a/src/gallium/drivers/i965/brw_wm_fp.c +++ /dev/null | |||
@@ -1,1223 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "pipe/p_shader_tokens.h" | ||
34 | |||
35 | #include "util/u_math.h" | ||
36 | #include "util/u_memory.h" | ||
37 | |||
38 | #include "tgsi/tgsi_parse.h" | ||
39 | #include "tgsi/tgsi_dump.h" | ||
40 | #include "tgsi/tgsi_info.h" | ||
41 | #include "tgsi/tgsi_util.h" | ||
42 | |||
43 | #include "brw_wm.h" | ||
44 | #include "brw_debug.h" | ||
45 | |||
46 | |||
47 | /*********************************************************************** | ||
48 | * Source regs | ||
49 | */ | ||
50 | |||
51 | static struct brw_fp_src src_reg(GLuint file, GLuint idx) | ||
52 | { | ||
53 | struct brw_fp_src reg; | ||
54 | reg.file = file; | ||
55 | reg.index = idx; | ||
56 | reg.swizzle = BRW_SWIZZLE_XYZW; | ||
57 | reg.indirect = 0; | ||
58 | reg.negate = 0; | ||
59 | reg.abs = 0; | ||
60 | return reg; | ||
61 | } | ||
62 | |||
63 | static struct brw_fp_src src_reg_from_dst(struct brw_fp_dst dst) | ||
64 | { | ||
65 | return src_reg(dst.file, dst.index); | ||
66 | } | ||
67 | |||
68 | static struct brw_fp_src src_undef( void ) | ||
69 | { | ||
70 | return src_reg(TGSI_FILE_NULL, 0); | ||
71 | } | ||
72 | |||
73 | static GLboolean src_is_undef(struct brw_fp_src src) | ||
74 | { | ||
75 | return src.file == TGSI_FILE_NULL; | ||
76 | } | ||
77 | |||
78 | static struct brw_fp_src src_swizzle( struct brw_fp_src reg, int x, int y, int z, int w ) | ||
79 | { | ||
80 | unsigned swz = reg.swizzle; | ||
81 | |||
82 | reg.swizzle = ( BRW_GET_SWZ(swz, x) << 0 | | ||
83 | BRW_GET_SWZ(swz, y) << 2 | | ||
84 | BRW_GET_SWZ(swz, z) << 4 | | ||
85 | BRW_GET_SWZ(swz, w) << 6 ); | ||
86 | |||
87 | return reg; | ||
88 | } | ||
89 | |||
90 | static struct brw_fp_src src_scalar( struct brw_fp_src reg, int x ) | ||
91 | { | ||
92 | return src_swizzle(reg, x, x, x, x); | ||
93 | } | ||
94 | |||
95 | static struct brw_fp_src src_abs( struct brw_fp_src src ) | ||
96 | { | ||
97 | src.negate = 0; | ||
98 | src.abs = 1; | ||
99 | return src; | ||
100 | } | ||
101 | |||
102 | static struct brw_fp_src src_negate( struct brw_fp_src src ) | ||
103 | { | ||
104 | src.negate = 1; | ||
105 | src.abs = 0; | ||
106 | return src; | ||
107 | } | ||
108 | |||
109 | |||
110 | static int match_or_expand_immediate( const float *v, | ||
111 | unsigned nr, | ||
112 | float *v2, | ||
113 | unsigned *nr2, | ||
114 | unsigned *swizzle ) | ||
115 | { | ||
116 | unsigned i, j; | ||
117 | |||
118 | *swizzle = 0; | ||
119 | |||
120 | for (i = 0; i < nr; i++) { | ||
121 | boolean found = FALSE; | ||
122 | |||
123 | for (j = 0; j < *nr2 && !found; j++) { | ||
124 | if (v[i] == v2[j]) { | ||
125 | *swizzle |= j << (i * 2); | ||
126 | found = TRUE; | ||
127 | } | ||
128 | } | ||
129 | |||
130 | if (!found) { | ||
131 | if (*nr2 >= 4) | ||
132 | return FALSE; | ||
133 | |||
134 | v2[*nr2] = v[i]; | ||
135 | *swizzle |= *nr2 << (i * 2); | ||
136 | (*nr2)++; | ||
137 | } | ||
138 | } | ||
139 | |||
140 | return TRUE; | ||
141 | } | ||
142 | |||
143 | |||
144 | |||
145 | /* Internally generated immediates: overkill... | ||
146 | */ | ||
147 | static struct brw_fp_src src_imm( struct brw_wm_compile *c, | ||
148 | const GLfloat *v, | ||
149 | unsigned nr) | ||
150 | { | ||
151 | unsigned i, j; | ||
152 | unsigned swizzle; | ||
153 | |||
154 | /* Could do a first pass where we examine all existing immediates | ||
155 | * without expanding. | ||
156 | */ | ||
157 | |||
158 | for (i = 0; i < c->nr_immediates; i++) { | ||
159 | if (match_or_expand_immediate( v, | ||
160 | nr, | ||
161 | c->immediate[i].v, | ||
162 | &c->immediate[i].nr, | ||
163 | &swizzle )) | ||
164 | goto out; | ||
165 | } | ||
166 | |||
167 | if (c->nr_immediates < Elements(c->immediate)) { | ||
168 | i = c->nr_immediates++; | ||
169 | if (match_or_expand_immediate( v, | ||
170 | nr, | ||
171 | c->immediate[i].v, | ||
172 | &c->immediate[i].nr, | ||
173 | &swizzle )) | ||
174 | goto out; | ||
175 | } | ||
176 | |||
177 | c->error = 1; | ||
178 | return src_undef(); | ||
179 | |||
180 | out: | ||
181 | /* Make sure that all referenced elements are from this immediate. | ||
182 | * Has the effect of making size-one immediates into scalars. | ||
183 | */ | ||
184 | for (j = nr; j < 4; j++) | ||
185 | swizzle |= (swizzle & 0x3) << (j * 2); | ||
186 | |||
187 | return src_swizzle( src_reg( TGSI_FILE_IMMEDIATE, i ), | ||
188 | BRW_GET_SWZ(swizzle, X), | ||
189 | BRW_GET_SWZ(swizzle, Y), | ||
190 | BRW_GET_SWZ(swizzle, Z), | ||
191 | BRW_GET_SWZ(swizzle, W) ); | ||
192 | } | ||
193 | |||
194 | |||
195 | |||
196 | static struct brw_fp_src src_imm1f( struct brw_wm_compile *c, | ||
197 | GLfloat f ) | ||
198 | { | ||
199 | return src_imm(c, &f, 1); | ||
200 | } | ||
201 | |||
202 | static struct brw_fp_src src_imm4f( struct brw_wm_compile *c, | ||
203 | GLfloat x, | ||
204 | GLfloat y, | ||
205 | GLfloat z, | ||
206 | GLfloat w) | ||
207 | { | ||
208 | GLfloat f[4] = {x,y,z,w}; | ||
209 | return src_imm(c, f, 4); | ||
210 | } | ||
211 | |||
212 | |||
213 | |||
214 | /*********************************************************************** | ||
215 | * Dest regs | ||
216 | */ | ||
217 | |||
218 | static struct brw_fp_dst dst_reg(GLuint file, GLuint idx) | ||
219 | { | ||
220 | struct brw_fp_dst reg; | ||
221 | reg.file = file; | ||
222 | reg.index = idx; | ||
223 | reg.writemask = BRW_WRITEMASK_XYZW; | ||
224 | reg.indirect = 0; | ||
225 | reg.saturate = 0; | ||
226 | return reg; | ||
227 | } | ||
228 | |||
229 | static struct brw_fp_dst dst_mask( struct brw_fp_dst reg, int mask ) | ||
230 | { | ||
231 | reg.writemask &= mask; | ||
232 | return reg; | ||
233 | } | ||
234 | |||
235 | static struct brw_fp_dst dst_undef( void ) | ||
236 | { | ||
237 | return dst_reg(TGSI_FILE_NULL, 0); | ||
238 | } | ||
239 | |||
240 | static boolean dst_is_undef( struct brw_fp_dst dst ) | ||
241 | { | ||
242 | return dst.file == TGSI_FILE_NULL; | ||
243 | } | ||
244 | |||
245 | static struct brw_fp_dst dst_saturate( struct brw_fp_dst reg, boolean flag ) | ||
246 | { | ||
247 | reg.saturate = flag; | ||
248 | return reg; | ||
249 | } | ||
250 | |||
251 | static struct brw_fp_dst get_temp( struct brw_wm_compile *c ) | ||
252 | { | ||
253 | int bit = ffs( ~c->fp_temp ); | ||
254 | |||
255 | if (!bit) { | ||
256 | debug_printf("%s: out of temporaries\n", __FILE__); | ||
257 | } | ||
258 | |||
259 | c->fp_temp |= 1<<(bit-1); | ||
260 | return dst_reg(TGSI_FILE_TEMPORARY, c->fp_first_internal_temp+(bit-1)); | ||
261 | } | ||
262 | |||
263 | |||
264 | static void release_temp( struct brw_wm_compile *c, struct brw_fp_dst temp ) | ||
265 | { | ||
266 | c->fp_temp &= ~(1 << (temp.index - c->fp_first_internal_temp)); | ||
267 | } | ||
268 | |||
269 | |||
270 | /*********************************************************************** | ||
271 | * Instructions | ||
272 | */ | ||
273 | |||
274 | static struct brw_fp_instruction *get_fp_inst(struct brw_wm_compile *c) | ||
275 | { | ||
276 | return &c->fp_instructions[c->nr_fp_insns++]; | ||
277 | } | ||
278 | |||
279 | static struct brw_fp_instruction * emit_tex_op(struct brw_wm_compile *c, | ||
280 | GLuint op, | ||
281 | struct brw_fp_dst dest, | ||
282 | GLuint tex_unit, | ||
283 | GLuint target, | ||
284 | GLuint sampler, | ||
285 | struct brw_fp_src src0, | ||
286 | struct brw_fp_src src1, | ||
287 | struct brw_fp_src src2 ) | ||
288 | { | ||
289 | struct brw_fp_instruction *inst = get_fp_inst(c); | ||
290 | |||
291 | if (tex_unit || target) | ||
292 | assert(op == TGSI_OPCODE_TXP || | ||
293 | op == TGSI_OPCODE_TXB || | ||
294 | op == TGSI_OPCODE_TEX || | ||
295 | op == WM_FB_WRITE); | ||
296 | |||
297 | inst->opcode = op; | ||
298 | inst->dst = dest; | ||
299 | inst->tex_unit = tex_unit; | ||
300 | inst->target = target; | ||
301 | inst->sampler = sampler; | ||
302 | inst->src[0] = src0; | ||
303 | inst->src[1] = src1; | ||
304 | inst->src[2] = src2; | ||
305 | |||
306 | return inst; | ||
307 | } | ||
308 | |||
309 | |||
310 | static INLINE void emit_op3(struct brw_wm_compile *c, | ||
311 | GLuint op, | ||
312 | struct brw_fp_dst dest, | ||
313 | struct brw_fp_src src0, | ||
314 | struct brw_fp_src src1, | ||
315 | struct brw_fp_src src2 ) | ||
316 | { | ||
317 | emit_tex_op(c, op, dest, 0, 0, 0, src0, src1, src2); | ||
318 | } | ||
319 | |||
320 | |||
321 | static INLINE void emit_op2(struct brw_wm_compile *c, | ||
322 | GLuint op, | ||
323 | struct brw_fp_dst dest, | ||
324 | struct brw_fp_src src0, | ||
325 | struct brw_fp_src src1) | ||
326 | { | ||
327 | emit_tex_op(c, op, dest, 0, 0, 0, src0, src1, src_undef()); | ||
328 | } | ||
329 | |||
330 | static INLINE void emit_op1(struct brw_wm_compile *c, | ||
331 | GLuint op, | ||
332 | struct brw_fp_dst dest, | ||
333 | struct brw_fp_src src0) | ||
334 | { | ||
335 | emit_tex_op(c, op, dest, 0, 0, 0, src0, src_undef(), src_undef()); | ||
336 | } | ||
337 | |||
338 | static INLINE void emit_op0(struct brw_wm_compile *c, | ||
339 | GLuint op, | ||
340 | struct brw_fp_dst dest) | ||
341 | { | ||
342 | emit_tex_op(c, op, dest, 0, 0, 0, src_undef(), src_undef(), src_undef()); | ||
343 | } | ||
344 | |||
345 | |||
346 | |||
347 | /* Many opcodes produce the same value across all the result channels. | ||
348 | * We'd rather not have to support that splatting in the opcode implementations, | ||
349 | * and brw_wm_pass*.c wants to optimize them out by shuffling references around | ||
350 | * anyway. We can easily get both by emitting the opcode to one channel, and | ||
351 | * then MOVing it to the others, which brw_wm_pass*.c already understands. | ||
352 | */ | ||
353 | static void emit_scalar_insn(struct brw_wm_compile *c, | ||
354 | unsigned opcode, | ||
355 | struct brw_fp_dst dst, | ||
356 | struct brw_fp_src src0, | ||
357 | struct brw_fp_src src1, | ||
358 | struct brw_fp_src src2 ) | ||
359 | { | ||
360 | unsigned first_chan = ffs(dst.writemask) - 1; | ||
361 | unsigned first_mask = 1 << first_chan; | ||
362 | |||
363 | if (dst.writemask == 0) | ||
364 | return; | ||
365 | |||
366 | emit_op3( c, opcode, | ||
367 | dst_mask(dst, first_mask), | ||
368 | src0, src1, src2 ); | ||
369 | |||
370 | if (dst.writemask != first_mask) { | ||
371 | emit_op1(c, TGSI_OPCODE_MOV, | ||
372 | dst_mask(dst, ~first_mask), | ||
373 | src_scalar(src_reg_from_dst(dst), first_chan)); | ||
374 | } | ||
375 | } | ||
376 | |||
377 | |||
378 | /*********************************************************************** | ||
379 | * Special instructions for interpolation and other tasks | ||
380 | */ | ||
381 | |||
382 | static struct brw_fp_src get_pixel_xy( struct brw_wm_compile *c ) | ||
383 | { | ||
384 | if (src_is_undef(c->fp_pixel_xy)) { | ||
385 | struct brw_fp_dst pixel_xy = get_temp(c); | ||
386 | struct brw_fp_src payload_r0_depth = src_reg(BRW_FILE_PAYLOAD, PAYLOAD_DEPTH); | ||
387 | |||
388 | |||
389 | /* Emit the out calculations, and hold onto the results. Use | ||
390 | * two instructions as a temporary is required. | ||
391 | */ | ||
392 | /* pixel_xy.xy = PIXELXY payload[0]; | ||
393 | */ | ||
394 | emit_op1(c, | ||
395 | WM_PIXELXY, | ||
396 | dst_mask(pixel_xy, BRW_WRITEMASK_XY), | ||
397 | payload_r0_depth); | ||
398 | |||
399 | c->fp_pixel_xy = src_reg_from_dst(pixel_xy); | ||
400 | } | ||
401 | |||
402 | return c->fp_pixel_xy; | ||
403 | } | ||
404 | |||
405 | static struct brw_fp_src get_delta_xy( struct brw_wm_compile *c ) | ||
406 | { | ||
407 | if (src_is_undef(c->fp_delta_xy)) { | ||
408 | struct brw_fp_dst delta_xy = get_temp(c); | ||
409 | struct brw_fp_src pixel_xy = get_pixel_xy(c); | ||
410 | struct brw_fp_src payload_r0_depth = src_reg(BRW_FILE_PAYLOAD, PAYLOAD_DEPTH); | ||
411 | |||
412 | /* deltas.xy = DELTAXY pixel_xy, payload[0] | ||
413 | */ | ||
414 | emit_op3(c, | ||
415 | WM_DELTAXY, | ||
416 | dst_mask(delta_xy, BRW_WRITEMASK_XY), | ||
417 | pixel_xy, | ||
418 | payload_r0_depth, | ||
419 | src_undef()); | ||
420 | |||
421 | c->fp_delta_xy = src_reg_from_dst(delta_xy); | ||
422 | } | ||
423 | |||
424 | return c->fp_delta_xy; | ||
425 | } | ||
426 | |||
427 | static struct brw_fp_src get_pixel_w( struct brw_wm_compile *c ) | ||
428 | { | ||
429 | if (src_is_undef(c->fp_pixel_w)) { | ||
430 | struct brw_fp_dst pixel_w = get_temp(c); | ||
431 | struct brw_fp_src deltas = get_delta_xy(c); | ||
432 | |||
433 | /* XXX: assuming position is always first -- valid? | ||
434 | */ | ||
435 | struct brw_fp_src interp_wpos = src_reg(BRW_FILE_PAYLOAD, 0); | ||
436 | |||
437 | /* deltas.xyw = DELTAS2 deltas.xy, payload.interp_wpos.x | ||
438 | */ | ||
439 | emit_op3(c, | ||
440 | WM_PIXELW, | ||
441 | dst_mask(pixel_w, BRW_WRITEMASK_W), | ||
442 | interp_wpos, | ||
443 | deltas, | ||
444 | src_undef()); | ||
445 | |||
446 | |||
447 | c->fp_pixel_w = src_reg_from_dst(pixel_w); | ||
448 | } | ||
449 | |||
450 | return c->fp_pixel_w; | ||
451 | } | ||
452 | |||
453 | |||
454 | /*********************************************************************** | ||
455 | * Emit INTERP instructions ahead of first use of each attrib. | ||
456 | */ | ||
457 | |||
458 | static void emit_interp( struct brw_wm_compile *c, | ||
459 | GLuint idx, | ||
460 | GLuint semantic, | ||
461 | GLuint interp_mode ) | ||
462 | { | ||
463 | struct brw_fp_dst dst = dst_reg(TGSI_FILE_INPUT, idx); | ||
464 | struct brw_fp_src interp = src_reg(BRW_FILE_PAYLOAD, idx); | ||
465 | struct brw_fp_src deltas = get_delta_xy(c); | ||
466 | |||
467 | /* Need to use PINTERP on attributes which have been | ||
468 | * multiplied by 1/W in the SF program, and LINTERP on those | ||
469 | * which have not: | ||
470 | */ | ||
471 | switch (semantic) { | ||
472 | case TGSI_SEMANTIC_POSITION: | ||
473 | /* Have to treat wpos.xy specially: | ||
474 | */ | ||
475 | emit_op1(c, | ||
476 | WM_WPOSXY, | ||
477 | dst_mask(dst, BRW_WRITEMASK_XY), | ||
478 | get_pixel_xy(c)); | ||
479 | |||
480 | /* TGSI_FILE_INPUT.attr.xyzw = INTERP payload.interp[attr].x, deltas.xyw | ||
481 | */ | ||
482 | emit_op2(c, | ||
483 | WM_LINTERP, | ||
484 | dst_mask(dst, BRW_WRITEMASK_ZW), | ||
485 | interp, | ||
486 | deltas); | ||
487 | break; | ||
488 | |||
489 | case TGSI_SEMANTIC_COLOR: | ||
490 | if (c->key.flat_shade) { | ||
491 | emit_op1(c, | ||
492 | WM_CINTERP, | ||
493 | dst, | ||
494 | interp); | ||
495 | } | ||
496 | else if (interp_mode == TGSI_INTERPOLATE_LINEAR) { | ||
497 | emit_op2(c, | ||
498 | WM_LINTERP, | ||
499 | dst, | ||
500 | interp, | ||
501 | deltas); | ||
502 | } | ||
503 | else { | ||
504 | emit_op3(c, | ||
505 | WM_PINTERP, | ||
506 | dst, | ||
507 | interp, | ||
508 | deltas, | ||
509 | get_pixel_w(c)); | ||
510 | } | ||
511 | |||
512 | break; | ||
513 | |||
514 | case TGSI_SEMANTIC_FOG: | ||
515 | /* Interpolate the fog coordinate */ | ||
516 | emit_op3(c, | ||
517 | WM_PINTERP, | ||
518 | dst_mask(dst, BRW_WRITEMASK_X), | ||
519 | interp, | ||
520 | deltas, | ||
521 | get_pixel_w(c)); | ||
522 | |||
523 | emit_op1(c, | ||
524 | TGSI_OPCODE_MOV, | ||
525 | dst_mask(dst, BRW_WRITEMASK_YZ), | ||
526 | src_imm1f(c, 0.0)); | ||
527 | |||
528 | emit_op1(c, | ||
529 | TGSI_OPCODE_MOV, | ||
530 | dst_mask(dst, BRW_WRITEMASK_W), | ||
531 | src_imm1f(c, 1.0)); | ||
532 | break; | ||
533 | |||
534 | case TGSI_SEMANTIC_FACE: | ||
535 | /* XXX review/test this case */ | ||
536 | emit_op0(c, | ||
537 | WM_FRONTFACING, | ||
538 | dst_mask(dst, BRW_WRITEMASK_X)); | ||
539 | |||
540 | emit_op1(c, | ||
541 | TGSI_OPCODE_MOV, | ||
542 | dst_mask(dst, BRW_WRITEMASK_YZ), | ||
543 | src_imm1f(c, 0.0)); | ||
544 | |||
545 | emit_op1(c, | ||
546 | TGSI_OPCODE_MOV, | ||
547 | dst_mask(dst, BRW_WRITEMASK_W), | ||
548 | src_imm1f(c, 1.0)); | ||
549 | break; | ||
550 | |||
551 | case TGSI_SEMANTIC_PSIZE: | ||
552 | /* XXX review/test this case */ | ||
553 | emit_op3(c, | ||
554 | WM_PINTERP, | ||
555 | dst_mask(dst, BRW_WRITEMASK_XY), | ||
556 | interp, | ||
557 | deltas, | ||
558 | get_pixel_w(c)); | ||
559 | |||
560 | emit_op1(c, | ||
561 | TGSI_OPCODE_MOV, | ||
562 | dst_mask(dst, BRW_WRITEMASK_Z), | ||
563 | src_imm1f(c, 0.0f)); | ||
564 | |||
565 | emit_op1(c, | ||
566 | TGSI_OPCODE_MOV, | ||
567 | dst_mask(dst, BRW_WRITEMASK_W), | ||
568 | src_imm1f(c, 1.0f)); | ||
569 | break; | ||
570 | |||
571 | default: | ||
572 | switch (interp_mode) { | ||
573 | case TGSI_INTERPOLATE_CONSTANT: | ||
574 | emit_op1(c, | ||
575 | WM_CINTERP, | ||
576 | dst, | ||
577 | interp); | ||
578 | break; | ||
579 | |||
580 | case TGSI_INTERPOLATE_LINEAR: | ||
581 | emit_op2(c, | ||
582 | WM_LINTERP, | ||
583 | dst, | ||
584 | interp, | ||
585 | deltas); | ||
586 | break; | ||
587 | |||
588 | case TGSI_INTERPOLATE_PERSPECTIVE: | ||
589 | emit_op3(c, | ||
590 | WM_PINTERP, | ||
591 | dst, | ||
592 | interp, | ||
593 | deltas, | ||
594 | get_pixel_w(c)); | ||
595 | break; | ||
596 | } | ||
597 | break; | ||
598 | } | ||
599 | } | ||
600 | |||
601 | |||
602 | /*********************************************************************** | ||
603 | * Expand various instructions here to simpler forms. | ||
604 | */ | ||
605 | static void precalc_dst( struct brw_wm_compile *c, | ||
606 | struct brw_fp_dst dst, | ||
607 | struct brw_fp_src src0, | ||
608 | struct brw_fp_src src1 ) | ||
609 | { | ||
610 | if (dst.writemask & BRW_WRITEMASK_Y) { | ||
611 | /* dst.y = mul src0.y, src1.y | ||
612 | */ | ||
613 | emit_op2(c, | ||
614 | TGSI_OPCODE_MUL, | ||
615 | dst_mask(dst, BRW_WRITEMASK_Y), | ||
616 | src0, | ||
617 | src1); | ||
618 | } | ||
619 | |||
620 | if (dst.writemask & BRW_WRITEMASK_XZ) { | ||
621 | /* dst.z = mov src0.zzzz | ||
622 | */ | ||
623 | emit_op1(c, | ||
624 | TGSI_OPCODE_MOV, | ||
625 | dst_mask(dst, BRW_WRITEMASK_Z), | ||
626 | src_scalar(src0, Z)); | ||
627 | |||
628 | /* dst.x = imm1f(1.0) | ||
629 | */ | ||
630 | emit_op1(c, | ||
631 | TGSI_OPCODE_MOV, | ||
632 | dst_saturate(dst_mask(dst, BRW_WRITEMASK_X), 0), | ||
633 | src_imm1f(c, 1.0)); | ||
634 | } | ||
635 | if (dst.writemask & BRW_WRITEMASK_W) { | ||
636 | /* dst.w = mov src1.w | ||
637 | */ | ||
638 | emit_op1(c, | ||
639 | TGSI_OPCODE_MOV, | ||
640 | dst_mask(dst, BRW_WRITEMASK_W), | ||
641 | src1); | ||
642 | } | ||
643 | } | ||
644 | |||
645 | |||
646 | static void precalc_lit( struct brw_wm_compile *c, | ||
647 | struct brw_fp_dst dst, | ||
648 | struct brw_fp_src src0 ) | ||
649 | { | ||
650 | if (dst.writemask & BRW_WRITEMASK_XW) { | ||
651 | /* dst.xw = imm(1.0f) | ||
652 | */ | ||
653 | emit_op1(c, | ||
654 | TGSI_OPCODE_MOV, | ||
655 | dst_saturate(dst_mask(dst, BRW_WRITEMASK_XW), 0), | ||
656 | src_imm1f(c, 1.0f)); | ||
657 | } | ||
658 | |||
659 | if (dst.writemask & BRW_WRITEMASK_YZ) { | ||
660 | emit_op1(c, | ||
661 | TGSI_OPCODE_LIT, | ||
662 | dst_mask(dst, BRW_WRITEMASK_YZ), | ||
663 | src0); | ||
664 | } | ||
665 | } | ||
666 | |||
667 | |||
668 | /** | ||
669 | * Some TEX instructions require extra code, cube map coordinate | ||
670 | * normalization, or coordinate scaling for RECT textures, etc. | ||
671 | * This function emits those extra instructions and the TEX | ||
672 | * instruction itself. | ||
673 | */ | ||
674 | static void precalc_tex( struct brw_wm_compile *c, | ||
675 | struct brw_fp_dst dst, | ||
676 | unsigned target, | ||
677 | unsigned unit, | ||
678 | struct brw_fp_src src0, | ||
679 | struct brw_fp_src sampler ) | ||
680 | { | ||
681 | struct brw_fp_src coord; | ||
682 | struct brw_fp_dst tmp = dst_undef(); | ||
683 | |||
684 | assert(unit < BRW_MAX_TEX_UNIT); | ||
685 | |||
686 | /* Cubemap: find longest component of coord vector and normalize | ||
687 | * it. | ||
688 | */ | ||
689 | if (target == TGSI_TEXTURE_CUBE) { | ||
690 | struct brw_fp_src tmpsrc; | ||
691 | |||
692 | tmp = get_temp(c); | ||
693 | tmpsrc = src_reg_from_dst(tmp); | ||
694 | |||
695 | /* tmp = abs(src0) */ | ||
696 | emit_op1(c, | ||
697 | TGSI_OPCODE_MOV, | ||
698 | tmp, | ||
699 | src_abs(src0)); | ||
700 | |||
701 | /* tmp.X = MAX(tmp.X, tmp.Y) */ | ||
702 | emit_op2(c, TGSI_OPCODE_MAX, | ||
703 | dst_mask(tmp, BRW_WRITEMASK_X), | ||
704 | src_scalar(tmpsrc, X), | ||
705 | src_scalar(tmpsrc, Y)); | ||
706 | |||
707 | /* tmp.X = MAX(tmp.X, tmp.Z) */ | ||
708 | emit_op2(c, TGSI_OPCODE_MAX, | ||
709 | dst_mask(tmp, BRW_WRITEMASK_X), | ||
710 | tmpsrc, | ||
711 | src_scalar(tmpsrc, Z)); | ||
712 | |||
713 | /* tmp.X = 1 / tmp.X */ | ||
714 | emit_op1(c, TGSI_OPCODE_RCP, | ||
715 | dst_mask(tmp, BRW_WRITEMASK_X), | ||
716 | tmpsrc); | ||
717 | |||
718 | /* tmp = src0 * tmp.xxxx */ | ||
719 | emit_op2(c, TGSI_OPCODE_MUL, | ||
720 | tmp, | ||
721 | src0, | ||
722 | src_scalar(tmpsrc, X)); | ||
723 | |||
724 | coord = tmpsrc; | ||
725 | } | ||
726 | else if (target == TGSI_TEXTURE_RECT || | ||
727 | target == TGSI_TEXTURE_SHADOWRECT) { | ||
728 | /* XXX: need a mechanism for internally generated constants. | ||
729 | */ | ||
730 | coord = src0; | ||
731 | } | ||
732 | else { | ||
733 | coord = src0; | ||
734 | } | ||
735 | |||
736 | /* Need to emit YUV texture conversions by hand. Probably need to | ||
737 | * do this here - the alternative is in brw_wm_emit.c, but the | ||
738 | * conversion requires allocating a temporary variable which we | ||
739 | * don't have the facility to do that late in the compilation. | ||
740 | */ | ||
741 | if (c->key.yuvtex_mask & (1 << unit)) { | ||
742 | /* convert ycbcr to RGBA */ | ||
743 | GLboolean swap_uv = c->key.yuvtex_swap_mask & (1<<unit); | ||
744 | struct brw_fp_dst tmp = get_temp(c); | ||
745 | struct brw_fp_src tmpsrc = src_reg_from_dst(tmp); | ||
746 | struct brw_fp_src C0 = src_imm4f( c, -.5, -.0625, -.5, 1.164 ); | ||
747 | struct brw_fp_src C1 = src_imm4f( c, 1.596, -0.813, 2.018, -.391 ); | ||
748 | |||
749 | /* tmp = TEX ... | ||
750 | */ | ||
751 | emit_tex_op(c, | ||
752 | TGSI_OPCODE_TEX, | ||
753 | dst_saturate(tmp, dst.saturate), | ||
754 | unit, | ||
755 | target, | ||
756 | sampler.index, | ||
757 | coord, | ||
758 | src_undef(), | ||
759 | src_undef()); | ||
760 | |||
761 | /* tmp.xyz = ADD TMP, C0 | ||
762 | */ | ||
763 | emit_op2(c, TGSI_OPCODE_ADD, | ||
764 | dst_mask(tmp, BRW_WRITEMASK_XYZ), | ||
765 | tmpsrc, | ||
766 | C0); | ||
767 | |||
768 | /* YUV.y = MUL YUV.y, C0.w | ||
769 | */ | ||
770 | emit_op2(c, TGSI_OPCODE_MUL, | ||
771 | dst_mask(tmp, BRW_WRITEMASK_Y), | ||
772 | tmpsrc, | ||
773 | src_scalar(C0, W)); | ||
774 | |||
775 | /* | ||
776 | * if (UV swaped) | ||
777 | * RGB.xyz = MAD YUV.zzx, C1, YUV.y | ||
778 | * else | ||
779 | * RGB.xyz = MAD YUV.xxz, C1, YUV.y | ||
780 | */ | ||
781 | |||
782 | emit_op3(c, TGSI_OPCODE_MAD, | ||
783 | dst_mask(dst, BRW_WRITEMASK_XYZ), | ||
784 | ( swap_uv ? | ||
785 | src_swizzle(tmpsrc, Z,Z,X,X) : | ||
786 | src_swizzle(tmpsrc, X,X,Z,Z)), | ||
787 | C1, | ||
788 | src_scalar(tmpsrc, Y)); | ||
789 | |||
790 | /* RGB.y = MAD YUV.z, C1.w, RGB.y | ||
791 | */ | ||
792 | emit_op3(c, | ||
793 | TGSI_OPCODE_MAD, | ||
794 | dst_mask(dst, BRW_WRITEMASK_Y), | ||
795 | src_scalar(tmpsrc, Z), | ||
796 | src_scalar(C1, W), | ||
797 | src_scalar(src_reg_from_dst(dst), Y)); | ||
798 | |||
799 | release_temp(c, tmp); | ||
800 | } | ||
801 | else { | ||
802 | /* ordinary RGBA tex instruction */ | ||
803 | emit_tex_op(c, | ||
804 | TGSI_OPCODE_TEX, | ||
805 | dst, | ||
806 | unit, | ||
807 | target, | ||
808 | sampler.index, | ||
809 | coord, | ||
810 | src_undef(), | ||
811 | src_undef()); | ||
812 | } | ||
813 | |||
814 | /* XXX: add GL_EXT_texture_swizzle support to gallium -- by | ||
815 | * generating shader variants in mesa state tracker. | ||
816 | */ | ||
817 | |||
818 | /* Release this temp if we ended up allocating it: | ||
819 | */ | ||
820 | if (!dst_is_undef(tmp)) | ||
821 | release_temp(c, tmp); | ||
822 | } | ||
823 | |||
824 | |||
825 | /** | ||
826 | * Check if the given TXP instruction really needs the divide-by-W step. | ||
827 | */ | ||
828 | static GLboolean projtex( struct brw_wm_compile *c, | ||
829 | unsigned target, | ||
830 | struct brw_fp_src src ) | ||
831 | { | ||
832 | /* Only try to detect the simplest cases. Could detect (later) | ||
833 | * cases where we are trying to emit code like RCP {1.0}, MUL x, | ||
834 | * {1.0}, and so on. | ||
835 | * | ||
836 | * More complex cases than this typically only arise from | ||
837 | * user-provided fragment programs anyway: | ||
838 | */ | ||
839 | if (target == TGSI_TEXTURE_CUBE) | ||
840 | return GL_FALSE; /* ut2004 gun rendering !?! */ | ||
841 | |||
842 | if (src.file == TGSI_FILE_INPUT && | ||
843 | BRW_GET_SWZ(src.swizzle, W) == W && | ||
844 | c->fp->info.input_interpolate[src.index] != TGSI_INTERPOLATE_PERSPECTIVE) | ||
845 | return GL_FALSE; | ||
846 | |||
847 | return GL_TRUE; | ||
848 | } | ||
849 | |||
850 | |||
851 | /** | ||
852 | * Emit code for TXP. | ||
853 | */ | ||
854 | static void precalc_txp( struct brw_wm_compile *c, | ||
855 | struct brw_fp_dst dst, | ||
856 | unsigned target, | ||
857 | unsigned unit, | ||
858 | struct brw_fp_src src0, | ||
859 | struct brw_fp_src sampler ) | ||
860 | { | ||
861 | if (projtex(c, target, src0)) { | ||
862 | struct brw_fp_dst tmp = get_temp(c); | ||
863 | |||
864 | /* tmp0.w = RCP inst.arg[0][3] | ||
865 | */ | ||
866 | emit_op1(c, | ||
867 | TGSI_OPCODE_RCP, | ||
868 | dst_mask(tmp, BRW_WRITEMASK_W), | ||
869 | src_scalar(src0, W)); | ||
870 | |||
871 | /* tmp0.xyz = MUL inst.arg[0], tmp0.wwww | ||
872 | */ | ||
873 | emit_op2(c, | ||
874 | TGSI_OPCODE_MUL, | ||
875 | dst_mask(tmp, BRW_WRITEMASK_XYZ), | ||
876 | src0, | ||
877 | src_scalar(src_reg_from_dst(tmp), W)); | ||
878 | |||
879 | /* dst = TEX tmp0 | ||
880 | */ | ||
881 | precalc_tex(c, | ||
882 | dst, | ||
883 | target, | ||
884 | unit, | ||
885 | src_reg_from_dst(tmp), | ||
886 | sampler ); | ||
887 | |||
888 | release_temp(c, tmp); | ||
889 | } | ||
890 | else | ||
891 | { | ||
892 | /* dst = TEX src0 | ||
893 | */ | ||
894 | precalc_tex(c, dst, target, unit, src0, sampler); | ||
895 | } | ||
896 | } | ||
897 | |||
898 | |||
899 | /* XXX: note this returns a src_reg. | ||
900 | */ | ||
901 | static struct brw_fp_src | ||
902 | find_output_by_semantic( struct brw_wm_compile *c, | ||
903 | unsigned semantic, | ||
904 | unsigned index ) | ||
905 | { | ||
906 | const struct tgsi_shader_info *info = &c->fp->info; | ||
907 | unsigned i; | ||
908 | |||
909 | for (i = 0; i < info->num_outputs; i++) | ||
910 | if (info->output_semantic_name[i] == semantic && | ||
911 | info->output_semantic_index[i] == index) | ||
912 | return src_reg( TGSI_FILE_OUTPUT, i ); | ||
913 | |||
914 | /* If not found, return some arbitrary immediate value: | ||
915 | * | ||
916 | * XXX: this is a good idea but immediates are up generating extra | ||
917 | * curbe entries atm, as they would have in the original driver. | ||
918 | */ | ||
919 | return src_reg( TGSI_FILE_OUTPUT, 0 ); /* src_imm1f(c, 1.0); */ | ||
920 | } | ||
921 | |||
922 | |||
923 | static void emit_fb_write( struct brw_wm_compile *c ) | ||
924 | { | ||
925 | struct brw_fp_src payload_r0_depth = src_reg(BRW_FILE_PAYLOAD, PAYLOAD_DEPTH); | ||
926 | struct brw_fp_src outdepth = find_output_by_semantic(c, TGSI_SEMANTIC_POSITION, 0); | ||
927 | GLuint i; | ||
928 | |||
929 | |||
930 | outdepth = src_scalar(outdepth, Z); | ||
931 | |||
932 | for (i = 0 ; i < c->key.nr_cbufs; i++) { | ||
933 | struct brw_fp_src outcolor; | ||
934 | |||
935 | outcolor = find_output_by_semantic(c, TGSI_SEMANTIC_COLOR, i); | ||
936 | |||
937 | /* Use emit_tex_op so that we can specify the inst->target | ||
938 | * field, which is abused to contain the FB write target and the | ||
939 | * EOT marker | ||
940 | */ | ||
941 | emit_tex_op(c, WM_FB_WRITE, | ||
942 | dst_undef(), | ||
943 | (i == c->key.nr_cbufs - 1), /* EOT */ | ||
944 | i, | ||
945 | 0, /* no sampler */ | ||
946 | outcolor, | ||
947 | payload_r0_depth, | ||
948 | outdepth); | ||
949 | } | ||
950 | } | ||
951 | |||
952 | |||
953 | static struct brw_fp_dst translate_dst( struct brw_wm_compile *c, | ||
954 | const struct tgsi_full_dst_register *dst, | ||
955 | unsigned saturate ) | ||
956 | { | ||
957 | struct brw_fp_dst out; | ||
958 | |||
959 | out.file = dst->Register.File; | ||
960 | out.index = dst->Register.Index; | ||
961 | out.writemask = dst->Register.WriteMask; | ||
962 | out.indirect = dst->Register.Indirect; | ||
963 | out.saturate = (saturate == TGSI_SAT_ZERO_ONE); | ||
964 | |||
965 | if (out.indirect) { | ||
966 | assert(dst->Indirect.File == TGSI_FILE_ADDRESS); | ||
967 | assert(dst->Indirect.Index == 0); | ||
968 | } | ||
969 | |||
970 | return out; | ||
971 | } | ||
972 | |||
973 | |||
974 | static struct brw_fp_src translate_src( struct brw_wm_compile *c, | ||
975 | const struct tgsi_full_src_register *src ) | ||
976 | { | ||
977 | struct brw_fp_src out; | ||
978 | |||
979 | out.file = src->Register.File; | ||
980 | out.index = src->Register.Index; | ||
981 | out.indirect = src->Register.Indirect; | ||
982 | |||
983 | out.swizzle = ((src->Register.SwizzleX << 0) | | ||
984 | (src->Register.SwizzleY << 2) | | ||
985 | (src->Register.SwizzleZ << 4) | | ||
986 | (src->Register.SwizzleW << 6)); | ||
987 | |||
988 | switch (tgsi_util_get_full_src_register_sign_mode( src, 0 )) { | ||
989 | case TGSI_UTIL_SIGN_CLEAR: | ||
990 | out.abs = 1; | ||
991 | out.negate = 0; | ||
992 | break; | ||
993 | |||
994 | case TGSI_UTIL_SIGN_SET: | ||
995 | out.abs = 1; | ||
996 | out.negate = 1; | ||
997 | break; | ||
998 | |||
999 | case TGSI_UTIL_SIGN_TOGGLE: | ||
1000 | out.abs = 0; | ||
1001 | out.negate = 1; | ||
1002 | break; | ||
1003 | |||
1004 | case TGSI_UTIL_SIGN_KEEP: | ||
1005 | default: | ||
1006 | out.abs = 0; | ||
1007 | out.negate = 0; | ||
1008 | break; | ||
1009 | } | ||
1010 | |||
1011 | if (out.indirect) { | ||
1012 | assert(src->Indirect.File == TGSI_FILE_ADDRESS); | ||
1013 | assert(src->Indirect.Index == 0); | ||
1014 | } | ||
1015 | |||
1016 | return out; | ||
1017 | } | ||
1018 | |||
1019 | |||
1020 | |||
1021 | static void emit_insn( struct brw_wm_compile *c, | ||
1022 | const struct tgsi_full_instruction *inst ) | ||
1023 | { | ||
1024 | unsigned opcode = inst->Instruction.Opcode; | ||
1025 | struct brw_fp_dst dst; | ||
1026 | struct brw_fp_src src[3]; | ||
1027 | int i; | ||
1028 | |||
1029 | dst = translate_dst( c, &inst->Dst[0], | ||
1030 | inst->Instruction.Saturate ); | ||
1031 | |||
1032 | for (i = 0; i < inst->Instruction.NumSrcRegs; i++) | ||
1033 | src[i] = translate_src( c, &inst->Src[i] ); | ||
1034 | |||
1035 | switch (opcode) { | ||
1036 | case TGSI_OPCODE_ABS: | ||
1037 | emit_op1(c, TGSI_OPCODE_MOV, | ||
1038 | dst, | ||
1039 | src_abs(src[0])); | ||
1040 | break; | ||
1041 | |||
1042 | case TGSI_OPCODE_SUB: | ||
1043 | emit_op2(c, TGSI_OPCODE_ADD, | ||
1044 | dst, | ||
1045 | src[0], | ||
1046 | src_negate(src[1])); | ||
1047 | break; | ||
1048 | |||
1049 | case TGSI_OPCODE_SCS: | ||
1050 | emit_op1(c, TGSI_OPCODE_SCS, | ||
1051 | dst_mask(dst, BRW_WRITEMASK_XY), | ||
1052 | src[0]); | ||
1053 | break; | ||
1054 | |||
1055 | case TGSI_OPCODE_DST: | ||
1056 | precalc_dst(c, dst, src[0], src[1]); | ||
1057 | break; | ||
1058 | |||
1059 | case TGSI_OPCODE_LIT: | ||
1060 | precalc_lit(c, dst, src[0]); | ||
1061 | break; | ||
1062 | |||
1063 | case TGSI_OPCODE_TEX: | ||
1064 | precalc_tex(c, dst, | ||
1065 | inst->Texture.Texture, | ||
1066 | src[1].index, /* use sampler unit for tex idx */ | ||
1067 | src[0], /* coord */ | ||
1068 | src[1]); /* sampler */ | ||
1069 | break; | ||
1070 | |||
1071 | case TGSI_OPCODE_TXP: | ||
1072 | precalc_txp(c, dst, | ||
1073 | inst->Texture.Texture, | ||
1074 | src[1].index, /* use sampler unit for tex idx */ | ||
1075 | src[0], /* coord */ | ||
1076 | src[1]); /* sampler */ | ||
1077 | break; | ||
1078 | |||
1079 | case TGSI_OPCODE_TXB: | ||
1080 | /* XXX: TXB not done | ||
1081 | */ | ||
1082 | precalc_tex(c, dst, | ||
1083 | inst->Texture.Texture, | ||
1084 | src[1].index, /* use sampler unit for tex idx*/ | ||
1085 | src[0], | ||
1086 | src[1]); | ||
1087 | break; | ||
1088 | |||
1089 | case TGSI_OPCODE_XPD: | ||
1090 | emit_op2(c, TGSI_OPCODE_XPD, | ||
1091 | dst_mask(dst, BRW_WRITEMASK_XYZ), | ||
1092 | src[0], | ||
1093 | src[1]); | ||
1094 | break; | ||
1095 | |||
1096 | case TGSI_OPCODE_KIL: | ||
1097 | emit_op1(c, TGSI_OPCODE_KIL, | ||
1098 | dst_mask(dst_undef(), 0), | ||
1099 | src[0]); | ||
1100 | break; | ||
1101 | |||
1102 | case TGSI_OPCODE_END: | ||
1103 | emit_fb_write(c); | ||
1104 | break; | ||
1105 | default: | ||
1106 | if (!c->key.has_flow_control && | ||
1107 | brw_wm_is_scalar_result(opcode)) | ||
1108 | emit_scalar_insn(c, opcode, dst, src[0], src[1], src[2]); | ||
1109 | else | ||
1110 | emit_op3(c, opcode, dst, src[0], src[1], src[2]); | ||
1111 | break; | ||
1112 | } | ||
1113 | } | ||
1114 | |||
1115 | /** | ||
1116 | * Initial pass for fragment program code generation. | ||
1117 | * This function is used by both the GLSL and non-GLSL paths. | ||
1118 | */ | ||
1119 | int brw_wm_pass_fp( struct brw_wm_compile *c ) | ||
1120 | { | ||
1121 | struct brw_fragment_shader *fs = c->fp; | ||
1122 | struct tgsi_parse_context parse; | ||
1123 | struct tgsi_full_instruction *inst; | ||
1124 | struct tgsi_full_declaration *decl; | ||
1125 | const float *imm; | ||
1126 | GLuint size; | ||
1127 | GLuint i; | ||
1128 | |||
1129 | if (BRW_DEBUG & DEBUG_WM) { | ||
1130 | debug_printf("pre-fp:\n"); | ||
1131 | tgsi_dump(fs->tokens, 0); | ||
1132 | } | ||
1133 | |||
1134 | c->fp_pixel_xy = src_undef(); | ||
1135 | c->fp_delta_xy = src_undef(); | ||
1136 | c->fp_pixel_w = src_undef(); | ||
1137 | c->nr_fp_insns = 0; | ||
1138 | c->nr_immediates = 0; | ||
1139 | |||
1140 | |||
1141 | /* Loop over all instructions doing assorted simplifications and | ||
1142 | * transformations. | ||
1143 | */ | ||
1144 | tgsi_parse_init( &parse, fs->tokens ); | ||
1145 | while( !tgsi_parse_end_of_tokens( &parse ) ) { | ||
1146 | tgsi_parse_token( &parse ); | ||
1147 | |||
1148 | switch( parse.FullToken.Token.Type ) { | ||
1149 | case TGSI_TOKEN_TYPE_DECLARATION: | ||
1150 | /* Turn intput declarations into special WM_* instructions. | ||
1151 | * | ||
1152 | * XXX: For non-branching shaders, consider deferring variable | ||
1153 | * initialization as late as possible to minimize register | ||
1154 | * usage. This is how the original BRW driver worked. | ||
1155 | * | ||
1156 | * In a branching shader, must preamble instructions at decl | ||
1157 | * time, as instruction order in the shader does not | ||
1158 | * correspond to the order instructions are executed in the | ||
1159 | * wild. | ||
1160 | * | ||
1161 | * This is where special instructions such as WM_CINTERP, | ||
1162 | * WM_LINTERP, WM_PINTERP and WM_WPOSXY are emitted to | ||
1163 | * compute shader inputs from the payload registers and pixel | ||
1164 | * position. | ||
1165 | */ | ||
1166 | decl = &parse.FullToken.FullDeclaration; | ||
1167 | if( decl->Declaration.File == TGSI_FILE_INPUT ) { | ||
1168 | unsigned first, last, mask; | ||
1169 | unsigned attrib; | ||
1170 | |||
1171 | first = decl->Range.First; | ||
1172 | last = decl->Range.Last; | ||
1173 | mask = decl->Declaration.UsageMask; | ||
1174 | |||
1175 | for (attrib = first; attrib <= last; attrib++) { | ||
1176 | emit_interp(c, | ||
1177 | attrib, | ||
1178 | decl->Semantic.Name, | ||
1179 | decl->Declaration.Interpolate ); | ||
1180 | } | ||
1181 | } | ||
1182 | |||
1183 | break; | ||
1184 | |||
1185 | case TGSI_TOKEN_TYPE_IMMEDIATE: | ||
1186 | /* Unlike VS programs we can probably manage fine encoding | ||
1187 | * immediate values directly into the emitted EU | ||
1188 | * instructions, as we probably only need to reference one | ||
1189 | * float value per instruction. Just save the data for now | ||
1190 | * and use directly later. | ||
1191 | */ | ||
1192 | i = c->nr_immediates++; | ||
1193 | imm = &parse.FullToken.FullImmediate.u[i].Float; | ||
1194 | size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1; | ||
1195 | |||
1196 | if (c->nr_immediates >= BRW_WM_MAX_CONST) | ||
1197 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
1198 | |||
1199 | for (i = 0; i < size; i++) | ||
1200 | c->immediate[c->nr_immediates].v[i] = imm[i]; | ||
1201 | |||
1202 | for (; i < 4; i++) | ||
1203 | c->immediate[c->nr_immediates].v[i] = 0.0; | ||
1204 | |||
1205 | c->immediate[c->nr_immediates].nr = size; | ||
1206 | c->nr_immediates++; | ||
1207 | break; | ||
1208 | |||
1209 | case TGSI_TOKEN_TYPE_INSTRUCTION: | ||
1210 | inst = &parse.FullToken.FullInstruction; | ||
1211 | emit_insn(c, inst); | ||
1212 | break; | ||
1213 | } | ||
1214 | } | ||
1215 | |||
1216 | if (BRW_DEBUG & DEBUG_WM) { | ||
1217 | brw_wm_print_fp_program( c, "pass_fp" ); | ||
1218 | debug_printf("\n"); | ||
1219 | } | ||
1220 | |||
1221 | return c->error; | ||
1222 | } | ||
1223 | |||
diff --git a/src/gallium/drivers/i965/brw_wm_glsl.c b/src/gallium/drivers/i965/brw_wm_glsl.c deleted file mode 100644 index fb8e40d928e..00000000000 --- a/src/gallium/drivers/i965/brw_wm_glsl.c +++ /dev/null | |||
@@ -1,2032 +0,0 @@ | |||
1 | #include "util/u_math.h" | ||
2 | |||
3 | |||
4 | #include "brw_context.h" | ||
5 | #include "brw_eu.h" | ||
6 | #include "brw_wm.h" | ||
7 | |||
8 | |||
9 | static struct brw_reg get_dst_reg(struct brw_wm_compile *c, | ||
10 | const struct brw_fp_instruction *inst, | ||
11 | GLuint component); | ||
12 | |||
13 | |||
14 | static void | ||
15 | reclaim_temps(struct brw_wm_compile *c); | ||
16 | |||
17 | |||
18 | /** Mark GRF register as used. */ | ||
19 | static void | ||
20 | prealloc_grf(struct brw_wm_compile *c, int r) | ||
21 | { | ||
22 | c->used_grf[r] = GL_TRUE; | ||
23 | } | ||
24 | |||
25 | |||
26 | /** Mark given GRF register as not in use. */ | ||
27 | static void | ||
28 | release_grf(struct brw_wm_compile *c, int r) | ||
29 | { | ||
30 | /*assert(c->used_grf[r]);*/ | ||
31 | c->used_grf[r] = GL_FALSE; | ||
32 | c->first_free_grf = MIN2(c->first_free_grf, r); | ||
33 | } | ||
34 | |||
35 | |||
36 | /** Return index of a free GRF, mark it as used. */ | ||
37 | static int | ||
38 | alloc_grf(struct brw_wm_compile *c) | ||
39 | { | ||
40 | GLuint r; | ||
41 | for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) { | ||
42 | if (!c->used_grf[r]) { | ||
43 | c->used_grf[r] = GL_TRUE; | ||
44 | c->first_free_grf = r + 1; /* a guess */ | ||
45 | return r; | ||
46 | } | ||
47 | } | ||
48 | |||
49 | /* no free temps, try to reclaim some */ | ||
50 | reclaim_temps(c); | ||
51 | c->first_free_grf = 0; | ||
52 | |||
53 | /* try alloc again */ | ||
54 | for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) { | ||
55 | if (!c->used_grf[r]) { | ||
56 | c->used_grf[r] = GL_TRUE; | ||
57 | c->first_free_grf = r + 1; /* a guess */ | ||
58 | return r; | ||
59 | } | ||
60 | } | ||
61 | |||
62 | for (r = 0; r < BRW_WM_MAX_GRF; r++) { | ||
63 | assert(c->used_grf[r]); | ||
64 | } | ||
65 | |||
66 | /* really, no free GRF regs found */ | ||
67 | if (!c->out_of_regs) { | ||
68 | /* print warning once per compilation */ | ||
69 | debug_printf("%s: ran out of registers for fragment program", __FUNCTION__); | ||
70 | c->out_of_regs = GL_TRUE; | ||
71 | } | ||
72 | |||
73 | return -1; | ||
74 | } | ||
75 | |||
76 | |||
77 | /** Return number of GRF registers used */ | ||
78 | static int | ||
79 | num_grf_used(const struct brw_wm_compile *c) | ||
80 | { | ||
81 | int r; | ||
82 | for (r = BRW_WM_MAX_GRF - 1; r >= 0; r--) | ||
83 | if (c->used_grf[r]) | ||
84 | return r + 1; | ||
85 | return 0; | ||
86 | } | ||
87 | |||
88 | |||
89 | |||
90 | /** | ||
91 | * Record the mapping of a Mesa register to a hardware register. | ||
92 | */ | ||
93 | static void set_reg(struct brw_wm_compile *c, int file, int index, | ||
94 | int component, struct brw_reg reg) | ||
95 | { | ||
96 | c->wm_regs[file][index][component].reg = reg; | ||
97 | c->wm_regs[file][index][component].inited = GL_TRUE; | ||
98 | } | ||
99 | |||
100 | static struct brw_reg alloc_tmp(struct brw_wm_compile *c) | ||
101 | { | ||
102 | struct brw_reg reg; | ||
103 | |||
104 | /* if we need to allocate another temp, grow the tmp_regs[] array */ | ||
105 | if (c->tmp_index == c->tmp_max) { | ||
106 | int r = alloc_grf(c); | ||
107 | if (r < 0) { | ||
108 | /*printf("Out of temps in %s\n", __FUNCTION__);*/ | ||
109 | r = 50; /* XXX random register! */ | ||
110 | } | ||
111 | c->tmp_regs[ c->tmp_max++ ] = r; | ||
112 | } | ||
113 | |||
114 | /* form the GRF register */ | ||
115 | reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0); | ||
116 | /*printf("alloc_temp %d\n", reg.nr);*/ | ||
117 | assert(reg.nr < BRW_WM_MAX_GRF); | ||
118 | return reg; | ||
119 | |||
120 | } | ||
121 | |||
122 | /** | ||
123 | * Save current temp register info. | ||
124 | * There must be a matching call to release_tmps(). | ||
125 | */ | ||
126 | static int mark_tmps(struct brw_wm_compile *c) | ||
127 | { | ||
128 | return c->tmp_index; | ||
129 | } | ||
130 | |||
131 | static struct brw_reg lookup_tmp( struct brw_wm_compile *c, int index ) | ||
132 | { | ||
133 | return brw_vec8_grf( c->tmp_regs[ index ], 0 ); | ||
134 | } | ||
135 | |||
136 | static void release_tmps(struct brw_wm_compile *c, int mark) | ||
137 | { | ||
138 | c->tmp_index = mark; | ||
139 | } | ||
140 | |||
141 | /** | ||
142 | * Convert Mesa src register to brw register. | ||
143 | * | ||
144 | * Since we're running in SOA mode each Mesa register corresponds to four | ||
145 | * hardware registers. We allocate the hardware registers as needed here. | ||
146 | * | ||
147 | * \param file register file, one of PROGRAM_x | ||
148 | * \param index register number | ||
149 | * \param component src component (X=0, Y=1, Z=2, W=3) | ||
150 | * \param nr not used?!? | ||
151 | * \param neg negate value? | ||
152 | * \param abs take absolute value? | ||
153 | */ | ||
154 | static struct brw_reg | ||
155 | get_reg(struct brw_wm_compile *c, int file, int index, int component, | ||
156 | int nr, GLuint neg, GLuint abs) | ||
157 | { | ||
158 | struct brw_reg reg; | ||
159 | switch (file) { | ||
160 | case TGSI_FILE_NULL: | ||
161 | return brw_null_reg(); | ||
162 | |||
163 | case TGSI_FILE_CONSTANT: | ||
164 | case TGSI_FILE_TEMPORARY: | ||
165 | case TGSI_FILE_INPUT: | ||
166 | case TGSI_FILE_OUTPUT: | ||
167 | case BRW_FILE_PAYLOAD: | ||
168 | break; | ||
169 | |||
170 | default: | ||
171 | debug_printf("%s: Unexpected file type\n", __FUNCTION__); | ||
172 | return brw_null_reg(); | ||
173 | } | ||
174 | |||
175 | assert(index < 256); | ||
176 | assert(component < 4); | ||
177 | |||
178 | /* see if we've already allocated a HW register for this Mesa register */ | ||
179 | if (c->wm_regs[file][index][component].inited) { | ||
180 | /* yes, re-use */ | ||
181 | reg = c->wm_regs[file][index][component].reg; | ||
182 | } | ||
183 | else { | ||
184 | /* no, allocate new register */ | ||
185 | int grf = alloc_grf(c); | ||
186 | /*printf("alloc grf %d for reg %d:%d.%d\n", grf, file, index, component);*/ | ||
187 | if (grf < 0) { | ||
188 | /* totally out of temps */ | ||
189 | grf = 51; /* XXX random register! */ | ||
190 | } | ||
191 | |||
192 | reg = brw_vec8_grf(grf, 0); | ||
193 | /*printf("Alloc new grf %d for %d.%d\n", reg.nr, index, component);*/ | ||
194 | |||
195 | set_reg(c, file, index, component, reg); | ||
196 | } | ||
197 | |||
198 | if (neg & (1 << component)) { | ||
199 | reg = negate(reg); | ||
200 | } | ||
201 | if (abs) | ||
202 | reg = brw_abs(reg); | ||
203 | return reg; | ||
204 | } | ||
205 | |||
206 | |||
207 | |||
208 | |||
209 | /** | ||
210 | * Find first/last instruction that references each temporary register. | ||
211 | */ | ||
212 | GLboolean | ||
213 | _mesa_find_temp_intervals(const struct prog_instruction *instructions, | ||
214 | GLuint numInstructions, | ||
215 | GLint intBegin[MAX_PROGRAM_TEMPS], | ||
216 | GLint intEnd[MAX_PROGRAM_TEMPS]) | ||
217 | { | ||
218 | struct loop_info | ||
219 | { | ||
220 | GLuint Start, End; /**< Start, end instructions of loop */ | ||
221 | }; | ||
222 | struct loop_info loopStack[MAX_LOOP_NESTING]; | ||
223 | GLuint loopStackDepth = 0; | ||
224 | GLuint i; | ||
225 | |||
226 | for (i = 0; i < MAX_PROGRAM_TEMPS; i++){ | ||
227 | intBegin[i] = intEnd[i] = -1; | ||
228 | } | ||
229 | |||
230 | /* Scan instructions looking for temporary registers */ | ||
231 | for (i = 0; i < numInstructions; i++) { | ||
232 | const struct prog_instruction *inst = instructions + i; | ||
233 | if (inst->Opcode == OPCODE_BGNLOOP) { | ||
234 | loopStack[loopStackDepth].Start = i; | ||
235 | loopStack[loopStackDepth].End = inst->BranchTarget; | ||
236 | loopStackDepth++; | ||
237 | } | ||
238 | else if (inst->Opcode == OPCODE_ENDLOOP) { | ||
239 | loopStackDepth--; | ||
240 | } | ||
241 | else if (inst->Opcode == OPCODE_CAL) { | ||
242 | return GL_FALSE; | ||
243 | } | ||
244 | else { | ||
245 | const GLuint numSrc = 3; | ||
246 | GLuint j; | ||
247 | for (j = 0; j < numSrc; j++) { | ||
248 | if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) { | ||
249 | const GLuint index = inst->SrcReg[j].Index; | ||
250 | if (inst->SrcReg[j].RelAddr) | ||
251 | return GL_FALSE; | ||
252 | update_interval(intBegin, intEnd, index, i); | ||
253 | if (loopStackDepth > 0) { | ||
254 | /* extend temp register's interval to end of loop */ | ||
255 | GLuint loopEnd = loopStack[loopStackDepth - 1].End; | ||
256 | update_interval(intBegin, intEnd, index, loopEnd); | ||
257 | } | ||
258 | } | ||
259 | } | ||
260 | if (inst->DstReg.File == PROGRAM_TEMPORARY) { | ||
261 | const GLuint index = inst->DstReg.Index; | ||
262 | if (inst->DstReg.RelAddr) | ||
263 | return GL_FALSE; | ||
264 | update_interval(intBegin, intEnd, index, i); | ||
265 | if (loopStackDepth > 0) { | ||
266 | /* extend temp register's interval to end of loop */ | ||
267 | GLuint loopEnd = loopStack[loopStackDepth - 1].End; | ||
268 | update_interval(intBegin, intEnd, index, loopEnd); | ||
269 | } | ||
270 | } | ||
271 | } | ||
272 | } | ||
273 | |||
274 | return GL_TRUE; | ||
275 | } | ||
276 | |||
277 | |||
278 | /** | ||
279 | * This is called if we run out of GRF registers. Examine the live intervals | ||
280 | * of temp regs in the program and free those which won't be used again. | ||
281 | */ | ||
282 | static void | ||
283 | reclaim_temps(struct brw_wm_compile *c) | ||
284 | { | ||
285 | GLint intBegin[BRW_WM_MAX_TEMPS]; | ||
286 | GLint intEnd[BRW_WM_MAX_TEMPS]; | ||
287 | int index; | ||
288 | |||
289 | /*printf("Reclaim temps:\n");*/ | ||
290 | |||
291 | _mesa_find_temp_intervals(c->fp_instructions, c->nr_fp_insns, | ||
292 | intBegin, intEnd); | ||
293 | |||
294 | for (index = 0; index < BRW_WM_MAX_TEMPS; index++) { | ||
295 | if (intEnd[index] != -1 && intEnd[index] < c->cur_inst) { | ||
296 | /* program temp[i] can be freed */ | ||
297 | int component; | ||
298 | /*printf(" temp[%d] is dead\n", index);*/ | ||
299 | for (component = 0; component < 4; component++) { | ||
300 | if (c->wm_regs[TGSI_FILE_TEMPORARY][index][component].inited) { | ||
301 | int r = c->wm_regs[TGSI_FILE_TEMPORARY][index][component].reg.nr; | ||
302 | release_grf(c, r); | ||
303 | /* | ||
304 | printf(" Reclaim temp %d, reg %d at inst %d\n", | ||
305 | index, r, c->cur_inst); | ||
306 | */ | ||
307 | c->wm_regs[TGSI_FILE_TEMPORARY][index][component].inited = GL_FALSE; | ||
308 | } | ||
309 | } | ||
310 | } | ||
311 | } | ||
312 | } | ||
313 | |||
314 | |||
315 | |||
316 | |||
317 | /** | ||
318 | * Preallocate registers. This sets up the Mesa to hardware register | ||
319 | * mapping for certain registers, such as constants (uniforms/state vars) | ||
320 | * and shader inputs. | ||
321 | */ | ||
322 | static void prealloc_reg(struct brw_wm_compile *c) | ||
323 | { | ||
324 | int i, j; | ||
325 | struct brw_reg reg; | ||
326 | int urb_read_length = 0; | ||
327 | GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted; | ||
328 | GLuint reg_index = 0; | ||
329 | |||
330 | memset(c->used_grf, GL_FALSE, sizeof(c->used_grf)); | ||
331 | c->first_free_grf = 0; | ||
332 | |||
333 | for (i = 0; i < 4; i++) { | ||
334 | if (i < c->key.nr_depth_regs) | ||
335 | reg = brw_vec8_grf(i * 2, 0); | ||
336 | else | ||
337 | reg = brw_vec8_grf(0, 0); | ||
338 | set_reg(c, TGSI_FILE_PAYLOAD, PAYLOAD_DEPTH, i, reg); | ||
339 | } | ||
340 | reg_index += 2 * c->key.nr_depth_regs; | ||
341 | |||
342 | /* constants */ | ||
343 | { | ||
344 | const GLuint nr_params = c->fp->program.Base.Parameters->NumParameters; | ||
345 | const GLuint nr_temps = c->fp->program.Base.NumTemporaries; | ||
346 | |||
347 | /* use a real constant buffer, or just use a section of the GRF? */ | ||
348 | /* XXX this heuristic may need adjustment... */ | ||
349 | if ((nr_params + nr_temps) * 4 + reg_index > 80) | ||
350 | c->fp->use_const_buffer = GL_TRUE; | ||
351 | else | ||
352 | c->fp->use_const_buffer = GL_FALSE; | ||
353 | /*printf("WM use_const_buffer = %d\n", c->fp->use_const_buffer);*/ | ||
354 | |||
355 | if (c->fp->use_const_buffer) { | ||
356 | /* We'll use a real constant buffer and fetch constants from | ||
357 | * it with a dataport read message. | ||
358 | */ | ||
359 | |||
360 | /* number of float constants in CURBE */ | ||
361 | c->prog_data.nr_params = 0; | ||
362 | } | ||
363 | else { | ||
364 | const struct gl_program_parameter_list *plist = | ||
365 | c->fp->program.Base.Parameters; | ||
366 | int index = 0; | ||
367 | |||
368 | /* number of float constants in CURBE */ | ||
369 | c->prog_data.nr_params = 4 * nr_params; | ||
370 | |||
371 | /* loop over program constants (float[4]) */ | ||
372 | for (i = 0; i < nr_params; i++) { | ||
373 | /* loop over XYZW channels */ | ||
374 | for (j = 0; j < 4; j++, index++) { | ||
375 | reg = brw_vec1_grf(reg_index + index / 8, index % 8); | ||
376 | /* Save pointer to parameter/constant value. | ||
377 | * Constants will be copied in prepare_constant_buffer() | ||
378 | */ | ||
379 | c->prog_data.param[index] = &plist->ParameterValues[i][j]; | ||
380 | set_reg(c, TGSI_FILE_STATE_VAR, i, j, reg); | ||
381 | } | ||
382 | } | ||
383 | /* number of constant regs used (each reg is float[8]) */ | ||
384 | c->nr_creg = 2 * ((4 * nr_params + 15) / 16); | ||
385 | reg_index += c->nr_creg; | ||
386 | } | ||
387 | } | ||
388 | |||
389 | /* fragment shader inputs */ | ||
390 | for (i = 0; i < VERT_RESULT_MAX; i++) { | ||
391 | int fp_input; | ||
392 | |||
393 | if (i >= VERT_RESULT_VAR0) | ||
394 | fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0; | ||
395 | else if (i <= VERT_RESULT_TEX7) | ||
396 | fp_input = i; | ||
397 | else | ||
398 | fp_input = -1; | ||
399 | |||
400 | if (fp_input >= 0 && inputs & (1 << fp_input)) { | ||
401 | urb_read_length = reg_index; | ||
402 | reg = brw_vec8_grf(reg_index, 0); | ||
403 | for (j = 0; j < 4; j++) | ||
404 | set_reg(c, TGSI_FILE_PAYLOAD, fp_input, j, reg); | ||
405 | } | ||
406 | if (c->key.nr_vp_outputs > i) { | ||
407 | reg_index += 2; | ||
408 | } | ||
409 | } | ||
410 | |||
411 | c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2; | ||
412 | c->prog_data.urb_read_length = urb_read_length; | ||
413 | c->prog_data.curb_read_length = c->nr_creg; | ||
414 | c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0); | ||
415 | reg_index++; | ||
416 | c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0); | ||
417 | reg_index += 2; | ||
418 | |||
419 | /* mark GRF regs [0..reg_index-1] as in-use */ | ||
420 | for (i = 0; i < reg_index; i++) | ||
421 | prealloc_grf(c, i); | ||
422 | |||
423 | /* Don't use GRF 126, 127. Using them seems to lead to GPU lock-ups */ | ||
424 | prealloc_grf(c, 126); | ||
425 | prealloc_grf(c, 127); | ||
426 | |||
427 | for (i = 0; i < c->nr_fp_insns; i++) { | ||
428 | const struct brw_fp_instruction *inst = &c->fp_instructions[i]; | ||
429 | struct brw_reg dst[4]; | ||
430 | |||
431 | switch (inst->Opcode) { | ||
432 | case OPCODE_TEX: | ||
433 | case OPCODE_TXB: | ||
434 | /* Allocate the channels of texture results contiguously, | ||
435 | * since they are written out that way by the sampler unit. | ||
436 | */ | ||
437 | for (j = 0; j < 4; j++) { | ||
438 | dst[j] = get_dst_reg(c, inst, j); | ||
439 | if (j != 0) | ||
440 | assert(dst[j].nr == dst[j - 1].nr + 1); | ||
441 | } | ||
442 | break; | ||
443 | default: | ||
444 | break; | ||
445 | } | ||
446 | } | ||
447 | |||
448 | /* An instruction may reference up to three constants. | ||
449 | * They'll be found in these registers. | ||
450 | * XXX alloc these on demand! | ||
451 | */ | ||
452 | if (c->fp->use_const_buffer) { | ||
453 | for (i = 0; i < 3; i++) { | ||
454 | c->current_const[i].index = -1; | ||
455 | c->current_const[i].reg = brw_vec8_grf(alloc_grf(c), 0); | ||
456 | } | ||
457 | } | ||
458 | #if 0 | ||
459 | printf("USE CONST BUFFER? %d\n", c->fp->use_const_buffer); | ||
460 | printf("AFTER PRE_ALLOC, reg_index = %d\n", reg_index); | ||
461 | #endif | ||
462 | } | ||
463 | |||
464 | |||
465 | /** | ||
466 | * Check if any of the instruction's src registers are constants, uniforms, | ||
467 | * or statevars. If so, fetch any constants that we don't already have in | ||
468 | * the three GRF slots. | ||
469 | */ | ||
470 | static void fetch_constants(struct brw_wm_compile *c, | ||
471 | const struct brw_fp_instruction *inst) | ||
472 | { | ||
473 | struct brw_compile *p = &c->func; | ||
474 | GLuint i; | ||
475 | |||
476 | /* loop over instruction src regs */ | ||
477 | for (i = 0; i < 3; i++) { | ||
478 | const struct prog_src_register *src = &inst->SrcReg[i]; | ||
479 | if (src->File == TGSI_FILE_IMMEDIATE || | ||
480 | src->File == TGSI_FILE_CONSTANT) { | ||
481 | c->current_const[i].index = src->Index; | ||
482 | |||
483 | #if 0 | ||
484 | printf(" fetch const[%d] for arg %d into reg %d\n", | ||
485 | src->Index, i, c->current_const[i].reg.nr); | ||
486 | #endif | ||
487 | |||
488 | /* need to fetch the constant now */ | ||
489 | brw_dp_READ_4(p, | ||
490 | c->current_const[i].reg, /* writeback dest */ | ||
491 | src->RelAddr, /* relative indexing? */ | ||
492 | 16 * src->Index, /* byte offset */ | ||
493 | SURF_INDEX_FRAG_CONST_BUFFER/* binding table index */ | ||
494 | ); | ||
495 | } | ||
496 | } | ||
497 | } | ||
498 | |||
499 | |||
500 | /** | ||
501 | * Convert Mesa dst register to brw register. | ||
502 | */ | ||
503 | static struct brw_reg get_dst_reg(struct brw_wm_compile *c, | ||
504 | const struct brw_fp_instruction *inst, | ||
505 | GLuint component) | ||
506 | { | ||
507 | const int nr = 1; | ||
508 | return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr, | ||
509 | 0, 0); | ||
510 | } | ||
511 | |||
512 | |||
513 | static struct brw_reg | ||
514 | get_src_reg_const(struct brw_wm_compile *c, | ||
515 | const struct brw_fp_instruction *inst, | ||
516 | GLuint srcRegIndex, GLuint component) | ||
517 | { | ||
518 | /* We should have already fetched the constant from the constant | ||
519 | * buffer in fetch_constants(). Now we just have to return a | ||
520 | * register description that extracts the needed component and | ||
521 | * smears it across all eight vector components. | ||
522 | */ | ||
523 | const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; | ||
524 | struct brw_reg const_reg; | ||
525 | |||
526 | assert(component < 4); | ||
527 | assert(srcRegIndex < 3); | ||
528 | assert(c->current_const[srcRegIndex].index != -1); | ||
529 | const_reg = c->current_const[srcRegIndex].reg; | ||
530 | |||
531 | /* extract desired float from the const_reg, and smear */ | ||
532 | const_reg = stride(const_reg, 0, 1, 0); | ||
533 | const_reg.subnr = component * 4; | ||
534 | |||
535 | if (src->Negate) | ||
536 | const_reg = negate(const_reg); | ||
537 | if (src->Abs) | ||
538 | const_reg = brw_abs(const_reg); | ||
539 | |||
540 | #if 0 | ||
541 | printf(" form const[%d].%d for arg %d, reg %d\n", | ||
542 | c->current_const[srcRegIndex].index, | ||
543 | component, | ||
544 | srcRegIndex, | ||
545 | const_reg.nr); | ||
546 | #endif | ||
547 | |||
548 | return const_reg; | ||
549 | } | ||
550 | |||
551 | |||
552 | /** | ||
553 | * Convert Mesa src register to brw register. | ||
554 | */ | ||
555 | static struct brw_reg get_src_reg(struct brw_wm_compile *c, | ||
556 | const struct brw_fp_instruction *inst, | ||
557 | GLuint srcRegIndex, GLuint channel) | ||
558 | { | ||
559 | const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; | ||
560 | const GLuint nr = 1; | ||
561 | const GLuint component = BRW_GET_SWZ(src->Swizzle, channel); | ||
562 | |||
563 | /* Extended swizzle terms */ | ||
564 | if (component == SWIZZLE_ZERO) { | ||
565 | return brw_imm_f(0.0F); | ||
566 | } | ||
567 | else if (component == SWIZZLE_ONE) { | ||
568 | return brw_imm_f(1.0F); | ||
569 | } | ||
570 | |||
571 | if (c->fp->use_const_buffer && | ||
572 | (src->File == TGSI_FILE_STATE_VAR || | ||
573 | src->File == TGSI_FILE_CONSTANT || | ||
574 | src->File == TGSI_FILE_UNIFORM)) { | ||
575 | return get_src_reg_const(c, inst, srcRegIndex, component); | ||
576 | } | ||
577 | else { | ||
578 | /* other type of source register */ | ||
579 | return get_reg(c, src->File, src->Index, component, nr, | ||
580 | src->Negate, src->Abs); | ||
581 | } | ||
582 | } | ||
583 | |||
584 | |||
585 | /** | ||
586 | * Same as \sa get_src_reg() but if the register is a immediate, emit | ||
587 | * a brw_reg encoding the immediate. | ||
588 | * Note that a brw instruction only allows one src operand to be a immediate. | ||
589 | * For instructions with more than one operand, only the second can be a | ||
590 | * immediate. This means that we treat some immediates as constants | ||
591 | * (which why TGSI_FILE_IMMEDIATE is checked in fetch_constants()). | ||
592 | * | ||
593 | */ | ||
594 | static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, | ||
595 | const struct brw_fp_instruction *inst, | ||
596 | GLuint srcRegIndex, GLuint channel) | ||
597 | { | ||
598 | const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; | ||
599 | if (src->File == TGSI_FILE_IMMEDIATE) { | ||
600 | /* an immediate */ | ||
601 | const int component = BRW_GET_SWZ(src->Swizzle, channel); | ||
602 | const GLfloat *param = | ||
603 | c->fp->program.Base.Parameters->ParameterValues[src->Index]; | ||
604 | GLfloat value = param[component]; | ||
605 | if (src->Negate) | ||
606 | value = -value; | ||
607 | if (src->Abs) | ||
608 | value = FABSF(value); | ||
609 | #if 0 | ||
610 | printf(" form immed value %f for chan %d\n", value, channel); | ||
611 | #endif | ||
612 | return brw_imm_f(value); | ||
613 | } | ||
614 | else { | ||
615 | return get_src_reg(c, inst, srcRegIndex, channel); | ||
616 | } | ||
617 | } | ||
618 | |||
619 | |||
620 | /** | ||
621 | * Subroutines are minimal support for resusable instruction sequences. | ||
622 | * They are implemented as simply as possible to minimise overhead: there | ||
623 | * is no explicit support for communication between the caller and callee | ||
624 | * other than saving the return address in a temporary register, nor is | ||
625 | * there any automatic local storage. This implies that great care is | ||
626 | * required before attempting reentrancy or any kind of nested | ||
627 | * subroutine invocations. | ||
628 | */ | ||
629 | static void invoke_subroutine( struct brw_wm_compile *c, | ||
630 | enum _subroutine subroutine, | ||
631 | void (*emit)( struct brw_wm_compile * ) ) | ||
632 | { | ||
633 | struct brw_compile *p = &c->func; | ||
634 | |||
635 | assert( subroutine < BRW_WM_MAX_SUBROUTINE ); | ||
636 | |||
637 | if( c->subroutines[ subroutine ] ) { | ||
638 | /* subroutine previously emitted: reuse existing instructions */ | ||
639 | |||
640 | int mark = mark_tmps( c ); | ||
641 | struct brw_reg return_address = retype( alloc_tmp( c ), | ||
642 | BRW_REGISTER_TYPE_UD ); | ||
643 | int here = p->nr_insn; | ||
644 | |||
645 | brw_push_insn_state(p); | ||
646 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
647 | brw_ADD( p, return_address, brw_ip_reg(), brw_imm_ud( 2 << 4 ) ); | ||
648 | |||
649 | brw_ADD( p, brw_ip_reg(), brw_ip_reg(), | ||
650 | brw_imm_d( ( c->subroutines[ subroutine ] - | ||
651 | here - 1 ) << 4 ) ); | ||
652 | brw_pop_insn_state(p); | ||
653 | |||
654 | release_tmps( c, mark ); | ||
655 | } else { | ||
656 | /* previously unused subroutine: emit, and mark for later reuse */ | ||
657 | |||
658 | int mark = mark_tmps( c ); | ||
659 | struct brw_reg return_address = retype( alloc_tmp( c ), | ||
660 | BRW_REGISTER_TYPE_UD ); | ||
661 | struct brw_instruction *calc; | ||
662 | int base = p->nr_insn; | ||
663 | |||
664 | brw_push_insn_state(p); | ||
665 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
666 | calc = brw_ADD( p, return_address, brw_ip_reg(), brw_imm_ud( 0 ) ); | ||
667 | brw_pop_insn_state(p); | ||
668 | |||
669 | c->subroutines[ subroutine ] = p->nr_insn; | ||
670 | |||
671 | emit( c ); | ||
672 | |||
673 | brw_push_insn_state(p); | ||
674 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
675 | brw_MOV( p, brw_ip_reg(), return_address ); | ||
676 | brw_pop_insn_state(p); | ||
677 | |||
678 | brw_set_src1( calc, brw_imm_ud( ( p->nr_insn - base ) << 4 ) ); | ||
679 | |||
680 | release_tmps( c, mark ); | ||
681 | } | ||
682 | } | ||
683 | |||
684 | static void emit_trunc( struct brw_wm_compile *c, | ||
685 | const struct brw_fp_instruction *inst) | ||
686 | { | ||
687 | int i; | ||
688 | struct brw_compile *p = &c->func; | ||
689 | GLuint mask = inst->DstReg.WriteMask; | ||
690 | brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); | ||
691 | for (i = 0; i < 4; i++) { | ||
692 | if (mask & (1<<i)) { | ||
693 | struct brw_reg src, dst; | ||
694 | dst = get_dst_reg(c, inst, i); | ||
695 | src = get_src_reg(c, inst, 0, i); | ||
696 | brw_RNDZ(p, dst, src); | ||
697 | } | ||
698 | } | ||
699 | brw_set_saturate(p, 0); | ||
700 | } | ||
701 | |||
702 | static void emit_mov( struct brw_wm_compile *c, | ||
703 | const struct brw_fp_instruction *inst) | ||
704 | { | ||
705 | int i; | ||
706 | struct brw_compile *p = &c->func; | ||
707 | GLuint mask = inst->DstReg.WriteMask; | ||
708 | brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); | ||
709 | for (i = 0; i < 4; i++) { | ||
710 | if (mask & (1<<i)) { | ||
711 | struct brw_reg src, dst; | ||
712 | dst = get_dst_reg(c, inst, i); | ||
713 | /* XXX some moves from immediate value don't work reliably!!! */ | ||
714 | /*src = get_src_reg_imm(c, inst, 0, i);*/ | ||
715 | src = get_src_reg(c, inst, 0, i); | ||
716 | brw_MOV(p, dst, src); | ||
717 | } | ||
718 | } | ||
719 | brw_set_saturate(p, 0); | ||
720 | } | ||
721 | |||
722 | static void emit_pixel_xy(struct brw_wm_compile *c, | ||
723 | const struct brw_fp_instruction *inst) | ||
724 | { | ||
725 | struct brw_reg r1 = brw_vec1_grf(1, 0); | ||
726 | struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); | ||
727 | |||
728 | struct brw_reg dst0, dst1; | ||
729 | struct brw_compile *p = &c->func; | ||
730 | GLuint mask = inst->DstReg.WriteMask; | ||
731 | |||
732 | dst0 = get_dst_reg(c, inst, 0); | ||
733 | dst1 = get_dst_reg(c, inst, 1); | ||
734 | /* Calculate pixel centers by adding 1 or 0 to each of the | ||
735 | * micro-tile coordinates passed in r1. | ||
736 | */ | ||
737 | if (mask & WRITEMASK_X) { | ||
738 | brw_ADD(p, | ||
739 | vec8(retype(dst0, BRW_REGISTER_TYPE_UW)), | ||
740 | stride(suboffset(r1_uw, 4), 2, 4, 0), | ||
741 | brw_imm_v(0x10101010)); | ||
742 | } | ||
743 | |||
744 | if (mask & WRITEMASK_Y) { | ||
745 | brw_ADD(p, | ||
746 | vec8(retype(dst1, BRW_REGISTER_TYPE_UW)), | ||
747 | stride(suboffset(r1_uw, 5), 2, 4, 0), | ||
748 | brw_imm_v(0x11001100)); | ||
749 | } | ||
750 | } | ||
751 | |||
752 | static void emit_delta_xy(struct brw_wm_compile *c, | ||
753 | const struct brw_fp_instruction *inst) | ||
754 | { | ||
755 | struct brw_reg r1 = brw_vec1_grf(1, 0); | ||
756 | struct brw_reg dst0, dst1, src0, src1; | ||
757 | struct brw_compile *p = &c->func; | ||
758 | GLuint mask = inst->DstReg.WriteMask; | ||
759 | |||
760 | dst0 = get_dst_reg(c, inst, 0); | ||
761 | dst1 = get_dst_reg(c, inst, 1); | ||
762 | src0 = get_src_reg(c, inst, 0, 0); | ||
763 | src1 = get_src_reg(c, inst, 0, 1); | ||
764 | /* Calc delta X,Y by subtracting origin in r1 from the pixel | ||
765 | * centers. | ||
766 | */ | ||
767 | if (mask & WRITEMASK_X) { | ||
768 | brw_ADD(p, | ||
769 | dst0, | ||
770 | retype(src0, BRW_REGISTER_TYPE_UW), | ||
771 | negate(r1)); | ||
772 | } | ||
773 | |||
774 | if (mask & WRITEMASK_Y) { | ||
775 | brw_ADD(p, | ||
776 | dst1, | ||
777 | retype(src1, BRW_REGISTER_TYPE_UW), | ||
778 | negate(suboffset(r1,1))); | ||
779 | |||
780 | } | ||
781 | } | ||
782 | |||
783 | static void fire_fb_write( struct brw_wm_compile *c, | ||
784 | GLuint base_reg, | ||
785 | GLuint nr, | ||
786 | GLuint target, | ||
787 | GLuint eot) | ||
788 | { | ||
789 | struct brw_compile *p = &c->func; | ||
790 | /* Pass through control information: | ||
791 | */ | ||
792 | /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ | ||
793 | { | ||
794 | brw_push_insn_state(p); | ||
795 | brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */ | ||
796 | brw_MOV(p, | ||
797 | brw_message_reg(base_reg + 1), | ||
798 | brw_vec8_grf(1, 0)); | ||
799 | brw_pop_insn_state(p); | ||
800 | } | ||
801 | /* Send framebuffer write message: */ | ||
802 | brw_fb_WRITE(p, | ||
803 | retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), | ||
804 | base_reg, | ||
805 | retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), | ||
806 | target, | ||
807 | nr, | ||
808 | 0, | ||
809 | eot); | ||
810 | } | ||
811 | |||
812 | static void emit_fb_write(struct brw_wm_compile *c, | ||
813 | const struct brw_fp_instruction *inst) | ||
814 | { | ||
815 | struct brw_compile *p = &c->func; | ||
816 | int nr = 2; | ||
817 | int channel; | ||
818 | GLuint target, eot; | ||
819 | struct brw_reg src0; | ||
820 | |||
821 | /* Reserve a space for AA - may not be needed: | ||
822 | */ | ||
823 | if (c->key.aa_dest_stencil_reg) | ||
824 | nr += 1; | ||
825 | |||
826 | brw_push_insn_state(p); | ||
827 | for (channel = 0; channel < 4; channel++) { | ||
828 | src0 = get_src_reg(c, inst, 0, channel); | ||
829 | /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ | ||
830 | /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ | ||
831 | brw_MOV(p, brw_message_reg(nr + channel), src0); | ||
832 | } | ||
833 | /* skip over the regs populated above: */ | ||
834 | nr += 8; | ||
835 | brw_pop_insn_state(p); | ||
836 | |||
837 | if (c->key.source_depth_to_render_target) { | ||
838 | if (c->key.computes_depth) { | ||
839 | src0 = get_src_reg(c, inst, 2, 2); | ||
840 | brw_MOV(p, brw_message_reg(nr), src0); | ||
841 | } | ||
842 | else { | ||
843 | src0 = get_src_reg(c, inst, 1, 1); | ||
844 | brw_MOV(p, brw_message_reg(nr), src0); | ||
845 | } | ||
846 | |||
847 | nr += 2; | ||
848 | } | ||
849 | |||
850 | if (c->key.dest_depth_reg) { | ||
851 | const GLuint comp = c->key.dest_depth_reg / 2; | ||
852 | const GLuint off = c->key.dest_depth_reg % 2; | ||
853 | |||
854 | if (off != 0) { | ||
855 | /* XXX this code needs review/testing */ | ||
856 | struct brw_reg arg1_0 = get_src_reg(c, inst, 1, comp); | ||
857 | struct brw_reg arg1_1 = get_src_reg(c, inst, 1, comp+1); | ||
858 | |||
859 | brw_push_insn_state(p); | ||
860 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
861 | |||
862 | brw_MOV(p, brw_message_reg(nr), offset(arg1_0, 1)); | ||
863 | /* 2nd half? */ | ||
864 | brw_MOV(p, brw_message_reg(nr+1), arg1_1); | ||
865 | brw_pop_insn_state(p); | ||
866 | } | ||
867 | else | ||
868 | { | ||
869 | struct brw_reg src = get_src_reg(c, inst, 1, 1); | ||
870 | brw_MOV(p, brw_message_reg(nr), src); | ||
871 | } | ||
872 | nr += 2; | ||
873 | } | ||
874 | |||
875 | target = inst->Aux >> 1; | ||
876 | eot = inst->Aux & 1; | ||
877 | fire_fb_write(c, 0, nr, target, eot); | ||
878 | } | ||
879 | |||
880 | static void emit_pixel_w( struct brw_wm_compile *c, | ||
881 | const struct brw_fp_instruction *inst) | ||
882 | { | ||
883 | struct brw_compile *p = &c->func; | ||
884 | GLuint mask = inst->DstReg.WriteMask; | ||
885 | if (mask & WRITEMASK_W) { | ||
886 | struct brw_reg dst, src0, delta0, delta1; | ||
887 | struct brw_reg interp3; | ||
888 | |||
889 | dst = get_dst_reg(c, inst, 3); | ||
890 | src0 = get_src_reg(c, inst, 0, 0); | ||
891 | delta0 = get_src_reg(c, inst, 1, 0); | ||
892 | delta1 = get_src_reg(c, inst, 1, 1); | ||
893 | |||
894 | interp3 = brw_vec1_grf(src0.nr+1, 4); | ||
895 | /* Calc 1/w - just linterp wpos[3] optimized by putting the | ||
896 | * result straight into a message reg. | ||
897 | */ | ||
898 | brw_LINE(p, brw_null_reg(), interp3, delta0); | ||
899 | brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1); | ||
900 | |||
901 | /* Calc w */ | ||
902 | brw_math_16( p, dst, | ||
903 | BRW_MATH_FUNCTION_INV, | ||
904 | BRW_MATH_SATURATE_NONE, | ||
905 | 2, brw_null_reg(), | ||
906 | BRW_MATH_PRECISION_FULL); | ||
907 | } | ||
908 | } | ||
909 | |||
910 | static void emit_linterp(struct brw_wm_compile *c, | ||
911 | const struct brw_fp_instruction *inst) | ||
912 | { | ||
913 | struct brw_compile *p = &c->func; | ||
914 | GLuint mask = inst->DstReg.WriteMask; | ||
915 | struct brw_reg interp[4]; | ||
916 | struct brw_reg dst, delta0, delta1; | ||
917 | struct brw_reg src0; | ||
918 | GLuint nr, i; | ||
919 | |||
920 | src0 = get_src_reg(c, inst, 0, 0); | ||
921 | delta0 = get_src_reg(c, inst, 1, 0); | ||
922 | delta1 = get_src_reg(c, inst, 1, 1); | ||
923 | nr = src0.nr; | ||
924 | |||
925 | interp[0] = brw_vec1_grf(nr, 0); | ||
926 | interp[1] = brw_vec1_grf(nr, 4); | ||
927 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
928 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
929 | |||
930 | for(i = 0; i < 4; i++ ) { | ||
931 | if (mask & (1<<i)) { | ||
932 | dst = get_dst_reg(c, inst, i); | ||
933 | brw_LINE(p, brw_null_reg(), interp[i], delta0); | ||
934 | brw_MAC(p, dst, suboffset(interp[i],1), delta1); | ||
935 | } | ||
936 | } | ||
937 | } | ||
938 | |||
939 | static void emit_cinterp(struct brw_wm_compile *c, | ||
940 | const struct brw_fp_instruction *inst) | ||
941 | { | ||
942 | struct brw_compile *p = &c->func; | ||
943 | GLuint mask = inst->DstReg.WriteMask; | ||
944 | |||
945 | struct brw_reg interp[4]; | ||
946 | struct brw_reg dst, src0; | ||
947 | GLuint nr, i; | ||
948 | |||
949 | src0 = get_src_reg(c, inst, 0, 0); | ||
950 | nr = src0.nr; | ||
951 | |||
952 | interp[0] = brw_vec1_grf(nr, 0); | ||
953 | interp[1] = brw_vec1_grf(nr, 4); | ||
954 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
955 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
956 | |||
957 | for(i = 0; i < 4; i++ ) { | ||
958 | if (mask & (1<<i)) { | ||
959 | dst = get_dst_reg(c, inst, i); | ||
960 | brw_MOV(p, dst, suboffset(interp[i],3)); | ||
961 | } | ||
962 | } | ||
963 | } | ||
964 | |||
965 | static void emit_pinterp(struct brw_wm_compile *c, | ||
966 | const struct brw_fp_instruction *inst) | ||
967 | { | ||
968 | struct brw_compile *p = &c->func; | ||
969 | GLuint mask = inst->DstReg.WriteMask; | ||
970 | |||
971 | struct brw_reg interp[4]; | ||
972 | struct brw_reg dst, delta0, delta1; | ||
973 | struct brw_reg src0, w; | ||
974 | GLuint nr, i; | ||
975 | |||
976 | src0 = get_src_reg(c, inst, 0, 0); | ||
977 | delta0 = get_src_reg(c, inst, 1, 0); | ||
978 | delta1 = get_src_reg(c, inst, 1, 1); | ||
979 | w = get_src_reg(c, inst, 2, 3); | ||
980 | nr = src0.nr; | ||
981 | |||
982 | interp[0] = brw_vec1_grf(nr, 0); | ||
983 | interp[1] = brw_vec1_grf(nr, 4); | ||
984 | interp[2] = brw_vec1_grf(nr+1, 0); | ||
985 | interp[3] = brw_vec1_grf(nr+1, 4); | ||
986 | |||
987 | for(i = 0; i < 4; i++ ) { | ||
988 | if (mask & (1<<i)) { | ||
989 | dst = get_dst_reg(c, inst, i); | ||
990 | brw_LINE(p, brw_null_reg(), interp[i], delta0); | ||
991 | brw_MAC(p, dst, suboffset(interp[i],1), | ||
992 | delta1); | ||
993 | brw_MUL(p, dst, dst, w); | ||
994 | } | ||
995 | } | ||
996 | } | ||
997 | |||
998 | /* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ | ||
999 | static void emit_frontfacing(struct brw_wm_compile *c, | ||
1000 | const struct brw_fp_instruction *inst) | ||
1001 | { | ||
1002 | struct brw_compile *p = &c->func; | ||
1003 | struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); | ||
1004 | struct brw_reg dst; | ||
1005 | GLuint mask = inst->DstReg.WriteMask; | ||
1006 | int i; | ||
1007 | |||
1008 | for (i = 0; i < 4; i++) { | ||
1009 | if (mask & (1<<i)) { | ||
1010 | dst = get_dst_reg(c, inst, i); | ||
1011 | brw_MOV(p, dst, brw_imm_f(0.0)); | ||
1012 | } | ||
1013 | } | ||
1014 | |||
1015 | /* bit 31 is "primitive is back face", so checking < (1 << 31) gives | ||
1016 | * us front face | ||
1017 | */ | ||
1018 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, r1_6ud, brw_imm_ud(1 << 31)); | ||
1019 | for (i = 0; i < 4; i++) { | ||
1020 | if (mask & (1<<i)) { | ||
1021 | dst = get_dst_reg(c, inst, i); | ||
1022 | brw_MOV(p, dst, brw_imm_f(1.0)); | ||
1023 | } | ||
1024 | } | ||
1025 | brw_set_predicate_control_flag_value(p, 0xff); | ||
1026 | } | ||
1027 | |||
1028 | static void emit_xpd(struct brw_wm_compile *c, | ||
1029 | const struct brw_fp_instruction *inst) | ||
1030 | { | ||
1031 | int i; | ||
1032 | struct brw_compile *p = &c->func; | ||
1033 | GLuint mask = inst->DstReg.WriteMask; | ||
1034 | for (i = 0; i < 4; i++) { | ||
1035 | GLuint i2 = (i+2)%3; | ||
1036 | GLuint i1 = (i+1)%3; | ||
1037 | if (mask & (1<<i)) { | ||
1038 | struct brw_reg src0, src1, dst; | ||
1039 | dst = get_dst_reg(c, inst, i); | ||
1040 | src0 = negate(get_src_reg(c, inst, 0, i2)); | ||
1041 | src1 = get_src_reg_imm(c, inst, 1, i1); | ||
1042 | brw_MUL(p, brw_null_reg(), src0, src1); | ||
1043 | src0 = get_src_reg(c, inst, 0, i1); | ||
1044 | src1 = get_src_reg_imm(c, inst, 1, i2); | ||
1045 | brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); | ||
1046 | brw_MAC(p, dst, src0, src1); | ||
1047 | brw_set_saturate(p, 0); | ||
1048 | } | ||
1049 | } | ||
1050 | brw_set_saturate(p, 0); | ||
1051 | } | ||
1052 | |||
1053 | static void emit_dp3(struct brw_wm_compile *c, | ||
1054 | const struct brw_fp_instruction *inst) | ||
1055 | { | ||
1056 | struct brw_reg src0[3], src1[3], dst; | ||
1057 | int i; | ||
1058 | struct brw_compile *p = &c->func; | ||
1059 | GLuint mask = inst->DstReg.WriteMask; | ||
1060 | int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; | ||
1061 | |||
1062 | if (!(mask & WRITEMASK_XYZW)) | ||
1063 | return; | ||
1064 | |||
1065 | assert(is_power_of_two(mask & WRITEMASK_XYZW)); | ||
1066 | |||
1067 | for (i = 0; i < 3; i++) { | ||
1068 | src0[i] = get_src_reg(c, inst, 0, i); | ||
1069 | src1[i] = get_src_reg_imm(c, inst, 1, i); | ||
1070 | } | ||
1071 | |||
1072 | dst = get_dst_reg(c, inst, dst_chan); | ||
1073 | brw_MUL(p, brw_null_reg(), src0[0], src1[0]); | ||
1074 | brw_MAC(p, brw_null_reg(), src0[1], src1[1]); | ||
1075 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1076 | brw_MAC(p, dst, src0[2], src1[2]); | ||
1077 | brw_set_saturate(p, 0); | ||
1078 | } | ||
1079 | |||
1080 | static void emit_dp4(struct brw_wm_compile *c, | ||
1081 | const struct brw_fp_instruction *inst) | ||
1082 | { | ||
1083 | struct brw_reg src0[4], src1[4], dst; | ||
1084 | int i; | ||
1085 | struct brw_compile *p = &c->func; | ||
1086 | GLuint mask = inst->DstReg.WriteMask; | ||
1087 | int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; | ||
1088 | |||
1089 | if (!(mask & WRITEMASK_XYZW)) | ||
1090 | return; | ||
1091 | |||
1092 | assert(is_power_of_two(mask & WRITEMASK_XYZW)); | ||
1093 | |||
1094 | for (i = 0; i < 4; i++) { | ||
1095 | src0[i] = get_src_reg(c, inst, 0, i); | ||
1096 | src1[i] = get_src_reg_imm(c, inst, 1, i); | ||
1097 | } | ||
1098 | dst = get_dst_reg(c, inst, dst_chan); | ||
1099 | brw_MUL(p, brw_null_reg(), src0[0], src1[0]); | ||
1100 | brw_MAC(p, brw_null_reg(), src0[1], src1[1]); | ||
1101 | brw_MAC(p, brw_null_reg(), src0[2], src1[2]); | ||
1102 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1103 | brw_MAC(p, dst, src0[3], src1[3]); | ||
1104 | brw_set_saturate(p, 0); | ||
1105 | } | ||
1106 | |||
1107 | static void emit_dph(struct brw_wm_compile *c, | ||
1108 | const struct brw_fp_instruction *inst) | ||
1109 | { | ||
1110 | struct brw_reg src0[4], src1[4], dst; | ||
1111 | int i; | ||
1112 | struct brw_compile *p = &c->func; | ||
1113 | GLuint mask = inst->DstReg.WriteMask; | ||
1114 | int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; | ||
1115 | |||
1116 | if (!(mask & WRITEMASK_XYZW)) | ||
1117 | return; | ||
1118 | |||
1119 | assert(is_power_of_two(mask & WRITEMASK_XYZW)); | ||
1120 | |||
1121 | for (i = 0; i < 4; i++) { | ||
1122 | src0[i] = get_src_reg(c, inst, 0, i); | ||
1123 | src1[i] = get_src_reg_imm(c, inst, 1, i); | ||
1124 | } | ||
1125 | dst = get_dst_reg(c, inst, dst_chan); | ||
1126 | brw_MUL(p, brw_null_reg(), src0[0], src1[0]); | ||
1127 | brw_MAC(p, brw_null_reg(), src0[1], src1[1]); | ||
1128 | brw_MAC(p, dst, src0[2], src1[2]); | ||
1129 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1130 | brw_ADD(p, dst, dst, src1[3]); | ||
1131 | brw_set_saturate(p, 0); | ||
1132 | } | ||
1133 | |||
1134 | /** | ||
1135 | * Emit a scalar instruction, like RCP, RSQ, LOG, EXP. | ||
1136 | * Note that the result of the function is smeared across the dest | ||
1137 | * register's X, Y, Z and W channels (subject to writemasking of course). | ||
1138 | */ | ||
1139 | static void emit_math1(struct brw_wm_compile *c, | ||
1140 | const struct brw_fp_instruction *inst, GLuint func) | ||
1141 | { | ||
1142 | struct brw_compile *p = &c->func; | ||
1143 | struct brw_reg src0, dst; | ||
1144 | GLuint mask = inst->DstReg.WriteMask; | ||
1145 | int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; | ||
1146 | |||
1147 | if (!(mask & WRITEMASK_XYZW)) | ||
1148 | return; | ||
1149 | |||
1150 | assert(is_power_of_two(mask & WRITEMASK_XYZW)); | ||
1151 | |||
1152 | /* Get first component of source register */ | ||
1153 | dst = get_dst_reg(c, inst, dst_chan); | ||
1154 | src0 = get_src_reg(c, inst, 0, 0); | ||
1155 | |||
1156 | brw_MOV(p, brw_message_reg(2), src0); | ||
1157 | brw_math(p, | ||
1158 | dst, | ||
1159 | func, | ||
1160 | (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, | ||
1161 | 2, | ||
1162 | brw_null_reg(), | ||
1163 | BRW_MATH_DATA_VECTOR, | ||
1164 | BRW_MATH_PRECISION_FULL); | ||
1165 | } | ||
1166 | |||
1167 | static void emit_rcp(struct brw_wm_compile *c, | ||
1168 | const struct brw_fp_instruction *inst) | ||
1169 | { | ||
1170 | emit_math1(c, inst, BRW_MATH_FUNCTION_INV); | ||
1171 | } | ||
1172 | |||
1173 | static void emit_rsq(struct brw_wm_compile *c, | ||
1174 | const struct brw_fp_instruction *inst) | ||
1175 | { | ||
1176 | emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ); | ||
1177 | } | ||
1178 | |||
1179 | static void emit_sin(struct brw_wm_compile *c, | ||
1180 | const struct brw_fp_instruction *inst) | ||
1181 | { | ||
1182 | emit_math1(c, inst, BRW_MATH_FUNCTION_SIN); | ||
1183 | } | ||
1184 | |||
1185 | static void emit_cos(struct brw_wm_compile *c, | ||
1186 | const struct brw_fp_instruction *inst) | ||
1187 | { | ||
1188 | emit_math1(c, inst, BRW_MATH_FUNCTION_COS); | ||
1189 | } | ||
1190 | |||
1191 | static void emit_ex2(struct brw_wm_compile *c, | ||
1192 | const struct brw_fp_instruction *inst) | ||
1193 | { | ||
1194 | emit_math1(c, inst, BRW_MATH_FUNCTION_EXP); | ||
1195 | } | ||
1196 | |||
1197 | static void emit_lg2(struct brw_wm_compile *c, | ||
1198 | const struct brw_fp_instruction *inst) | ||
1199 | { | ||
1200 | emit_math1(c, inst, BRW_MATH_FUNCTION_LOG); | ||
1201 | } | ||
1202 | |||
1203 | static void emit_add(struct brw_wm_compile *c, | ||
1204 | const struct brw_fp_instruction *inst) | ||
1205 | { | ||
1206 | struct brw_compile *p = &c->func; | ||
1207 | struct brw_reg src0, src1, dst; | ||
1208 | GLuint mask = inst->DstReg.WriteMask; | ||
1209 | int i; | ||
1210 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1211 | for (i = 0 ; i < 4; i++) { | ||
1212 | if (mask & (1<<i)) { | ||
1213 | dst = get_dst_reg(c, inst, i); | ||
1214 | src0 = get_src_reg(c, inst, 0, i); | ||
1215 | src1 = get_src_reg_imm(c, inst, 1, i); | ||
1216 | brw_ADD(p, dst, src0, src1); | ||
1217 | } | ||
1218 | } | ||
1219 | brw_set_saturate(p, 0); | ||
1220 | } | ||
1221 | |||
1222 | static void emit_arl(struct brw_wm_compile *c, | ||
1223 | const struct brw_fp_instruction *inst) | ||
1224 | { | ||
1225 | struct brw_compile *p = &c->func; | ||
1226 | struct brw_reg src0, addr_reg; | ||
1227 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1228 | addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE, | ||
1229 | BRW_ARF_ADDRESS, 0); | ||
1230 | src0 = get_src_reg(c, inst, 0, 0); /* channel 0 */ | ||
1231 | brw_MOV(p, addr_reg, src0); | ||
1232 | brw_set_saturate(p, 0); | ||
1233 | } | ||
1234 | |||
1235 | |||
1236 | static void emit_mul(struct brw_wm_compile *c, | ||
1237 | const struct brw_fp_instruction *inst) | ||
1238 | { | ||
1239 | struct brw_compile *p = &c->func; | ||
1240 | struct brw_reg src0, src1, dst; | ||
1241 | GLuint mask = inst->DstReg.WriteMask; | ||
1242 | int i; | ||
1243 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1244 | for (i = 0 ; i < 4; i++) { | ||
1245 | if (mask & (1<<i)) { | ||
1246 | dst = get_dst_reg(c, inst, i); | ||
1247 | src0 = get_src_reg(c, inst, 0, i); | ||
1248 | src1 = get_src_reg_imm(c, inst, 1, i); | ||
1249 | brw_MUL(p, dst, src0, src1); | ||
1250 | } | ||
1251 | } | ||
1252 | brw_set_saturate(p, 0); | ||
1253 | } | ||
1254 | |||
1255 | static void emit_frc(struct brw_wm_compile *c, | ||
1256 | const struct brw_fp_instruction *inst) | ||
1257 | { | ||
1258 | struct brw_compile *p = &c->func; | ||
1259 | struct brw_reg src0, dst; | ||
1260 | GLuint mask = inst->DstReg.WriteMask; | ||
1261 | int i; | ||
1262 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1263 | for (i = 0 ; i < 4; i++) { | ||
1264 | if (mask & (1<<i)) { | ||
1265 | dst = get_dst_reg(c, inst, i); | ||
1266 | src0 = get_src_reg_imm(c, inst, 0, i); | ||
1267 | brw_FRC(p, dst, src0); | ||
1268 | } | ||
1269 | } | ||
1270 | if (inst->SaturateMode != SATURATE_OFF) | ||
1271 | brw_set_saturate(p, 0); | ||
1272 | } | ||
1273 | |||
1274 | static void emit_flr(struct brw_wm_compile *c, | ||
1275 | const struct brw_fp_instruction *inst) | ||
1276 | { | ||
1277 | struct brw_compile *p = &c->func; | ||
1278 | struct brw_reg src0, dst; | ||
1279 | GLuint mask = inst->DstReg.WriteMask; | ||
1280 | int i; | ||
1281 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1282 | for (i = 0 ; i < 4; i++) { | ||
1283 | if (mask & (1<<i)) { | ||
1284 | dst = get_dst_reg(c, inst, i); | ||
1285 | src0 = get_src_reg_imm(c, inst, 0, i); | ||
1286 | brw_RNDD(p, dst, src0); | ||
1287 | } | ||
1288 | } | ||
1289 | brw_set_saturate(p, 0); | ||
1290 | } | ||
1291 | |||
1292 | |||
1293 | static void emit_min_max(struct brw_wm_compile *c, | ||
1294 | const struct brw_fp_instruction *inst) | ||
1295 | { | ||
1296 | struct brw_compile *p = &c->func; | ||
1297 | const GLuint mask = inst->DstReg.WriteMask; | ||
1298 | const int mark = mark_tmps(c); | ||
1299 | int i; | ||
1300 | brw_push_insn_state(p); | ||
1301 | for (i = 0; i < 4; i++) { | ||
1302 | if (mask & (1<<i)) { | ||
1303 | struct brw_reg real_dst = get_dst_reg(c, inst, i); | ||
1304 | struct brw_reg src0 = get_src_reg(c, inst, 0, i); | ||
1305 | struct brw_reg src1 = get_src_reg(c, inst, 1, i); | ||
1306 | struct brw_reg dst; | ||
1307 | /* if dst==src0 or dst==src1 we need to use a temp reg */ | ||
1308 | GLboolean use_temp = brw_same_reg(dst, src0) || | ||
1309 | brw_same_reg(dst, src1); | ||
1310 | if (use_temp) | ||
1311 | dst = alloc_tmp(c); | ||
1312 | else | ||
1313 | dst = real_dst; | ||
1314 | |||
1315 | /* | ||
1316 | printf(" Min/max: dst %d src0 %d src1 %d\n", | ||
1317 | dst.nr, src0.nr, src1.nr); | ||
1318 | */ | ||
1319 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1320 | brw_MOV(p, dst, src0); | ||
1321 | brw_set_saturate(p, 0); | ||
1322 | |||
1323 | if (inst->Opcode == OPCODE_MIN) | ||
1324 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0); | ||
1325 | else | ||
1326 | brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, src1, src0); | ||
1327 | |||
1328 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1329 | brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); | ||
1330 | brw_MOV(p, dst, src1); | ||
1331 | brw_set_saturate(p, 0); | ||
1332 | brw_set_predicate_control_flag_value(p, 0xff); | ||
1333 | if (use_temp) | ||
1334 | brw_MOV(p, real_dst, dst); | ||
1335 | } | ||
1336 | } | ||
1337 | brw_pop_insn_state(p); | ||
1338 | release_tmps(c, mark); | ||
1339 | } | ||
1340 | |||
1341 | static void emit_pow(struct brw_wm_compile *c, | ||
1342 | const struct brw_fp_instruction *inst) | ||
1343 | { | ||
1344 | struct brw_compile *p = &c->func; | ||
1345 | struct brw_reg dst, src0, src1; | ||
1346 | GLuint mask = inst->DstReg.WriteMask; | ||
1347 | int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; | ||
1348 | |||
1349 | if (!(mask & WRITEMASK_XYZW)) | ||
1350 | return; | ||
1351 | |||
1352 | assert(is_power_of_two(mask & WRITEMASK_XYZW)); | ||
1353 | |||
1354 | dst = get_dst_reg(c, inst, dst_chan); | ||
1355 | src0 = get_src_reg_imm(c, inst, 0, 0); | ||
1356 | src1 = get_src_reg_imm(c, inst, 1, 0); | ||
1357 | |||
1358 | brw_MOV(p, brw_message_reg(2), src0); | ||
1359 | brw_MOV(p, brw_message_reg(3), src1); | ||
1360 | |||
1361 | brw_math(p, | ||
1362 | dst, | ||
1363 | BRW_MATH_FUNCTION_POW, | ||
1364 | (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, | ||
1365 | 2, | ||
1366 | brw_null_reg(), | ||
1367 | BRW_MATH_DATA_VECTOR, | ||
1368 | BRW_MATH_PRECISION_FULL); | ||
1369 | } | ||
1370 | |||
1371 | static void emit_lrp(struct brw_wm_compile *c, | ||
1372 | const struct brw_fp_instruction *inst) | ||
1373 | { | ||
1374 | struct brw_compile *p = &c->func; | ||
1375 | GLuint mask = inst->DstReg.WriteMask; | ||
1376 | struct brw_reg dst, tmp1, tmp2, src0, src1, src2; | ||
1377 | int i; | ||
1378 | int mark = mark_tmps(c); | ||
1379 | for (i = 0; i < 4; i++) { | ||
1380 | if (mask & (1<<i)) { | ||
1381 | dst = get_dst_reg(c, inst, i); | ||
1382 | src0 = get_src_reg(c, inst, 0, i); | ||
1383 | |||
1384 | src1 = get_src_reg_imm(c, inst, 1, i); | ||
1385 | |||
1386 | if (src1.nr == dst.nr) { | ||
1387 | tmp1 = alloc_tmp(c); | ||
1388 | brw_MOV(p, tmp1, src1); | ||
1389 | } else | ||
1390 | tmp1 = src1; | ||
1391 | |||
1392 | src2 = get_src_reg(c, inst, 2, i); | ||
1393 | if (src2.nr == dst.nr) { | ||
1394 | tmp2 = alloc_tmp(c); | ||
1395 | brw_MOV(p, tmp2, src2); | ||
1396 | } else | ||
1397 | tmp2 = src2; | ||
1398 | |||
1399 | brw_ADD(p, dst, negate(src0), brw_imm_f(1.0)); | ||
1400 | brw_MUL(p, brw_null_reg(), dst, tmp2); | ||
1401 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1402 | brw_MAC(p, dst, src0, tmp1); | ||
1403 | brw_set_saturate(p, 0); | ||
1404 | } | ||
1405 | release_tmps(c, mark); | ||
1406 | } | ||
1407 | } | ||
1408 | |||
1409 | /** | ||
1410 | * For GLSL shaders, this KIL will be unconditional. | ||
1411 | * It may be contained inside an IF/ENDIF structure of course. | ||
1412 | */ | ||
1413 | static void emit_kil(struct brw_wm_compile *c) | ||
1414 | { | ||
1415 | struct brw_compile *p = &c->func; | ||
1416 | struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); | ||
1417 | brw_push_insn_state(p); | ||
1418 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1419 | brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK | ||
1420 | brw_AND(p, depth, c->emit_mask_reg, depth); | ||
1421 | brw_pop_insn_state(p); | ||
1422 | } | ||
1423 | |||
1424 | static void emit_mad(struct brw_wm_compile *c, | ||
1425 | const struct brw_fp_instruction *inst) | ||
1426 | { | ||
1427 | struct brw_compile *p = &c->func; | ||
1428 | GLuint mask = inst->DstReg.WriteMask; | ||
1429 | struct brw_reg dst, src0, src1, src2; | ||
1430 | int i; | ||
1431 | |||
1432 | for (i = 0; i < 4; i++) { | ||
1433 | if (mask & (1<<i)) { | ||
1434 | dst = get_dst_reg(c, inst, i); | ||
1435 | src0 = get_src_reg(c, inst, 0, i); | ||
1436 | src1 = get_src_reg_imm(c, inst, 1, i); | ||
1437 | src2 = get_src_reg_imm(c, inst, 2, i); | ||
1438 | brw_MUL(p, dst, src0, src1); | ||
1439 | |||
1440 | brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); | ||
1441 | brw_ADD(p, dst, dst, src2); | ||
1442 | brw_set_saturate(p, 0); | ||
1443 | } | ||
1444 | } | ||
1445 | } | ||
1446 | |||
1447 | static void emit_sop(struct brw_wm_compile *c, | ||
1448 | const struct brw_fp_instruction *inst, GLuint cond) | ||
1449 | { | ||
1450 | struct brw_compile *p = &c->func; | ||
1451 | GLuint mask = inst->DstReg.WriteMask; | ||
1452 | struct brw_reg dst, src0, src1; | ||
1453 | int i; | ||
1454 | |||
1455 | for (i = 0; i < 4; i++) { | ||
1456 | if (mask & (1<<i)) { | ||
1457 | dst = get_dst_reg(c, inst, i); | ||
1458 | src0 = get_src_reg(c, inst, 0, i); | ||
1459 | src1 = get_src_reg_imm(c, inst, 1, i); | ||
1460 | brw_push_insn_state(p); | ||
1461 | brw_CMP(p, brw_null_reg(), cond, src0, src1); | ||
1462 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1463 | brw_MOV(p, dst, brw_imm_f(0.0)); | ||
1464 | brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); | ||
1465 | brw_MOV(p, dst, brw_imm_f(1.0)); | ||
1466 | brw_pop_insn_state(p); | ||
1467 | } | ||
1468 | } | ||
1469 | } | ||
1470 | |||
1471 | static void emit_slt(struct brw_wm_compile *c, | ||
1472 | const struct brw_fp_instruction *inst) | ||
1473 | { | ||
1474 | emit_sop(c, inst, BRW_CONDITIONAL_L); | ||
1475 | } | ||
1476 | |||
1477 | static void emit_sle(struct brw_wm_compile *c, | ||
1478 | const struct brw_fp_instruction *inst) | ||
1479 | { | ||
1480 | emit_sop(c, inst, BRW_CONDITIONAL_LE); | ||
1481 | } | ||
1482 | |||
1483 | static void emit_sgt(struct brw_wm_compile *c, | ||
1484 | const struct brw_fp_instruction *inst) | ||
1485 | { | ||
1486 | emit_sop(c, inst, BRW_CONDITIONAL_G); | ||
1487 | } | ||
1488 | |||
1489 | static void emit_sge(struct brw_wm_compile *c, | ||
1490 | const struct brw_fp_instruction *inst) | ||
1491 | { | ||
1492 | emit_sop(c, inst, BRW_CONDITIONAL_GE); | ||
1493 | } | ||
1494 | |||
1495 | static void emit_seq(struct brw_wm_compile *c, | ||
1496 | const struct brw_fp_instruction *inst) | ||
1497 | { | ||
1498 | emit_sop(c, inst, BRW_CONDITIONAL_EQ); | ||
1499 | } | ||
1500 | |||
1501 | static void emit_sne(struct brw_wm_compile *c, | ||
1502 | const struct brw_fp_instruction *inst) | ||
1503 | { | ||
1504 | emit_sop(c, inst, BRW_CONDITIONAL_NEQ); | ||
1505 | } | ||
1506 | |||
1507 | static INLINE struct brw_reg high_words( struct brw_reg reg ) | ||
1508 | { | ||
1509 | return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_W ), 1 ), | ||
1510 | 0, 8, 2 ); | ||
1511 | } | ||
1512 | |||
1513 | static INLINE struct brw_reg low_words( struct brw_reg reg ) | ||
1514 | { | ||
1515 | return stride( retype( reg, BRW_REGISTER_TYPE_W ), 0, 8, 2 ); | ||
1516 | } | ||
1517 | |||
1518 | static INLINE struct brw_reg even_bytes( struct brw_reg reg ) | ||
1519 | { | ||
1520 | return stride( retype( reg, BRW_REGISTER_TYPE_B ), 0, 16, 2 ); | ||
1521 | } | ||
1522 | |||
1523 | static INLINE struct brw_reg odd_bytes( struct brw_reg reg ) | ||
1524 | { | ||
1525 | return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_B ), 1 ), | ||
1526 | 0, 16, 2 ); | ||
1527 | } | ||
1528 | |||
1529 | |||
1530 | |||
1531 | static void emit_wpos_xy(struct brw_wm_compile *c, | ||
1532 | const struct brw_fp_instruction *inst) | ||
1533 | { | ||
1534 | struct brw_compile *p = &c->func; | ||
1535 | GLuint mask = inst->DstReg.WriteMask; | ||
1536 | struct brw_reg src0[2], dst[2]; | ||
1537 | |||
1538 | dst[0] = get_dst_reg(c, inst, 0); | ||
1539 | dst[1] = get_dst_reg(c, inst, 1); | ||
1540 | |||
1541 | src0[0] = get_src_reg(c, inst, 0, 0); | ||
1542 | src0[1] = get_src_reg(c, inst, 0, 1); | ||
1543 | |||
1544 | /* Calculate the pixel offset from window bottom left into destination | ||
1545 | * X and Y channels. | ||
1546 | */ | ||
1547 | if (mask & WRITEMASK_X) { | ||
1548 | /* X' = X */ | ||
1549 | brw_MOV(p, | ||
1550 | dst[0], | ||
1551 | retype(src0[0], BRW_REGISTER_TYPE_W)); | ||
1552 | } | ||
1553 | |||
1554 | if (mask & WRITEMASK_Y) { | ||
1555 | /* Y' = height - 1 - Y */ | ||
1556 | brw_ADD(p, | ||
1557 | dst[1], | ||
1558 | negate(retype(src0[1], BRW_REGISTER_TYPE_W)), | ||
1559 | brw_imm_d(c->key.drawable_height - 1)); | ||
1560 | } | ||
1561 | } | ||
1562 | |||
1563 | /* TODO | ||
1564 | BIAS on SIMD8 not working yet... | ||
1565 | */ | ||
1566 | static void emit_txb(struct brw_wm_compile *c, | ||
1567 | const struct brw_fp_instruction *inst) | ||
1568 | { | ||
1569 | struct brw_compile *p = &c->func; | ||
1570 | struct brw_reg dst[4], src[4], payload_reg; | ||
1571 | /* Note: tex_unit was already looked up through SamplerTextures[] */ | ||
1572 | const GLuint unit = inst->tex_unit; | ||
1573 | GLuint i; | ||
1574 | GLuint msg_type; | ||
1575 | |||
1576 | assert(unit < BRW_MAX_TEX_UNIT); | ||
1577 | |||
1578 | payload_reg = get_reg(c, TGSI_FILE_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); | ||
1579 | |||
1580 | for (i = 0; i < 4; i++) | ||
1581 | dst[i] = get_dst_reg(c, inst, i); | ||
1582 | for (i = 0; i < 4; i++) | ||
1583 | src[i] = get_src_reg(c, inst, 0, i); | ||
1584 | |||
1585 | switch (inst->tex_target) { | ||
1586 | case TEXTURE_1D_INDEX: | ||
1587 | brw_MOV(p, brw_message_reg(2), src[0]); /* s coord */ | ||
1588 | brw_MOV(p, brw_message_reg(3), brw_imm_f(0)); /* t coord */ | ||
1589 | brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); /* r coord */ | ||
1590 | break; | ||
1591 | case TEXTURE_2D_INDEX: | ||
1592 | case TEXTURE_RECT_INDEX: | ||
1593 | brw_MOV(p, brw_message_reg(2), src[0]); | ||
1594 | brw_MOV(p, brw_message_reg(3), src[1]); | ||
1595 | brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); | ||
1596 | break; | ||
1597 | case TEXTURE_3D_INDEX: | ||
1598 | case TEXTURE_CUBE_INDEX: | ||
1599 | brw_MOV(p, brw_message_reg(2), src[0]); | ||
1600 | brw_MOV(p, brw_message_reg(3), src[1]); | ||
1601 | brw_MOV(p, brw_message_reg(4), src[2]); | ||
1602 | break; | ||
1603 | default: | ||
1604 | /* invalid target */ | ||
1605 | abort(); | ||
1606 | } | ||
1607 | brw_MOV(p, brw_message_reg(5), src[3]); /* bias */ | ||
1608 | brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); /* ref (unused?) */ | ||
1609 | |||
1610 | if (p->brw->gen == 5) { | ||
1611 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG; | ||
1612 | } else { | ||
1613 | /* Does it work well on SIMD8? */ | ||
1614 | msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; | ||
1615 | } | ||
1616 | |||
1617 | brw_SAMPLE(p, | ||
1618 | retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ | ||
1619 | 1, /* msg_reg_nr */ | ||
1620 | retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ | ||
1621 | SURF_INDEX_TEXTURE(unit), | ||
1622 | unit, /* sampler */ | ||
1623 | inst->DstReg.WriteMask, /* writemask */ | ||
1624 | msg_type, /* msg_type */ | ||
1625 | 4, /* response_length */ | ||
1626 | 4, /* msg_length */ | ||
1627 | 0, /* eot */ | ||
1628 | 1, | ||
1629 | BRW_SAMPLER_SIMD_MODE_SIMD8); | ||
1630 | } | ||
1631 | |||
1632 | |||
1633 | static void emit_tex(struct brw_wm_compile *c, | ||
1634 | const struct brw_fp_instruction *inst) | ||
1635 | { | ||
1636 | struct brw_compile *p = &c->func; | ||
1637 | struct brw_reg dst[4], src[4], payload_reg; | ||
1638 | /* Note: tex_unit was already looked up through SamplerTextures[] */ | ||
1639 | const GLuint unit = inst->tex_unit; | ||
1640 | GLuint msg_len; | ||
1641 | GLuint i, nr; | ||
1642 | GLuint emit; | ||
1643 | GLboolean shadow = (c->key.shadowtex_mask & (1<<unit)) ? 1 : 0; | ||
1644 | GLuint msg_type; | ||
1645 | |||
1646 | assert(unit < BRW_MAX_TEX_UNIT); | ||
1647 | |||
1648 | payload_reg = get_reg(c, TGSI_FILE_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); | ||
1649 | |||
1650 | for (i = 0; i < 4; i++) | ||
1651 | dst[i] = get_dst_reg(c, inst, i); | ||
1652 | for (i = 0; i < 4; i++) | ||
1653 | src[i] = get_src_reg(c, inst, 0, i); | ||
1654 | |||
1655 | switch (inst->tex_target) { | ||
1656 | case TEXTURE_1D_INDEX: | ||
1657 | emit = WRITEMASK_X; | ||
1658 | nr = 1; | ||
1659 | break; | ||
1660 | case TEXTURE_2D_INDEX: | ||
1661 | case TEXTURE_RECT_INDEX: | ||
1662 | emit = WRITEMASK_XY; | ||
1663 | nr = 2; | ||
1664 | break; | ||
1665 | case TEXTURE_3D_INDEX: | ||
1666 | case TEXTURE_CUBE_INDEX: | ||
1667 | emit = WRITEMASK_XYZ; | ||
1668 | nr = 3; | ||
1669 | break; | ||
1670 | default: | ||
1671 | /* invalid target */ | ||
1672 | abort(); | ||
1673 | } | ||
1674 | msg_len = 1; | ||
1675 | |||
1676 | /* move/load S, T, R coords */ | ||
1677 | for (i = 0; i < nr; i++) { | ||
1678 | static const GLuint swz[4] = {0,1,2,2}; | ||
1679 | if (emit & (1<<i)) | ||
1680 | brw_MOV(p, brw_message_reg(msg_len+1), src[swz[i]]); | ||
1681 | else | ||
1682 | brw_MOV(p, brw_message_reg(msg_len+1), brw_imm_f(0)); | ||
1683 | msg_len += 1; | ||
1684 | } | ||
1685 | |||
1686 | if (shadow) { | ||
1687 | brw_MOV(p, brw_message_reg(5), brw_imm_f(0)); /* lod / bias */ | ||
1688 | brw_MOV(p, brw_message_reg(6), src[2]); /* ref value / R coord */ | ||
1689 | } | ||
1690 | |||
1691 | if (p->brw->gen == 5) { | ||
1692 | if (shadow) | ||
1693 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG; | ||
1694 | else | ||
1695 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_IGDNG; | ||
1696 | } else { | ||
1697 | /* Does it work for shadow on SIMD8 ? */ | ||
1698 | msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; | ||
1699 | } | ||
1700 | |||
1701 | brw_SAMPLE(p, | ||
1702 | retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ | ||
1703 | 1, /* msg_reg_nr */ | ||
1704 | retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ | ||
1705 | SURF_INDEX_TEXTURE(unit), | ||
1706 | unit, /* sampler */ | ||
1707 | inst->DstReg.WriteMask, /* writemask */ | ||
1708 | msg_type, /* msg_type */ | ||
1709 | 4, /* response_length */ | ||
1710 | shadow ? 6 : 4, /* msg_length */ | ||
1711 | 0, /* eot */ | ||
1712 | 1, | ||
1713 | BRW_SAMPLER_SIMD_MODE_SIMD8); | ||
1714 | |||
1715 | if (shadow) | ||
1716 | brw_MOV(p, dst[3], brw_imm_f(1.0)); | ||
1717 | } | ||
1718 | |||
1719 | |||
1720 | /** | ||
1721 | * Resolve subroutine calls after code emit is done. | ||
1722 | */ | ||
1723 | static void post_wm_emit( struct brw_wm_compile *c ) | ||
1724 | { | ||
1725 | brw_resolve_cals(&c->func); | ||
1726 | } | ||
1727 | |||
1728 | static void | ||
1729 | get_argument_regs(struct brw_wm_compile *c, | ||
1730 | const struct brw_fp_instruction *inst, | ||
1731 | int index, | ||
1732 | struct brw_reg *regs, | ||
1733 | int mask) | ||
1734 | { | ||
1735 | int i; | ||
1736 | |||
1737 | for (i = 0; i < 4; i++) { | ||
1738 | if (mask & (1 << i)) | ||
1739 | regs[i] = get_src_reg(c, inst, index, i); | ||
1740 | } | ||
1741 | } | ||
1742 | |||
1743 | static void brw_wm_emit_branching_shader(struct brw_context *brw, struct brw_wm_compile *c) | ||
1744 | { | ||
1745 | #define MAX_IF_DEPTH 32 | ||
1746 | #define MAX_LOOP_DEPTH 32 | ||
1747 | struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH]; | ||
1748 | GLuint i, if_depth = 0, loop_depth = 0; | ||
1749 | struct brw_compile *p = &c->func; | ||
1750 | struct brw_indirect stack_index = brw_indirect(0, 0); | ||
1751 | |||
1752 | c->out_of_regs = GL_FALSE; | ||
1753 | |||
1754 | prealloc_reg(c); | ||
1755 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); | ||
1756 | brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack)); | ||
1757 | |||
1758 | for (i = 0; i < c->nr_fp_insns; i++) { | ||
1759 | const struct brw_fp_instruction *inst = &c->fp_instructions[i]; | ||
1760 | int dst_flags; | ||
1761 | struct brw_reg args[3][4], dst[4]; | ||
1762 | int j; | ||
1763 | |||
1764 | c->cur_inst = i; | ||
1765 | |||
1766 | #if 0 | ||
1767 | debug_printf("Inst %d: ", i); | ||
1768 | _mesa_print_instruction(inst); | ||
1769 | #endif | ||
1770 | |||
1771 | /* fetch any constants that this instruction needs */ | ||
1772 | if (c->fp->use_const_buffer) | ||
1773 | fetch_constants(c, inst); | ||
1774 | |||
1775 | if (inst->CondUpdate) | ||
1776 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); | ||
1777 | else | ||
1778 | brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE); | ||
1779 | |||
1780 | dst_flags = inst->DstReg.WriteMask; | ||
1781 | if (inst->SaturateMode == SATURATE_ZERO_ONE) | ||
1782 | dst_flags |= SATURATE; | ||
1783 | |||
1784 | switch (inst->Opcode) { | ||
1785 | case WM_PIXELXY: | ||
1786 | emit_pixel_xy(c, inst); | ||
1787 | break; | ||
1788 | case WM_DELTAXY: | ||
1789 | emit_delta_xy(c, inst); | ||
1790 | break; | ||
1791 | case WM_PIXELW: | ||
1792 | emit_pixel_w(c, inst); | ||
1793 | break; | ||
1794 | case WM_LINTERP: | ||
1795 | emit_linterp(c, inst); | ||
1796 | break; | ||
1797 | case WM_PINTERP: | ||
1798 | emit_pinterp(c, inst); | ||
1799 | break; | ||
1800 | case WM_CINTERP: | ||
1801 | emit_cinterp(c, inst); | ||
1802 | break; | ||
1803 | case WM_WPOSXY: | ||
1804 | emit_wpos_xy(c, inst); | ||
1805 | break; | ||
1806 | case WM_FB_WRITE: | ||
1807 | emit_fb_write(c, inst); | ||
1808 | break; | ||
1809 | case WM_FRONTFACING: | ||
1810 | emit_frontfacing(c, inst); | ||
1811 | break; | ||
1812 | case OPCODE_ADD: | ||
1813 | emit_add(c, inst); | ||
1814 | break; | ||
1815 | case OPCODE_ARL: | ||
1816 | emit_arl(c, inst); | ||
1817 | break; | ||
1818 | case OPCODE_FRC: | ||
1819 | emit_frc(c, inst); | ||
1820 | break; | ||
1821 | case OPCODE_FLR: | ||
1822 | emit_flr(c, inst); | ||
1823 | break; | ||
1824 | case OPCODE_LRP: | ||
1825 | emit_lrp(c, inst); | ||
1826 | break; | ||
1827 | case OPCODE_TRUNC: | ||
1828 | emit_trunc(c, inst); | ||
1829 | break; | ||
1830 | case OPCODE_MOV: | ||
1831 | emit_mov(c, inst); | ||
1832 | break; | ||
1833 | case OPCODE_DP3: | ||
1834 | emit_dp3(c, inst); | ||
1835 | break; | ||
1836 | case OPCODE_DP4: | ||
1837 | emit_dp4(c, inst); | ||
1838 | break; | ||
1839 | case OPCODE_XPD: | ||
1840 | emit_xpd(c, inst); | ||
1841 | break; | ||
1842 | case OPCODE_DPH: | ||
1843 | emit_dph(c, inst); | ||
1844 | break; | ||
1845 | case OPCODE_RCP: | ||
1846 | emit_rcp(c, inst); | ||
1847 | break; | ||
1848 | case OPCODE_RSQ: | ||
1849 | emit_rsq(c, inst); | ||
1850 | break; | ||
1851 | case OPCODE_SIN: | ||
1852 | emit_sin(c, inst); | ||
1853 | break; | ||
1854 | case OPCODE_COS: | ||
1855 | emit_cos(c, inst); | ||
1856 | break; | ||
1857 | case OPCODE_EX2: | ||
1858 | emit_ex2(c, inst); | ||
1859 | break; | ||
1860 | case OPCODE_LG2: | ||
1861 | emit_lg2(c, inst); | ||
1862 | break; | ||
1863 | case OPCODE_MIN: | ||
1864 | case OPCODE_MAX: | ||
1865 | emit_min_max(c, inst); | ||
1866 | break; | ||
1867 | case OPCODE_DDX: | ||
1868 | case OPCODE_DDY: | ||
1869 | for (j = 0; j < 4; j++) { | ||
1870 | if (inst->DstReg.WriteMask & (1 << j)) | ||
1871 | dst[j] = get_dst_reg(c, inst, j); | ||
1872 | else | ||
1873 | dst[j] = brw_null_reg(); | ||
1874 | } | ||
1875 | get_argument_regs(c, inst, 0, args[0], WRITEMASK_XYZW); | ||
1876 | emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX), | ||
1877 | args[0]); | ||
1878 | break; | ||
1879 | case OPCODE_SLT: | ||
1880 | emit_slt(c, inst); | ||
1881 | break; | ||
1882 | case OPCODE_SLE: | ||
1883 | emit_sle(c, inst); | ||
1884 | break; | ||
1885 | case OPCODE_SGT: | ||
1886 | emit_sgt(c, inst); | ||
1887 | break; | ||
1888 | case OPCODE_SGE: | ||
1889 | emit_sge(c, inst); | ||
1890 | break; | ||
1891 | case OPCODE_SEQ: | ||
1892 | emit_seq(c, inst); | ||
1893 | break; | ||
1894 | case OPCODE_SNE: | ||
1895 | emit_sne(c, inst); | ||
1896 | break; | ||
1897 | case OPCODE_MUL: | ||
1898 | emit_mul(c, inst); | ||
1899 | break; | ||
1900 | case OPCODE_POW: | ||
1901 | emit_pow(c, inst); | ||
1902 | break; | ||
1903 | case OPCODE_MAD: | ||
1904 | emit_mad(c, inst); | ||
1905 | break; | ||
1906 | case OPCODE_TEX: | ||
1907 | emit_tex(c, inst); | ||
1908 | break; | ||
1909 | case OPCODE_TXB: | ||
1910 | emit_txb(c, inst); | ||
1911 | break; | ||
1912 | case OPCODE_KIL_NV: | ||
1913 | emit_kil(c); | ||
1914 | break; | ||
1915 | case OPCODE_IF: | ||
1916 | assert(if_depth < MAX_IF_DEPTH); | ||
1917 | if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8); | ||
1918 | break; | ||
1919 | case OPCODE_ELSE: | ||
1920 | if_inst[if_depth-1] = brw_ELSE(p, if_inst[if_depth-1]); | ||
1921 | break; | ||
1922 | case OPCODE_ENDIF: | ||
1923 | assert(if_depth > 0); | ||
1924 | brw_ENDIF(p, if_inst[--if_depth]); | ||
1925 | break; | ||
1926 | case OPCODE_BGNSUB: | ||
1927 | brw_save_label(p, inst->Comment, p->nr_insn); | ||
1928 | break; | ||
1929 | case OPCODE_ENDSUB: | ||
1930 | /* no-op */ | ||
1931 | break; | ||
1932 | case OPCODE_CAL: | ||
1933 | brw_push_insn_state(p); | ||
1934 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1935 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
1936 | brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); | ||
1937 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1938 | brw_ADD(p, get_addr_reg(stack_index), | ||
1939 | get_addr_reg(stack_index), brw_imm_d(4)); | ||
1940 | brw_save_call(&c->func, inst->label, p->nr_insn); | ||
1941 | brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); | ||
1942 | brw_pop_insn_state(p); | ||
1943 | break; | ||
1944 | |||
1945 | case OPCODE_RET: | ||
1946 | brw_push_insn_state(p); | ||
1947 | brw_set_mask_control(p, BRW_MASK_DISABLE); | ||
1948 | brw_ADD(p, get_addr_reg(stack_index), | ||
1949 | get_addr_reg(stack_index), brw_imm_d(-4)); | ||
1950 | brw_set_access_mode(p, BRW_ALIGN_1); | ||
1951 | brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0)); | ||
1952 | brw_set_access_mode(p, BRW_ALIGN_16); | ||
1953 | brw_pop_insn_state(p); | ||
1954 | |||
1955 | break; | ||
1956 | case OPCODE_BGNLOOP: | ||
1957 | /* XXX may need to invalidate the current_constant regs */ | ||
1958 | loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8); | ||
1959 | break; | ||
1960 | case OPCODE_BRK: | ||
1961 | brw_BREAK(p); | ||
1962 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1963 | break; | ||
1964 | case OPCODE_CONT: | ||
1965 | brw_CONT(p); | ||
1966 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
1967 | break; | ||
1968 | case OPCODE_ENDLOOP: | ||
1969 | { | ||
1970 | struct brw_instruction *inst0, *inst1; | ||
1971 | GLuint br = 1; | ||
1972 | |||
1973 | if (brw->gen == 5) | ||
1974 | br = 2; | ||
1975 | |||
1976 | loop_depth--; | ||
1977 | inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]); | ||
1978 | /* patch all the BREAK/CONT instructions from last BGNLOOP */ | ||
1979 | while (inst0 > loop_inst[loop_depth]) { | ||
1980 | inst0--; | ||
1981 | if (inst0->header.opcode == BRW_OPCODE_BREAK) { | ||
1982 | inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); | ||
1983 | inst0->bits3.if_else.pop_count = 0; | ||
1984 | } | ||
1985 | else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) { | ||
1986 | inst0->bits3.if_else.jump_count = br * (inst1 - inst0); | ||
1987 | inst0->bits3.if_else.pop_count = 0; | ||
1988 | } | ||
1989 | } | ||
1990 | } | ||
1991 | break; | ||
1992 | default: | ||
1993 | debug_printf("unsupported IR in fragment shader %d\n", | ||
1994 | inst->Opcode); | ||
1995 | } | ||
1996 | |||
1997 | if (inst->CondUpdate) | ||
1998 | brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); | ||
1999 | else | ||
2000 | brw_set_predicate_control(p, BRW_PREDICATE_NONE); | ||
2001 | } | ||
2002 | post_wm_emit(c); | ||
2003 | |||
2004 | if (BRW_DEBUG & DEBUG_WM) { | ||
2005 | debug_printf("wm-native:\n"); | ||
2006 | brw_disasm(stderr, p->store, p->nr_insn); | ||
2007 | } | ||
2008 | } | ||
2009 | |||
2010 | /** | ||
2011 | * Do GPU code generation for shaders that use GLSL features such as | ||
2012 | * flow control. Other shaders will be compiled with the | ||
2013 | */ | ||
2014 | void brw_wm_branching_shader_emit(struct brw_context *brw, struct brw_wm_compile *c) | ||
2015 | { | ||
2016 | if (BRW_DEBUG & DEBUG_WM) { | ||
2017 | debug_printf("%s:\n", __FUNCTION__); | ||
2018 | } | ||
2019 | |||
2020 | /* initial instruction translation/simplification */ | ||
2021 | brw_wm_pass_fp(c); | ||
2022 | |||
2023 | /* actual code generation */ | ||
2024 | brw_wm_emit_branching_shader(brw, c); | ||
2025 | |||
2026 | if (BRW_DEBUG & DEBUG_WM) { | ||
2027 | brw_wm_print_program(c, "brw_wm_branching_shader_emit done"); | ||
2028 | } | ||
2029 | |||
2030 | c->prog_data.total_grf = num_grf_used(c); | ||
2031 | c->prog_data.total_scratch = 0; | ||
2032 | } | ||
diff --git a/src/gallium/drivers/i965/brw_wm_iz.c b/src/gallium/drivers/i965/brw_wm_iz.c deleted file mode 100644 index 6f1e9fcc3c1..00000000000 --- a/src/gallium/drivers/i965/brw_wm_iz.c +++ /dev/null | |||
@@ -1,156 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_wm.h" | ||
34 | |||
35 | |||
36 | #undef P /* prompted depth */ | ||
37 | #undef C /* computed */ | ||
38 | #undef N /* non-promoted? */ | ||
39 | |||
40 | #define P 0 | ||
41 | #define C 1 | ||
42 | #define N 2 | ||
43 | |||
44 | const struct { | ||
45 | GLuint mode:2; | ||
46 | GLuint sd_present:1; | ||
47 | GLuint sd_to_rt:1; | ||
48 | GLuint dd_present:1; | ||
49 | GLuint ds_present:1; | ||
50 | } wm_iz_table[IZ_BIT_MAX] = | ||
51 | { | ||
52 | { P, 0, 0, 0, 0 }, | ||
53 | { P, 0, 0, 0, 0 }, | ||
54 | { P, 0, 0, 0, 0 }, | ||
55 | { P, 0, 0, 0, 0 }, | ||
56 | { P, 0, 0, 0, 0 }, | ||
57 | { N, 1, 1, 0, 0 }, | ||
58 | { N, 0, 1, 0, 0 }, | ||
59 | { N, 0, 1, 0, 0 }, | ||
60 | { P, 0, 0, 0, 0 }, | ||
61 | { P, 0, 0, 0, 0 }, | ||
62 | { C, 0, 1, 1, 0 }, | ||
63 | { C, 0, 1, 1, 0 }, | ||
64 | { P, 0, 0, 0, 0 }, | ||
65 | { N, 1, 1, 0, 0 }, | ||
66 | { C, 0, 1, 1, 0 }, | ||
67 | { C, 0, 1, 1, 0 }, | ||
68 | { P, 0, 0, 0, 0 }, | ||
69 | { P, 0, 0, 0, 0 }, | ||
70 | { P, 0, 0, 0, 0 }, | ||
71 | { P, 0, 0, 0, 0 }, | ||
72 | { P, 0, 0, 0, 0 }, | ||
73 | { N, 1, 1, 0, 0 }, | ||
74 | { N, 0, 1, 0, 0 }, | ||
75 | { N, 0, 1, 0, 0 }, | ||
76 | { P, 0, 0, 0, 0 }, | ||
77 | { P, 0, 0, 0, 0 }, | ||
78 | { C, 0, 1, 1, 0 }, | ||
79 | { C, 0, 1, 1, 0 }, | ||
80 | { P, 0, 0, 0, 0 }, | ||
81 | { N, 1, 1, 0, 0 }, | ||
82 | { C, 0, 1, 1, 0 }, | ||
83 | { C, 0, 1, 1, 0 }, | ||
84 | { P, 0, 0, 0, 0 }, | ||
85 | { P, 0, 0, 0, 0 }, | ||
86 | { P, 0, 0, 0, 0 }, | ||
87 | { P, 0, 0, 0, 0 }, | ||
88 | { P, 0, 0, 0, 0 }, | ||
89 | { N, 1, 1, 0, 1 }, | ||
90 | { N, 0, 1, 0, 1 }, | ||
91 | { N, 0, 1, 0, 1 }, | ||
92 | { P, 0, 0, 0, 0 }, | ||
93 | { P, 0, 0, 0, 0 }, | ||
94 | { C, 0, 1, 1, 1 }, | ||
95 | { C, 0, 1, 1, 1 }, | ||
96 | { P, 0, 0, 0, 0 }, | ||
97 | { N, 1, 1, 0, 1 }, | ||
98 | { C, 0, 1, 1, 1 }, | ||
99 | { C, 0, 1, 1, 1 }, | ||
100 | { P, 0, 0, 0, 0 }, | ||
101 | { C, 0, 0, 0, 1 }, | ||
102 | { P, 0, 0, 0, 0 }, | ||
103 | { C, 0, 1, 0, 1 }, | ||
104 | { P, 0, 0, 0, 0 }, | ||
105 | { C, 1, 1, 0, 1 }, | ||
106 | { C, 0, 1, 0, 1 }, | ||
107 | { C, 0, 1, 0, 1 }, | ||
108 | { P, 0, 0, 0, 0 }, | ||
109 | { C, 1, 1, 1, 1 }, | ||
110 | { C, 0, 1, 1, 1 }, | ||
111 | { C, 0, 1, 1, 1 }, | ||
112 | { P, 0, 0, 0, 0 }, | ||
113 | { C, 1, 1, 1, 1 }, | ||
114 | { C, 0, 1, 1, 1 }, | ||
115 | { C, 0, 1, 1, 1 } | ||
116 | }; | ||
117 | |||
118 | /** | ||
119 | * \param line_aa AA_NEVER, AA_ALWAYS or AA_SOMETIMES | ||
120 | * \param lookup bitmask of IZ_* flags | ||
121 | */ | ||
122 | void brw_wm_lookup_iz( GLuint line_aa, | ||
123 | GLuint lookup, | ||
124 | GLboolean ps_uses_depth, | ||
125 | struct brw_wm_prog_key *key ) | ||
126 | { | ||
127 | GLuint reg = 2; | ||
128 | |||
129 | assert (lookup < IZ_BIT_MAX); | ||
130 | |||
131 | if (lookup & IZ_PS_COMPUTES_DEPTH_BIT) | ||
132 | key->computes_depth = 1; | ||
133 | |||
134 | if (wm_iz_table[lookup].sd_present || ps_uses_depth) { | ||
135 | key->source_depth_reg = reg; | ||
136 | reg += 2; | ||
137 | } | ||
138 | |||
139 | if (wm_iz_table[lookup].sd_to_rt) | ||
140 | key->source_depth_to_render_target = 1; | ||
141 | |||
142 | if (wm_iz_table[lookup].ds_present || line_aa != AA_NEVER) { | ||
143 | key->aa_dest_stencil_reg = reg; | ||
144 | key->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present && | ||
145 | line_aa == AA_SOMETIMES); | ||
146 | reg++; | ||
147 | } | ||
148 | |||
149 | if (wm_iz_table[lookup].dd_present) { | ||
150 | key->dest_depth_reg = reg; | ||
151 | reg+=2; | ||
152 | } | ||
153 | |||
154 | key->nr_depth_regs = (reg+1)/2; | ||
155 | } | ||
156 | |||
diff --git a/src/gallium/drivers/i965/brw_wm_pass0.c b/src/gallium/drivers/i965/brw_wm_pass0.c deleted file mode 100644 index 0bacad2b0f0..00000000000 --- a/src/gallium/drivers/i965/brw_wm_pass0.c +++ /dev/null | |||
@@ -1,366 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_memory.h" | ||
33 | #include "util/u_math.h" | ||
34 | |||
35 | #include "brw_debug.h" | ||
36 | #include "brw_wm.h" | ||
37 | |||
38 | |||
39 | |||
40 | /*********************************************************************** | ||
41 | */ | ||
42 | |||
43 | static struct brw_wm_ref *get_ref( struct brw_wm_compile *c ) | ||
44 | { | ||
45 | assert(c->nr_refs < BRW_WM_MAX_REF); | ||
46 | return &c->refs[c->nr_refs++]; | ||
47 | } | ||
48 | |||
49 | static struct brw_wm_value *get_value( struct brw_wm_compile *c) | ||
50 | { | ||
51 | assert(c->nr_refs < BRW_WM_MAX_VREG); | ||
52 | return &c->vreg[c->nr_vreg++]; | ||
53 | } | ||
54 | |||
55 | /** return pointer to a newly allocated instruction */ | ||
56 | static struct brw_wm_instruction *get_instruction( struct brw_wm_compile *c ) | ||
57 | { | ||
58 | assert(c->nr_insns < BRW_WM_MAX_INSN); | ||
59 | return &c->instruction[c->nr_insns++]; | ||
60 | } | ||
61 | |||
62 | /*********************************************************************** | ||
63 | */ | ||
64 | |||
65 | /** Init the "undef" register */ | ||
66 | static void pass0_init_undef( struct brw_wm_compile *c) | ||
67 | { | ||
68 | struct brw_wm_ref *ref = &c->undef_ref; | ||
69 | ref->value = &c->undef_value; | ||
70 | ref->hw_reg = brw_vec8_grf(0, 0); | ||
71 | ref->insn = 0; | ||
72 | ref->prevuse = NULL; | ||
73 | } | ||
74 | |||
75 | /** Set a FP register to a value */ | ||
76 | static void pass0_set_fpreg_value( struct brw_wm_compile *c, | ||
77 | GLuint file, | ||
78 | GLuint idx, | ||
79 | GLuint component, | ||
80 | struct brw_wm_value *value ) | ||
81 | { | ||
82 | struct brw_wm_ref *ref = get_ref(c); | ||
83 | ref->value = value; | ||
84 | ref->hw_reg = brw_vec8_grf(0, 0); | ||
85 | ref->insn = 0; | ||
86 | ref->prevuse = NULL; | ||
87 | c->pass0_fp_reg[file][idx][component] = ref; | ||
88 | } | ||
89 | |||
90 | /** Set a FP register to a ref */ | ||
91 | static void pass0_set_fpreg_ref( struct brw_wm_compile *c, | ||
92 | GLuint file, | ||
93 | GLuint idx, | ||
94 | GLuint component, | ||
95 | const struct brw_wm_ref *src_ref ) | ||
96 | { | ||
97 | c->pass0_fp_reg[file][idx][component] = src_ref; | ||
98 | } | ||
99 | |||
100 | static const struct brw_wm_ref *get_param_ref( struct brw_wm_compile *c, | ||
101 | unsigned idx, | ||
102 | unsigned component) | ||
103 | { | ||
104 | GLuint i = idx * 4 + component; | ||
105 | |||
106 | if (i >= BRW_WM_MAX_PARAM) { | ||
107 | debug_printf("%s: out of params\n", __FUNCTION__); | ||
108 | c->prog_data.error = 1; | ||
109 | return NULL; | ||
110 | } | ||
111 | else { | ||
112 | struct brw_wm_ref *ref = get_ref(c); | ||
113 | |||
114 | c->nr_creg = MAX2(c->nr_creg, (i+16)/16); | ||
115 | |||
116 | /* Push the offsets into hw_reg. These will be added to the | ||
117 | * real register numbers once one is allocated in pass2. | ||
118 | */ | ||
119 | ref->hw_reg = brw_vec1_grf((i&8)?1:0, i%8); | ||
120 | ref->value = &c->creg[i/16]; | ||
121 | ref->insn = 0; | ||
122 | ref->prevuse = NULL; | ||
123 | |||
124 | return ref; | ||
125 | } | ||
126 | } | ||
127 | |||
128 | |||
129 | |||
130 | |||
131 | /* Lookup our internal registers | ||
132 | */ | ||
133 | static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c, | ||
134 | GLuint file, | ||
135 | GLuint idx, | ||
136 | GLuint component ) | ||
137 | { | ||
138 | const struct brw_wm_ref *ref = c->pass0_fp_reg[file][idx][component]; | ||
139 | |||
140 | if (!ref) { | ||
141 | switch (file) { | ||
142 | case TGSI_FILE_INPUT: | ||
143 | case TGSI_FILE_TEMPORARY: | ||
144 | case TGSI_FILE_OUTPUT: | ||
145 | case BRW_FILE_PAYLOAD: | ||
146 | /* should already be done?? */ | ||
147 | break; | ||
148 | |||
149 | case TGSI_FILE_CONSTANT: | ||
150 | ref = get_param_ref(c, | ||
151 | c->fp->info.immediate_count + idx, | ||
152 | component); | ||
153 | break; | ||
154 | |||
155 | case TGSI_FILE_IMMEDIATE: | ||
156 | ref = get_param_ref(c, | ||
157 | idx, | ||
158 | component); | ||
159 | break; | ||
160 | |||
161 | default: | ||
162 | assert(0); | ||
163 | break; | ||
164 | } | ||
165 | |||
166 | c->pass0_fp_reg[file][idx][component] = ref; | ||
167 | } | ||
168 | |||
169 | if (!ref) | ||
170 | ref = &c->undef_ref; | ||
171 | |||
172 | return ref; | ||
173 | } | ||
174 | |||
175 | |||
176 | |||
177 | /*********************************************************************** | ||
178 | * Straight translation to internal instruction format | ||
179 | */ | ||
180 | |||
181 | static void pass0_set_dst( struct brw_wm_compile *c, | ||
182 | struct brw_wm_instruction *out, | ||
183 | const struct brw_fp_instruction *inst, | ||
184 | GLuint writemask ) | ||
185 | { | ||
186 | const struct brw_fp_dst dst = inst->dst; | ||
187 | GLuint i; | ||
188 | |||
189 | for (i = 0; i < 4; i++) { | ||
190 | if (writemask & (1<<i)) { | ||
191 | out->dst[i] = get_value(c); | ||
192 | pass0_set_fpreg_value(c, dst.file, dst.index, i, out->dst[i]); | ||
193 | } | ||
194 | } | ||
195 | |||
196 | out->writemask = writemask; | ||
197 | } | ||
198 | |||
199 | |||
200 | static const struct brw_wm_ref *get_fp_src_reg_ref( struct brw_wm_compile *c, | ||
201 | struct brw_fp_src src, | ||
202 | GLuint i ) | ||
203 | { | ||
204 | return pass0_get_reg(c, src.file, src.index, BRW_GET_SWZ(src.swizzle,i)); | ||
205 | } | ||
206 | |||
207 | |||
208 | static struct brw_wm_ref *get_new_ref( struct brw_wm_compile *c, | ||
209 | struct brw_fp_src src, | ||
210 | GLuint i, | ||
211 | struct brw_wm_instruction *insn) | ||
212 | { | ||
213 | const struct brw_wm_ref *ref = get_fp_src_reg_ref(c, src, i); | ||
214 | struct brw_wm_ref *newref = get_ref(c); | ||
215 | |||
216 | newref->value = ref->value; | ||
217 | newref->hw_reg = ref->hw_reg; | ||
218 | |||
219 | if (insn) { | ||
220 | newref->insn = insn - c->instruction; | ||
221 | newref->prevuse = newref->value->lastuse; | ||
222 | newref->value->lastuse = newref; | ||
223 | } | ||
224 | |||
225 | if (src.negate) | ||
226 | newref->hw_reg.negate ^= 1; | ||
227 | |||
228 | if (src.abs) { | ||
229 | newref->hw_reg.negate = 0; | ||
230 | newref->hw_reg.abs = 1; | ||
231 | } | ||
232 | |||
233 | return newref; | ||
234 | } | ||
235 | |||
236 | |||
237 | static void | ||
238 | translate_insn(struct brw_wm_compile *c, | ||
239 | const struct brw_fp_instruction *inst) | ||
240 | { | ||
241 | struct brw_wm_instruction *out = get_instruction(c); | ||
242 | GLuint writemask = inst->dst.writemask; | ||
243 | GLuint nr_args = brw_wm_nr_args(inst->opcode); | ||
244 | GLuint i, j; | ||
245 | |||
246 | /* Copy some data out of the instruction | ||
247 | */ | ||
248 | out->opcode = inst->opcode; | ||
249 | out->saturate = inst->dst.saturate; | ||
250 | out->tex_unit = inst->tex_unit; | ||
251 | out->target = inst->target; | ||
252 | |||
253 | /* Nasty hack: | ||
254 | */ | ||
255 | out->eot = (inst->opcode == WM_FB_WRITE && | ||
256 | inst->tex_unit != 0); | ||
257 | |||
258 | |||
259 | /* Args: | ||
260 | */ | ||
261 | for (i = 0; i < nr_args; i++) { | ||
262 | for (j = 0; j < 4; j++) { | ||
263 | out->src[i][j] = get_new_ref(c, inst->src[i], j, out); | ||
264 | } | ||
265 | } | ||
266 | |||
267 | /* Dst: | ||
268 | */ | ||
269 | pass0_set_dst(c, out, inst, writemask); | ||
270 | } | ||
271 | |||
272 | |||
273 | |||
274 | /*********************************************************************** | ||
275 | * Optimize moves and swizzles away: | ||
276 | */ | ||
277 | static void pass0_precalc_mov( struct brw_wm_compile *c, | ||
278 | const struct brw_fp_instruction *inst ) | ||
279 | { | ||
280 | const struct brw_fp_dst dst = inst->dst; | ||
281 | GLuint writemask = dst.writemask; | ||
282 | struct brw_wm_ref *refs[4]; | ||
283 | GLuint i; | ||
284 | |||
285 | /* Get the effect of a MOV by manipulating our register table: | ||
286 | * First get all refs, then assign refs. This ensures that "in-place" | ||
287 | * swizzles such as: | ||
288 | * MOV t, t.xxyx | ||
289 | * are handled correctly. Previously, these two steps were done in | ||
290 | * one loop and the above case was incorrectly handled. | ||
291 | */ | ||
292 | for (i = 0; i < 4; i++) { | ||
293 | refs[i] = get_new_ref(c, inst->src[0], i, NULL); | ||
294 | } | ||
295 | for (i = 0; i < 4; i++) { | ||
296 | if (writemask & (1 << i)) { | ||
297 | pass0_set_fpreg_ref( c, dst.file, dst.index, i, refs[i]); | ||
298 | } | ||
299 | } | ||
300 | } | ||
301 | |||
302 | |||
303 | /* Initialize payload "registers". | ||
304 | */ | ||
305 | static void pass0_init_payload( struct brw_wm_compile *c ) | ||
306 | { | ||
307 | GLuint i; | ||
308 | |||
309 | for (i = 0; i < 4; i++) { | ||
310 | GLuint j = i >= c->key.nr_depth_regs ? 0 : i; | ||
311 | pass0_set_fpreg_value( c, BRW_FILE_PAYLOAD, PAYLOAD_DEPTH, i, | ||
312 | &c->payload.depth[j] ); | ||
313 | } | ||
314 | |||
315 | for (i = 0; i < c->key.nr_inputs; i++) | ||
316 | pass0_set_fpreg_value( c, BRW_FILE_PAYLOAD, i, 0, | ||
317 | &c->payload.input_interp[i] ); | ||
318 | } | ||
319 | |||
320 | |||
321 | /*********************************************************************** | ||
322 | * PASS 0 | ||
323 | * | ||
324 | * Work forwards to give each calculated value a unique number. Where | ||
325 | * an instruction produces duplicate values (eg DP3), all are given | ||
326 | * the same number. | ||
327 | * | ||
328 | * Translate away swizzling and eliminate non-saturating moves. | ||
329 | * | ||
330 | * Translate instructions from our fp_instruction structs to our | ||
331 | * internal brw_wm_instruction representation. | ||
332 | */ | ||
333 | void brw_wm_pass0( struct brw_wm_compile *c ) | ||
334 | { | ||
335 | GLuint insn; | ||
336 | |||
337 | c->nr_vreg = 0; | ||
338 | c->nr_insns = 0; | ||
339 | |||
340 | pass0_init_undef(c); | ||
341 | pass0_init_payload(c); | ||
342 | |||
343 | for (insn = 0; insn < c->nr_fp_insns; insn++) { | ||
344 | const struct brw_fp_instruction *inst = &c->fp_instructions[insn]; | ||
345 | |||
346 | /* Optimize away moves, otherwise emit translated instruction: | ||
347 | */ | ||
348 | switch (inst->opcode) { | ||
349 | case TGSI_OPCODE_MOV: | ||
350 | if (!inst->dst.saturate) { | ||
351 | pass0_precalc_mov(c, inst); | ||
352 | } | ||
353 | else { | ||
354 | translate_insn(c, inst); | ||
355 | } | ||
356 | break; | ||
357 | default: | ||
358 | translate_insn(c, inst); | ||
359 | break; | ||
360 | } | ||
361 | } | ||
362 | |||
363 | if (BRW_DEBUG & DEBUG_WM) { | ||
364 | brw_wm_print_program(c, "pass0"); | ||
365 | } | ||
366 | } | ||
diff --git a/src/gallium/drivers/i965/brw_wm_pass1.c b/src/gallium/drivers/i965/brw_wm_pass1.c deleted file mode 100644 index 005747f00ba..00000000000 --- a/src/gallium/drivers/i965/brw_wm_pass1.c +++ /dev/null | |||
@@ -1,292 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_wm.h" | ||
34 | #include "brw_debug.h" | ||
35 | |||
36 | |||
37 | static GLuint get_tracked_mask(struct brw_wm_compile *c, | ||
38 | struct brw_wm_instruction *inst) | ||
39 | { | ||
40 | GLuint i; | ||
41 | for (i = 0; i < 4; i++) { | ||
42 | if (inst->writemask & (1<<i)) { | ||
43 | if (!inst->dst[i]->contributes_to_output) { | ||
44 | inst->writemask &= ~(1<<i); | ||
45 | inst->dst[i] = 0; | ||
46 | } | ||
47 | } | ||
48 | } | ||
49 | |||
50 | return inst->writemask; | ||
51 | } | ||
52 | |||
53 | /* Remove a reference from a value's usage chain. | ||
54 | */ | ||
55 | static void unlink_ref(struct brw_wm_ref *ref) | ||
56 | { | ||
57 | struct brw_wm_value *value = ref->value; | ||
58 | |||
59 | if (ref == value->lastuse) { | ||
60 | value->lastuse = ref->prevuse; | ||
61 | } | ||
62 | else { | ||
63 | struct brw_wm_ref *i = value->lastuse; | ||
64 | while (i->prevuse != ref) i = i->prevuse; | ||
65 | i->prevuse = ref->prevuse; | ||
66 | } | ||
67 | } | ||
68 | |||
69 | static void track_arg(struct brw_wm_compile *c, | ||
70 | struct brw_wm_instruction *inst, | ||
71 | GLuint arg, | ||
72 | GLuint readmask) | ||
73 | { | ||
74 | GLuint i; | ||
75 | |||
76 | for (i = 0; i < 4; i++) { | ||
77 | struct brw_wm_ref *ref = inst->src[arg][i]; | ||
78 | if (ref) { | ||
79 | if (readmask & (1<<i)) { | ||
80 | ref->value->contributes_to_output = 1; | ||
81 | } | ||
82 | else { | ||
83 | unlink_ref(ref); | ||
84 | inst->src[arg][i] = NULL; | ||
85 | } | ||
86 | } | ||
87 | } | ||
88 | } | ||
89 | |||
90 | static GLuint get_texcoord_mask( GLuint tex_idx ) | ||
91 | { | ||
92 | switch (tex_idx) { | ||
93 | case TGSI_TEXTURE_1D: | ||
94 | return BRW_WRITEMASK_X; | ||
95 | case TGSI_TEXTURE_2D: | ||
96 | case TGSI_TEXTURE_RECT: | ||
97 | return BRW_WRITEMASK_XY; | ||
98 | case TGSI_TEXTURE_3D: | ||
99 | return BRW_WRITEMASK_XYZ; | ||
100 | case TGSI_TEXTURE_CUBE: | ||
101 | return BRW_WRITEMASK_XYZ; | ||
102 | |||
103 | case TGSI_TEXTURE_SHADOW1D: | ||
104 | return BRW_WRITEMASK_XZ; | ||
105 | case TGSI_TEXTURE_SHADOW2D: | ||
106 | case TGSI_TEXTURE_SHADOWRECT: | ||
107 | return BRW_WRITEMASK_XYZ; | ||
108 | default: | ||
109 | assert(0); | ||
110 | return 0; | ||
111 | } | ||
112 | } | ||
113 | |||
114 | |||
115 | /* Step two: Basically this is dead code elimination. | ||
116 | * | ||
117 | * Iterate backwards over instructions, noting which values | ||
118 | * contribute to the final result. Adjust writemasks to only | ||
119 | * calculate these values. | ||
120 | */ | ||
121 | void brw_wm_pass1( struct brw_wm_compile *c ) | ||
122 | { | ||
123 | GLint insn; | ||
124 | |||
125 | for (insn = c->nr_insns-1; insn >= 0; insn--) { | ||
126 | struct brw_wm_instruction *inst = &c->instruction[insn]; | ||
127 | GLuint writemask; | ||
128 | GLuint read0, read1, read2; | ||
129 | |||
130 | if (inst->opcode == TGSI_OPCODE_KIL) { | ||
131 | track_arg(c, inst, 0, BRW_WRITEMASK_XYZW); /* All args contribute to final */ | ||
132 | continue; | ||
133 | } | ||
134 | |||
135 | if (inst->opcode == WM_FB_WRITE) { | ||
136 | track_arg(c, inst, 0, BRW_WRITEMASK_XYZW); | ||
137 | track_arg(c, inst, 1, BRW_WRITEMASK_XYZW); | ||
138 | if (c->key.source_depth_to_render_target && | ||
139 | c->key.computes_depth) | ||
140 | track_arg(c, inst, 2, BRW_WRITEMASK_Z); | ||
141 | else | ||
142 | track_arg(c, inst, 2, 0); | ||
143 | continue; | ||
144 | } | ||
145 | |||
146 | /* Lookup all the registers which were written by this | ||
147 | * instruction and get a mask of those that contribute to the output: | ||
148 | */ | ||
149 | writemask = get_tracked_mask(c, inst); | ||
150 | if (!writemask) { | ||
151 | GLuint arg; | ||
152 | for (arg = 0; arg < 3; arg++) | ||
153 | track_arg(c, inst, arg, 0); | ||
154 | continue; | ||
155 | } | ||
156 | |||
157 | read0 = 0; | ||
158 | read1 = 0; | ||
159 | read2 = 0; | ||
160 | |||
161 | /* Mark all inputs which contribute to the marked outputs: | ||
162 | */ | ||
163 | switch (inst->opcode) { | ||
164 | case TGSI_OPCODE_ABS: | ||
165 | case TGSI_OPCODE_FLR: | ||
166 | case TGSI_OPCODE_FRC: | ||
167 | case TGSI_OPCODE_MOV: | ||
168 | case TGSI_OPCODE_TRUNC: | ||
169 | read0 = writemask; | ||
170 | break; | ||
171 | |||
172 | case TGSI_OPCODE_SUB: | ||
173 | case TGSI_OPCODE_SLT: | ||
174 | case TGSI_OPCODE_SLE: | ||
175 | case TGSI_OPCODE_SGE: | ||
176 | case TGSI_OPCODE_SGT: | ||
177 | case TGSI_OPCODE_SEQ: | ||
178 | case TGSI_OPCODE_SNE: | ||
179 | case TGSI_OPCODE_ADD: | ||
180 | case TGSI_OPCODE_MAX: | ||
181 | case TGSI_OPCODE_MIN: | ||
182 | case TGSI_OPCODE_MUL: | ||
183 | read0 = writemask; | ||
184 | read1 = writemask; | ||
185 | break; | ||
186 | |||
187 | case TGSI_OPCODE_DDX: | ||
188 | case TGSI_OPCODE_DDY: | ||
189 | read0 = writemask; | ||
190 | break; | ||
191 | |||
192 | case TGSI_OPCODE_MAD: | ||
193 | case TGSI_OPCODE_CMP: | ||
194 | case TGSI_OPCODE_LRP: | ||
195 | read0 = writemask; | ||
196 | read1 = writemask; | ||
197 | read2 = writemask; | ||
198 | break; | ||
199 | |||
200 | case TGSI_OPCODE_XPD: | ||
201 | if (writemask & BRW_WRITEMASK_X) read0 |= BRW_WRITEMASK_YZ; | ||
202 | if (writemask & BRW_WRITEMASK_Y) read0 |= BRW_WRITEMASK_XZ; | ||
203 | if (writemask & BRW_WRITEMASK_Z) read0 |= BRW_WRITEMASK_XY; | ||
204 | read1 = read0; | ||
205 | break; | ||
206 | |||
207 | case TGSI_OPCODE_COS: | ||
208 | case TGSI_OPCODE_EX2: | ||
209 | case TGSI_OPCODE_LG2: | ||
210 | case TGSI_OPCODE_RCP: | ||
211 | case TGSI_OPCODE_RSQ: | ||
212 | case TGSI_OPCODE_SIN: | ||
213 | case TGSI_OPCODE_SCS: | ||
214 | case WM_CINTERP: | ||
215 | case WM_PIXELXY: | ||
216 | read0 = BRW_WRITEMASK_X; | ||
217 | break; | ||
218 | |||
219 | case TGSI_OPCODE_POW: | ||
220 | read0 = BRW_WRITEMASK_X; | ||
221 | read1 = BRW_WRITEMASK_X; | ||
222 | break; | ||
223 | |||
224 | case TGSI_OPCODE_TEX: | ||
225 | case TGSI_OPCODE_TXP: | ||
226 | read0 = get_texcoord_mask(inst->target); | ||
227 | break; | ||
228 | |||
229 | case TGSI_OPCODE_TXB: | ||
230 | read0 = get_texcoord_mask(inst->target) | BRW_WRITEMASK_W; | ||
231 | break; | ||
232 | |||
233 | case WM_WPOSXY: | ||
234 | read0 = writemask & BRW_WRITEMASK_XY; | ||
235 | break; | ||
236 | |||
237 | case WM_DELTAXY: | ||
238 | read0 = writemask & BRW_WRITEMASK_XY; | ||
239 | read1 = BRW_WRITEMASK_X; | ||
240 | break; | ||
241 | |||
242 | case WM_PIXELW: | ||
243 | read0 = BRW_WRITEMASK_X; | ||
244 | read1 = BRW_WRITEMASK_XY; | ||
245 | break; | ||
246 | |||
247 | case WM_LINTERP: | ||
248 | read0 = BRW_WRITEMASK_X; | ||
249 | read1 = BRW_WRITEMASK_XY; | ||
250 | break; | ||
251 | |||
252 | case WM_PINTERP: | ||
253 | read0 = BRW_WRITEMASK_X; /* interpolant */ | ||
254 | read1 = BRW_WRITEMASK_XY; /* deltas */ | ||
255 | read2 = BRW_WRITEMASK_W; /* pixel w */ | ||
256 | break; | ||
257 | |||
258 | case TGSI_OPCODE_DP3: | ||
259 | read0 = BRW_WRITEMASK_XYZ; | ||
260 | read1 = BRW_WRITEMASK_XYZ; | ||
261 | break; | ||
262 | |||
263 | case TGSI_OPCODE_DPH: | ||
264 | read0 = BRW_WRITEMASK_XYZ; | ||
265 | read1 = BRW_WRITEMASK_XYZW; | ||
266 | break; | ||
267 | |||
268 | case TGSI_OPCODE_DP4: | ||
269 | read0 = BRW_WRITEMASK_XYZW; | ||
270 | read1 = BRW_WRITEMASK_XYZW; | ||
271 | break; | ||
272 | |||
273 | case TGSI_OPCODE_LIT: | ||
274 | read0 = BRW_WRITEMASK_XYW; | ||
275 | break; | ||
276 | |||
277 | case TGSI_OPCODE_DST: | ||
278 | case WM_FRONTFACING: | ||
279 | case TGSI_OPCODE_KILP: | ||
280 | default: | ||
281 | break; | ||
282 | } | ||
283 | |||
284 | track_arg(c, inst, 0, read0); | ||
285 | track_arg(c, inst, 1, read1); | ||
286 | track_arg(c, inst, 2, read2); | ||
287 | } | ||
288 | |||
289 | if (BRW_DEBUG & DEBUG_WM) { | ||
290 | brw_wm_print_program(c, "pass1"); | ||
291 | } | ||
292 | } | ||
diff --git a/src/gallium/drivers/i965/brw_wm_pass2.c b/src/gallium/drivers/i965/brw_wm_pass2.c deleted file mode 100644 index 19248b45195..00000000000 --- a/src/gallium/drivers/i965/brw_wm_pass2.c +++ /dev/null | |||
@@ -1,334 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | |||
33 | #include "brw_debug.h" | ||
34 | #include "brw_wm.h" | ||
35 | |||
36 | |||
37 | /* Use these to force spilling so that that functionality can be | ||
38 | * tested with known-good examples rather than having to construct new | ||
39 | * tests. | ||
40 | */ | ||
41 | #define TEST_PAYLOAD_SPILLS 0 | ||
42 | #define TEST_DST_SPILLS 0 | ||
43 | |||
44 | static void spill_value(struct brw_wm_compile *c, | ||
45 | struct brw_wm_value *value); | ||
46 | |||
47 | static void prealloc_reg(struct brw_wm_compile *c, | ||
48 | struct brw_wm_value *value, | ||
49 | GLuint reg) | ||
50 | { | ||
51 | if (value->lastuse) { | ||
52 | /* Set nextuse to zero, it will be corrected by | ||
53 | * update_register_usage(). | ||
54 | */ | ||
55 | c->pass2_grf[reg].value = value; | ||
56 | c->pass2_grf[reg].nextuse = 0; | ||
57 | |||
58 | value->resident = &c->pass2_grf[reg]; | ||
59 | value->hw_reg = brw_vec8_grf(reg*2, 0); | ||
60 | |||
61 | if (TEST_PAYLOAD_SPILLS) | ||
62 | spill_value(c, value); | ||
63 | } | ||
64 | } | ||
65 | |||
66 | |||
67 | /* Initialize all the register values. Do the initial setup | ||
68 | * calculations for interpolants. | ||
69 | */ | ||
70 | static void init_registers( struct brw_wm_compile *c ) | ||
71 | { | ||
72 | GLuint reg = 0; | ||
73 | GLuint j; | ||
74 | |||
75 | for (j = 0; j < c->grf_limit; j++) | ||
76 | c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN; | ||
77 | |||
78 | /* Pre-allocate incoming payload regs: | ||
79 | */ | ||
80 | for (j = 0; j < c->key.nr_depth_regs; j++) | ||
81 | prealloc_reg(c, &c->payload.depth[j], reg++); | ||
82 | |||
83 | for (j = 0; j < c->nr_creg; j++) | ||
84 | prealloc_reg(c, &c->creg[j], reg++); | ||
85 | |||
86 | reg++; /* XXX: skip over position output */ | ||
87 | |||
88 | /* XXX: currently just hope the VS outputs line up with FS inputs: | ||
89 | */ | ||
90 | for (j = 0; j < c->key.nr_inputs; j++) | ||
91 | prealloc_reg(c, &c->payload.input_interp[j], reg++); | ||
92 | |||
93 | c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2; | ||
94 | c->prog_data.urb_read_length = (c->key.nr_inputs + 1) * 2; | ||
95 | c->prog_data.curb_read_length = c->nr_creg * 2; | ||
96 | |||
97 | /* Note this allocation: | ||
98 | */ | ||
99 | c->max_wm_grf = reg * 2; | ||
100 | } | ||
101 | |||
102 | |||
103 | /* Update the nextuse value for each register in our file. | ||
104 | */ | ||
105 | static void update_register_usage(struct brw_wm_compile *c, | ||
106 | GLuint thisinsn) | ||
107 | { | ||
108 | GLuint i; | ||
109 | |||
110 | for (i = 1; i < c->grf_limit; i++) { | ||
111 | struct brw_wm_grf *grf = &c->pass2_grf[i]; | ||
112 | |||
113 | /* Only search those which can change: | ||
114 | */ | ||
115 | if (grf->nextuse < thisinsn) { | ||
116 | const struct brw_wm_ref *ref = grf->value->lastuse; | ||
117 | |||
118 | /* Has last use of value been passed? | ||
119 | */ | ||
120 | if (ref->insn < thisinsn) { | ||
121 | grf->value->resident = 0; | ||
122 | grf->value = 0; | ||
123 | grf->nextuse = BRW_WM_MAX_INSN; | ||
124 | } | ||
125 | else { | ||
126 | /* Else loop through chain to update: | ||
127 | */ | ||
128 | while (ref->prevuse && ref->prevuse->insn >= thisinsn) | ||
129 | ref = ref->prevuse; | ||
130 | |||
131 | grf->nextuse = ref->insn; | ||
132 | } | ||
133 | } | ||
134 | } | ||
135 | } | ||
136 | |||
137 | |||
138 | static void spill_value(struct brw_wm_compile *c, | ||
139 | struct brw_wm_value *value) | ||
140 | { | ||
141 | /* Allocate a spill slot. Note that allocations start from 0x40 - | ||
142 | * the first slot is reserved to mean "undef" in brw_wm_emit.c | ||
143 | */ | ||
144 | if (!value->spill_slot) { | ||
145 | c->last_scratch += 0x40; | ||
146 | value->spill_slot = c->last_scratch; | ||
147 | } | ||
148 | |||
149 | /* The spill will be done in brw_wm_emit.c immediately after the | ||
150 | * value is calculated, so we can just take this reg without any | ||
151 | * further work. | ||
152 | */ | ||
153 | value->resident->value = NULL; | ||
154 | value->resident->nextuse = BRW_WM_MAX_INSN; | ||
155 | value->resident = NULL; | ||
156 | } | ||
157 | |||
158 | |||
159 | |||
160 | /* Search for contiguous region with the most distant nearest | ||
161 | * member. Free regs count as very distant. | ||
162 | * | ||
163 | * TODO: implement spill-to-reg so that we can rearrange discontigous | ||
164 | * free regs and then spill the oldest non-free regs in sequence. | ||
165 | * This would mean inserting instructions in this pass. | ||
166 | */ | ||
167 | static GLuint search_contiguous_regs(struct brw_wm_compile *c, | ||
168 | GLuint nr, | ||
169 | GLuint thisinsn) | ||
170 | { | ||
171 | struct brw_wm_grf *grf = c->pass2_grf; | ||
172 | GLuint furthest = 0; | ||
173 | GLuint reg = 0; | ||
174 | GLuint i, j; | ||
175 | |||
176 | /* Start search at 1: r0 is special and can't be used or spilled. | ||
177 | */ | ||
178 | for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) { | ||
179 | GLuint group_nextuse = BRW_WM_MAX_INSN; | ||
180 | |||
181 | for (j = 0; j < nr; j++) { | ||
182 | if (grf[i+j].nextuse < group_nextuse) | ||
183 | group_nextuse = grf[i+j].nextuse; | ||
184 | } | ||
185 | |||
186 | if (group_nextuse > furthest) { | ||
187 | furthest = group_nextuse; | ||
188 | reg = i; | ||
189 | } | ||
190 | } | ||
191 | |||
192 | assert(furthest != thisinsn); | ||
193 | |||
194 | /* Any non-empty regs will need to be spilled: | ||
195 | */ | ||
196 | for (j = 0; j < nr; j++) | ||
197 | if (grf[reg+j].value) | ||
198 | spill_value(c, grf[reg+j].value); | ||
199 | |||
200 | return reg; | ||
201 | } | ||
202 | |||
203 | |||
204 | static void alloc_contiguous_dest(struct brw_wm_compile *c, | ||
205 | struct brw_wm_value *dst[], | ||
206 | GLuint nr, | ||
207 | GLuint thisinsn) | ||
208 | { | ||
209 | GLuint reg = search_contiguous_regs(c, nr, thisinsn); | ||
210 | GLuint i; | ||
211 | |||
212 | for (i = 0; i < nr; i++) { | ||
213 | if (!dst[i]) { | ||
214 | /* Need to grab a dummy value in TEX case. Don't introduce | ||
215 | * it into the tracking scheme. | ||
216 | */ | ||
217 | dst[i] = &c->vreg[c->nr_vreg++]; | ||
218 | } | ||
219 | else { | ||
220 | assert(!dst[i]->resident); | ||
221 | assert(c->pass2_grf[reg+i].nextuse != thisinsn); | ||
222 | |||
223 | c->pass2_grf[reg+i].value = dst[i]; | ||
224 | c->pass2_grf[reg+i].nextuse = thisinsn; | ||
225 | |||
226 | dst[i]->resident = &c->pass2_grf[reg+i]; | ||
227 | } | ||
228 | |||
229 | dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0); | ||
230 | } | ||
231 | |||
232 | if ((reg+nr)*2 > c->max_wm_grf) | ||
233 | c->max_wm_grf = (reg+nr) * 2; | ||
234 | } | ||
235 | |||
236 | |||
237 | static void load_args(struct brw_wm_compile *c, | ||
238 | struct brw_wm_instruction *inst) | ||
239 | { | ||
240 | GLuint thisinsn = inst - c->instruction; | ||
241 | GLuint i,j; | ||
242 | |||
243 | for (i = 0; i < 3; i++) { | ||
244 | for (j = 0; j < 4; j++) { | ||
245 | struct brw_wm_ref *ref = inst->src[i][j]; | ||
246 | |||
247 | if (ref) { | ||
248 | if (!ref->value->resident) { | ||
249 | /* Need to bring the value in from scratch space. The code for | ||
250 | * this will be done in brw_wm_emit.c, here we just do the | ||
251 | * register allocation and mark the ref as requiring a fill. | ||
252 | */ | ||
253 | GLuint reg = search_contiguous_regs(c, 1, thisinsn); | ||
254 | |||
255 | c->pass2_grf[reg].value = ref->value; | ||
256 | c->pass2_grf[reg].nextuse = thisinsn; | ||
257 | |||
258 | ref->value->resident = &c->pass2_grf[reg]; | ||
259 | |||
260 | /* Note that a fill is required: | ||
261 | */ | ||
262 | ref->unspill_reg = reg*2; | ||
263 | } | ||
264 | |||
265 | /* Adjust the hw_reg to point at the value's current location: | ||
266 | */ | ||
267 | assert(ref->value == ref->value->resident->value); | ||
268 | ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2; | ||
269 | } | ||
270 | } | ||
271 | } | ||
272 | } | ||
273 | |||
274 | |||
275 | |||
276 | /* Step 3: Work forwards once again. Perform register allocations, | ||
277 | * taking into account instructions like TEX which require contiguous | ||
278 | * result registers. Where necessary spill registers to scratch space | ||
279 | * and reload later. | ||
280 | */ | ||
281 | void brw_wm_pass2( struct brw_wm_compile *c ) | ||
282 | { | ||
283 | GLuint insn; | ||
284 | GLuint i; | ||
285 | |||
286 | init_registers(c); | ||
287 | |||
288 | for (insn = 0; insn < c->nr_insns; insn++) { | ||
289 | struct brw_wm_instruction *inst = &c->instruction[insn]; | ||
290 | |||
291 | /* Update registers' nextuse values: | ||
292 | */ | ||
293 | update_register_usage(c, insn); | ||
294 | |||
295 | /* May need to unspill some args. | ||
296 | */ | ||
297 | load_args(c, inst); | ||
298 | |||
299 | /* Allocate registers to hold results: | ||
300 | */ | ||
301 | switch (inst->opcode) { | ||
302 | case TGSI_OPCODE_TEX: | ||
303 | case TGSI_OPCODE_TXB: | ||
304 | case TGSI_OPCODE_TXP: | ||
305 | alloc_contiguous_dest(c, inst->dst, 4, insn); | ||
306 | break; | ||
307 | |||
308 | default: | ||
309 | for (i = 0; i < 4; i++) { | ||
310 | if (inst->writemask & (1<<i)) { | ||
311 | assert(inst->dst[i]); | ||
312 | alloc_contiguous_dest(c, &inst->dst[i], 1, insn); | ||
313 | } | ||
314 | } | ||
315 | break; | ||
316 | } | ||
317 | |||
318 | if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) { | ||
319 | for (i = 0; i < 4; i++) | ||
320 | if (inst->dst[i]) | ||
321 | spill_value(c, inst->dst[i]); | ||
322 | } | ||
323 | } | ||
324 | |||
325 | if (BRW_DEBUG & DEBUG_WM) { | ||
326 | brw_wm_print_program(c, "pass2"); | ||
327 | } | ||
328 | |||
329 | c->state = PASS2_DONE; | ||
330 | |||
331 | if (BRW_DEBUG & DEBUG_WM) { | ||
332 | brw_wm_print_program(c, "pass2/done"); | ||
333 | } | ||
334 | } | ||
diff --git a/src/gallium/drivers/i965/brw_wm_sampler_state.c b/src/gallium/drivers/i965/brw_wm_sampler_state.c deleted file mode 100644 index 8406a1a9e20..00000000000 --- a/src/gallium/drivers/i965/brw_wm_sampler_state.c +++ /dev/null | |||
@@ -1,228 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | #include "util/u_format.h" | ||
34 | |||
35 | #include "brw_context.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_defines.h" | ||
38 | #include "brw_resource.h" | ||
39 | |||
40 | |||
41 | /* Samplers aren't strictly wm state from the hardware's perspective, | ||
42 | * but that is the only situation in which we use them in this driver. | ||
43 | */ | ||
44 | |||
45 | |||
46 | |||
47 | static enum pipe_error | ||
48 | upload_default_color( struct brw_context *brw, | ||
49 | const GLfloat *color, | ||
50 | struct brw_winsys_buffer **bo_out ) | ||
51 | { | ||
52 | struct brw_sampler_default_color sdc; | ||
53 | enum pipe_error ret; | ||
54 | |||
55 | COPY_4V(sdc.color, color); | ||
56 | |||
57 | ret = brw_cache_data( &brw->cache, BRW_SAMPLER_DEFAULT_COLOR, &sdc, | ||
58 | NULL, 0, bo_out ); | ||
59 | if (ret) | ||
60 | return ret; | ||
61 | |||
62 | return PIPE_OK; | ||
63 | } | ||
64 | |||
65 | |||
66 | struct wm_sampler_key { | ||
67 | int sampler_count; | ||
68 | struct brw_sampler_state sampler[BRW_MAX_TEX_UNIT]; | ||
69 | }; | ||
70 | |||
71 | |||
72 | /** Sets up the cache key for sampler state for all texture units */ | ||
73 | static void | ||
74 | brw_wm_sampler_populate_key(struct brw_context *brw, | ||
75 | struct wm_sampler_key *key) | ||
76 | { | ||
77 | int i; | ||
78 | |||
79 | memset(key, 0, sizeof(*key)); | ||
80 | |||
81 | key->sampler_count = MIN2(brw->curr.num_fragment_sampler_views, | ||
82 | brw->curr.num_samplers); | ||
83 | |||
84 | for (i = 0; i < key->sampler_count; i++) { | ||
85 | const struct brw_texture *tex = brw_texture(brw->curr.fragment_sampler_views[i]->texture); | ||
86 | const struct brw_sampler *sampler = brw->curr.sampler[i]; | ||
87 | struct brw_sampler_state *entry = &key->sampler[i]; | ||
88 | |||
89 | entry->ss0 = sampler->ss0; | ||
90 | entry->ss1 = sampler->ss1; | ||
91 | entry->ss2.default_color_pointer = 0; /* reloc */ | ||
92 | entry->ss3 = sampler->ss3; | ||
93 | |||
94 | /* Cube-maps on 965 and later must use the same wrap mode for all 3 | ||
95 | * coordinate dimensions. Futher, only CUBE and CLAMP are valid. | ||
96 | */ | ||
97 | if (tex->b.b.target == PIPE_TEXTURE_CUBE) { | ||
98 | if (FALSE && | ||
99 | (sampler->ss0.min_filter != BRW_MAPFILTER_NEAREST || | ||
100 | sampler->ss0.mag_filter != BRW_MAPFILTER_NEAREST)) { | ||
101 | entry->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CUBE; | ||
102 | entry->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CUBE; | ||
103 | entry->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CUBE; | ||
104 | } else { | ||
105 | entry->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; | ||
106 | entry->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; | ||
107 | entry->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; | ||
108 | } | ||
109 | } else if (tex->b.b.target == PIPE_TEXTURE_1D) { | ||
110 | /* There's a bug in 1D texture sampling - it actually pays | ||
111 | * attention to the wrap_t value, though it should not. | ||
112 | * Override the wrap_t value here to GL_REPEAT to keep | ||
113 | * any nonexistent border pixels from floating in. | ||
114 | */ | ||
115 | entry->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP; | ||
116 | } | ||
117 | } | ||
118 | } | ||
119 | |||
120 | |||
121 | static enum pipe_error | ||
122 | brw_wm_sampler_update_default_colors(struct brw_context *brw) | ||
123 | { | ||
124 | enum pipe_error ret; | ||
125 | int nr = MIN2(brw->curr.num_fragment_sampler_views, | ||
126 | brw->curr.num_samplers); | ||
127 | int i; | ||
128 | |||
129 | for (i = 0; i < nr; i++) { | ||
130 | const struct brw_texture *tex = brw_texture(brw->curr.fragment_sampler_views[i]->texture); | ||
131 | const struct brw_sampler *sampler = brw->curr.sampler[i]; | ||
132 | const float *bc; | ||
133 | float bordercolor[4] = { | ||
134 | sampler->border_color[0], | ||
135 | sampler->border_color[0], | ||
136 | sampler->border_color[0], | ||
137 | sampler->border_color[0] | ||
138 | }; | ||
139 | |||
140 | if (util_format_is_depth_or_stencil(tex->b.b.format)) { | ||
141 | bc = bordercolor; | ||
142 | } | ||
143 | else { | ||
144 | bc = sampler->border_color; | ||
145 | } | ||
146 | |||
147 | /* GL specs that border color for depth textures is taken from the | ||
148 | * R channel, while the hardware uses A. Spam R into all the | ||
149 | * channels for safety. | ||
150 | */ | ||
151 | ret = upload_default_color(brw, | ||
152 | bc, | ||
153 | &brw->wm.sdc_bo[i]); | ||
154 | if (ret) | ||
155 | return ret; | ||
156 | } | ||
157 | |||
158 | return PIPE_OK; | ||
159 | } | ||
160 | |||
161 | |||
162 | |||
163 | /* All samplers must be uploaded in a single contiguous array. | ||
164 | */ | ||
165 | static int upload_wm_samplers( struct brw_context *brw ) | ||
166 | { | ||
167 | struct wm_sampler_key key; | ||
168 | struct brw_winsys_reloc reloc[BRW_MAX_TEX_UNIT]; | ||
169 | enum pipe_error ret; | ||
170 | int i; | ||
171 | |||
172 | brw_wm_sampler_update_default_colors(brw); | ||
173 | brw_wm_sampler_populate_key(brw, &key); | ||
174 | |||
175 | if (brw->wm.sampler_count != key.sampler_count) { | ||
176 | brw->wm.sampler_count = key.sampler_count; | ||
177 | brw->state.dirty.cache |= CACHE_NEW_SAMPLER; | ||
178 | } | ||
179 | |||
180 | if (brw->wm.sampler_count == 0) { | ||
181 | bo_reference(&brw->wm.sampler_bo, NULL); | ||
182 | return PIPE_OK; | ||
183 | } | ||
184 | |||
185 | /* Emit SDC relocations */ | ||
186 | for (i = 0; i < key.sampler_count; i++) { | ||
187 | make_reloc( &reloc[i], | ||
188 | BRW_USAGE_SAMPLER, | ||
189 | 0, | ||
190 | i * sizeof(struct brw_sampler_state) + | ||
191 | offsetof(struct brw_sampler_state, ss2), | ||
192 | brw->wm.sdc_bo[i]); | ||
193 | } | ||
194 | |||
195 | |||
196 | if (brw_search_cache(&brw->cache, BRW_SAMPLER, | ||
197 | &key, sizeof(key), | ||
198 | reloc, key.sampler_count, | ||
199 | NULL, | ||
200 | &brw->wm.sampler_bo)) | ||
201 | return PIPE_OK; | ||
202 | |||
203 | /* If we didnt find it in the cache, compute the state and put it in the | ||
204 | * cache. | ||
205 | */ | ||
206 | ret = brw_upload_cache(&brw->cache, BRW_SAMPLER, | ||
207 | &key, sizeof(key), | ||
208 | reloc, key.sampler_count, | ||
209 | &key.sampler, sizeof(key.sampler), | ||
210 | NULL, NULL, | ||
211 | &brw->wm.sampler_bo); | ||
212 | if (ret) | ||
213 | return ret; | ||
214 | |||
215 | |||
216 | return 0; | ||
217 | } | ||
218 | |||
219 | const struct brw_tracked_state brw_wm_samplers = { | ||
220 | .dirty = { | ||
221 | .mesa = PIPE_NEW_BOUND_TEXTURES | PIPE_NEW_SAMPLERS, | ||
222 | .brw = 0, | ||
223 | .cache = 0 | ||
224 | }, | ||
225 | .prepare = upload_wm_samplers, | ||
226 | }; | ||
227 | |||
228 | |||
diff --git a/src/gallium/drivers/i965/brw_wm_state.c b/src/gallium/drivers/i965/brw_wm_state.c deleted file mode 100644 index a690003ecbd..00000000000 --- a/src/gallium/drivers/i965/brw_wm_state.c +++ /dev/null | |||
@@ -1,340 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "util/u_math.h" | ||
33 | |||
34 | #include "brw_context.h" | ||
35 | #include "brw_state.h" | ||
36 | #include "brw_defines.h" | ||
37 | #include "brw_wm.h" | ||
38 | #include "brw_debug.h" | ||
39 | #include "brw_pipe_rast.h" | ||
40 | |||
41 | /*********************************************************************** | ||
42 | * WM unit - fragment programs and rasterization | ||
43 | */ | ||
44 | |||
45 | struct brw_wm_unit_key { | ||
46 | unsigned int total_grf, total_scratch; | ||
47 | unsigned int urb_entry_read_length; | ||
48 | unsigned int curb_entry_read_length; | ||
49 | unsigned int dispatch_grf_start_reg; | ||
50 | |||
51 | unsigned int curbe_offset; | ||
52 | unsigned int urb_size; | ||
53 | |||
54 | unsigned int max_threads; | ||
55 | |||
56 | unsigned int nr_surfaces, sampler_count; | ||
57 | GLboolean uses_depth, computes_depth, uses_kill, has_flow_control; | ||
58 | GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable; | ||
59 | GLfloat offset_units, offset_factor; | ||
60 | }; | ||
61 | |||
62 | static void | ||
63 | wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) | ||
64 | { | ||
65 | const struct brw_fragment_shader *fp = brw->curr.fragment_shader; | ||
66 | |||
67 | memset(key, 0, sizeof(*key)); | ||
68 | |||
69 | if (BRW_DEBUG & DEBUG_SINGLE_THREAD) | ||
70 | key->max_threads = 1; | ||
71 | else { | ||
72 | /* WM maximum threads is number of EUs times number of threads per EU. */ | ||
73 | if (brw->gen == 5) | ||
74 | key->max_threads = 12 * 6; | ||
75 | else if (brw->is_g4x) | ||
76 | key->max_threads = 10 * 5; | ||
77 | else | ||
78 | key->max_threads = 8 * 4; | ||
79 | } | ||
80 | |||
81 | /* CACHE_NEW_WM_PROG */ | ||
82 | key->total_grf = brw->wm.prog_data->total_grf; | ||
83 | key->urb_entry_read_length = brw->wm.prog_data->urb_read_length; | ||
84 | key->curb_entry_read_length = brw->wm.prog_data->curb_read_length; | ||
85 | key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf; | ||
86 | key->total_scratch = align(brw->wm.prog_data->total_scratch, 1024); | ||
87 | |||
88 | /* BRW_NEW_URB_FENCE */ | ||
89 | key->urb_size = brw->urb.vsize; | ||
90 | |||
91 | /* BRW_NEW_CURBE_OFFSETS */ | ||
92 | key->curbe_offset = brw->curbe.wm_start; | ||
93 | |||
94 | /* BRW_NEW_NR_SURFACEs */ | ||
95 | key->nr_surfaces = brw->wm.nr_surfaces; | ||
96 | |||
97 | /* CACHE_NEW_SAMPLER */ | ||
98 | key->sampler_count = brw->wm.sampler_count; | ||
99 | |||
100 | /* PIPE_NEW_RAST */ | ||
101 | key->polygon_stipple = brw->curr.rast->templ.poly_stipple_enable; | ||
102 | |||
103 | /* PIPE_NEW_FRAGMENT_PROGRAM */ | ||
104 | key->uses_depth = fp->uses_depth; | ||
105 | key->computes_depth = fp->info.writes_z; | ||
106 | |||
107 | /* PIPE_NEW_DEPTH_BUFFER | ||
108 | * | ||
109 | * Override for NULL depthbuffer case, required by the Pixel Shader Computed | ||
110 | * Depth field. | ||
111 | */ | ||
112 | if (brw->curr.fb.zsbuf == NULL) | ||
113 | key->computes_depth = 0; | ||
114 | |||
115 | /* PIPE_NEW_DEPTH_STENCIL_ALPHA */ | ||
116 | key->uses_kill = (fp->info.uses_kill || | ||
117 | brw->curr.zstencil->cc3.alpha_test); | ||
118 | |||
119 | key->has_flow_control = fp->has_flow_control; | ||
120 | |||
121 | /* temporary sanity check assertion */ | ||
122 | assert(fp->has_flow_control == 0); | ||
123 | |||
124 | /* PIPE_NEW_QUERY */ | ||
125 | key->stats_wm = (brw->query.stats_wm != 0); | ||
126 | |||
127 | /* PIPE_NEW_RAST */ | ||
128 | key->line_stipple = brw->curr.rast->templ.line_stipple_enable; | ||
129 | |||
130 | |||
131 | key->offset_enable = (brw->curr.rast->templ.offset_point || | ||
132 | brw->curr.rast->templ.offset_line || | ||
133 | brw->curr.rast->templ.offset_tri); | ||
134 | |||
135 | key->offset_units = brw->curr.rast->templ.offset_units; | ||
136 | key->offset_factor = brw->curr.rast->templ.offset_scale; | ||
137 | } | ||
138 | |||
139 | /** | ||
140 | * Setup wm hardware state. See page 225 of Volume 2 | ||
141 | */ | ||
142 | static enum pipe_error | ||
143 | wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, | ||
144 | struct brw_winsys_reloc *reloc, | ||
145 | unsigned nr_reloc, | ||
146 | struct brw_winsys_buffer **bo_out) | ||
147 | { | ||
148 | struct brw_wm_unit_state wm; | ||
149 | enum pipe_error ret; | ||
150 | |||
151 | memset(&wm, 0, sizeof(wm)); | ||
152 | |||
153 | wm.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1; | ||
154 | wm.thread0.kernel_start_pointer = 0; /* reloc */ | ||
155 | wm.thread1.depth_coef_urb_read_offset = 1; | ||
156 | wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; | ||
157 | |||
158 | if (brw->gen == 5) | ||
159 | wm.thread1.binding_table_entry_count = 0; /* hardware requirement */ | ||
160 | else | ||
161 | wm.thread1.binding_table_entry_count = key->nr_surfaces; | ||
162 | |||
163 | if (key->total_scratch != 0) { | ||
164 | wm.thread2.scratch_space_base_pointer = 0; /* reloc */ | ||
165 | wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1; | ||
166 | } else { | ||
167 | wm.thread2.scratch_space_base_pointer = 0; | ||
168 | wm.thread2.per_thread_scratch_space = 0; | ||
169 | } | ||
170 | |||
171 | wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg; | ||
172 | wm.thread3.urb_entry_read_length = key->urb_entry_read_length; | ||
173 | wm.thread3.urb_entry_read_offset = 0; | ||
174 | wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length; | ||
175 | wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; | ||
176 | |||
177 | if (brw->gen == 5) | ||
178 | wm.wm4.sampler_count = 0; /* hardware requirement */ | ||
179 | else | ||
180 | wm.wm4.sampler_count = (key->sampler_count + 1) / 4; | ||
181 | |||
182 | /* reloc */ | ||
183 | wm.wm4.sampler_state_pointer = 0; | ||
184 | |||
185 | wm.wm5.program_uses_depth = key->uses_depth; | ||
186 | wm.wm5.program_computes_depth = key->computes_depth; | ||
187 | wm.wm5.program_uses_killpixel = key->uses_kill; | ||
188 | |||
189 | if (key->has_flow_control) | ||
190 | wm.wm5.enable_8_pix = 1; | ||
191 | else | ||
192 | wm.wm5.enable_16_pix = 1; | ||
193 | |||
194 | wm.wm5.max_threads = key->max_threads - 1; | ||
195 | wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */ | ||
196 | wm.wm5.legacy_line_rast = 0; | ||
197 | wm.wm5.legacy_global_depth_bias = 0; | ||
198 | wm.wm5.early_depth_test = 1; /* never need to disable */ | ||
199 | wm.wm5.line_aa_region_width = 0; | ||
200 | wm.wm5.line_endcap_aa_region_width = 1; | ||
201 | |||
202 | wm.wm5.polygon_stipple = key->polygon_stipple; | ||
203 | |||
204 | if (key->offset_enable) { | ||
205 | wm.wm5.depth_offset = 1; | ||
206 | /* Something wierd going on with legacy_global_depth_bias, | ||
207 | * offset_constant, scaling and MRD. This value passes glean | ||
208 | * but gives some odd results elsewere (eg. the | ||
209 | * quad-offset-units test). | ||
210 | */ | ||
211 | wm.global_depth_offset_constant = key->offset_units * 2; | ||
212 | |||
213 | /* This is the only value that passes glean: | ||
214 | */ | ||
215 | wm.global_depth_offset_scale = key->offset_factor; | ||
216 | } | ||
217 | |||
218 | wm.wm5.line_stipple = key->line_stipple; | ||
219 | |||
220 | if ((BRW_DEBUG & DEBUG_STATS) || key->stats_wm) | ||
221 | wm.wm4.stats_enable = 1; | ||
222 | |||
223 | ret = brw_upload_cache(&brw->cache, BRW_WM_UNIT, | ||
224 | key, sizeof(*key), | ||
225 | reloc, nr_reloc, | ||
226 | &wm, sizeof(wm), | ||
227 | NULL, NULL, | ||
228 | bo_out); | ||
229 | if (ret) | ||
230 | return ret; | ||
231 | |||
232 | return PIPE_OK; | ||
233 | } | ||
234 | |||
235 | |||
236 | static enum pipe_error upload_wm_unit( struct brw_context *brw ) | ||
237 | { | ||
238 | struct brw_wm_unit_key key; | ||
239 | struct brw_winsys_reloc reloc[3]; | ||
240 | unsigned nr_reloc = 0; | ||
241 | enum pipe_error ret; | ||
242 | unsigned grf_reg_count; | ||
243 | unsigned per_thread_scratch_space; | ||
244 | unsigned stats_enable; | ||
245 | unsigned sampler_count; | ||
246 | |||
247 | wm_unit_populate_key(brw, &key); | ||
248 | |||
249 | |||
250 | /* Allocate the necessary scratch space if we haven't already. Don't | ||
251 | * bother reducing the allocation later, since we use scratch so | ||
252 | * rarely. | ||
253 | */ | ||
254 | assert(key.total_scratch <= 12 * 1024); | ||
255 | if (key.total_scratch) { | ||
256 | GLuint total = key.total_scratch * key.max_threads; | ||
257 | |||
258 | /* Do we need a new buffer: | ||
259 | */ | ||
260 | if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) | ||
261 | bo_reference(&brw->wm.scratch_bo, NULL); | ||
262 | |||
263 | if (brw->wm.scratch_bo == NULL) { | ||
264 | ret = brw->sws->bo_alloc(brw->sws, | ||
265 | BRW_BUFFER_TYPE_SHADER_SCRATCH, | ||
266 | total, | ||
267 | 4096, | ||
268 | &brw->wm.scratch_bo); | ||
269 | if (ret) | ||
270 | return ret; | ||
271 | } | ||
272 | } | ||
273 | |||
274 | |||
275 | /* XXX: temporary: | ||
276 | */ | ||
277 | grf_reg_count = (align(key.total_grf, 16) / 16 - 1); | ||
278 | per_thread_scratch_space = key.total_scratch / 1024 - 1; | ||
279 | stats_enable = (BRW_DEBUG & DEBUG_STATS) || key.stats_wm; | ||
280 | sampler_count = brw->gen == 5 ? 0 :(key.sampler_count + 1) / 4; | ||
281 | |||
282 | /* Emit WM program relocation */ | ||
283 | make_reloc(&reloc[nr_reloc++], | ||
284 | BRW_USAGE_STATE, | ||
285 | grf_reg_count << 1, | ||
286 | offsetof(struct brw_wm_unit_state, thread0), | ||
287 | brw->wm.prog_bo); | ||
288 | |||
289 | /* Emit scratch space relocation */ | ||
290 | if (key.total_scratch != 0) { | ||
291 | make_reloc(&reloc[nr_reloc++], | ||
292 | BRW_USAGE_SCRATCH, | ||
293 | per_thread_scratch_space, | ||
294 | offsetof(struct brw_wm_unit_state, thread2), | ||
295 | brw->wm.scratch_bo); | ||
296 | } | ||
297 | |||
298 | /* Emit sampler state relocation */ | ||
299 | if (key.sampler_count != 0) { | ||
300 | make_reloc(&reloc[nr_reloc++], | ||
301 | BRW_USAGE_STATE, | ||
302 | stats_enable | (sampler_count << 2), | ||
303 | offsetof(struct brw_wm_unit_state, wm4), | ||
304 | brw->wm.sampler_bo); | ||
305 | } | ||
306 | |||
307 | |||
308 | if (brw_search_cache(&brw->cache, BRW_WM_UNIT, | ||
309 | &key, sizeof(key), | ||
310 | reloc, nr_reloc, | ||
311 | NULL, | ||
312 | &brw->wm.state_bo)) | ||
313 | return PIPE_OK; | ||
314 | |||
315 | ret = wm_unit_create_from_key(brw, &key, | ||
316 | reloc, nr_reloc, | ||
317 | &brw->wm.state_bo); | ||
318 | if (ret) | ||
319 | return ret; | ||
320 | |||
321 | return PIPE_OK; | ||
322 | } | ||
323 | |||
324 | const struct brw_tracked_state brw_wm_unit = { | ||
325 | .dirty = { | ||
326 | .mesa = (PIPE_NEW_FRAGMENT_SHADER | | ||
327 | PIPE_NEW_DEPTH_BUFFER | | ||
328 | PIPE_NEW_RAST | | ||
329 | PIPE_NEW_DEPTH_STENCIL_ALPHA | | ||
330 | PIPE_NEW_QUERY), | ||
331 | |||
332 | .brw = (BRW_NEW_CURBE_OFFSETS | | ||
333 | BRW_NEW_NR_WM_SURFACES), | ||
334 | |||
335 | .cache = (CACHE_NEW_WM_PROG | | ||
336 | CACHE_NEW_SAMPLER) | ||
337 | }, | ||
338 | .prepare = upload_wm_unit, | ||
339 | }; | ||
340 | |||
diff --git a/src/gallium/drivers/i965/brw_wm_surface_state.c b/src/gallium/drivers/i965/brw_wm_surface_state.c deleted file mode 100644 index 0d80a0114af..00000000000 --- a/src/gallium/drivers/i965/brw_wm_surface_state.c +++ /dev/null | |||
@@ -1,293 +0,0 @@ | |||
1 | /* | ||
2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. | ||
3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
4 | develop this 3D driver. | ||
5 | |||
6 | Permission is hereby granted, free of charge, to any person obtaining | ||
7 | a copy of this software and associated documentation files (the | ||
8 | "Software"), to deal in the Software without restriction, including | ||
9 | without limitation the rights to use, copy, modify, merge, publish, | ||
10 | distribute, sublicense, and/or sell copies of the Software, and to | ||
11 | permit persons to whom the Software is furnished to do so, subject to | ||
12 | the following conditions: | ||
13 | |||
14 | The above copyright notice and this permission notice (including the | ||
15 | next paragraph) shall be included in all copies or substantial | ||
16 | portions of the Software. | ||
17 | |||
18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | ||
21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | |||
26 | **********************************************************************/ | ||
27 | /* | ||
28 | * Authors: | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | */ | ||
31 | |||
32 | #include "pipe/p_format.h" | ||
33 | |||
34 | #include "brw_batchbuffer.h" | ||
35 | #include "brw_context.h" | ||
36 | #include "brw_state.h" | ||
37 | #include "brw_resource.h" | ||
38 | |||
39 | |||
40 | |||
41 | |||
42 | static enum pipe_error | ||
43 | brw_update_texture_surface( struct brw_context *brw, | ||
44 | struct brw_texture *tex, | ||
45 | struct brw_winsys_buffer **bo_out) | ||
46 | { | ||
47 | struct brw_winsys_reloc reloc[1]; | ||
48 | enum pipe_error ret; | ||
49 | |||
50 | /* Emit relocation to surface contents */ | ||
51 | make_reloc(&reloc[0], | ||
52 | BRW_USAGE_SAMPLER, | ||
53 | 0, | ||
54 | offsetof(struct brw_surface_state, ss1), | ||
55 | tex->bo); | ||
56 | |||
57 | if (brw_search_cache(&brw->surface_cache, | ||
58 | BRW_SS_SURFACE, | ||
59 | &tex->ss, sizeof tex->ss, | ||
60 | reloc, Elements(reloc), | ||
61 | NULL, | ||
62 | bo_out)) | ||
63 | return PIPE_OK; | ||
64 | |||
65 | ret = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE, | ||
66 | &tex->ss, sizeof tex->ss, | ||
67 | reloc, Elements(reloc), | ||
68 | &tex->ss, sizeof tex->ss, | ||
69 | NULL, NULL, | ||
70 | bo_out); | ||
71 | if (ret) | ||
72 | return ret; | ||
73 | |||
74 | return PIPE_OK; | ||
75 | } | ||
76 | |||
77 | |||
78 | |||
79 | |||
80 | |||
81 | |||
82 | |||
83 | |||
84 | /** | ||
85 | * Sets up a surface state structure to point at the given region. | ||
86 | * While it is only used for the front/back buffer currently, it should be | ||
87 | * usable for further buffers when doing ARB_draw_buffer support. | ||
88 | */ | ||
89 | static enum pipe_error | ||
90 | brw_update_render_surface(struct brw_context *brw, | ||
91 | struct brw_surface *surface, | ||
92 | struct brw_winsys_buffer **bo_out) | ||
93 | { | ||
94 | struct brw_surf_ss0 blend_ss0 = brw->curr.blend->ss0; | ||
95 | struct brw_surface_state ss; | ||
96 | struct brw_winsys_reloc reloc[1]; | ||
97 | enum pipe_error ret; | ||
98 | |||
99 | /* XXX: we will only be rendering to this surface: | ||
100 | */ | ||
101 | make_reloc(&reloc[0], | ||
102 | BRW_USAGE_RENDER_TARGET, | ||
103 | 0, | ||
104 | offsetof(struct brw_surface_state, ss1), | ||
105 | surface->bo); | ||
106 | |||
107 | /* Surfaces are potentially shared between contexts, so can't | ||
108 | * scribble the in-place ss0 value in the surface. | ||
109 | */ | ||
110 | memcpy(&ss, &surface->ss, sizeof ss); | ||
111 | |||
112 | ss.ss0.color_blend = blend_ss0.color_blend; | ||
113 | ss.ss0.writedisable_blue = blend_ss0.writedisable_blue; | ||
114 | ss.ss0.writedisable_green = blend_ss0.writedisable_green; | ||
115 | ss.ss0.writedisable_red = blend_ss0.writedisable_red; | ||
116 | ss.ss0.writedisable_alpha = blend_ss0.writedisable_alpha; | ||
117 | |||
118 | if (brw_search_cache(&brw->surface_cache, | ||
119 | BRW_SS_SURFACE, | ||
120 | &ss, sizeof(ss), | ||
121 | reloc, Elements(reloc), | ||
122 | NULL, | ||
123 | bo_out)) | ||
124 | return PIPE_OK; | ||
125 | |||
126 | ret = brw_upload_cache(&brw->surface_cache, | ||
127 | BRW_SS_SURFACE, | ||
128 | &ss, sizeof ss, | ||
129 | reloc, Elements(reloc), | ||
130 | &ss, sizeof ss, | ||
131 | NULL, NULL, | ||
132 | bo_out); | ||
133 | if (ret) | ||
134 | return ret; | ||
135 | |||
136 | return PIPE_OK; | ||
137 | } | ||
138 | |||
139 | |||
140 | /** | ||
141 | * Constructs the binding table for the WM surface state, which maps unit | ||
142 | * numbers to surface state objects. | ||
143 | */ | ||
144 | static enum pipe_error | ||
145 | brw_wm_get_binding_table(struct brw_context *brw, | ||
146 | struct brw_winsys_buffer **bo_out ) | ||
147 | { | ||
148 | enum pipe_error ret; | ||
149 | struct brw_winsys_reloc reloc[BRW_WM_MAX_SURF]; | ||
150 | uint32_t data[BRW_WM_MAX_SURF]; | ||
151 | GLuint nr_relocs = 0; | ||
152 | GLuint data_size = brw->wm.nr_surfaces * sizeof data[0]; | ||
153 | int i; | ||
154 | |||
155 | assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF); | ||
156 | assert(brw->wm.nr_surfaces > 0); | ||
157 | |||
158 | /* Emit binding table relocations to surface state | ||
159 | */ | ||
160 | for (i = 0; i < brw->wm.nr_surfaces; i++) { | ||
161 | if (brw->wm.surf_bo[i]) { | ||
162 | make_reloc(&reloc[nr_relocs++], | ||
163 | BRW_USAGE_STATE, | ||
164 | 0, | ||
165 | i * sizeof(GLuint), | ||
166 | brw->wm.surf_bo[i]); | ||
167 | } | ||
168 | } | ||
169 | |||
170 | /* Note there is no key for this search beyond the values in the | ||
171 | * relocation array: | ||
172 | */ | ||
173 | if (brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND, | ||
174 | NULL, 0, | ||
175 | reloc, nr_relocs, | ||
176 | NULL, | ||
177 | bo_out)) | ||
178 | return PIPE_OK; | ||
179 | |||
180 | /* Upload zero data, will all be overwitten with relocation | ||
181 | * offsets: | ||
182 | */ | ||
183 | for (i = 0; i < brw->wm.nr_surfaces; i++) | ||
184 | data[i] = 0; | ||
185 | |||
186 | ret = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND, | ||
187 | NULL, 0, | ||
188 | reloc, nr_relocs, | ||
189 | data, data_size, | ||
190 | NULL, NULL, | ||
191 | bo_out); | ||
192 | if (ret) | ||
193 | return ret; | ||
194 | |||
195 | return PIPE_OK; | ||
196 | } | ||
197 | |||
198 | static enum pipe_error prepare_wm_surfaces(struct brw_context *brw ) | ||
199 | { | ||
200 | enum pipe_error ret; | ||
201 | int nr_surfaces = 0; | ||
202 | GLuint i; | ||
203 | |||
204 | /* PIPE_NEW_COLOR_BUFFERS | PIPE_NEW_BLEND | ||
205 | * | ||
206 | * Update surfaces for drawing buffers. Mixes in colormask and | ||
207 | * blend state. | ||
208 | * | ||
209 | * XXX: no color buffer case | ||
210 | */ | ||
211 | for (i = 0; i < brw->curr.fb.nr_cbufs; i++) { | ||
212 | ret = brw_update_render_surface(brw, | ||
213 | brw_surface(brw->curr.fb.cbufs[i]), | ||
214 | &brw->wm.surf_bo[BTI_COLOR_BUF(i)]); | ||
215 | if (ret) | ||
216 | return ret; | ||
217 | |||
218 | nr_surfaces = BTI_COLOR_BUF(i) + 1; | ||
219 | } | ||
220 | |||
221 | |||
222 | |||
223 | /* PIPE_NEW_FRAGMENT_CONSTANTS | ||
224 | */ | ||
225 | #if 0 | ||
226 | if (brw->curr.fragment_constants) { | ||
227 | ret = brw_update_fragment_constant_surface( | ||
228 | brw, | ||
229 | brw->curr.fragment_constants, | ||
230 | &brw->wm.surf_bo[BTI_FRAGMENT_CONSTANTS]); | ||
231 | |||
232 | if (ret) | ||
233 | return ret; | ||
234 | |||
235 | nr_surfaces = BTI_FRAGMENT_CONSTANTS + 1; | ||
236 | } | ||
237 | else { | ||
238 | bo_reference(&brw->wm.surf_bo[SURF_FRAG_CONSTANTS], NULL); | ||
239 | } | ||
240 | #endif | ||
241 | |||
242 | |||
243 | /* PIPE_NEW_TEXTURE | ||
244 | */ | ||
245 | for (i = 0; i < brw->curr.num_fragment_sampler_views; i++) { | ||
246 | ret = brw_update_texture_surface(brw, | ||
247 | brw_texture(brw->curr.fragment_sampler_views[i]->texture), | ||
248 | &brw->wm.surf_bo[BTI_TEXTURE(i)]); | ||
249 | if (ret) | ||
250 | return ret; | ||
251 | |||
252 | nr_surfaces = BTI_TEXTURE(i) + 1; | ||
253 | } | ||
254 | |||
255 | /* Clear any inactive entries: | ||
256 | */ | ||
257 | for (i = brw->curr.fb.nr_cbufs; i < BRW_MAX_DRAW_BUFFERS; i++) | ||
258 | bo_reference(&brw->wm.surf_bo[BTI_COLOR_BUF(i)], NULL); | ||
259 | |||
260 | if (!brw->curr.fragment_constants) | ||
261 | bo_reference(&brw->wm.surf_bo[BTI_FRAGMENT_CONSTANTS], NULL); | ||
262 | |||
263 | /* XXX: no pipe_max_textures define?? */ | ||
264 | for (i = brw->curr.num_fragment_sampler_views; i < PIPE_MAX_SAMPLERS; i++) | ||
265 | bo_reference(&brw->wm.surf_bo[BTI_TEXTURE(i)], NULL); | ||
266 | |||
267 | if (brw->wm.nr_surfaces != nr_surfaces) { | ||
268 | brw->wm.nr_surfaces = nr_surfaces; | ||
269 | brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES; | ||
270 | } | ||
271 | |||
272 | ret = brw_wm_get_binding_table(brw, &brw->wm.bind_bo); | ||
273 | if (ret) | ||
274 | return ret; | ||
275 | |||
276 | return PIPE_OK; | ||
277 | } | ||
278 | |||
279 | const struct brw_tracked_state brw_wm_surfaces = { | ||
280 | .dirty = { | ||
281 | .mesa = (PIPE_NEW_COLOR_BUFFERS | | ||
282 | PIPE_NEW_BOUND_TEXTURES | | ||
283 | PIPE_NEW_FRAGMENT_CONSTANTS | | ||
284 | PIPE_NEW_BLEND), | ||
285 | .brw = (BRW_NEW_CONTEXT | | ||
286 | BRW_NEW_WM_SURFACES), | ||
287 | .cache = 0 | ||
288 | }, | ||
289 | .prepare = prepare_wm_surfaces, | ||
290 | }; | ||
291 | |||
292 | |||
293 | |||
diff --git a/src/gallium/drivers/i965/intel_decode.c b/src/gallium/drivers/i965/intel_decode.c deleted file mode 100644 index 1abe869f1ae..00000000000 --- a/src/gallium/drivers/i965/intel_decode.c +++ /dev/null | |||
@@ -1,2078 +0,0 @@ | |||
1 | /* -*- c-basic-offset: 4 -*- */ | ||
2 | /* | ||
3 | * Copyright © 2007 Intel Corporation | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the "Software"), | ||
7 | * to deal in the Software without restriction, including without limitation | ||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
9 | * and/or sell copies of the Software, and to permit persons to whom the | ||
10 | * Software is furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice (including the next | ||
13 | * paragraph) shall be included in all copies or substantial portions of the | ||
14 | * Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
22 | * IN THE SOFTWARE. | ||
23 | * | ||
24 | * Authors: | ||
25 | * Eric Anholt <eric@anholt.net> | ||
26 | * | ||
27 | */ | ||
28 | |||
29 | /** @file intel_decode.c | ||
30 | * This file contains code to print out batchbuffer contents in a | ||
31 | * human-readable format. | ||
32 | * | ||
33 | * The current version only supports i915 packets, and only pretty-prints a | ||
34 | * subset of them. The intention is for it to make just a best attempt to | ||
35 | * decode, but never crash in the process. | ||
36 | */ | ||
37 | |||
38 | #include <stdio.h> | ||
39 | #include <stdarg.h> | ||
40 | #include <stdint.h> | ||
41 | #include <string.h> | ||
42 | |||
43 | #include "util/u_memory.h" | ||
44 | #include "util/u_string.h" | ||
45 | |||
46 | #include "intel_decode.h" | ||
47 | #include "brw_reg.h" | ||
48 | |||
49 | /*#include "intel_chipset.h"*/ | ||
50 | #define IS_9XX(x) 1 /* XXX */ | ||
51 | |||
52 | #define BUFFER_FAIL(_count, _len, _name) do { \ | ||
53 | fprintf(out, "Buffer size too small in %s (%d < %d)\n", \ | ||
54 | (_name), (_count), (_len)); \ | ||
55 | (*failures)++; \ | ||
56 | return count; \ | ||
57 | } while (0) | ||
58 | |||
59 | static FILE *out; | ||
60 | static uint32_t saved_s2 = 0, saved_s4 = 0; | ||
61 | static char saved_s2_set = 0, saved_s4_set = 0; | ||
62 | |||
63 | static float | ||
64 | int_as_float(uint32_t intval) | ||
65 | { | ||
66 | union intfloat { | ||
67 | uint32_t i; | ||
68 | float f; | ||
69 | } uval; | ||
70 | |||
71 | uval.i = intval; | ||
72 | return uval.f; | ||
73 | } | ||
74 | |||
75 | static void | ||
76 | instr_out(const uint32_t *data, uint32_t hw_offset, unsigned int index, | ||
77 | char *fmt, ...) | ||
78 | { | ||
79 | va_list va; | ||
80 | |||
81 | fprintf(out, "0x%08x: 0x%08x:%s ", hw_offset + index * 4, data[index], | ||
82 | index == 0 ? "" : " "); | ||
83 | va_start(va, fmt); | ||
84 | vfprintf(out, fmt, va); | ||
85 | va_end(va); | ||
86 | } | ||
87 | |||
88 | |||
89 | static int | ||
90 | decode_mi(const uint32_t *data, int count, uint32_t hw_offset, int *failures) | ||
91 | { | ||
92 | unsigned int opcode; | ||
93 | |||
94 | struct { | ||
95 | uint32_t opcode; | ||
96 | int len_mask; | ||
97 | int min_len; | ||
98 | int max_len; | ||
99 | char *name; | ||
100 | } opcodes_mi[] = { | ||
101 | { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" }, | ||
102 | { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" }, | ||
103 | { 0x30, 0x3f, 3, 3, "MI_BATCH_BUFFER" }, | ||
104 | { 0x31, 0x3f, 2, 2, "MI_BATCH_BUFFER_START" }, | ||
105 | { 0x14, 0x3f, 3, 3, "MI_DISPLAY_BUFFER_INFO" }, | ||
106 | { 0x04, 0, 1, 1, "MI_FLUSH" }, | ||
107 | { 0x22, 0x1f, 3, 3, "MI_LOAD_REGISTER_IMM" }, | ||
108 | { 0x13, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" }, | ||
109 | { 0x12, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_INCL" }, | ||
110 | { 0x00, 0, 1, 1, "MI_NOOP" }, | ||
111 | { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" }, | ||
112 | { 0x07, 0, 1, 1, "MI_REPORT_HEAD" }, | ||
113 | { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" }, | ||
114 | { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" }, | ||
115 | { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" }, | ||
116 | { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" }, | ||
117 | { 0x02, 0, 1, 1, "MI_USER_INTERRUPT" }, | ||
118 | { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" }, | ||
119 | }; | ||
120 | |||
121 | switch ((data[0] & 0x1f800000) >> 23) { | ||
122 | case 0x0a: | ||
123 | instr_out(data, hw_offset, 0, "MI_BATCH_BUFFER_END\n"); | ||
124 | return -1; | ||
125 | } | ||
126 | |||
127 | for (opcode = 0; opcode < Elements(opcodes_mi); opcode++) { | ||
128 | if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { | ||
129 | unsigned int len = 1, i; | ||
130 | |||
131 | instr_out(data, hw_offset, 0, "%s\n", opcodes_mi[opcode].name); | ||
132 | if (opcodes_mi[opcode].max_len > 1) { | ||
133 | len = (data[0] & opcodes_mi[opcode].len_mask) + 2; | ||
134 | if (len < opcodes_mi[opcode].min_len || | ||
135 | len > opcodes_mi[opcode].max_len) | ||
136 | { | ||
137 | fprintf(out, "Bad length (%d) in %s, [%d, %d]\n", | ||
138 | len, opcodes_mi[opcode].name, | ||
139 | opcodes_mi[opcode].min_len, | ||
140 | opcodes_mi[opcode].max_len); | ||
141 | } | ||
142 | } | ||
143 | |||
144 | for (i = 1; i < len; i++) { | ||
145 | if (i >= count) | ||
146 | BUFFER_FAIL(count, len, opcodes_mi[opcode].name); | ||
147 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
148 | } | ||
149 | |||
150 | return len; | ||
151 | } | ||
152 | } | ||
153 | |||
154 | instr_out(data, hw_offset, 0, "MI UNKNOWN\n"); | ||
155 | (*failures)++; | ||
156 | return 1; | ||
157 | } | ||
158 | |||
159 | static int | ||
160 | decode_2d(const uint32_t *data, int count, uint32_t hw_offset, int *failures) | ||
161 | { | ||
162 | unsigned int opcode, len; | ||
163 | char *format = NULL; | ||
164 | |||
165 | struct { | ||
166 | uint32_t opcode; | ||
167 | int min_len; | ||
168 | int max_len; | ||
169 | char *name; | ||
170 | } opcodes_2d[] = { | ||
171 | { 0x40, 5, 5, "COLOR_BLT" }, | ||
172 | { 0x43, 6, 6, "SRC_COPY_BLT" }, | ||
173 | { 0x01, 8, 8, "XY_SETUP_BLT" }, | ||
174 | { 0x11, 9, 9, "XY_SETUP_MONO_PATTERN_SL_BLT" }, | ||
175 | { 0x03, 3, 3, "XY_SETUP_CLIP_BLT" }, | ||
176 | { 0x24, 2, 2, "XY_PIXEL_BLT" }, | ||
177 | { 0x25, 3, 3, "XY_SCANLINES_BLT" }, | ||
178 | { 0x26, 4, 4, "Y_TEXT_BLT" }, | ||
179 | { 0x31, 5, 134, "XY_TEXT_IMMEDIATE_BLT" }, | ||
180 | { 0x50, 6, 6, "XY_COLOR_BLT" }, | ||
181 | { 0x51, 6, 6, "XY_PAT_BLT" }, | ||
182 | { 0x76, 8, 8, "XY_PAT_CHROMA_BLT" }, | ||
183 | { 0x72, 7, 135, "XY_PAT_BLT_IMMEDIATE" }, | ||
184 | { 0x77, 9, 137, "XY_PAT_CHROMA_BLT_IMMEDIATE" }, | ||
185 | { 0x52, 9, 9, "XY_MONO_PAT_BLT" }, | ||
186 | { 0x59, 7, 7, "XY_MONO_PAT_FIXED_BLT" }, | ||
187 | { 0x53, 8, 8, "XY_SRC_COPY_BLT" }, | ||
188 | { 0x54, 8, 8, "XY_MONO_SRC_COPY_BLT" }, | ||
189 | { 0x71, 9, 137, "XY_MONO_SRC_COPY_IMMEDIATE_BLT" }, | ||
190 | { 0x55, 9, 9, "XY_FULL_BLT" }, | ||
191 | { 0x55, 9, 137, "XY_FULL_IMMEDIATE_PATTERN_BLT" }, | ||
192 | { 0x56, 9, 9, "XY_FULL_MONO_SRC_BLT" }, | ||
193 | { 0x75, 10, 138, "XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT" }, | ||
194 | { 0x57, 12, 12, "XY_FULL_MONO_PATTERN_BLT" }, | ||
195 | { 0x58, 12, 12, "XY_FULL_MONO_PATTERN_MONO_SRC_BLT" }, | ||
196 | }; | ||
197 | |||
198 | switch ((data[0] & 0x1fc00000) >> 22) { | ||
199 | case 0x50: | ||
200 | instr_out(data, hw_offset, 0, | ||
201 | "XY_COLOR_BLT (rgb %sabled, alpha %sabled, dst tile %d)\n", | ||
202 | (data[0] & (1 << 20)) ? "en" : "dis", | ||
203 | (data[0] & (1 << 21)) ? "en" : "dis", | ||
204 | (data[0] >> 11) & 1); | ||
205 | |||
206 | len = (data[0] & 0x000000ff) + 2; | ||
207 | if (len != 6) | ||
208 | fprintf(out, "Bad count in XY_COLOR_BLT\n"); | ||
209 | if (count < 6) | ||
210 | BUFFER_FAIL(count, len, "XY_COLOR_BLT"); | ||
211 | |||
212 | switch ((data[1] >> 24) & 0x3) { | ||
213 | case 0: | ||
214 | format="8"; | ||
215 | break; | ||
216 | case 1: | ||
217 | format="565"; | ||
218 | break; | ||
219 | case 2: | ||
220 | format="1555"; | ||
221 | break; | ||
222 | case 3: | ||
223 | format="8888"; | ||
224 | break; | ||
225 | } | ||
226 | |||
227 | instr_out(data, hw_offset, 1, "format %s, pitch %d, " | ||
228 | "clipping %sabled\n", format, | ||
229 | (short)(data[1] & 0xffff), | ||
230 | data[1] & (1 << 30) ? "en" : "dis"); | ||
231 | instr_out(data, hw_offset, 2, "(%d,%d)\n", | ||
232 | data[2] & 0xffff, data[2] >> 16); | ||
233 | instr_out(data, hw_offset, 3, "(%d,%d)\n", | ||
234 | data[3] & 0xffff, data[3] >> 16); | ||
235 | instr_out(data, hw_offset, 4, "offset 0x%08x\n", data[4]); | ||
236 | instr_out(data, hw_offset, 5, "color\n"); | ||
237 | return len; | ||
238 | case 0x53: | ||
239 | instr_out(data, hw_offset, 0, | ||
240 | "XY_SRC_COPY_BLT (rgb %sabled, alpha %sabled, " | ||
241 | "src tile %d, dst tile %d)\n", | ||
242 | (data[0] & (1 << 20)) ? "en" : "dis", | ||
243 | (data[0] & (1 << 21)) ? "en" : "dis", | ||
244 | (data[0] >> 15) & 1, | ||
245 | (data[0] >> 11) & 1); | ||
246 | |||
247 | len = (data[0] & 0x000000ff) + 2; | ||
248 | if (len != 8) | ||
249 | fprintf(out, "Bad count in XY_SRC_COPY_BLT\n"); | ||
250 | if (count < 8) | ||
251 | BUFFER_FAIL(count, len, "XY_SRC_COPY_BLT"); | ||
252 | |||
253 | switch ((data[1] >> 24) & 0x3) { | ||
254 | case 0: | ||
255 | format="8"; | ||
256 | break; | ||
257 | case 1: | ||
258 | format="565"; | ||
259 | break; | ||
260 | case 2: | ||
261 | format="1555"; | ||
262 | break; | ||
263 | case 3: | ||
264 | format="8888"; | ||
265 | break; | ||
266 | } | ||
267 | |||
268 | instr_out(data, hw_offset, 1, "format %s, dst pitch %d, " | ||
269 | "clipping %sabled\n", format, | ||
270 | (short)(data[1] & 0xffff), | ||
271 | data[1] & (1 << 30) ? "en" : "dis"); | ||
272 | instr_out(data, hw_offset, 2, "dst (%d,%d)\n", | ||
273 | data[2] & 0xffff, data[2] >> 16); | ||
274 | instr_out(data, hw_offset, 3, "dst (%d,%d)\n", | ||
275 | data[3] & 0xffff, data[3] >> 16); | ||
276 | instr_out(data, hw_offset, 4, "dst offset 0x%08x\n", data[4]); | ||
277 | instr_out(data, hw_offset, 5, "src (%d,%d)\n", | ||
278 | data[5] & 0xffff, data[5] >> 16); | ||
279 | instr_out(data, hw_offset, 6, "src pitch %d\n", | ||
280 | (short)(data[6] & 0xffff)); | ||
281 | instr_out(data, hw_offset, 7, "src offset 0x%08x\n", data[7]); | ||
282 | return len; | ||
283 | } | ||
284 | |||
285 | for (opcode = 0; opcode < Elements(opcodes_2d); opcode++) { | ||
286 | if ((data[0] & 0x1fc00000) >> 22 == opcodes_2d[opcode].opcode) { | ||
287 | unsigned int i; | ||
288 | |||
289 | len = 1; | ||
290 | instr_out(data, hw_offset, 0, "%s\n", opcodes_2d[opcode].name); | ||
291 | if (opcodes_2d[opcode].max_len > 1) { | ||
292 | len = (data[0] & 0x000000ff) + 2; | ||
293 | if (len < opcodes_2d[opcode].min_len || | ||
294 | len > opcodes_2d[opcode].max_len) | ||
295 | { | ||
296 | fprintf(out, "Bad count in %s\n", opcodes_2d[opcode].name); | ||
297 | } | ||
298 | } | ||
299 | |||
300 | for (i = 1; i < len; i++) { | ||
301 | if (i >= count) | ||
302 | BUFFER_FAIL(count, len, opcodes_2d[opcode].name); | ||
303 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
304 | } | ||
305 | |||
306 | return len; | ||
307 | } | ||
308 | } | ||
309 | |||
310 | instr_out(data, hw_offset, 0, "2D UNKNOWN\n"); | ||
311 | (*failures)++; | ||
312 | return 1; | ||
313 | } | ||
314 | |||
315 | static int | ||
316 | decode_3d_1c(const uint32_t *data, int count, uint32_t hw_offset, int *failures) | ||
317 | { | ||
318 | uint32_t opcode; | ||
319 | |||
320 | opcode = (data[0] & 0x00f80000) >> 19; | ||
321 | |||
322 | switch (opcode) { | ||
323 | case 0x11: | ||
324 | instr_out(data, hw_offset, 0, "3DSTATE_DEPTH_SUBRECTANGLE_DISABLE\n"); | ||
325 | return 1; | ||
326 | case 0x10: | ||
327 | instr_out(data, hw_offset, 0, "3DSTATE_SCISSOR_ENABLE\n"); | ||
328 | return 1; | ||
329 | case 0x01: | ||
330 | instr_out(data, hw_offset, 0, "3DSTATE_MAP_COORD_SET_I830\n"); | ||
331 | return 1; | ||
332 | case 0x0a: | ||
333 | instr_out(data, hw_offset, 0, "3DSTATE_MAP_CUBE_I830\n"); | ||
334 | return 1; | ||
335 | case 0x05: | ||
336 | instr_out(data, hw_offset, 0, "3DSTATE_MAP_TEX_STREAM_I830\n"); | ||
337 | return 1; | ||
338 | } | ||
339 | |||
340 | instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_1c opcode = 0x%x\n", | ||
341 | opcode); | ||
342 | (*failures)++; | ||
343 | return 1; | ||
344 | } | ||
345 | |||
346 | /** Sets the string dstname to describe the destination of the PS instruction */ | ||
347 | static void | ||
348 | i915_get_instruction_dst(const uint32_t *data, int i, char *dstname, int do_mask) | ||
349 | { | ||
350 | uint32_t a0 = data[i]; | ||
351 | int dst_nr = (a0 >> 14) & 0xf; | ||
352 | char dstmask[8]; | ||
353 | char *sat; | ||
354 | |||
355 | if (do_mask) { | ||
356 | if (((a0 >> 10) & 0xf) == 0xf) { | ||
357 | dstmask[0] = 0; | ||
358 | } else { | ||
359 | int dstmask_index = 0; | ||
360 | |||
361 | dstmask[dstmask_index++] = '.'; | ||
362 | if (a0 & (1 << 10)) | ||
363 | dstmask[dstmask_index++] = 'x'; | ||
364 | if (a0 & (1 << 11)) | ||
365 | dstmask[dstmask_index++] = 'y'; | ||
366 | if (a0 & (1 << 12)) | ||
367 | dstmask[dstmask_index++] = 'z'; | ||
368 | if (a0 & (1 << 13)) | ||
369 | dstmask[dstmask_index++] = 'w'; | ||
370 | dstmask[dstmask_index++] = 0; | ||
371 | } | ||
372 | |||
373 | if (a0 & (1 << 22)) | ||
374 | sat = ".sat"; | ||
375 | else | ||
376 | sat = ""; | ||
377 | } else { | ||
378 | dstmask[0] = 0; | ||
379 | sat = ""; | ||
380 | } | ||
381 | |||
382 | switch ((a0 >> 19) & 0x7) { | ||
383 | case 0: | ||
384 | if (dst_nr > 15) | ||
385 | fprintf(out, "bad destination reg R%d\n", dst_nr); | ||
386 | sprintf(dstname, "R%d%s%s", dst_nr, dstmask, sat); | ||
387 | break; | ||
388 | case 4: | ||
389 | if (dst_nr > 0) | ||
390 | fprintf(out, "bad destination reg oC%d\n", dst_nr); | ||
391 | sprintf(dstname, "oC%s%s", dstmask, sat); | ||
392 | break; | ||
393 | case 5: | ||
394 | if (dst_nr > 0) | ||
395 | fprintf(out, "bad destination reg oD%d\n", dst_nr); | ||
396 | sprintf(dstname, "oD%s%s", dstmask, sat); | ||
397 | break; | ||
398 | case 6: | ||
399 | if (dst_nr > 3) | ||
400 | fprintf(out, "bad destination reg U%d\n", dst_nr); | ||
401 | sprintf(dstname, "U%d%s%s", dst_nr, dstmask, sat); | ||
402 | break; | ||
403 | default: | ||
404 | sprintf(dstname, "RESERVED"); | ||
405 | break; | ||
406 | } | ||
407 | } | ||
408 | |||
409 | static char * | ||
410 | i915_get_channel_swizzle(uint32_t select) | ||
411 | { | ||
412 | switch (select & 0x7) { | ||
413 | case 0: | ||
414 | return (select & 8) ? "-x" : "x"; | ||
415 | case 1: | ||
416 | return (select & 8) ? "-y" : "y"; | ||
417 | case 2: | ||
418 | return (select & 8) ? "-z" : "z"; | ||
419 | case 3: | ||
420 | return (select & 8) ? "-w" : "w"; | ||
421 | case 4: | ||
422 | return (select & 8) ? "-0" : "0"; | ||
423 | case 5: | ||
424 | return (select & 8) ? "-1" : "1"; | ||
425 | default: | ||
426 | return (select & 8) ? "-bad" : "bad"; | ||
427 | } | ||
428 | } | ||
429 | |||
430 | static void | ||
431 | i915_get_instruction_src_name(uint32_t src_type, uint32_t src_nr, char *name) | ||
432 | { | ||
433 | switch (src_type) { | ||
434 | case 0: | ||
435 | sprintf(name, "R%d", src_nr); | ||
436 | if (src_nr > 15) | ||
437 | fprintf(out, "bad src reg %s\n", name); | ||
438 | break; | ||
439 | case 1: | ||
440 | if (src_nr < 8) | ||
441 | sprintf(name, "T%d", src_nr); | ||
442 | else if (src_nr == 8) | ||
443 | sprintf(name, "DIFFUSE"); | ||
444 | else if (src_nr == 9) | ||
445 | sprintf(name, "SPECULAR"); | ||
446 | else if (src_nr == 10) | ||
447 | sprintf(name, "FOG"); | ||
448 | else { | ||
449 | fprintf(out, "bad src reg T%d\n", src_nr); | ||
450 | sprintf(name, "RESERVED"); | ||
451 | } | ||
452 | break; | ||
453 | case 2: | ||
454 | sprintf(name, "C%d", src_nr); | ||
455 | if (src_nr > 31) | ||
456 | fprintf(out, "bad src reg %s\n", name); | ||
457 | break; | ||
458 | case 4: | ||
459 | sprintf(name, "oC"); | ||
460 | if (src_nr > 0) | ||
461 | fprintf(out, "bad src reg oC%d\n", src_nr); | ||
462 | break; | ||
463 | case 5: | ||
464 | sprintf(name, "oD"); | ||
465 | if (src_nr > 0) | ||
466 | fprintf(out, "bad src reg oD%d\n", src_nr); | ||
467 | break; | ||
468 | case 6: | ||
469 | sprintf(name, "U%d", src_nr); | ||
470 | if (src_nr > 3) | ||
471 | fprintf(out, "bad src reg %s\n", name); | ||
472 | break; | ||
473 | default: | ||
474 | fprintf(out, "bad src reg type %d\n", src_type); | ||
475 | sprintf(name, "RESERVED"); | ||
476 | break; | ||
477 | } | ||
478 | } | ||
479 | |||
480 | static void | ||
481 | i915_get_instruction_src0(const uint32_t *data, int i, char *srcname) | ||
482 | { | ||
483 | uint32_t a0 = data[i]; | ||
484 | uint32_t a1 = data[i + 1]; | ||
485 | int src_nr = (a0 >> 2) & 0x1f; | ||
486 | char *swizzle_x = i915_get_channel_swizzle((a1 >> 28) & 0xf); | ||
487 | char *swizzle_y = i915_get_channel_swizzle((a1 >> 24) & 0xf); | ||
488 | char *swizzle_z = i915_get_channel_swizzle((a1 >> 20) & 0xf); | ||
489 | char *swizzle_w = i915_get_channel_swizzle((a1 >> 16) & 0xf); | ||
490 | char swizzle[100]; | ||
491 | |||
492 | i915_get_instruction_src_name((a0 >> 7) & 0x7, src_nr, srcname); | ||
493 | util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); | ||
494 | if (strcmp(swizzle, ".xyzw") != 0) | ||
495 | strcat(srcname, swizzle); | ||
496 | } | ||
497 | |||
498 | static void | ||
499 | i915_get_instruction_src1(const uint32_t *data, int i, char *srcname) | ||
500 | { | ||
501 | uint32_t a1 = data[i + 1]; | ||
502 | uint32_t a2 = data[i + 2]; | ||
503 | int src_nr = (a1 >> 8) & 0x1f; | ||
504 | char *swizzle_x = i915_get_channel_swizzle((a1 >> 4) & 0xf); | ||
505 | char *swizzle_y = i915_get_channel_swizzle((a1 >> 0) & 0xf); | ||
506 | char *swizzle_z = i915_get_channel_swizzle((a2 >> 28) & 0xf); | ||
507 | char *swizzle_w = i915_get_channel_swizzle((a2 >> 24) & 0xf); | ||
508 | char swizzle[100]; | ||
509 | |||
510 | i915_get_instruction_src_name((a1 >> 13) & 0x7, src_nr, srcname); | ||
511 | util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); | ||
512 | if (strcmp(swizzle, ".xyzw") != 0) | ||
513 | strcat(srcname, swizzle); | ||
514 | } | ||
515 | |||
516 | static void | ||
517 | i915_get_instruction_src2(const uint32_t *data, int i, char *srcname) | ||
518 | { | ||
519 | uint32_t a2 = data[i + 2]; | ||
520 | int src_nr = (a2 >> 16) & 0x1f; | ||
521 | char *swizzle_x = i915_get_channel_swizzle((a2 >> 12) & 0xf); | ||
522 | char *swizzle_y = i915_get_channel_swizzle((a2 >> 8) & 0xf); | ||
523 | char *swizzle_z = i915_get_channel_swizzle((a2 >> 4) & 0xf); | ||
524 | char *swizzle_w = i915_get_channel_swizzle((a2 >> 0) & 0xf); | ||
525 | char swizzle[100]; | ||
526 | |||
527 | i915_get_instruction_src_name((a2 >> 21) & 0x7, src_nr, srcname); | ||
528 | util_snprintf(swizzle, sizeof(swizzle), ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, swizzle_w); | ||
529 | if (strcmp(swizzle, ".xyzw") != 0) | ||
530 | strcat(srcname, swizzle); | ||
531 | } | ||
532 | |||
533 | static void | ||
534 | i915_get_instruction_addr(uint32_t src_type, uint32_t src_nr, char *name) | ||
535 | { | ||
536 | switch (src_type) { | ||
537 | case 0: | ||
538 | sprintf(name, "R%d", src_nr); | ||
539 | if (src_nr > 15) | ||
540 | fprintf(out, "bad src reg %s\n", name); | ||
541 | break; | ||
542 | case 1: | ||
543 | if (src_nr < 8) | ||
544 | sprintf(name, "T%d", src_nr); | ||
545 | else if (src_nr == 8) | ||
546 | sprintf(name, "DIFFUSE"); | ||
547 | else if (src_nr == 9) | ||
548 | sprintf(name, "SPECULAR"); | ||
549 | else if (src_nr == 10) | ||
550 | sprintf(name, "FOG"); | ||
551 | else { | ||
552 | fprintf(out, "bad src reg T%d\n", src_nr); | ||
553 | sprintf(name, "RESERVED"); | ||
554 | } | ||
555 | break; | ||
556 | case 4: | ||
557 | sprintf(name, "oC"); | ||
558 | if (src_nr > 0) | ||
559 | fprintf(out, "bad src reg oC%d\n", src_nr); | ||
560 | break; | ||
561 | case 5: | ||
562 | sprintf(name, "oD"); | ||
563 | if (src_nr > 0) | ||
564 | fprintf(out, "bad src reg oD%d\n", src_nr); | ||
565 | break; | ||
566 | default: | ||
567 | fprintf(out, "bad src reg type %d\n", src_type); | ||
568 | sprintf(name, "RESERVED"); | ||
569 | break; | ||
570 | } | ||
571 | } | ||
572 | |||
573 | static void | ||
574 | i915_decode_alu1(const uint32_t *data, uint32_t hw_offset, | ||
575 | int i, char *instr_prefix, char *op_name) | ||
576 | { | ||
577 | char dst[100], src0[100]; | ||
578 | |||
579 | i915_get_instruction_dst(data, i, dst, 1); | ||
580 | i915_get_instruction_src0(data, i, src0); | ||
581 | |||
582 | instr_out(data, hw_offset, i++, "%s: %s %s, %s\n", instr_prefix, | ||
583 | op_name, dst, src0); | ||
584 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
585 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
586 | } | ||
587 | |||
588 | static void | ||
589 | i915_decode_alu2(const uint32_t *data, uint32_t hw_offset, | ||
590 | int i, char *instr_prefix, char *op_name) | ||
591 | { | ||
592 | char dst[100], src0[100], src1[100]; | ||
593 | |||
594 | i915_get_instruction_dst(data, i, dst, 1); | ||
595 | i915_get_instruction_src0(data, i, src0); | ||
596 | i915_get_instruction_src1(data, i, src1); | ||
597 | |||
598 | instr_out(data, hw_offset, i++, "%s: %s %s, %s, %s\n", instr_prefix, | ||
599 | op_name, dst, src0, src1); | ||
600 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
601 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
602 | } | ||
603 | |||
604 | static void | ||
605 | i915_decode_alu3(const uint32_t *data, uint32_t hw_offset, | ||
606 | int i, char *instr_prefix, char *op_name) | ||
607 | { | ||
608 | char dst[100], src0[100], src1[100], src2[100]; | ||
609 | |||
610 | i915_get_instruction_dst(data, i, dst, 1); | ||
611 | i915_get_instruction_src0(data, i, src0); | ||
612 | i915_get_instruction_src1(data, i, src1); | ||
613 | i915_get_instruction_src2(data, i, src2); | ||
614 | |||
615 | instr_out(data, hw_offset, i++, "%s: %s %s, %s, %s, %s\n", instr_prefix, | ||
616 | op_name, dst, src0, src1, src2); | ||
617 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
618 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
619 | } | ||
620 | |||
621 | static void | ||
622 | i915_decode_tex(const uint32_t *data, uint32_t hw_offset, int i, char *instr_prefix, | ||
623 | char *tex_name) | ||
624 | { | ||
625 | uint32_t t0 = data[i]; | ||
626 | uint32_t t1 = data[i + 1]; | ||
627 | char dst_name[100]; | ||
628 | char addr_name[100]; | ||
629 | int sampler_nr; | ||
630 | |||
631 | i915_get_instruction_dst(data, i, dst_name, 0); | ||
632 | i915_get_instruction_addr((t1 >> 24) & 0x7, | ||
633 | (t1 >> 17) & 0xf, | ||
634 | addr_name); | ||
635 | sampler_nr = t0 & 0xf; | ||
636 | |||
637 | instr_out(data, hw_offset, i++, "%s: %s %s, S%d, %s\n", instr_prefix, | ||
638 | tex_name, dst_name, sampler_nr, addr_name); | ||
639 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
640 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
641 | } | ||
642 | |||
643 | static void | ||
644 | i915_decode_dcl(const uint32_t *data, uint32_t hw_offset, int i, char *instr_prefix) | ||
645 | { | ||
646 | uint32_t d0 = data[i]; | ||
647 | char *sampletype; | ||
648 | int dcl_nr = (d0 >> 14) & 0xf; | ||
649 | char *dcl_x = d0 & (1 << 10) ? "x" : ""; | ||
650 | char *dcl_y = d0 & (1 << 11) ? "y" : ""; | ||
651 | char *dcl_z = d0 & (1 << 12) ? "z" : ""; | ||
652 | char *dcl_w = d0 & (1 << 13) ? "w" : ""; | ||
653 | char dcl_mask[10]; | ||
654 | |||
655 | switch ((d0 >> 19) & 0x3) { | ||
656 | case 1: | ||
657 | util_snprintf(dcl_mask, sizeof(dcl_mask), ".%s%s%s%s", dcl_x, dcl_y, dcl_z, dcl_w); | ||
658 | if (strcmp(dcl_mask, ".") == 0) | ||
659 | fprintf(out, "bad (empty) dcl mask\n"); | ||
660 | |||
661 | if (dcl_nr > 10) | ||
662 | fprintf(out, "bad T%d dcl register number\n", dcl_nr); | ||
663 | if (dcl_nr < 8) { | ||
664 | if (strcmp(dcl_mask, ".x") != 0 && | ||
665 | strcmp(dcl_mask, ".xy") != 0 && | ||
666 | strcmp(dcl_mask, ".xz") != 0 && | ||
667 | strcmp(dcl_mask, ".w") != 0 && | ||
668 | strcmp(dcl_mask, ".xyzw") != 0) { | ||
669 | fprintf(out, "bad T%d.%s dcl mask\n", dcl_nr, dcl_mask); | ||
670 | } | ||
671 | instr_out(data, hw_offset, i++, "%s: DCL T%d%s\n", instr_prefix, | ||
672 | dcl_nr, dcl_mask); | ||
673 | } else { | ||
674 | if (strcmp(dcl_mask, ".xz") == 0) | ||
675 | fprintf(out, "errataed bad dcl mask %s\n", dcl_mask); | ||
676 | else if (strcmp(dcl_mask, ".xw") == 0) | ||
677 | fprintf(out, "errataed bad dcl mask %s\n", dcl_mask); | ||
678 | else if (strcmp(dcl_mask, ".xzw") == 0) | ||
679 | fprintf(out, "errataed bad dcl mask %s\n", dcl_mask); | ||
680 | |||
681 | if (dcl_nr == 8) { | ||
682 | instr_out(data, hw_offset, i++, "%s: DCL DIFFUSE%s\n", instr_prefix, | ||
683 | dcl_mask); | ||
684 | } else if (dcl_nr == 9) { | ||
685 | instr_out(data, hw_offset, i++, "%s: DCL SPECULAR%s\n", instr_prefix, | ||
686 | dcl_mask); | ||
687 | } else if (dcl_nr == 10) { | ||
688 | instr_out(data, hw_offset, i++, "%s: DCL FOG%s\n", instr_prefix, | ||
689 | dcl_mask); | ||
690 | } | ||
691 | } | ||
692 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
693 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
694 | break; | ||
695 | case 3: | ||
696 | switch ((d0 >> 22) & 0x3) { | ||
697 | case 0: | ||
698 | sampletype = "2D"; | ||
699 | break; | ||
700 | case 1: | ||
701 | sampletype = "CUBE"; | ||
702 | break; | ||
703 | case 2: | ||
704 | sampletype = "3D"; | ||
705 | break; | ||
706 | default: | ||
707 | sampletype = "RESERVED"; | ||
708 | break; | ||
709 | } | ||
710 | if (dcl_nr > 15) | ||
711 | fprintf(out, "bad S%d dcl register number\n", dcl_nr); | ||
712 | instr_out(data, hw_offset, i++, "%s: DCL S%d %s\n", instr_prefix, | ||
713 | dcl_nr, sampletype); | ||
714 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
715 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
716 | break; | ||
717 | default: | ||
718 | instr_out(data, hw_offset, i++, "%s: DCL RESERVED%d\n", instr_prefix, dcl_nr); | ||
719 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
720 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
721 | } | ||
722 | } | ||
723 | |||
724 | static void | ||
725 | i915_decode_instruction(const uint32_t *data, uint32_t hw_offset, | ||
726 | int i, char *instr_prefix) | ||
727 | { | ||
728 | switch ((data[i] >> 24) & 0x1f) { | ||
729 | case 0x0: | ||
730 | instr_out(data, hw_offset, i++, "%s: NOP\n", instr_prefix); | ||
731 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
732 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
733 | break; | ||
734 | case 0x01: | ||
735 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "ADD"); | ||
736 | break; | ||
737 | case 0x02: | ||
738 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "MOV"); | ||
739 | break; | ||
740 | case 0x03: | ||
741 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "MUL"); | ||
742 | break; | ||
743 | case 0x04: | ||
744 | i915_decode_alu3(data, hw_offset, i, instr_prefix, "MAD"); | ||
745 | break; | ||
746 | case 0x05: | ||
747 | i915_decode_alu3(data, hw_offset, i, instr_prefix, "DP2ADD"); | ||
748 | break; | ||
749 | case 0x06: | ||
750 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "DP3"); | ||
751 | break; | ||
752 | case 0x07: | ||
753 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "DP4"); | ||
754 | break; | ||
755 | case 0x08: | ||
756 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "FRC"); | ||
757 | break; | ||
758 | case 0x09: | ||
759 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "RCP"); | ||
760 | break; | ||
761 | case 0x0a: | ||
762 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "RSQ"); | ||
763 | break; | ||
764 | case 0x0b: | ||
765 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "EXP"); | ||
766 | break; | ||
767 | case 0x0c: | ||
768 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "LOG"); | ||
769 | break; | ||
770 | case 0x0d: | ||
771 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "CMP"); | ||
772 | break; | ||
773 | case 0x0e: | ||
774 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "MIN"); | ||
775 | break; | ||
776 | case 0x0f: | ||
777 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "MAX"); | ||
778 | break; | ||
779 | case 0x10: | ||
780 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "FLR"); | ||
781 | break; | ||
782 | case 0x11: | ||
783 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "MOD"); | ||
784 | break; | ||
785 | case 0x12: | ||
786 | i915_decode_alu1(data, hw_offset, i, instr_prefix, "TRC"); | ||
787 | break; | ||
788 | case 0x13: | ||
789 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "SGE"); | ||
790 | break; | ||
791 | case 0x14: | ||
792 | i915_decode_alu2(data, hw_offset, i, instr_prefix, "SLT"); | ||
793 | break; | ||
794 | case 0x15: | ||
795 | i915_decode_tex(data, hw_offset, i, instr_prefix, "TEXLD"); | ||
796 | break; | ||
797 | case 0x16: | ||
798 | i915_decode_tex(data, hw_offset, i, instr_prefix, "TEXLDP"); | ||
799 | break; | ||
800 | case 0x17: | ||
801 | i915_decode_tex(data, hw_offset, i, instr_prefix, "TEXLDB"); | ||
802 | break; | ||
803 | case 0x19: | ||
804 | i915_decode_dcl(data, hw_offset, i, instr_prefix); | ||
805 | break; | ||
806 | default: | ||
807 | instr_out(data, hw_offset, i++, "%s: unknown\n", instr_prefix); | ||
808 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
809 | instr_out(data, hw_offset, i++, "%s\n", instr_prefix); | ||
810 | break; | ||
811 | } | ||
812 | } | ||
813 | |||
814 | static int | ||
815 | decode_3d_1d(const uint32_t *data, int count, | ||
816 | uint32_t hw_offset, | ||
817 | uint32_t devid, | ||
818 | int *failures) | ||
819 | { | ||
820 | unsigned int len, i, c, idx, word, map, sampler, instr; | ||
821 | char *format; | ||
822 | uint32_t opcode; | ||
823 | |||
824 | struct { | ||
825 | uint32_t opcode; | ||
826 | int i830_only; | ||
827 | int min_len; | ||
828 | int max_len; | ||
829 | char *name; | ||
830 | } opcodes_3d_1d[] = { | ||
831 | { 0x8e, 0, 3, 3, "3DSTATE_BUFFER_INFO" }, | ||
832 | { 0x86, 0, 4, 4, "3DSTATE_CHROMA_KEY" }, | ||
833 | { 0x9c, 0, 7, 7, "3DSTATE_CLEAR_PARAMETERS" }, | ||
834 | { 0x88, 0, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" }, | ||
835 | { 0x99, 0, 2, 2, "3DSTATE_DEFAULT_DIFFUSE" }, | ||
836 | { 0x9a, 0, 2, 2, "3DSTATE_DEFAULT_SPECULAR" }, | ||
837 | { 0x98, 0, 2, 2, "3DSTATE_DEFAULT_Z" }, | ||
838 | { 0x97, 0, 2, 2, "3DSTATE_DEPTH_OFFSET_SCALE" }, | ||
839 | { 0x85, 0, 2, 2, "3DSTATE_DEST_BUFFER_VARIABLES" }, | ||
840 | { 0x80, 0, 5, 5, "3DSTATE_DRAWING_RECTANGLE" }, | ||
841 | { 0x9d, 0, 65, 65, "3DSTATE_FILTER_COEFFICIENTS_4X4" }, | ||
842 | { 0x9e, 0, 4, 4, "3DSTATE_MONO_FILTER" }, | ||
843 | { 0x89, 0, 4, 4, "3DSTATE_FOG_MODE" }, | ||
844 | { 0x8f, 0, 2, 16, "3DSTATE_MAP_PALLETE_LOAD_32" }, | ||
845 | { 0x81, 0, 3, 3, "3DSTATE_SCISSOR_RECTANGLE" }, | ||
846 | { 0x83, 0, 2, 2, "3DSTATE_SPAN_STIPPLE" }, | ||
847 | { 0x8c, 1, 2, 2, "3DSTATE_MAP_COORD_TRANSFORM_I830" }, | ||
848 | { 0x8b, 1, 2, 2, "3DSTATE_MAP_VERTEX_TRANSFORM_I830" }, | ||
849 | { 0x8d, 1, 3, 3, "3DSTATE_W_STATE_I830" }, | ||
850 | { 0x01, 1, 2, 2, "3DSTATE_COLOR_FACTOR_I830" }, | ||
851 | { 0x02, 1, 2, 2, "3DSTATE_MAP_COORD_SETBIND_I830" }, | ||
852 | }, *opcode_3d_1d; | ||
853 | |||
854 | opcode = (data[0] & 0x00ff0000) >> 16; | ||
855 | |||
856 | switch (opcode) { | ||
857 | case 0x07: | ||
858 | /* This instruction is unusual. A 0 length means just 1 DWORD instead of | ||
859 | * 2. The 0 length is specified in one place to be unsupported, but | ||
860 | * stated to be required in another, and 0 length LOAD_INDIRECTs appear | ||
861 | * to cause no harm at least. | ||
862 | */ | ||
863 | instr_out(data, hw_offset, 0, "3DSTATE_LOAD_INDIRECT\n"); | ||
864 | len = (data[0] & 0x000000ff) + 1; | ||
865 | i = 1; | ||
866 | if (data[0] & (0x01 << 8)) { | ||
867 | if (i + 2 >= count) | ||
868 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
869 | instr_out(data, hw_offset, i++, "SIS.0\n"); | ||
870 | instr_out(data, hw_offset, i++, "SIS.1\n"); | ||
871 | } | ||
872 | if (data[0] & (0x02 << 8)) { | ||
873 | if (i + 1 >= count) | ||
874 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
875 | instr_out(data, hw_offset, i++, "DIS.0\n"); | ||
876 | } | ||
877 | if (data[0] & (0x04 << 8)) { | ||
878 | if (i + 2 >= count) | ||
879 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
880 | instr_out(data, hw_offset, i++, "SSB.0\n"); | ||
881 | instr_out(data, hw_offset, i++, "SSB.1\n"); | ||
882 | } | ||
883 | if (data[0] & (0x08 << 8)) { | ||
884 | if (i + 2 >= count) | ||
885 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
886 | instr_out(data, hw_offset, i++, "MSB.0\n"); | ||
887 | instr_out(data, hw_offset, i++, "MSB.1\n"); | ||
888 | } | ||
889 | if (data[0] & (0x10 << 8)) { | ||
890 | if (i + 2 >= count) | ||
891 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
892 | instr_out(data, hw_offset, i++, "PSP.0\n"); | ||
893 | instr_out(data, hw_offset, i++, "PSP.1\n"); | ||
894 | } | ||
895 | if (data[0] & (0x20 << 8)) { | ||
896 | if (i + 2 >= count) | ||
897 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); | ||
898 | instr_out(data, hw_offset, i++, "PSC.0\n"); | ||
899 | instr_out(data, hw_offset, i++, "PSC.1\n"); | ||
900 | } | ||
901 | if (len != i) { | ||
902 | fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n"); | ||
903 | (*failures)++; | ||
904 | return len; | ||
905 | } | ||
906 | return len; | ||
907 | case 0x04: | ||
908 | instr_out(data, hw_offset, 0, "3DSTATE_LOAD_STATE_IMMEDIATE_1\n"); | ||
909 | len = (data[0] & 0x0000000f) + 2; | ||
910 | i = 1; | ||
911 | for (word = 0; word <= 8; word++) { | ||
912 | if (data[0] & (1 << (4 + word))) { | ||
913 | if (i >= count) | ||
914 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_1"); | ||
915 | |||
916 | /* save vertex state for decode */ | ||
917 | if (IS_9XX(devid)) { | ||
918 | if (word == 2) { | ||
919 | saved_s2_set = 1; | ||
920 | saved_s2 = data[i]; | ||
921 | } | ||
922 | if (word == 4) { | ||
923 | saved_s4_set = 1; | ||
924 | saved_s4 = data[i]; | ||
925 | } | ||
926 | } | ||
927 | |||
928 | instr_out(data, hw_offset, i++, "S%d\n", word); | ||
929 | } | ||
930 | } | ||
931 | if (len != i) { | ||
932 | fprintf(out, "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_1\n"); | ||
933 | (*failures)++; | ||
934 | } | ||
935 | return len; | ||
936 | case 0x03: | ||
937 | instr_out(data, hw_offset, 0, "3DSTATE_LOAD_STATE_IMMEDIATE_2\n"); | ||
938 | len = (data[0] & 0x0000000f) + 2; | ||
939 | i = 1; | ||
940 | for (word = 6; word <= 14; word++) { | ||
941 | if (data[0] & (1 << word)) { | ||
942 | if (i >= count) | ||
943 | BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_2"); | ||
944 | |||
945 | if (word == 6) | ||
946 | instr_out(data, hw_offset, i++, "TBCF\n"); | ||
947 | else if (word >= 7 && word <= 10) { | ||
948 | instr_out(data, hw_offset, i++, "TB%dC\n", word - 7); | ||
949 | instr_out(data, hw_offset, i++, "TB%dA\n", word - 7); | ||
950 | } else if (word >= 11 && word <= 14) { | ||
951 | instr_out(data, hw_offset, i++, "TM%dS0\n", word - 11); | ||
952 | instr_out(data, hw_offset, i++, "TM%dS1\n", word - 11); | ||
953 | instr_out(data, hw_offset, i++, "TM%dS2\n", word - 11); | ||
954 | instr_out(data, hw_offset, i++, "TM%dS3\n", word - 11); | ||
955 | instr_out(data, hw_offset, i++, "TM%dS4\n", word - 11); | ||
956 | } | ||
957 | } | ||
958 | } | ||
959 | if (len != i) { | ||
960 | fprintf(out, "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_2\n"); | ||
961 | (*failures)++; | ||
962 | } | ||
963 | return len; | ||
964 | case 0x00: | ||
965 | instr_out(data, hw_offset, 0, "3DSTATE_MAP_STATE\n"); | ||
966 | len = (data[0] & 0x0000003f) + 2; | ||
967 | instr_out(data, hw_offset, 1, "mask\n"); | ||
968 | |||
969 | i = 2; | ||
970 | for (map = 0; map <= 15; map++) { | ||
971 | if (data[1] & (1 << map)) { | ||
972 | int width, height, pitch, dword; | ||
973 | const char *tiling; | ||
974 | |||
975 | if (i + 3 >= count) | ||
976 | BUFFER_FAIL(count, len, "3DSTATE_MAP_STATE"); | ||
977 | instr_out(data, hw_offset, i++, "map %d MS2\n", map); | ||
978 | |||
979 | dword = data[i]; | ||
980 | width = ((dword >> 10) & ((1 << 11) - 1))+1; | ||
981 | height = ((dword >> 21) & ((1 << 11) - 1))+1; | ||
982 | |||
983 | tiling = "none"; | ||
984 | if (dword & (1 << 2)) | ||
985 | tiling = "fenced"; | ||
986 | else if (dword & (1 << 1)) | ||
987 | tiling = dword & (1 << 0) ? "Y" : "X"; | ||
988 | instr_out(data, hw_offset, i++, "map %d MS3 [width=%d, height=%d, tiling=%s]\n", map, width, height, tiling); | ||
989 | |||
990 | dword = data[i]; | ||
991 | pitch = 4*(((dword >> 21) & ((1 << 11) - 1))+1); | ||
992 | instr_out(data, hw_offset, i++, "map %d MS4 [pitch=%d]\n", map, pitch); | ||
993 | } | ||
994 | } | ||
995 | if (len != i) { | ||
996 | fprintf(out, "Bad count in 3DSTATE_MAP_STATE\n"); | ||
997 | (*failures)++; | ||
998 | return len; | ||
999 | } | ||
1000 | return len; | ||
1001 | case 0x06: | ||
1002 | instr_out(data, hw_offset, 0, "3DSTATE_PIXEL_SHADER_CONSTANTS\n"); | ||
1003 | len = (data[0] & 0x000000ff) + 2; | ||
1004 | |||
1005 | i = 2; | ||
1006 | for (c = 0; c <= 31; c++) { | ||
1007 | if (data[1] & (1 << c)) { | ||
1008 | if (i + 4 >= count) | ||
1009 | BUFFER_FAIL(count, len, "3DSTATE_PIXEL_SHADER_CONSTANTS"); | ||
1010 | instr_out(data, hw_offset, i, "C%d.X = %f\n", | ||
1011 | c, int_as_float(data[i])); | ||
1012 | i++; | ||
1013 | instr_out(data, hw_offset, i, "C%d.Y = %f\n", | ||
1014 | c, int_as_float(data[i])); | ||
1015 | i++; | ||
1016 | instr_out(data, hw_offset, i, "C%d.Z = %f\n", | ||
1017 | c, int_as_float(data[i])); | ||
1018 | i++; | ||
1019 | instr_out(data, hw_offset, i, "C%d.W = %f\n", | ||
1020 | c, int_as_float(data[i])); | ||
1021 | i++; | ||
1022 | } | ||
1023 | } | ||
1024 | if (len != i) { | ||
1025 | fprintf(out, "Bad count in 3DSTATE_PIXEL_SHADER_CONSTANTS\n"); | ||
1026 | (*failures)++; | ||
1027 | } | ||
1028 | return len; | ||
1029 | case 0x05: | ||
1030 | instr_out(data, hw_offset, 0, "3DSTATE_PIXEL_SHADER_PROGRAM\n"); | ||
1031 | len = (data[0] & 0x000000ff) + 2; | ||
1032 | if ((len - 1) % 3 != 0 || len > 370) { | ||
1033 | fprintf(out, "Bad count in 3DSTATE_PIXEL_SHADER_PROGRAM\n"); | ||
1034 | (*failures)++; | ||
1035 | } | ||
1036 | i = 1; | ||
1037 | for (instr = 0; instr < (len - 1) / 3; instr++) { | ||
1038 | char instr_prefix[10]; | ||
1039 | |||
1040 | if (i + 3 >= count) | ||
1041 | BUFFER_FAIL(count, len, "3DSTATE_PIXEL_SHADER_PROGRAM"); | ||
1042 | util_snprintf(instr_prefix, sizeof(instr_prefix), "PS%03d", instr); | ||
1043 | i915_decode_instruction(data, hw_offset, i, instr_prefix); | ||
1044 | i += 3; | ||
1045 | } | ||
1046 | return len; | ||
1047 | case 0x01: | ||
1048 | if (!IS_9XX(devid)) | ||
1049 | break; | ||
1050 | instr_out(data, hw_offset, 0, "3DSTATE_SAMPLER_STATE\n"); | ||
1051 | instr_out(data, hw_offset, 1, "mask\n"); | ||
1052 | len = (data[0] & 0x0000003f) + 2; | ||
1053 | i = 2; | ||
1054 | for (sampler = 0; sampler <= 15; sampler++) { | ||
1055 | if (data[1] & (1 << sampler)) { | ||
1056 | if (i + 3 >= count) | ||
1057 | BUFFER_FAIL(count, len, "3DSTATE_SAMPLER_STATE"); | ||
1058 | instr_out(data, hw_offset, i++, "sampler %d SS2\n", | ||
1059 | sampler); | ||
1060 | instr_out(data, hw_offset, i++, "sampler %d SS3\n", | ||
1061 | sampler); | ||
1062 | instr_out(data, hw_offset, i++, "sampler %d SS4\n", | ||
1063 | sampler); | ||
1064 | } | ||
1065 | } | ||
1066 | if (len != i) { | ||
1067 | fprintf(out, "Bad count in 3DSTATE_SAMPLER_STATE\n"); | ||
1068 | (*failures)++; | ||
1069 | } | ||
1070 | return len; | ||
1071 | case 0x85: | ||
1072 | len = (data[0] & 0x0000000f) + 2; | ||
1073 | |||
1074 | if (len != 2) | ||
1075 | fprintf(out, "Bad count in 3DSTATE_DEST_BUFFER_VARIABLES\n"); | ||
1076 | if (count < 2) | ||
1077 | BUFFER_FAIL(count, len, "3DSTATE_DEST_BUFFER_VARIABLES"); | ||
1078 | |||
1079 | instr_out(data, hw_offset, 0, | ||
1080 | "3DSTATE_DEST_BUFFER_VARIABLES\n"); | ||
1081 | |||
1082 | switch ((data[1] >> 8) & 0xf) { | ||
1083 | case 0x0: format = "g8"; break; | ||
1084 | case 0x1: format = "x1r5g5b5"; break; | ||
1085 | case 0x2: format = "r5g6b5"; break; | ||
1086 | case 0x3: format = "a8r8g8b8"; break; | ||
1087 | case 0x4: format = "ycrcb_swapy"; break; | ||
1088 | case 0x5: format = "ycrcb_normal"; break; | ||
1089 | case 0x6: format = "ycrcb_swapuv"; break; | ||
1090 | case 0x7: format = "ycrcb_swapuvy"; break; | ||
1091 | case 0x8: format = "a4r4g4b4"; break; | ||
1092 | case 0x9: format = "a1r5g5b5"; break; | ||
1093 | case 0xa: format = "a2r10g10b10"; break; | ||
1094 | default: format = "BAD"; break; | ||
1095 | } | ||
1096 | instr_out(data, hw_offset, 1, "%s format, early Z %sabled\n", | ||
1097 | format, | ||
1098 | (data[1] & (1 << 31)) ? "en" : "dis"); | ||
1099 | return len; | ||
1100 | |||
1101 | case 0x8e: | ||
1102 | { | ||
1103 | const char *name, *tiling; | ||
1104 | |||
1105 | len = (data[0] & 0x0000000f) + 2; | ||
1106 | if (len != 3) | ||
1107 | fprintf(out, "Bad count in 3DSTATE_BUFFER_INFO\n"); | ||
1108 | if (count < 3) | ||
1109 | BUFFER_FAIL(count, len, "3DSTATE_BUFFER_INFO"); | ||
1110 | |||
1111 | switch((data[1] >> 24) & 0x7) { | ||
1112 | case 0x3: name = "color"; break; | ||
1113 | case 0x7: name = "depth"; break; | ||
1114 | default: name = "unknown"; break; | ||
1115 | } | ||
1116 | |||
1117 | tiling = "none"; | ||
1118 | if (data[1] & (1 << 23)) | ||
1119 | tiling = "fenced"; | ||
1120 | else if (data[1] & (1 << 22)) | ||
1121 | tiling = data[1] & (1 << 21) ? "Y" : "X"; | ||
1122 | |||
1123 | instr_out(data, hw_offset, 0, "3DSTATE_BUFFER_INFO\n"); | ||
1124 | instr_out(data, hw_offset, 1, "%s, tiling = %s, pitch=%d\n", name, tiling, data[1]&0xffff); | ||
1125 | |||
1126 | instr_out(data, hw_offset, 2, "address\n"); | ||
1127 | return len; | ||
1128 | } | ||
1129 | } | ||
1130 | |||
1131 | for (idx = 0; idx < Elements(opcodes_3d_1d); idx++) | ||
1132 | { | ||
1133 | opcode_3d_1d = &opcodes_3d_1d[idx]; | ||
1134 | if (opcode_3d_1d->i830_only && IS_9XX(devid)) | ||
1135 | continue; | ||
1136 | |||
1137 | if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) { | ||
1138 | len = 1; | ||
1139 | |||
1140 | instr_out(data, hw_offset, 0, "%s\n", opcode_3d_1d->name); | ||
1141 | if (opcode_3d_1d->max_len > 1) { | ||
1142 | len = (data[0] & 0x0000ffff) + 2; | ||
1143 | if (len < opcode_3d_1d->min_len || | ||
1144 | len > opcode_3d_1d->max_len) | ||
1145 | { | ||
1146 | fprintf(out, "Bad count in %s\n", | ||
1147 | opcode_3d_1d->name); | ||
1148 | (*failures)++; | ||
1149 | } | ||
1150 | } | ||
1151 | |||
1152 | for (i = 1; i < len; i++) { | ||
1153 | if (i >= count) | ||
1154 | BUFFER_FAIL(count, len, opcode_3d_1d->name); | ||
1155 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
1156 | } | ||
1157 | |||
1158 | return len; | ||
1159 | } | ||
1160 | } | ||
1161 | |||
1162 | instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_1d opcode = 0x%x\n", opcode); | ||
1163 | (*failures)++; | ||
1164 | return 1; | ||
1165 | } | ||
1166 | |||
1167 | static int | ||
1168 | decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset, | ||
1169 | int *failures) | ||
1170 | { | ||
1171 | char immediate = (data[0] & (1 << 23)) == 0; | ||
1172 | unsigned int len, i, ret; | ||
1173 | char *primtype; | ||
1174 | int original_s2 = saved_s2; | ||
1175 | int original_s4 = saved_s4; | ||
1176 | |||
1177 | switch ((data[0] >> 18) & 0xf) { | ||
1178 | case 0x0: primtype = "TRILIST"; break; | ||
1179 | case 0x1: primtype = "TRISTRIP"; break; | ||
1180 | case 0x2: primtype = "TRISTRIP_REVERSE"; break; | ||
1181 | case 0x3: primtype = "TRIFAN"; break; | ||
1182 | case 0x4: primtype = "POLYGON"; break; | ||
1183 | case 0x5: primtype = "LINELIST"; break; | ||
1184 | case 0x6: primtype = "LINESTRIP"; break; | ||
1185 | case 0x7: primtype = "RECTLIST"; break; | ||
1186 | case 0x8: primtype = "POINTLIST"; break; | ||
1187 | case 0x9: primtype = "DIB"; break; | ||
1188 | case 0xa: primtype = "CLEAR_RECT"; saved_s4 = 3 << 6; saved_s2 = ~0; break; | ||
1189 | default: primtype = "unknown"; break; | ||
1190 | } | ||
1191 | |||
1192 | /* XXX: 3DPRIM_DIB not supported */ | ||
1193 | if (immediate) { | ||
1194 | len = (data[0] & 0x0003ffff) + 2; | ||
1195 | instr_out(data, hw_offset, 0, "3DPRIMITIVE inline %s\n", primtype); | ||
1196 | if (count < len) | ||
1197 | BUFFER_FAIL(count, len, "3DPRIMITIVE inline"); | ||
1198 | if (!saved_s2_set || !saved_s4_set) { | ||
1199 | fprintf(out, "unknown vertex format\n"); | ||
1200 | for (i = 1; i < len; i++) { | ||
1201 | instr_out(data, hw_offset, i, | ||
1202 | " vertex data (%f float)\n", | ||
1203 | int_as_float(data[i])); | ||
1204 | } | ||
1205 | } else { | ||
1206 | unsigned int vertex = 0; | ||
1207 | for (i = 1; i < len;) { | ||
1208 | unsigned int tc; | ||
1209 | |||
1210 | #define VERTEX_OUT(fmt, ...) do { \ | ||
1211 | if (i < len) \ | ||
1212 | instr_out(data, hw_offset, i, " V%d."fmt"\n", vertex, __VA_ARGS__); \ | ||
1213 | else \ | ||
1214 | fprintf(out, " missing data in V%d\n", vertex); \ | ||
1215 | i++; \ | ||
1216 | } while (0) | ||
1217 | |||
1218 | VERTEX_OUT("X = %f", int_as_float(data[i])); | ||
1219 | VERTEX_OUT("Y = %f", int_as_float(data[i])); | ||
1220 | switch (saved_s4 >> 6 & 0x7) { | ||
1221 | case 0x1: | ||
1222 | VERTEX_OUT("Z = %f", int_as_float(data[i])); | ||
1223 | break; | ||
1224 | case 0x2: | ||
1225 | VERTEX_OUT("Z = %f", int_as_float(data[i])); | ||
1226 | VERTEX_OUT("W = %f", int_as_float(data[i])); | ||
1227 | break; | ||
1228 | case 0x3: | ||
1229 | break; | ||
1230 | case 0x4: | ||
1231 | VERTEX_OUT("W = %f", int_as_float(data[i])); | ||
1232 | break; | ||
1233 | default: | ||
1234 | fprintf(out, "bad S4 position mask\n"); | ||
1235 | } | ||
1236 | |||
1237 | if (saved_s4 & (1 << 10)) { | ||
1238 | VERTEX_OUT("color = (A=0x%02x, R=0x%02x, G=0x%02x, " | ||
1239 | "B=0x%02x)", | ||
1240 | data[i] >> 24, | ||
1241 | (data[i] >> 16) & 0xff, | ||
1242 | (data[i] >> 8) & 0xff, | ||
1243 | data[i] & 0xff); | ||
1244 | } | ||
1245 | if (saved_s4 & (1 << 11)) { | ||
1246 | VERTEX_OUT("spec = (A=0x%02x, R=0x%02x, G=0x%02x, " | ||
1247 | "B=0x%02x)", | ||
1248 | data[i] >> 24, | ||
1249 | (data[i] >> 16) & 0xff, | ||
1250 | (data[i] >> 8) & 0xff, | ||
1251 | data[i] & 0xff); | ||
1252 | } | ||
1253 | if (saved_s4 & (1 << 12)) | ||
1254 | VERTEX_OUT("width = 0x%08x)", data[i]); | ||
1255 | |||
1256 | for (tc = 0; tc <= 7; tc++) { | ||
1257 | switch ((saved_s2 >> (tc * 4)) & 0xf) { | ||
1258 | case 0x0: | ||
1259 | VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); | ||
1260 | VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); | ||
1261 | break; | ||
1262 | case 0x1: | ||
1263 | VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); | ||
1264 | VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); | ||
1265 | VERTEX_OUT("T%d.Z = %f", tc, int_as_float(data[i])); | ||
1266 | break; | ||
1267 | case 0x2: | ||
1268 | VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); | ||
1269 | VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); | ||
1270 | VERTEX_OUT("T%d.Z = %f", tc, int_as_float(data[i])); | ||
1271 | VERTEX_OUT("T%d.W = %f", tc, int_as_float(data[i])); | ||
1272 | break; | ||
1273 | case 0x3: | ||
1274 | VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); | ||
1275 | break; | ||
1276 | case 0x4: | ||
1277 | VERTEX_OUT("T%d.XY = 0x%08x half-float", tc, data[i]); | ||
1278 | break; | ||
1279 | case 0x5: | ||
1280 | VERTEX_OUT("T%d.XY = 0x%08x half-float", tc, data[i]); | ||
1281 | VERTEX_OUT("T%d.ZW = 0x%08x half-float", tc, data[i]); | ||
1282 | break; | ||
1283 | case 0xf: | ||
1284 | break; | ||
1285 | default: | ||
1286 | fprintf(out, "bad S2.T%d format\n", tc); | ||
1287 | } | ||
1288 | } | ||
1289 | vertex++; | ||
1290 | } | ||
1291 | } | ||
1292 | |||
1293 | ret = len; | ||
1294 | } else { | ||
1295 | /* indirect vertices */ | ||
1296 | len = data[0] & 0x0000ffff; /* index count */ | ||
1297 | if (data[0] & (1 << 17)) { | ||
1298 | /* random vertex access */ | ||
1299 | if (count < (len + 1) / 2 + 1) { | ||
1300 | BUFFER_FAIL(count, (len + 1) / 2 + 1, | ||
1301 | "3DPRIMITIVE random indirect"); | ||
1302 | } | ||
1303 | instr_out(data, hw_offset, 0, | ||
1304 | "3DPRIMITIVE random indirect %s (%d)\n", primtype, len); | ||
1305 | if (len == 0) { | ||
1306 | /* vertex indices continue until 0xffff is found */ | ||
1307 | for (i = 1; i < count; i++) { | ||
1308 | if ((data[i] & 0xffff) == 0xffff) { | ||
1309 | instr_out(data, hw_offset, i, | ||
1310 | " indices: (terminator)\n"); | ||
1311 | ret = i; | ||
1312 | goto out; | ||
1313 | } else if ((data[i] >> 16) == 0xffff) { | ||
1314 | instr_out(data, hw_offset, i, | ||
1315 | " indices: 0x%04x, " | ||
1316 | "(terminator)\n", | ||
1317 | data[i] & 0xffff); | ||
1318 | ret = i; | ||
1319 | goto out; | ||
1320 | } else { | ||
1321 | instr_out(data, hw_offset, i, | ||
1322 | " indices: 0x%04x, 0x%04x\n", | ||
1323 | data[i] & 0xffff, data[i] >> 16); | ||
1324 | } | ||
1325 | } | ||
1326 | fprintf(out, | ||
1327 | "3DPRIMITIVE: no terminator found in index buffer\n"); | ||
1328 | (*failures)++; | ||
1329 | ret = count; | ||
1330 | goto out; | ||
1331 | } else { | ||
1332 | /* fixed size vertex index buffer */ | ||
1333 | for (i = 0; i < len; i += 2) { | ||
1334 | if (i * 2 == len - 1) { | ||
1335 | instr_out(data, hw_offset, i, | ||
1336 | " indices: 0x%04x\n", | ||
1337 | data[i] & 0xffff); | ||
1338 | } else { | ||
1339 | instr_out(data, hw_offset, i, | ||
1340 | " indices: 0x%04x, 0x%04x\n", | ||
1341 | data[i] & 0xffff, data[i] >> 16); | ||
1342 | } | ||
1343 | } | ||
1344 | } | ||
1345 | ret = (len + 1) / 2 + 1; | ||
1346 | goto out; | ||
1347 | } else { | ||
1348 | /* sequential vertex access */ | ||
1349 | if (count < 2) | ||
1350 | BUFFER_FAIL(count, 2, "3DPRIMITIVE seq indirect"); | ||
1351 | instr_out(data, hw_offset, 0, | ||
1352 | "3DPRIMITIVE sequential indirect %s, %d starting from " | ||
1353 | "%d\n", primtype, len, data[1] & 0xffff); | ||
1354 | instr_out(data, hw_offset, 1, " start\n"); | ||
1355 | ret = 2; | ||
1356 | goto out; | ||
1357 | } | ||
1358 | } | ||
1359 | |||
1360 | out: | ||
1361 | saved_s2 = original_s2; | ||
1362 | saved_s4 = original_s4; | ||
1363 | return ret; | ||
1364 | } | ||
1365 | |||
1366 | static int | ||
1367 | decode_3d(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures) | ||
1368 | { | ||
1369 | uint32_t opcode; | ||
1370 | unsigned int idx; | ||
1371 | |||
1372 | struct { | ||
1373 | uint32_t opcode; | ||
1374 | int min_len; | ||
1375 | int max_len; | ||
1376 | char *name; | ||
1377 | } opcodes_3d[] = { | ||
1378 | { 0x06, 1, 1, "3DSTATE_ANTI_ALIASING" }, | ||
1379 | { 0x08, 1, 1, "3DSTATE_BACKFACE_STENCIL_OPS" }, | ||
1380 | { 0x09, 1, 1, "3DSTATE_BACKFACE_STENCIL_MASKS" }, | ||
1381 | { 0x16, 1, 1, "3DSTATE_COORD_SET_BINDINGS" }, | ||
1382 | { 0x15, 1, 1, "3DSTATE_FOG_COLOR" }, | ||
1383 | { 0x0b, 1, 1, "3DSTATE_INDEPENDENT_ALPHA_BLEND" }, | ||
1384 | { 0x0d, 1, 1, "3DSTATE_MODES_4" }, | ||
1385 | { 0x0c, 1, 1, "3DSTATE_MODES_5" }, | ||
1386 | { 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" }, | ||
1387 | }, *opcode_3d; | ||
1388 | |||
1389 | opcode = (data[0] & 0x1f000000) >> 24; | ||
1390 | |||
1391 | switch (opcode) { | ||
1392 | case 0x1f: | ||
1393 | return decode_3d_primitive(data, count, hw_offset, failures); | ||
1394 | case 0x1d: | ||
1395 | return decode_3d_1d(data, count, hw_offset, devid, failures); | ||
1396 | case 0x1c: | ||
1397 | return decode_3d_1c(data, count, hw_offset, failures); | ||
1398 | } | ||
1399 | |||
1400 | for (idx = 0; idx < Elements(opcodes_3d); idx++) { | ||
1401 | opcode_3d = &opcodes_3d[idx]; | ||
1402 | if (opcode == opcode_3d->opcode) { | ||
1403 | unsigned int len = 1, i; | ||
1404 | |||
1405 | instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name); | ||
1406 | if (opcode_3d->max_len > 1) { | ||
1407 | len = (data[0] & 0xff) + 2; | ||
1408 | if (len < opcode_3d->min_len || | ||
1409 | len > opcode_3d->max_len) | ||
1410 | { | ||
1411 | fprintf(out, "Bad count in %s\n", opcode_3d->name); | ||
1412 | } | ||
1413 | } | ||
1414 | |||
1415 | for (i = 1; i < len; i++) { | ||
1416 | if (i >= count) | ||
1417 | BUFFER_FAIL(count, len, opcode_3d->name); | ||
1418 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
1419 | } | ||
1420 | return len; | ||
1421 | } | ||
1422 | } | ||
1423 | |||
1424 | instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d opcode = 0x%x\n", opcode); | ||
1425 | (*failures)++; | ||
1426 | return 1; | ||
1427 | } | ||
1428 | |||
1429 | static const char * | ||
1430 | get_965_surfacetype(unsigned int surfacetype) | ||
1431 | { | ||
1432 | switch (surfacetype) { | ||
1433 | case 0: return "1D"; | ||
1434 | case 1: return "2D"; | ||
1435 | case 2: return "3D"; | ||
1436 | case 3: return "CUBE"; | ||
1437 | case 4: return "BUFFER"; | ||
1438 | case 7: return "NULL"; | ||
1439 | default: return "unknown"; | ||
1440 | } | ||
1441 | } | ||
1442 | |||
1443 | static const char * | ||
1444 | get_965_depthformat(unsigned int depthformat) | ||
1445 | { | ||
1446 | switch (depthformat) { | ||
1447 | case 0: return "s8_z24float"; | ||
1448 | case 1: return "z32float"; | ||
1449 | case 2: return "z24s8"; | ||
1450 | case 5: return "z16"; | ||
1451 | default: return "unknown"; | ||
1452 | } | ||
1453 | } | ||
1454 | |||
1455 | static const char * | ||
1456 | get_965_element_component(uint32_t data, int component) | ||
1457 | { | ||
1458 | uint32_t component_control = (data >> (16 + (3 - component) * 4)) & 0x7; | ||
1459 | |||
1460 | switch (component_control) { | ||
1461 | case 0: | ||
1462 | return "nostore"; | ||
1463 | case 1: | ||
1464 | switch (component) { | ||
1465 | case 0: return "X"; | ||
1466 | case 1: return "Y"; | ||
1467 | case 2: return "Z"; | ||
1468 | case 3: return "W"; | ||
1469 | default: return "fail"; | ||
1470 | } | ||
1471 | case 2: | ||
1472 | return "0.0"; | ||
1473 | case 3: | ||
1474 | return "1.0"; | ||
1475 | case 4: | ||
1476 | return "0x1"; | ||
1477 | case 5: | ||
1478 | return "VID"; | ||
1479 | default: | ||
1480 | return "fail"; | ||
1481 | } | ||
1482 | } | ||
1483 | |||
1484 | static const char * | ||
1485 | get_965_prim_type(uint32_t data) | ||
1486 | { | ||
1487 | uint32_t primtype = (data >> 10) & 0x1f; | ||
1488 | |||
1489 | switch (primtype) { | ||
1490 | case 0x01: return "point list"; | ||
1491 | case 0x02: return "line list"; | ||
1492 | case 0x03: return "line strip"; | ||
1493 | case 0x04: return "tri list"; | ||
1494 | case 0x05: return "tri strip"; | ||
1495 | case 0x06: return "tri fan"; | ||
1496 | case 0x07: return "quad list"; | ||
1497 | case 0x08: return "quad strip"; | ||
1498 | case 0x09: return "line list adj"; | ||
1499 | case 0x0a: return "line strip adj"; | ||
1500 | case 0x0b: return "tri list adj"; | ||
1501 | case 0x0c: return "tri strip adj"; | ||
1502 | case 0x0d: return "tri strip reverse"; | ||
1503 | case 0x0e: return "polygon"; | ||
1504 | case 0x0f: return "rect list"; | ||
1505 | case 0x10: return "line loop"; | ||
1506 | case 0x11: return "point list bf"; | ||
1507 | case 0x12: return "line strip cont"; | ||
1508 | case 0x13: return "line strip bf"; | ||
1509 | case 0x14: return "line strip cont bf"; | ||
1510 | case 0x15: return "tri fan no stipple"; | ||
1511 | default: return "fail"; | ||
1512 | } | ||
1513 | } | ||
1514 | static int | ||
1515 | i965_decode_urb_fence(const uint32_t *data, uint32_t hw_offset, int len, int count, | ||
1516 | int *failures) | ||
1517 | { | ||
1518 | uint32_t vs_fence, clip_fence, gs_fence, sf_fence, vfe_fence, cs_fence; | ||
1519 | |||
1520 | if (len != 3) | ||
1521 | fprintf(out, "Bad count in URB_FENCE\n"); | ||
1522 | if (count < 3) | ||
1523 | BUFFER_FAIL(count, len, "URB_FENCE"); | ||
1524 | |||
1525 | vs_fence = data[1] & 0x3ff; | ||
1526 | gs_fence = (data[1] >> 10) & 0x3ff; | ||
1527 | clip_fence = (data[1] >> 20) & 0x3ff; | ||
1528 | sf_fence = data[2] & 0x3ff; | ||
1529 | vfe_fence = (data[2] >> 10) & 0x3ff; | ||
1530 | cs_fence = (data[2] >> 20) & 0x7ff; | ||
1531 | |||
1532 | instr_out(data, hw_offset, 0, "URB_FENCE: %s%s%s%s%s%s\n", | ||
1533 | (data[0] >> 13) & 1 ? "cs " : "", | ||
1534 | (data[0] >> 12) & 1 ? "vfe " : "", | ||
1535 | (data[0] >> 11) & 1 ? "sf " : "", | ||
1536 | (data[0] >> 10) & 1 ? "clip " : "", | ||
1537 | (data[0] >> 9) & 1 ? "gs " : "", | ||
1538 | (data[0] >> 8) & 1 ? "vs " : ""); | ||
1539 | instr_out(data, hw_offset, 1, | ||
1540 | "vs fence: %d, clip_fence: %d, gs_fence: %d\n", | ||
1541 | vs_fence, clip_fence, gs_fence); | ||
1542 | instr_out(data, hw_offset, 2, | ||
1543 | "sf fence: %d, vfe_fence: %d, cs_fence: %d\n", | ||
1544 | sf_fence, vfe_fence, cs_fence); | ||
1545 | if (gs_fence < vs_fence) | ||
1546 | fprintf(out, "gs fence < vs fence!\n"); | ||
1547 | if (clip_fence < gs_fence) | ||
1548 | fprintf(out, "clip fence < gs fence!\n"); | ||
1549 | if (sf_fence < clip_fence) | ||
1550 | fprintf(out, "sf fence < clip fence!\n"); | ||
1551 | if (cs_fence < sf_fence) | ||
1552 | fprintf(out, "cs fence < sf fence!\n"); | ||
1553 | |||
1554 | return len; | ||
1555 | } | ||
1556 | |||
1557 | static void | ||
1558 | state_base_out(const uint32_t *data, uint32_t hw_offset, unsigned int index, | ||
1559 | char *name) | ||
1560 | { | ||
1561 | if (data[index] & 1) { | ||
1562 | instr_out(data, hw_offset, index, "%s state base address 0x%08x\n", | ||
1563 | name, data[index] & ~1); | ||
1564 | } else { | ||
1565 | instr_out(data, hw_offset, index, "%s state base not updated\n", | ||
1566 | name); | ||
1567 | } | ||
1568 | } | ||
1569 | |||
1570 | static void | ||
1571 | state_max_out(const uint32_t *data, uint32_t hw_offset, unsigned int index, | ||
1572 | char *name) | ||
1573 | { | ||
1574 | if (data[index] & 1) { | ||
1575 | if (data[index] == 1) { | ||
1576 | instr_out(data, hw_offset, index, | ||
1577 | "%s state upper bound disabled\n", name); | ||
1578 | } else { | ||
1579 | instr_out(data, hw_offset, index, "%s state upper bound 0x%08x\n", | ||
1580 | name, data[index] & ~1); | ||
1581 | } | ||
1582 | } else { | ||
1583 | instr_out(data, hw_offset, index, "%s state upper bound not updated\n", | ||
1584 | name); | ||
1585 | } | ||
1586 | } | ||
1587 | |||
1588 | static int | ||
1589 | decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures) | ||
1590 | { | ||
1591 | uint32_t opcode; | ||
1592 | unsigned int idx, len; | ||
1593 | int i, sba_len; | ||
1594 | char *desc1 = NULL; | ||
1595 | |||
1596 | struct { | ||
1597 | uint32_t opcode; | ||
1598 | int min_len; | ||
1599 | int max_len; | ||
1600 | char *name; | ||
1601 | } opcodes_3d[] = { | ||
1602 | { 0x6000, 3, 3, "URB_FENCE" }, | ||
1603 | { 0x6001, 2, 2, "CS_URB_STATE" }, | ||
1604 | { 0x6002, 2, 2, "CONSTANT_BUFFER" }, | ||
1605 | { 0x6101, 6, 6, "STATE_BASE_ADDRESS" }, | ||
1606 | { 0x6102, 2, 2 , "STATE_SIP" }, | ||
1607 | { 0x6104, 1, 1, "3DSTATE_PIPELINE_SELECT" }, | ||
1608 | { 0x680b, 1, 1, "3DSTATE_VF_STATISTICS" }, | ||
1609 | { 0x6904, 1, 1, "3DSTATE_PIPELINE_SELECT" }, | ||
1610 | { 0x7800, 7, 7, "3DSTATE_PIPELINED_POINTERS" }, | ||
1611 | { 0x7801, 6, 6, "3DSTATE_BINDING_TABLE_POINTERS" }, | ||
1612 | { 0x780b, 1, 1, "3DSTATE_VF_STATISTICS" }, | ||
1613 | { 0x7808, 5, 257, "3DSTATE_VERTEX_BUFFERS" }, | ||
1614 | { 0x7809, 3, 256, "3DSTATE_VERTEX_ELEMENTS" }, | ||
1615 | { 0x780a, 3, 3, "3DSTATE_INDEX_BUFFER" }, | ||
1616 | { 0x7900, 4, 4, "3DSTATE_DRAWING_RECTANGLE" }, | ||
1617 | { 0x7901, 5, 5, "3DSTATE_CONSTANT_COLOR" }, | ||
1618 | { 0x7905, 5, 7, "3DSTATE_DEPTH_BUFFER" }, | ||
1619 | { 0x7906, 2, 2, "3DSTATE_POLY_STIPPLE_OFFSET" }, | ||
1620 | { 0x7907, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" }, | ||
1621 | { 0x7908, 3, 3, "3DSTATE_LINE_STIPPLE" }, | ||
1622 | { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, | ||
1623 | { 0x7909, 2, 2, "3DSTATE_CLEAR_PARAMS" }, | ||
1624 | { 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, | ||
1625 | { 0x790b, 4, 4, "3DSTATE_GS_SVB_INDEX" }, | ||
1626 | { 0x790d, 3, 3, "3DSTATE_MULTISAMPLE" }, | ||
1627 | { 0x7b00, 6, 6, "3DPRIMITIVE" }, | ||
1628 | { 0x7802, 4, 4, "3DSTATE_SAMPLER_STATE_POINTERS" }, | ||
1629 | { 0x7805, 3, 3, "3DSTATE_URB" }, | ||
1630 | { 0x780e, 4, 4, "3DSTATE_CC_STATE_POINTERS" }, | ||
1631 | { 0x7810, 6, 6, "3DSTATE_VS_STATE" }, | ||
1632 | { 0x7811, 7, 7, "3DSTATE_GS_STATE" }, | ||
1633 | { 0x7812, 4, 4, "3DSTATE_CLIP_STATE" }, | ||
1634 | { 0x7813, 20, 20, "3DSTATE_SF_STATE" }, | ||
1635 | { 0x7814, 9, 9, "3DSTATE_WM_STATE" }, | ||
1636 | { 0x7812, 4, 4, "3DSTATE_CLIP_STATE" }, | ||
1637 | { 0x7815, 5, 5, "3DSTATE_CONSTANT_VS_STATE" }, | ||
1638 | { 0x7816, 5, 5, "3DSTATE_CONSTANT_GS_STATE" }, | ||
1639 | { 0x7817, 5, 5, "3DSTATE_CONSTANT_PS_STATE" }, | ||
1640 | { 0x7818, 2, 2, "3DSTATE_SAMPLE_MASK" }, | ||
1641 | }, *opcode_3d; | ||
1642 | |||
1643 | len = (data[0] & 0x0000ffff) + 2; | ||
1644 | |||
1645 | opcode = (data[0] & 0xffff0000) >> 16; | ||
1646 | switch (opcode) { | ||
1647 | case 0x6000: | ||
1648 | len = (data[0] & 0x000000ff) + 2; | ||
1649 | return i965_decode_urb_fence(data, hw_offset, len, count, failures); | ||
1650 | case 0x6001: | ||
1651 | instr_out(data, hw_offset, 0, "CS_URB_STATE\n"); | ||
1652 | instr_out(data, hw_offset, 1, "entry_size: %d [%d bytes], n_entries: %d\n", | ||
1653 | (data[1] >> 4) & 0x1f, | ||
1654 | (((data[1] >> 4) & 0x1f) + 1) * 64, | ||
1655 | data[1] & 0x7); | ||
1656 | return len; | ||
1657 | case 0x6002: | ||
1658 | len = (data[0] & 0x000000ff) + 2; | ||
1659 | instr_out(data, hw_offset, 0, "CONSTANT_BUFFER: %s\n", | ||
1660 | (data[0] >> 8) & 1 ? "valid" : "invalid"); | ||
1661 | instr_out(data, hw_offset, 1, "offset: 0x%08x, length: %d bytes\n", | ||
1662 | data[1] & ~0x3f, ((data[1] & 0x3f) + 1) * 64); | ||
1663 | return len; | ||
1664 | case 0x6101: | ||
1665 | if (IS_GEN6(devid)) | ||
1666 | sba_len = 10; | ||
1667 | else if (IS_IRONLAKE(devid)) | ||
1668 | sba_len = 8; | ||
1669 | else | ||
1670 | sba_len = 6; | ||
1671 | if (len != sba_len) | ||
1672 | fprintf(out, "Bad count in STATE_BASE_ADDRESS\n"); | ||
1673 | if (len != sba_len) | ||
1674 | BUFFER_FAIL(count, len, "STATE_BASE_ADDRESS"); | ||
1675 | |||
1676 | i = 0; | ||
1677 | instr_out(data, hw_offset, 0, | ||
1678 | "STATE_BASE_ADDRESS\n"); | ||
1679 | i++; | ||
1680 | |||
1681 | state_base_out(data, hw_offset, i++, "general"); | ||
1682 | state_base_out(data, hw_offset, i++, "surface"); | ||
1683 | if (IS_GEN6(devid)) | ||
1684 | state_base_out(data, hw_offset, i++, "dynamic"); | ||
1685 | state_base_out(data, hw_offset, i++, "indirect"); | ||
1686 | if (IS_IRONLAKE(devid) || IS_GEN6(devid)) | ||
1687 | state_base_out(data, hw_offset, i++, "instruction"); | ||
1688 | |||
1689 | state_max_out(data, hw_offset, i++, "general"); | ||
1690 | if (IS_GEN6(devid)) | ||
1691 | state_max_out(data, hw_offset, i++, "dynamic"); | ||
1692 | state_max_out(data, hw_offset, i++, "indirect"); | ||
1693 | if (IS_IRONLAKE(devid) || IS_GEN6(devid)) | ||
1694 | state_max_out(data, hw_offset, i++, "instruction"); | ||
1695 | |||
1696 | return len; | ||
1697 | case 0x7800: | ||
1698 | if (len != 7) | ||
1699 | fprintf(out, "Bad count in 3DSTATE_PIPELINED_POINTERS\n"); | ||
1700 | if (count < 7) | ||
1701 | BUFFER_FAIL(count, len, "3DSTATE_PIPELINED_POINTERS"); | ||
1702 | |||
1703 | instr_out(data, hw_offset, 0, | ||
1704 | "3DSTATE_PIPELINED_POINTERS\n"); | ||
1705 | instr_out(data, hw_offset, 1, "VS state\n"); | ||
1706 | instr_out(data, hw_offset, 2, "GS state\n"); | ||
1707 | instr_out(data, hw_offset, 3, "Clip state\n"); | ||
1708 | instr_out(data, hw_offset, 4, "SF state\n"); | ||
1709 | instr_out(data, hw_offset, 5, "WM state\n"); | ||
1710 | instr_out(data, hw_offset, 6, "CC state\n"); | ||
1711 | return len; | ||
1712 | case 0x7801: | ||
1713 | len = (data[0] & 0x000000ff) + 2; | ||
1714 | if (len != 6 && len != 4) | ||
1715 | fprintf(out, "Bad count in 3DSTATE_BINDING_TABLE_POINTERS\n"); | ||
1716 | if (len == 6) { | ||
1717 | if (count < 6) | ||
1718 | BUFFER_FAIL(count, len, "3DSTATE_BINDING_TABLE_POINTERS"); | ||
1719 | instr_out(data, hw_offset, 0, | ||
1720 | "3DSTATE_BINDING_TABLE_POINTERS\n"); | ||
1721 | instr_out(data, hw_offset, 1, "VS binding table\n"); | ||
1722 | instr_out(data, hw_offset, 2, "GS binding table\n"); | ||
1723 | instr_out(data, hw_offset, 3, "Clip binding table\n"); | ||
1724 | instr_out(data, hw_offset, 4, "SF binding table\n"); | ||
1725 | instr_out(data, hw_offset, 5, "WM binding table\n"); | ||
1726 | } else { | ||
1727 | if (count < 4) | ||
1728 | BUFFER_FAIL(count, len, "3DSTATE_BINDING_TABLE_POINTERS"); | ||
1729 | |||
1730 | instr_out(data, hw_offset, 0, | ||
1731 | "3DSTATE_BINDING_TABLE_POINTERS: VS mod %d, " | ||
1732 | "GS mod %d, PS mod %d\n", | ||
1733 | (data[0] & (1 << 8)) != 0, | ||
1734 | (data[0] & (1 << 9)) != 0, | ||
1735 | (data[0] & (1 << 10)) != 0); | ||
1736 | instr_out(data, hw_offset, 1, "VS binding table\n"); | ||
1737 | instr_out(data, hw_offset, 2, "GS binding table\n"); | ||
1738 | instr_out(data, hw_offset, 3, "WM binding table\n"); | ||
1739 | } | ||
1740 | |||
1741 | return len; | ||
1742 | |||
1743 | case 0x7808: | ||
1744 | len = (data[0] & 0xff) + 2; | ||
1745 | if ((len - 1) % 4 != 0) | ||
1746 | fprintf(out, "Bad count in 3DSTATE_VERTEX_BUFFERS\n"); | ||
1747 | if (count < len) | ||
1748 | BUFFER_FAIL(count, len, "3DSTATE_VERTEX_BUFFERS"); | ||
1749 | instr_out(data, hw_offset, 0, "3DSTATE_VERTEX_BUFFERS\n"); | ||
1750 | |||
1751 | for (i = 1; i < len;) { | ||
1752 | instr_out(data, hw_offset, i, "buffer %d: %s, pitch %db\n", | ||
1753 | data[i] >> 27, | ||
1754 | data[i] & (1 << 26) ? "random" : "sequential", | ||
1755 | data[i] & 0x07ff); | ||
1756 | i++; | ||
1757 | instr_out(data, hw_offset, i++, "buffer address\n"); | ||
1758 | instr_out(data, hw_offset, i++, "max index\n"); | ||
1759 | instr_out(data, hw_offset, i++, "mbz\n"); | ||
1760 | } | ||
1761 | return len; | ||
1762 | |||
1763 | case 0x7809: | ||
1764 | len = (data[0] & 0xff) + 2; | ||
1765 | if ((len + 1) % 2 != 0) | ||
1766 | fprintf(out, "Bad count in 3DSTATE_VERTEX_ELEMENTS\n"); | ||
1767 | if (count < len) | ||
1768 | BUFFER_FAIL(count, len, "3DSTATE_VERTEX_ELEMENTS"); | ||
1769 | instr_out(data, hw_offset, 0, "3DSTATE_VERTEX_ELEMENTS\n"); | ||
1770 | |||
1771 | for (i = 1; i < len;) { | ||
1772 | instr_out(data, hw_offset, i, "buffer %d: %svalid, type 0x%04x, " | ||
1773 | "src offset 0x%04x bytes\n", | ||
1774 | data[i] >> 27, | ||
1775 | data[i] & (1 << 26) ? "" : "in", | ||
1776 | (data[i] >> 16) & 0x1ff, | ||
1777 | data[i] & 0x07ff); | ||
1778 | i++; | ||
1779 | instr_out(data, hw_offset, i, "(%s, %s, %s, %s), " | ||
1780 | "dst offset 0x%02x bytes\n", | ||
1781 | get_965_element_component(data[i], 0), | ||
1782 | get_965_element_component(data[i], 1), | ||
1783 | get_965_element_component(data[i], 2), | ||
1784 | get_965_element_component(data[i], 3), | ||
1785 | (data[i] & 0xff) * 4); | ||
1786 | i++; | ||
1787 | } | ||
1788 | return len; | ||
1789 | |||
1790 | case 0x780d: | ||
1791 | len = (data[0] & 0xff) + 2; | ||
1792 | if (len != 4) | ||
1793 | fprintf(out, "Bad count in 3DSTATE_VIEWPORT_STATE_POINTERS\n"); | ||
1794 | if (count < len) | ||
1795 | BUFFER_FAIL(count, len, "3DSTATE_VIEWPORT_STATE_POINTERS"); | ||
1796 | instr_out(data, hw_offset, 0, "3DSTATE_VIEWPORT_STATE_POINTERS\n"); | ||
1797 | instr_out(data, hw_offset, 1, "clip\n"); | ||
1798 | instr_out(data, hw_offset, 2, "sf\n"); | ||
1799 | instr_out(data, hw_offset, 3, "cc\n"); | ||
1800 | return len; | ||
1801 | |||
1802 | case 0x780a: | ||
1803 | len = (data[0] & 0xff) + 2; | ||
1804 | if (len != 3) | ||
1805 | fprintf(out, "Bad count in 3DSTATE_INDEX_BUFFER\n"); | ||
1806 | if (count < len) | ||
1807 | BUFFER_FAIL(count, len, "3DSTATE_INDEX_BUFFER"); | ||
1808 | instr_out(data, hw_offset, 0, "3DSTATE_INDEX_BUFFER\n"); | ||
1809 | instr_out(data, hw_offset, 1, "beginning buffer address\n"); | ||
1810 | instr_out(data, hw_offset, 2, "ending buffer address\n"); | ||
1811 | return len; | ||
1812 | |||
1813 | case 0x7900: | ||
1814 | if (len != 4) | ||
1815 | fprintf(out, "Bad count in 3DSTATE_DRAWING_RECTANGLE\n"); | ||
1816 | if (count < 4) | ||
1817 | BUFFER_FAIL(count, len, "3DSTATE_DRAWING_RECTANGLE"); | ||
1818 | |||
1819 | instr_out(data, hw_offset, 0, | ||
1820 | "3DSTATE_DRAWING_RECTANGLE\n"); | ||
1821 | instr_out(data, hw_offset, 1, "top left: %d,%d\n", | ||
1822 | data[1] & 0xffff, | ||
1823 | (data[1] >> 16) & 0xffff); | ||
1824 | instr_out(data, hw_offset, 2, "bottom right: %d,%d\n", | ||
1825 | data[2] & 0xffff, | ||
1826 | (data[2] >> 16) & 0xffff); | ||
1827 | instr_out(data, hw_offset, 3, "origin: %d,%d\n", | ||
1828 | (int)data[3] & 0xffff, | ||
1829 | ((int)data[3] >> 16) & 0xffff); | ||
1830 | |||
1831 | return len; | ||
1832 | |||
1833 | case 0x7905: | ||
1834 | if (len < 5 || len > 7) | ||
1835 | fprintf(out, "Bad count in 3DSTATE_DEPTH_BUFFER\n"); | ||
1836 | if (count < len) | ||
1837 | BUFFER_FAIL(count, len, "3DSTATE_DEPTH_BUFFER"); | ||
1838 | |||
1839 | instr_out(data, hw_offset, 0, | ||
1840 | "3DSTATE_DEPTH_BUFFER\n"); | ||
1841 | instr_out(data, hw_offset, 1, "%s, %s, pitch = %d bytes, %stiled\n", | ||
1842 | get_965_surfacetype(data[1] >> 29), | ||
1843 | get_965_depthformat((data[1] >> 18) & 0x7), | ||
1844 | (data[1] & 0x0001ffff) + 1, | ||
1845 | data[1] & (1 << 27) ? "" : "not "); | ||
1846 | instr_out(data, hw_offset, 2, "depth offset\n"); | ||
1847 | instr_out(data, hw_offset, 3, "%dx%d\n", | ||
1848 | ((data[3] & 0x0007ffc0) >> 6) + 1, | ||
1849 | ((data[3] & 0xfff80000) >> 19) + 1); | ||
1850 | instr_out(data, hw_offset, 4, "volume depth\n"); | ||
1851 | if (len >= 6) | ||
1852 | instr_out(data, hw_offset, 5, "\n"); | ||
1853 | if (len >= 7) | ||
1854 | instr_out(data, hw_offset, 6, "render target view extent\n"); | ||
1855 | |||
1856 | return len; | ||
1857 | |||
1858 | case 0x7a00: | ||
1859 | len = (data[0] & 0xff) + 2; | ||
1860 | if (len != 4) | ||
1861 | fprintf(out, "Bad count in PIPE_CONTROL\n"); | ||
1862 | if (count < len) | ||
1863 | BUFFER_FAIL(count, len, "PIPE_CONTROL"); | ||
1864 | |||
1865 | switch ((data[0] >> 14) & 0x3) { | ||
1866 | case 0: desc1 = "no write"; break; | ||
1867 | case 1: desc1 = "qword write"; break; | ||
1868 | case 2: desc1 = "PS_DEPTH_COUNT write"; break; | ||
1869 | case 3: desc1 = "TIMESTAMP write"; break; | ||
1870 | } | ||
1871 | instr_out(data, hw_offset, 0, | ||
1872 | "PIPE_CONTROL: %s, %sdepth stall, %sRC write flush, " | ||
1873 | "%sinst flush\n", | ||
1874 | desc1, | ||
1875 | data[0] & (1 << 13) ? "" : "no ", | ||
1876 | data[0] & (1 << 12) ? "" : "no ", | ||
1877 | data[0] & (1 << 11) ? "" : "no "); | ||
1878 | instr_out(data, hw_offset, 1, "destination address\n"); | ||
1879 | instr_out(data, hw_offset, 2, "immediate dword low\n"); | ||
1880 | instr_out(data, hw_offset, 3, "immediate dword high\n"); | ||
1881 | return len; | ||
1882 | |||
1883 | case 0x7b00: | ||
1884 | len = (data[0] & 0xff) + 2; | ||
1885 | if (len != 6) | ||
1886 | fprintf(out, "Bad count in 3DPRIMITIVE\n"); | ||
1887 | if (count < len) | ||
1888 | BUFFER_FAIL(count, len, "3DPRIMITIVE"); | ||
1889 | |||
1890 | instr_out(data, hw_offset, 0, | ||
1891 | "3DPRIMITIVE: %s %s\n", | ||
1892 | get_965_prim_type(data[0]), | ||
1893 | (data[0] & (1 << 15)) ? "random" : "sequential"); | ||
1894 | instr_out(data, hw_offset, 1, "vertex count\n"); | ||
1895 | instr_out(data, hw_offset, 2, "start vertex\n"); | ||
1896 | instr_out(data, hw_offset, 3, "instance count\n"); | ||
1897 | instr_out(data, hw_offset, 4, "start instance\n"); | ||
1898 | instr_out(data, hw_offset, 5, "index bias\n"); | ||
1899 | return len; | ||
1900 | } | ||
1901 | |||
1902 | for (idx = 0; idx < Elements(opcodes_3d); idx++) { | ||
1903 | opcode_3d = &opcodes_3d[idx]; | ||
1904 | if ((data[0] & 0xffff0000) >> 16 == opcode_3d->opcode) { | ||
1905 | unsigned int i; | ||
1906 | len = 1; | ||
1907 | |||
1908 | instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name); | ||
1909 | if (opcode_3d->max_len > 1) { | ||
1910 | len = (data[0] & 0xff) + 2; | ||
1911 | if (len < opcode_3d->min_len || | ||
1912 | len > opcode_3d->max_len) | ||
1913 | { | ||
1914 | fprintf(out, "Bad count in %s\n", opcode_3d->name); | ||
1915 | } | ||
1916 | } | ||
1917 | |||
1918 | for (i = 1; i < len; i++) { | ||
1919 | if (i >= count) | ||
1920 | BUFFER_FAIL(count, len, opcode_3d->name); | ||
1921 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
1922 | } | ||
1923 | return len; | ||
1924 | } | ||
1925 | } | ||
1926 | |||
1927 | instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_965 opcode = 0x%x\n", opcode); | ||
1928 | (*failures)++; | ||
1929 | return 1; | ||
1930 | } | ||
1931 | |||
1932 | static int | ||
1933 | decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures) | ||
1934 | { | ||
1935 | unsigned int idx; | ||
1936 | uint32_t opcode; | ||
1937 | |||
1938 | struct { | ||
1939 | uint32_t opcode; | ||
1940 | int min_len; | ||
1941 | int max_len; | ||
1942 | char *name; | ||
1943 | } opcodes_3d[] = { | ||
1944 | { 0x02, 1, 1, "3DSTATE_MODES_3" }, | ||
1945 | { 0x03, 1, 1, "3DSTATE_ENABLES_1"}, | ||
1946 | { 0x04, 1, 1, "3DSTATE_ENABLES_2"}, | ||
1947 | { 0x05, 1, 1, "3DSTATE_VFT0"}, | ||
1948 | { 0x06, 1, 1, "3DSTATE_AA"}, | ||
1949 | { 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" }, | ||
1950 | { 0x08, 1, 1, "3DSTATE_MODES_1" }, | ||
1951 | { 0x09, 1, 1, "3DSTATE_STENCIL_TEST" }, | ||
1952 | { 0x0a, 1, 1, "3DSTATE_VFT1"}, | ||
1953 | { 0x0b, 1, 1, "3DSTATE_INDPT_ALPHA_BLEND" }, | ||
1954 | { 0x0c, 1, 1, "3DSTATE_MODES_5" }, | ||
1955 | { 0x0d, 1, 1, "3DSTATE_MAP_BLEND_OP" }, | ||
1956 | { 0x0e, 1, 1, "3DSTATE_MAP_BLEND_ARG" }, | ||
1957 | { 0x0f, 1, 1, "3DSTATE_MODES_2" }, | ||
1958 | { 0x15, 1, 1, "3DSTATE_FOG_COLOR" }, | ||
1959 | { 0x16, 1, 1, "3DSTATE_MODES_4" }, | ||
1960 | }, *opcode_3d; | ||
1961 | |||
1962 | opcode = (data[0] & 0x1f000000) >> 24; | ||
1963 | |||
1964 | switch (opcode) { | ||
1965 | case 0x1f: | ||
1966 | return decode_3d_primitive(data, count, hw_offset, failures); | ||
1967 | case 0x1d: | ||
1968 | return decode_3d_1d(data, count, hw_offset, devid, failures); | ||
1969 | case 0x1c: | ||
1970 | return decode_3d_1c(data, count, hw_offset, failures); | ||
1971 | } | ||
1972 | |||
1973 | for (idx = 0; idx < Elements(opcodes_3d); idx++) { | ||
1974 | opcode_3d = &opcodes_3d[idx]; | ||
1975 | if ((data[0] & 0x1f000000) >> 24 == opcode_3d->opcode) { | ||
1976 | unsigned int len = 1, i; | ||
1977 | |||
1978 | instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name); | ||
1979 | if (opcode_3d->max_len > 1) { | ||
1980 | len = (data[0] & 0xff) + 2; | ||
1981 | if (len < opcode_3d->min_len || | ||
1982 | len > opcode_3d->max_len) | ||
1983 | { | ||
1984 | fprintf(out, "Bad count in %s\n", opcode_3d->name); | ||
1985 | } | ||
1986 | } | ||
1987 | |||
1988 | for (i = 1; i < len; i++) { | ||
1989 | if (i >= count) | ||
1990 | BUFFER_FAIL(count, len, opcode_3d->name); | ||
1991 | instr_out(data, hw_offset, i, "dword %d\n", i); | ||
1992 | } | ||
1993 | return len; | ||
1994 | } | ||
1995 | } | ||
1996 | |||
1997 | instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_i830 opcode = 0x%x\n", opcode); | ||
1998 | (*failures)++; | ||
1999 | return 1; | ||
2000 | } | ||
2001 | |||
2002 | /** | ||
2003 | * Decodes an i830-i915 batch buffer, writing the output to stdout. | ||
2004 | * | ||
2005 | * \param data batch buffer contents | ||
2006 | * \param count number of DWORDs to decode in the batch buffer | ||
2007 | * \param hw_offset hardware address for the buffer | ||
2008 | */ | ||
2009 | int | ||
2010 | intel_decode(const uint32_t *data, int count, | ||
2011 | uint32_t hw_offset, | ||
2012 | uint32_t devid, | ||
2013 | uint32_t ignore_end_of_batchbuffer) | ||
2014 | { | ||
2015 | int ret; | ||
2016 | int index = 0; | ||
2017 | int failures = 0; | ||
2018 | |||
2019 | out = stderr; | ||
2020 | |||
2021 | while (index < count) { | ||
2022 | switch ((data[index] & 0xe0000000) >> 29) { | ||
2023 | case 0x0: | ||
2024 | ret = decode_mi(data + index, count - index, | ||
2025 | hw_offset + index * 4, &failures); | ||
2026 | |||
2027 | /* If MI_BATCHBUFFER_END happened, then dump the rest of the | ||
2028 | * output in case we some day want it in debugging, but don't | ||
2029 | * decode it since it'll just confuse in the common case. | ||
2030 | */ | ||
2031 | if (ret == -1) { | ||
2032 | if (ignore_end_of_batchbuffer) { | ||
2033 | index++; | ||
2034 | } else { | ||
2035 | for (index = index + 1; index < count; index++) { | ||
2036 | instr_out(data, hw_offset, index, "\n"); | ||
2037 | } | ||
2038 | } | ||
2039 | } else | ||
2040 | index += ret; | ||
2041 | break; | ||
2042 | case 0x2: | ||
2043 | index += decode_2d(data + index, count - index, | ||
2044 | hw_offset + index * 4, &failures); | ||
2045 | break; | ||
2046 | case 0x3: | ||
2047 | if (IS_965(devid)) { | ||
2048 | index += decode_3d_965(data + index, count - index, | ||
2049 | hw_offset + index * 4, | ||
2050 | devid, &failures); | ||
2051 | } else if (IS_9XX(devid)) { | ||
2052 | index += decode_3d(data + index, count - index, | ||
2053 | hw_offset + index * 4, | ||
2054 | devid, &failures); | ||
2055 | } else { | ||
2056 | index += decode_3d_i830(data + index, count - index, | ||
2057 | hw_offset + index * 4, | ||
2058 | devid, &failures); | ||
2059 | } | ||
2060 | break; | ||
2061 | default: | ||
2062 | instr_out(data, hw_offset, index, "UNKNOWN\n"); | ||
2063 | failures++; | ||
2064 | index++; | ||
2065 | break; | ||
2066 | } | ||
2067 | fflush(out); | ||
2068 | } | ||
2069 | |||
2070 | return failures; | ||
2071 | } | ||
2072 | |||
2073 | void intel_decode_context_reset(void) | ||
2074 | { | ||
2075 | saved_s2_set = 0; | ||
2076 | saved_s4_set = 1; | ||
2077 | } | ||
2078 | |||
diff --git a/src/gallium/drivers/i965/intel_decode.h b/src/gallium/drivers/i965/intel_decode.h deleted file mode 100644 index 7e7c108c0c6..00000000000 --- a/src/gallium/drivers/i965/intel_decode.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright © 2007 Intel Corporation | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
21 | * IN THE SOFTWARE. | ||
22 | * | ||
23 | * Authors: | ||
24 | * Eric Anholt <eric@anholt.net> | ||
25 | * | ||
26 | */ | ||
27 | |||
28 | #include "pipe/p_compiler.h" | ||
29 | |||
30 | int intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, uint32_t ignore_end_of_batchbuffer); | ||
31 | void intel_decode_context_reset(void); | ||
diff --git a/src/gallium/drivers/i965/intel_structs.h b/src/gallium/drivers/i965/intel_structs.h deleted file mode 100644 index ec6eec8910f..00000000000 --- a/src/gallium/drivers/i965/intel_structs.h +++ /dev/null | |||
@@ -1,134 +0,0 @@ | |||
1 | #ifndef INTEL_STRUCTS_H | ||
2 | #define INTEL_STRUCTS_H | ||
3 | |||
4 | #include "brw_types.h" | ||
5 | |||
6 | struct br0 { | ||
7 | GLuint length:8; | ||
8 | GLuint pad0:3; | ||
9 | GLuint dst_tiled:1; | ||
10 | GLuint pad1:8; | ||
11 | GLuint write_rgb:1; | ||
12 | GLuint write_alpha:1; | ||
13 | GLuint opcode:7; | ||
14 | GLuint client:3; | ||
15 | }; | ||
16 | |||
17 | |||
18 | struct br13 { | ||
19 | GLint dest_pitch:16; | ||
20 | GLuint rop:8; | ||
21 | GLuint color_depth:2; | ||
22 | GLuint pad1:3; | ||
23 | GLuint mono_source_transparency:1; | ||
24 | GLuint clipping_enable:1; | ||
25 | GLuint pad0:1; | ||
26 | }; | ||
27 | |||
28 | |||
29 | |||
30 | /* This is an attempt to move some of the 2D interaction in this | ||
31 | * driver to using structs for packets rather than a bunch of #defines | ||
32 | * and dwords. | ||
33 | */ | ||
34 | struct xy_color_blit { | ||
35 | struct br0 br0; | ||
36 | struct br13 br13; | ||
37 | |||
38 | struct { | ||
39 | GLuint dest_x1:16; | ||
40 | GLuint dest_y1:16; | ||
41 | } dw2; | ||
42 | |||
43 | struct { | ||
44 | GLuint dest_x2:16; | ||
45 | GLuint dest_y2:16; | ||
46 | } dw3; | ||
47 | |||
48 | GLuint dest_base_addr; | ||
49 | GLuint color; | ||
50 | }; | ||
51 | |||
52 | struct xy_src_copy_blit { | ||
53 | struct br0 br0; | ||
54 | struct br13 br13; | ||
55 | |||
56 | struct { | ||
57 | GLuint dest_x1:16; | ||
58 | GLuint dest_y1:16; | ||
59 | } dw2; | ||
60 | |||
61 | struct { | ||
62 | GLuint dest_x2:16; | ||
63 | GLuint dest_y2:16; | ||
64 | } dw3; | ||
65 | |||
66 | GLuint dest_base_addr; | ||
67 | |||
68 | struct { | ||
69 | GLuint src_x1:16; | ||
70 | GLuint src_y1:16; | ||
71 | } dw5; | ||
72 | |||
73 | struct { | ||
74 | GLint src_pitch:16; | ||
75 | GLuint pad:16; | ||
76 | } dw6; | ||
77 | |||
78 | GLuint src_base_addr; | ||
79 | }; | ||
80 | |||
81 | struct xy_setup_blit { | ||
82 | struct br0 br0; | ||
83 | struct br13 br13; | ||
84 | |||
85 | struct { | ||
86 | GLuint clip_x1:16; | ||
87 | GLuint clip_y1:16; | ||
88 | } dw2; | ||
89 | |||
90 | struct { | ||
91 | GLuint clip_x2:16; | ||
92 | GLuint clip_y2:16; | ||
93 | } dw3; | ||
94 | |||
95 | GLuint dest_base_addr; | ||
96 | GLuint background_color; | ||
97 | GLuint foreground_color; | ||
98 | GLuint pattern_base_addr; | ||
99 | }; | ||
100 | |||
101 | |||
102 | struct xy_text_immediate_blit { | ||
103 | struct { | ||
104 | GLuint length:8; | ||
105 | GLuint pad2:3; | ||
106 | GLuint dst_tiled:1; | ||
107 | GLuint pad1:4; | ||
108 | GLuint byte_packed:1; | ||
109 | GLuint pad0:5; | ||
110 | GLuint opcode:7; | ||
111 | GLuint client:3; | ||
112 | } dw0; | ||
113 | |||
114 | struct { | ||
115 | GLuint dest_x1:16; | ||
116 | GLuint dest_y1:16; | ||
117 | } dw1; | ||
118 | |||
119 | struct { | ||
120 | GLuint dest_x2:16; | ||
121 | GLuint dest_y2:16; | ||
122 | } dw2; | ||
123 | |||
124 | /* Src bitmap data follows as inline dwords. | ||
125 | */ | ||
126 | }; | ||
127 | |||
128 | |||
129 | #define CLIENT_2D 0x2 | ||
130 | #define OPCODE_XY_SETUP_BLT 0x1 | ||
131 | #define OPCODE_XY_COLOR_BLT 0x50 | ||
132 | #define OPCODE_XY_TEXT_IMMEDIATE_BLT 0x31 | ||
133 | |||
134 | #endif | ||
diff --git a/src/gallium/targets/dri-i965/Makefile b/src/gallium/targets/dri-i965/Makefile deleted file mode 100644 index 9e75bfe0831..00000000000 --- a/src/gallium/targets/dri-i965/Makefile +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | TOP = ../../../.. | ||
2 | include $(TOP)/configs/current | ||
3 | |||
4 | LIBNAME = i965_dri.so | ||
5 | |||
6 | PIPE_DRIVERS = \ | ||
7 | $(TOP)/src/gallium/state_trackers/dri/drm/libdridrm.a \ | ||
8 | $(TOP)/src/gallium/winsys/i965/drm/libi965drm.a \ | ||
9 | $(TOP)/src/gallium/winsys/sw/wrapper/libwsw.a \ | ||
10 | $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \ | ||
11 | $(TOP)/src/gallium/drivers/galahad/libgalahad.a \ | ||
12 | $(TOP)/src/gallium/drivers/trace/libtrace.a \ | ||
13 | $(TOP)/src/gallium/drivers/rbug/librbug.a \ | ||
14 | $(TOP)/src/gallium/drivers/i965/libi965.a | ||
15 | |||
16 | C_SOURCES = \ | ||
17 | target.c \ | ||
18 | $(COMMON_GALLIUM_SOURCES) \ | ||
19 | $(DRIVER_SOURCES) | ||
20 | |||
21 | DRIVER_DEFINES = \ | ||
22 | -DGALLIUM_RBUG -DGALLIUM_TRACE -DGALLIUM_GALAHAD -DGALLIUM_SOFTPIPE | ||
23 | |||
24 | ifeq ($(MESA_LLVM),1) | ||
25 | PIPE_DRIVERS += $(TOP)/src/gallium/drivers/llvmpipe/libllvmpipe.a | ||
26 | DRIVER_DEFINES += -DGALLIUM_LLVMPIPE | ||
27 | endif | ||
28 | |||
29 | include ../Makefile.dri | ||
30 | |||
31 | DRI_LIB_DEPS += -ldrm_intel | ||
32 | |||
33 | symlinks: | ||
diff --git a/src/gallium/targets/dri-i965/SConscript b/src/gallium/targets/dri-i965/SConscript deleted file mode 100644 index 01a458db228..00000000000 --- a/src/gallium/targets/dri-i965/SConscript +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | Import('*') | ||
2 | |||
3 | env = drienv.Clone() | ||
4 | |||
5 | env.PkgUseModules('DRM_INTEL') | ||
6 | |||
7 | env.Append(CPPDEFINES = [ | ||
8 | 'GALLIUM_SOFTPIPE', | ||
9 | 'GALLIUM_RBUG', | ||
10 | 'GALLIUM_TRACE' | ||
11 | ]) | ||
12 | |||
13 | env.Prepend(LIBS = [ | ||
14 | st_dri, | ||
15 | i965drm, | ||
16 | ws_wrapper, | ||
17 | i965, | ||
18 | trace, | ||
19 | rbug, | ||
20 | mesa, | ||
21 | glsl, | ||
22 | gallium, | ||
23 | COMMON_DRI_DRM_OBJECTS | ||
24 | ]) | ||
25 | |||
26 | module = env.LoadableModule( | ||
27 | target = 'i965_dri.so', | ||
28 | source = 'target.c', | ||
29 | SHLIBPREFIX = '', | ||
30 | ) | ||
31 | |||
32 | env.Alias('dri-i965', module) | ||
diff --git a/src/gallium/targets/dri-i965/target.c b/src/gallium/targets/dri-i965/target.c deleted file mode 100644 index 0434063f20f..00000000000 --- a/src/gallium/targets/dri-i965/target.c +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | |||
2 | #include "target-helpers/inline_wrapper_sw_helper.h" | ||
3 | #include "target-helpers/inline_debug_helper.h" | ||
4 | #include "state_tracker/drm_driver.h" | ||
5 | #include "i965/drm/i965_drm_public.h" | ||
6 | #include "i965/brw_public.h" | ||
7 | |||
8 | static struct pipe_screen * | ||
9 | create_screen(int fd) | ||
10 | { | ||
11 | struct brw_winsys_screen *bws; | ||
12 | struct pipe_screen *screen; | ||
13 | |||
14 | bws = i965_drm_winsys_screen_create(fd); | ||
15 | if (!bws) | ||
16 | return NULL; | ||
17 | |||
18 | screen = brw_screen_create(bws); | ||
19 | if (!screen) | ||
20 | return NULL; | ||
21 | |||
22 | screen = sw_screen_wrap(screen); | ||
23 | |||
24 | screen = debug_screen_wrap(screen); | ||
25 | |||
26 | return screen; | ||
27 | } | ||
28 | |||
29 | DRM_DRIVER_DESCRIPTOR("i915", "i965", create_screen, NULL) | ||
diff --git a/src/gallium/targets/egl-static/Makefile b/src/gallium/targets/egl-static/Makefile index 17a578d43af..79a098af448 100644 --- a/src/gallium/targets/egl-static/Makefile +++ b/src/gallium/targets/egl-static/Makefile | |||
@@ -96,16 +96,6 @@ egl_LIBS += \ | |||
96 | egl_SYS += -ldrm_intel | 96 | egl_SYS += -ldrm_intel |
97 | endif | 97 | endif |
98 | 98 | ||
99 | # i965 | ||
100 | ifneq ($(findstring i965/drm,$(GALLIUM_WINSYS_DIRS)),) | ||
101 | egl_CPPFLAGS += -D_EGL_PIPE_I995=1 | ||
102 | egl_LIBS += \ | ||
103 | $(TOP)/src/gallium/winsys/i965/drm/libi965drm.a \ | ||
104 | $(TOP)/src/gallium/drivers/i965/libi965.a \ | ||
105 | $(TOP)/src/gallium/winsys/sw/wrapper/libwsw.a | ||
106 | egl_SYS += -ldrm_intel | ||
107 | endif | ||
108 | |||
109 | # nouveau | 99 | # nouveau |
110 | ifneq ($(findstring nouveau/drm,$(GALLIUM_WINSYS_DIRS)),) | 100 | ifneq ($(findstring nouveau/drm,$(GALLIUM_WINSYS_DIRS)),) |
111 | egl_CPPFLAGS += -D_EGL_PIPE_NOUVEAU=1 | 101 | egl_CPPFLAGS += -D_EGL_PIPE_NOUVEAU=1 |
diff --git a/src/gallium/targets/egl-static/SConscript b/src/gallium/targets/egl-static/SConscript index a929d600349..e657e9f2ff5 100644 --- a/src/gallium/targets/egl-static/SConscript +++ b/src/gallium/targets/egl-static/SConscript | |||
@@ -90,12 +90,10 @@ if env['HAVE_DRM']: | |||
90 | env.PkgUseModules('DRM') | 90 | env.PkgUseModules('DRM') |
91 | 91 | ||
92 | if env['HAVE_DRM_INTEL']: | 92 | if env['HAVE_DRM_INTEL']: |
93 | env.Append(CPPDEFINES = ['_EGL_PIPE_I915', '_EGL_PIPE_I965']) | 93 | env.Append(CPPDEFINES = ['_EGL_PIPE_I915']) |
94 | env.Prepend(LIBS = [ | 94 | env.Prepend(LIBS = [ |
95 | i915drm, | 95 | i915drm, |
96 | i915, | 96 | i915, |
97 | i965drm, | ||
98 | i965, | ||
99 | ws_wrapper, | 97 | ws_wrapper, |
100 | ]) | 98 | ]) |
101 | 99 | ||
diff --git a/src/gallium/targets/egl-static/egl_pipe.c b/src/gallium/targets/egl-static/egl_pipe.c index f2b50bd0eab..887bcfd12c4 100644 --- a/src/gallium/targets/egl-static/egl_pipe.c +++ b/src/gallium/targets/egl-static/egl_pipe.c | |||
@@ -32,10 +32,7 @@ | |||
32 | /* for i915 */ | 32 | /* for i915 */ |
33 | #include "i915/drm/i915_drm_public.h" | 33 | #include "i915/drm/i915_drm_public.h" |
34 | #include "i915/i915_public.h" | 34 | #include "i915/i915_public.h" |
35 | /* for i965 */ | ||
36 | #include "target-helpers/inline_wrapper_sw_helper.h" | 35 | #include "target-helpers/inline_wrapper_sw_helper.h" |
37 | #include "i965/drm/i965_drm_public.h" | ||
38 | #include "i965/brw_public.h" | ||
39 | /* for nouveau */ | 36 | /* for nouveau */ |
40 | #include "nouveau/drm/nouveau_drm_public.h" | 37 | #include "nouveau/drm/nouveau_drm_public.h" |
41 | /* for r300 */ | 38 | /* for r300 */ |
@@ -71,31 +68,6 @@ pipe_i915_create_screen(int fd) | |||
71 | } | 68 | } |
72 | 69 | ||
73 | static struct pipe_screen * | 70 | static struct pipe_screen * |
74 | pipe_i965_create_screen(int fd) | ||
75 | { | ||
76 | #if _EGL_PIPE_I965 | ||
77 | struct brw_winsys_screen *bws; | ||
78 | struct pipe_screen *screen; | ||
79 | |||
80 | bws = i965_drm_winsys_screen_create(fd); | ||
81 | if (!bws) | ||
82 | return NULL; | ||
83 | |||
84 | screen = brw_screen_create(bws); | ||
85 | if (!screen) | ||
86 | return NULL; | ||
87 | |||
88 | screen = sw_screen_wrap(screen); | ||
89 | |||
90 | screen = debug_screen_wrap(screen); | ||
91 | |||
92 | return screen; | ||
93 | #else | ||
94 | return NULL; | ||
95 | #endif | ||
96 | } | ||
97 | |||
98 | static struct pipe_screen * | ||
99 | pipe_nouveau_create_screen(int fd) | 71 | pipe_nouveau_create_screen(int fd) |
100 | { | 72 | { |
101 | #if _EGL_PIPE_NOUVEAU | 73 | #if _EGL_PIPE_NOUVEAU |
@@ -187,8 +159,6 @@ egl_pipe_create_drm_screen(const char *name, int fd) | |||
187 | { | 159 | { |
188 | if (strcmp(name, "i915") == 0) | 160 | if (strcmp(name, "i915") == 0) |
189 | return pipe_i915_create_screen(fd); | 161 | return pipe_i915_create_screen(fd); |
190 | else if (strcmp(name, "i965") == 0) | ||
191 | return pipe_i965_create_screen(fd); | ||
192 | else if (strcmp(name, "nouveau") == 0) | 162 | else if (strcmp(name, "nouveau") == 0) |
193 | return pipe_nouveau_create_screen(fd); | 163 | return pipe_nouveau_create_screen(fd); |
194 | else if (strcmp(name, "r300") == 0) | 164 | else if (strcmp(name, "r300") == 0) |
diff --git a/src/gallium/targets/gbm/Makefile b/src/gallium/targets/gbm/Makefile index 15618a6f126..89fddfe9a7b 100644 --- a/src/gallium/targets/gbm/Makefile +++ b/src/gallium/targets/gbm/Makefile | |||
@@ -59,13 +59,6 @@ i915_LIBS = \ | |||
59 | $(TOP)/src/gallium/drivers/i915/libi915.a | 59 | $(TOP)/src/gallium/drivers/i915/libi915.a |
60 | i915_SYS = -ldrm_intel | 60 | i915_SYS = -ldrm_intel |
61 | 61 | ||
62 | # i965 pipe driver | ||
63 | i965_LIBS = \ | ||
64 | $(TOP)/src/gallium/winsys/i965/drm/libi965drm.a \ | ||
65 | $(TOP)/src/gallium/drivers/i965/libi965.a \ | ||
66 | $(TOP)/src/gallium/winsys/sw/wrapper/libwsw.a | ||
67 | i965_SYS = -ldrm_intel | ||
68 | |||
69 | # nouveau pipe driver | 62 | # nouveau pipe driver |
70 | nouveau_LIBS = \ | 63 | nouveau_LIBS = \ |
71 | $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ | 64 | $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ |
@@ -112,11 +105,6 @@ _pipe_TARGETS_CC += $(PIPE_PREFIX)i915.so | |||
112 | pipe_SOURCES += pipe_i915.c | 105 | pipe_SOURCES += pipe_i915.c |
113 | endif | 106 | endif |
114 | 107 | ||
115 | ifneq ($(findstring i965/drm,$(GALLIUM_WINSYS_DIRS)),) | ||
116 | _pipe_TARGETS_CC += $(PIPE_PREFIX)i965.so | ||
117 | pipe_SOURCES += pipe_i965.c | ||
118 | endif | ||
119 | |||
120 | ifneq ($(findstring nouveau/drm,$(GALLIUM_WINSYS_DIRS)),) | 108 | ifneq ($(findstring nouveau/drm,$(GALLIUM_WINSYS_DIRS)),) |
121 | _pipe_TARGETS_CXX += $(PIPE_PREFIX)nouveau.so | 109 | _pipe_TARGETS_CXX += $(PIPE_PREFIX)nouveau.so |
122 | pipe_SOURCES += pipe_nouveau.c | 110 | pipe_SOURCES += pipe_nouveau.c |
diff --git a/src/gallium/targets/gbm/pipe_i965.c b/src/gallium/targets/gbm/pipe_i965.c deleted file mode 100644 index 1eece9ce4b4..00000000000 --- a/src/gallium/targets/gbm/pipe_i965.c +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | |||
2 | #include "target-helpers/inline_debug_helper.h" | ||
3 | #include "target-helpers/inline_wrapper_sw_helper.h" | ||
4 | #include "state_tracker/drm_driver.h" | ||
5 | #include "i965/drm/i965_drm_public.h" | ||
6 | #include "i965/brw_public.h" | ||
7 | |||
8 | static struct pipe_screen * | ||
9 | create_screen(int fd) | ||
10 | { | ||
11 | struct brw_winsys_screen *bws; | ||
12 | struct pipe_screen *screen; | ||
13 | |||
14 | bws = i965_drm_winsys_screen_create(fd); | ||
15 | if (!bws) | ||
16 | return NULL; | ||
17 | |||
18 | screen = brw_screen_create(bws); | ||
19 | if (!screen) | ||
20 | return NULL; | ||
21 | |||
22 | screen = sw_screen_wrap(screen); | ||
23 | |||
24 | screen = debug_screen_wrap(screen); | ||
25 | |||
26 | return screen; | ||
27 | } | ||
28 | |||
29 | PUBLIC | ||
30 | DRM_DRIVER_DESCRIPTOR("i965", "i965", create_screen, NULL) | ||
diff --git a/src/gallium/targets/xorg-i965/Makefile b/src/gallium/targets/xorg-i965/Makefile deleted file mode 100644 index 36df276cb71..00000000000 --- a/src/gallium/targets/xorg-i965/Makefile +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | TOP = ../../../.. | ||
2 | include $(TOP)/configs/current | ||
3 | |||
4 | LIBNAME = i965g_drv.so | ||
5 | |||
6 | C_SOURCES = \ | ||
7 | intel_target.c \ | ||
8 | intel_xorg.c | ||
9 | |||
10 | DRIVER_DEFINES = \ | ||
11 | -DHAVE_CONFIG_H -DGALLIUM_SOFTPIPE \ | ||
12 | -DGALLIUM_RBUG -DGALLIUM_TRACE | ||
13 | |||
14 | DRIVER_PIPES = \ | ||
15 | $(TOP)/src/gallium/state_trackers/xorg/libxorgtracker.a \ | ||
16 | $(TOP)/src/gallium/winsys/i965/drm/libi965drm.a \ | ||
17 | $(TOP)/src/gallium/drivers/i965/libi965.a \ | ||
18 | $(TOP)/src/gallium/drivers/trace/libtrace.a \ | ||
19 | $(TOP)/src/gallium/drivers/rbug/librbug.a \ | ||
20 | $(TOP)/src/gallium/winsys/sw/wrapper/libwsw.a \ | ||
21 | $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a | ||
22 | |||
23 | DRIVER_LINKS = \ | ||
24 | $(shell $(PKG_CONFIG) --libs libdrm libdrm_intel) | ||
25 | |||
26 | include ../Makefile.xorg | ||
diff --git a/src/gallium/targets/xorg-i965/intel_target.c b/src/gallium/targets/xorg-i965/intel_target.c deleted file mode 100644 index 0434063f20f..00000000000 --- a/src/gallium/targets/xorg-i965/intel_target.c +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | |||
2 | #include "target-helpers/inline_wrapper_sw_helper.h" | ||
3 | #include "target-helpers/inline_debug_helper.h" | ||
4 | #include "state_tracker/drm_driver.h" | ||
5 | #include "i965/drm/i965_drm_public.h" | ||
6 | #include "i965/brw_public.h" | ||
7 | |||
8 | static struct pipe_screen * | ||
9 | create_screen(int fd) | ||
10 | { | ||
11 | struct brw_winsys_screen *bws; | ||
12 | struct pipe_screen *screen; | ||
13 | |||
14 | bws = i965_drm_winsys_screen_create(fd); | ||
15 | if (!bws) | ||
16 | return NULL; | ||
17 | |||
18 | screen = brw_screen_create(bws); | ||
19 | if (!screen) | ||
20 | return NULL; | ||
21 | |||
22 | screen = sw_screen_wrap(screen); | ||
23 | |||
24 | screen = debug_screen_wrap(screen); | ||
25 | |||
26 | return screen; | ||
27 | } | ||
28 | |||
29 | DRM_DRIVER_DESCRIPTOR("i915", "i965", create_screen, NULL) | ||
diff --git a/src/gallium/targets/xorg-i965/intel_xorg.c b/src/gallium/targets/xorg-i965/intel_xorg.c deleted file mode 100644 index f4608f0eb41..00000000000 --- a/src/gallium/targets/xorg-i965/intel_xorg.c +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the | ||
7 | * "Software"), to deal in the Software without restriction, including | ||
8 | * without limitation the rights to use, copy, modify, merge, publish, | ||
9 | * distribute, sub license, and/or sell copies of the Software, and to | ||
10 | * permit persons to whom the Software is furnished to do so, subject to | ||
11 | * the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice (including the | ||
14 | * next paragraph) shall be included in all copies or substantial portions | ||
15 | * of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
24 | * | ||
25 | * | ||
26 | * Author: Alan Hourihane <alanh@tungstengraphics.com> | ||
27 | * Author: Jakob Bornecrantz <wallbraker@gmail.com> | ||
28 | * | ||
29 | */ | ||
30 | |||
31 | #include "../../state_trackers/xorg/xorg_winsys.h" | ||
32 | |||
33 | static void intel_xorg_identify(int flags); | ||
34 | static Bool intel_xorg_pci_probe(DriverPtr driver, | ||
35 | int entity_num, | ||
36 | struct pci_device *device, | ||
37 | intptr_t match_data); | ||
38 | |||
39 | static const struct pci_id_match intel_xorg_device_match[] = { | ||
40 | {0x8086, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0}, | ||
41 | {0, 0, 0}, | ||
42 | }; | ||
43 | |||
44 | static SymTabRec intel_xorg_chipsets[] = { | ||
45 | {PCI_MATCH_ANY, "Intel Graphics Device"}, | ||
46 | {-1, NULL} | ||
47 | }; | ||
48 | |||
49 | static PciChipsets intel_xorg_pci_devices[] = { | ||
50 | {PCI_MATCH_ANY, PCI_MATCH_ANY, NULL}, | ||
51 | {-1, -1, NULL} | ||
52 | }; | ||
53 | |||
54 | static XF86ModuleVersionInfo intel_xorg_version = { | ||
55 | "modesetting", | ||
56 | MODULEVENDORSTRING, | ||
57 | MODINFOSTRING1, | ||
58 | MODINFOSTRING2, | ||
59 | XORG_VERSION_CURRENT, | ||
60 | 0, 1, 0, /* major, minor, patch */ | ||
61 | ABI_CLASS_VIDEODRV, | ||
62 | ABI_VIDEODRV_VERSION, | ||
63 | MOD_CLASS_VIDEODRV, | ||
64 | {0, 0, 0, 0} | ||
65 | }; | ||
66 | |||
67 | /* | ||
68 | * Xorg driver exported structures | ||
69 | */ | ||
70 | |||
71 | _X_EXPORT DriverRec modesetting = { | ||
72 | 1, | ||
73 | "modesetting", | ||
74 | intel_xorg_identify, | ||
75 | NULL, | ||
76 | xorg_tracker_available_options, | ||
77 | NULL, | ||
78 | 0, | ||
79 | NULL, | ||
80 | intel_xorg_device_match, | ||
81 | intel_xorg_pci_probe | ||
82 | }; | ||
83 | |||
84 | static MODULESETUPPROTO(intel_xorg_setup); | ||
85 | |||
86 | _X_EXPORT XF86ModuleData modesettingModuleData = { | ||
87 | &intel_xorg_version, | ||
88 | intel_xorg_setup, | ||
89 | NULL | ||
90 | }; | ||
91 | |||
92 | /* | ||
93 | * Xorg driver functions | ||
94 | */ | ||
95 | |||
96 | static pointer | ||
97 | intel_xorg_setup(pointer module, pointer opts, int *errmaj, int *errmin) | ||
98 | { | ||
99 | static Bool setupDone = 0; | ||
100 | |||
101 | /* This module should be loaded only once, but check to be sure. | ||
102 | */ | ||
103 | if (!setupDone) { | ||
104 | setupDone = 1; | ||
105 | xf86AddDriver(&modesetting, module, HaveDriverFuncs); | ||
106 | |||
107 | /* | ||
108 | * The return value must be non-NULL on success even though there | ||
109 | * is no TearDownProc. | ||
110 | */ | ||
111 | return (pointer) 1; | ||
112 | } else { | ||
113 | if (errmaj) | ||
114 | *errmaj = LDR_ONCEONLY; | ||
115 | return NULL; | ||
116 | } | ||
117 | } | ||
118 | |||
119 | static void | ||
120 | intel_xorg_identify(int flags) | ||
121 | { | ||
122 | xf86PrintChipsets("modesetting", "Driver for Modesetting Kernel Drivers", | ||
123 | intel_xorg_chipsets); | ||
124 | } | ||
125 | |||
126 | static Bool | ||
127 | intel_xorg_pci_probe(DriverPtr driver, | ||
128 | int entity_num, struct pci_device *device, intptr_t match_data) | ||
129 | { | ||
130 | ScrnInfoPtr scrn = NULL; | ||
131 | EntityInfoPtr entity; | ||
132 | |||
133 | scrn = xf86ConfigPciEntity(scrn, 0, entity_num, intel_xorg_pci_devices, | ||
134 | NULL, NULL, NULL, NULL, NULL); | ||
135 | if (scrn != NULL) { | ||
136 | scrn->driverVersion = 1; | ||
137 | scrn->driverName = "i965"; | ||
138 | scrn->name = "modesetting"; | ||
139 | scrn->Probe = NULL; | ||
140 | |||
141 | entity = xf86GetEntityInfo(entity_num); | ||
142 | |||
143 | /* Use all the functions from the xorg tracker */ | ||
144 | xorg_tracker_set_functions(scrn); | ||
145 | } | ||
146 | return scrn != NULL; | ||
147 | } | ||
diff --git a/src/gallium/winsys/SConscript b/src/gallium/winsys/SConscript index ee86ba4cd0b..f3a2453e834 100644 --- a/src/gallium/winsys/SConscript +++ b/src/gallium/winsys/SConscript | |||
@@ -31,9 +31,5 @@ if env['dri']: | |||
31 | ]) | 31 | ]) |
32 | 32 | ||
33 | SConscript([ | 33 | SConscript([ |
34 | 'i965/drm/SConscript', | ||
35 | ]) | ||
36 | |||
37 | SConscript([ | ||
38 | 'radeon/drm/SConscript', | 34 | 'radeon/drm/SConscript', |
39 | ]) | 35 | ]) |
diff --git a/src/gallium/winsys/i965/drm/Makefile b/src/gallium/winsys/i965/drm/Makefile deleted file mode 100644 index 830007ed478..00000000000 --- a/src/gallium/winsys/i965/drm/Makefile +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | TOP = ../../../../.. | ||
2 | include $(TOP)/configs/current | ||
3 | |||
4 | LIBNAME = i965drm | ||
5 | |||
6 | C_SOURCES = \ | ||
7 | i965_drm_buffer.c \ | ||
8 | i965_drm_winsys.c | ||
9 | |||
10 | LIBRARY_INCLUDES = $(shell $(PKG_CONFIG) libdrm --cflags-only-I) | ||
11 | |||
12 | LIBRARY_DEFINES = $(shell $(PKG_CONFIG) --cflags-only-other) | ||
13 | |||
14 | include ../../../Makefile.template | ||
diff --git a/src/gallium/winsys/i965/drm/SConscript b/src/gallium/winsys/i965/drm/SConscript deleted file mode 100644 index a0f32ded402..00000000000 --- a/src/gallium/winsys/i965/drm/SConscript +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Import('*') | ||
2 | |||
3 | env = env.Clone() | ||
4 | |||
5 | env.PkgUseModules('DRM') | ||
6 | |||
7 | i965drm_sources = [ | ||
8 | 'i965_drm_buffer.c', | ||
9 | 'i965_drm_winsys.c', | ||
10 | ] | ||
11 | |||
12 | i965drm = env.ConvenienceLibrary( | ||
13 | target ='i965drm', | ||
14 | source = i965drm_sources, | ||
15 | ) | ||
16 | |||
17 | Export('i965drm') | ||
diff --git a/src/gallium/winsys/i965/drm/i965_drm_buffer.c b/src/gallium/winsys/i965/drm/i965_drm_buffer.c deleted file mode 100644 index a904179eeb9..00000000000 --- a/src/gallium/winsys/i965/drm/i965_drm_buffer.c +++ /dev/null | |||
@@ -1,503 +0,0 @@ | |||
1 | |||
2 | #include "state_tracker/drm_driver.h" | ||
3 | #include "i965_drm_winsys.h" | ||
4 | #include "util/u_memory.h" | ||
5 | #include "util/u_inlines.h" | ||
6 | |||
7 | #include "i915_drm.h" | ||
8 | #include "intel_bufmgr.h" | ||
9 | |||
10 | |||
11 | |||
12 | const char *names[BRW_BUFFER_TYPE_MAX] = { | ||
13 | "TEXTURE", | ||
14 | "SCANOUT", | ||
15 | "VERTEX", | ||
16 | "CURBE", | ||
17 | "QUERY", | ||
18 | "SHADER_CONSTANTS", | ||
19 | "WM_SCRATCH", | ||
20 | "BATCH", | ||
21 | "GENERAL_STATE", | ||
22 | "SURFACE_STATE", | ||
23 | "PIXEL", | ||
24 | "GENERIC", | ||
25 | }; | ||
26 | |||
27 | const char *usages[BRW_USAGE_MAX] = { | ||
28 | "STATE", | ||
29 | "QUERY_RESULT", | ||
30 | "RENDER_TARGET", | ||
31 | "DEPTH_BUFFER", | ||
32 | "BLIT_SOURCE", | ||
33 | "BLIT_DEST", | ||
34 | "SAMPLER", | ||
35 | "VERTEX", | ||
36 | "SCRATCH" | ||
37 | }; | ||
38 | |||
39 | |||
40 | const char *data_types[BRW_DATA_MAX] = | ||
41 | { | ||
42 | "GS: CC_VP", | ||
43 | "GS: CC_UNIT", | ||
44 | "GS: WM_PROG", | ||
45 | "GS: SAMPLER_DEFAULT_COLOR", | ||
46 | "GS: SAMPLER", | ||
47 | "GS: WM_UNIT", | ||
48 | "GS: SF_PROG", | ||
49 | "GS: SF_VP", | ||
50 | "GS: SF_UNIT", | ||
51 | "GS: VS_UNIT", | ||
52 | "GS: VS_PROG", | ||
53 | "GS: GS_UNIT", | ||
54 | "GS: GS_PROG", | ||
55 | "GS: CLIP_VP", | ||
56 | "GS: CLIP_UNIT", | ||
57 | "GS: CLIP_PROG", | ||
58 | "SS: SURFACE", | ||
59 | "SS: SURF_BIND", | ||
60 | "CONSTANT DATA", | ||
61 | "BATCH DATA", | ||
62 | "(untyped)" | ||
63 | }; | ||
64 | |||
65 | static enum pipe_error | ||
66 | i965_libdrm_bo_alloc(struct brw_winsys_screen *sws, | ||
67 | enum brw_buffer_type type, | ||
68 | unsigned size, | ||
69 | unsigned alignment, | ||
70 | struct brw_winsys_buffer **bo_out) | ||
71 | { | ||
72 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(sws); | ||
73 | struct i965_libdrm_buffer *buf; | ||
74 | |||
75 | if (BRW_DUMP) | ||
76 | debug_printf("%s type %s sz %d align %d\n", | ||
77 | __FUNCTION__, names[type], size, alignment ); | ||
78 | |||
79 | buf = CALLOC_STRUCT(i965_libdrm_buffer); | ||
80 | if (!buf) | ||
81 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
82 | |||
83 | switch (type) { | ||
84 | case BRW_BUFFER_TYPE_TEXTURE: | ||
85 | /* case BRW_BUFFER_TYPE_SCANOUT:*/ | ||
86 | case BRW_BUFFER_TYPE_VERTEX: | ||
87 | case BRW_BUFFER_TYPE_CURBE: | ||
88 | case BRW_BUFFER_TYPE_QUERY: | ||
89 | case BRW_BUFFER_TYPE_SHADER_CONSTANTS: | ||
90 | case BRW_BUFFER_TYPE_SHADER_SCRATCH: | ||
91 | case BRW_BUFFER_TYPE_BATCH: | ||
92 | case BRW_BUFFER_TYPE_GENERAL_STATE: | ||
93 | case BRW_BUFFER_TYPE_SURFACE_STATE: | ||
94 | case BRW_BUFFER_TYPE_PIXEL: | ||
95 | case BRW_BUFFER_TYPE_GENERIC: | ||
96 | break; | ||
97 | case BRW_BUFFER_TYPE_SCANOUT: | ||
98 | buf->map_gtt = TRUE; | ||
99 | break; | ||
100 | default: | ||
101 | assert(0); | ||
102 | break; | ||
103 | } | ||
104 | |||
105 | buf->bo = drm_intel_bo_alloc(idws->gem, | ||
106 | names[type], | ||
107 | size, | ||
108 | alignment); | ||
109 | |||
110 | if (!buf->bo) | ||
111 | goto err; | ||
112 | |||
113 | pipe_reference_init(&buf->base.reference, 1); | ||
114 | buf->base.size = size; | ||
115 | buf->base.sws = sws; | ||
116 | |||
117 | *bo_out = &buf->base; | ||
118 | return PIPE_OK; | ||
119 | |||
120 | err: | ||
121 | assert(0); | ||
122 | FREE(buf); | ||
123 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
124 | } | ||
125 | |||
126 | static enum pipe_error | ||
127 | i965_libdrm_bo_from_handle(struct brw_winsys_screen *sws, | ||
128 | struct winsys_handle *whandle, | ||
129 | unsigned *stride, | ||
130 | unsigned *tile, | ||
131 | struct brw_winsys_buffer **bo_out) | ||
132 | { | ||
133 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(sws); | ||
134 | struct i965_libdrm_buffer *buf = CALLOC_STRUCT(i965_libdrm_buffer); | ||
135 | uint32_t swizzle = 0; | ||
136 | |||
137 | if (BRW_DUMP) | ||
138 | debug_printf("%s\n", __FUNCTION__); | ||
139 | |||
140 | if (!buf) | ||
141 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
142 | |||
143 | pipe_reference_init(&buf->base.reference, 1); | ||
144 | buf->bo = drm_intel_bo_gem_create_from_name(idws->gem, "FROM_HANDLE", whandle->handle); | ||
145 | buf->base.size = buf->bo->size; | ||
146 | buf->base.sws = &idws->base; | ||
147 | buf->flinked = TRUE; | ||
148 | buf->flink = whandle->handle; | ||
149 | |||
150 | |||
151 | if (!buf->bo) | ||
152 | goto err; | ||
153 | |||
154 | drm_intel_bo_get_tiling(buf->bo, &buf->tiling, &swizzle); | ||
155 | if (buf->tiling != 0) | ||
156 | buf->map_gtt = TRUE; | ||
157 | |||
158 | *tile = buf->tiling; | ||
159 | *stride = whandle->stride; | ||
160 | |||
161 | *bo_out = &buf->base; | ||
162 | return PIPE_OK; | ||
163 | |||
164 | err: | ||
165 | FREE(buf); | ||
166 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
167 | } | ||
168 | |||
169 | static enum pipe_error | ||
170 | i965_libdrm_bo_get_handle(struct brw_winsys_buffer *buffer, | ||
171 | struct winsys_handle *whandle, | ||
172 | unsigned stride) | ||
173 | { | ||
174 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
175 | |||
176 | if (BRW_DUMP) | ||
177 | debug_printf("%s\n", __FUNCTION__); | ||
178 | |||
179 | if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { | ||
180 | if (!buf->flinked) { | ||
181 | if (drm_intel_bo_flink(buf->bo, &buf->flink)) | ||
182 | return PIPE_ERROR_BAD_INPUT; | ||
183 | buf->flinked = TRUE; | ||
184 | } | ||
185 | |||
186 | whandle->handle = buf->flink; | ||
187 | } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { | ||
188 | whandle->handle = buf->bo->handle; | ||
189 | } else { | ||
190 | assert(!"unknown usage"); | ||
191 | return PIPE_ERROR_BAD_INPUT; | ||
192 | } | ||
193 | |||
194 | whandle->stride = stride; | ||
195 | return PIPE_OK; | ||
196 | } | ||
197 | |||
198 | static void | ||
199 | i965_libdrm_bo_destroy(struct brw_winsys_buffer *buffer) | ||
200 | { | ||
201 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
202 | |||
203 | if (BRW_DUMP) | ||
204 | debug_printf("%s\n", __FUNCTION__); | ||
205 | |||
206 | drm_intel_bo_unreference(buf->bo); | ||
207 | FREE(buffer); | ||
208 | } | ||
209 | |||
210 | static enum pipe_error | ||
211 | i965_libdrm_bo_emit_reloc(struct brw_winsys_buffer *buffer, | ||
212 | enum brw_buffer_usage usage, | ||
213 | unsigned delta, | ||
214 | unsigned offset, | ||
215 | struct brw_winsys_buffer *buffer2) | ||
216 | { | ||
217 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
218 | struct i965_libdrm_buffer *buf2 = i965_libdrm_buffer(buffer2); | ||
219 | int read, write; | ||
220 | int ret; | ||
221 | |||
222 | if (BRW_DUMP) | ||
223 | debug_printf("%s buf %p offset %x delta %x buf2 %p/%s/%s\n", | ||
224 | __FUNCTION__, (void *)buffer, | ||
225 | offset, delta, | ||
226 | (void *)buffer2, names[buf2->data_type], usages[usage]); | ||
227 | |||
228 | switch (usage) { | ||
229 | case BRW_USAGE_STATE: | ||
230 | read = I915_GEM_DOMAIN_INSTRUCTION; | ||
231 | write = 0; | ||
232 | break; | ||
233 | case BRW_USAGE_QUERY_RESULT: | ||
234 | read = I915_GEM_DOMAIN_INSTRUCTION; | ||
235 | write = I915_GEM_DOMAIN_INSTRUCTION; | ||
236 | break; | ||
237 | case BRW_USAGE_RENDER_TARGET: | ||
238 | read = I915_GEM_DOMAIN_RENDER; | ||
239 | write = 0; | ||
240 | break; | ||
241 | case BRW_USAGE_DEPTH_BUFFER: | ||
242 | read = I915_GEM_DOMAIN_RENDER; | ||
243 | write = I915_GEM_DOMAIN_RENDER; | ||
244 | break; | ||
245 | case BRW_USAGE_BLIT_SOURCE: | ||
246 | read = 0; | ||
247 | write = I915_GEM_DOMAIN_RENDER; | ||
248 | break; | ||
249 | case BRW_USAGE_BLIT_DEST: | ||
250 | read = I915_GEM_DOMAIN_RENDER; | ||
251 | write = I915_GEM_DOMAIN_RENDER; | ||
252 | break; | ||
253 | case BRW_USAGE_SAMPLER: | ||
254 | read = I915_GEM_DOMAIN_SAMPLER; | ||
255 | write = 0; | ||
256 | break; | ||
257 | case BRW_USAGE_VERTEX: | ||
258 | read = I915_GEM_DOMAIN_VERTEX; | ||
259 | write = 0; | ||
260 | break; | ||
261 | case BRW_USAGE_SCRATCH: | ||
262 | read = 0; | ||
263 | write = 0; | ||
264 | break; | ||
265 | default: | ||
266 | assert(0); | ||
267 | return -1; | ||
268 | } | ||
269 | |||
270 | /* Needed?? | ||
271 | ((uint32_t *)buf->bo->virtual)[offset/4] = (delta + | ||
272 | buf2->bo->offset); | ||
273 | */ | ||
274 | |||
275 | ret = dri_bo_emit_reloc( buf->bo, read, write, delta, offset, buf2->bo ); | ||
276 | if (ret) | ||
277 | return -1; | ||
278 | |||
279 | return 0; | ||
280 | } | ||
281 | |||
282 | static enum pipe_error | ||
283 | i965_libdrm_bo_exec(struct brw_winsys_buffer *buffer, | ||
284 | unsigned bytes_used) | ||
285 | { | ||
286 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
287 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(buffer->sws); | ||
288 | int ret; | ||
289 | |||
290 | if (BRW_DUMP) | ||
291 | debug_printf("execute buffer %p, bytes %d\n", (void *)buffer, bytes_used); | ||
292 | |||
293 | if (idws->send_cmd) { | ||
294 | ret = dri_bo_exec(buf->bo, bytes_used, NULL, 0, 0); | ||
295 | if (ret) | ||
296 | return PIPE_ERROR; | ||
297 | } | ||
298 | |||
299 | return PIPE_OK; | ||
300 | } | ||
301 | |||
302 | static enum pipe_error | ||
303 | i965_libdrm_bo_subdata(struct brw_winsys_buffer *buffer, | ||
304 | enum brw_buffer_data_type data_type, | ||
305 | size_t offset, | ||
306 | size_t size, | ||
307 | const void *data, | ||
308 | const struct brw_winsys_reloc *reloc, | ||
309 | unsigned nr_reloc) | ||
310 | { | ||
311 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
312 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(buffer->sws); | ||
313 | int ret, i; | ||
314 | |||
315 | (void)data_type; | ||
316 | |||
317 | if (BRW_DUMP) | ||
318 | debug_printf("%s buf %p off %d sz %d %s relocs: %d\n", | ||
319 | __FUNCTION__, | ||
320 | (void *)buffer, offset, size, | ||
321 | data_types[data_type], | ||
322 | nr_reloc); | ||
323 | |||
324 | if (BRW_DUMP) | ||
325 | brw_dump_data( idws->base.pci_id, | ||
326 | data_type, | ||
327 | buf->bo->offset + offset, | ||
328 | data, size, buffer->sws->gen ); | ||
329 | |||
330 | /* XXX: use bo_map_gtt/memcpy/unmap_gtt under some circumstances??? | ||
331 | */ | ||
332 | ret = drm_intel_bo_subdata(buf->bo, offset, size, (void*)data); | ||
333 | if (ret) | ||
334 | return PIPE_ERROR; | ||
335 | |||
336 | for (i = 0; i < nr_reloc; i++) { | ||
337 | i965_libdrm_bo_emit_reloc(buffer, reloc[i].usage, reloc[i].delta, | ||
338 | reloc[i].offset, reloc[i].bo); | ||
339 | } | ||
340 | |||
341 | return PIPE_OK; | ||
342 | } | ||
343 | |||
344 | static boolean | ||
345 | i965_libdrm_bo_is_busy(struct brw_winsys_buffer *buffer) | ||
346 | { | ||
347 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
348 | boolean ret; | ||
349 | |||
350 | if (BRW_DUMP) | ||
351 | debug_printf("%s %p\n", __FUNCTION__, (void *)buffer); | ||
352 | |||
353 | ret = drm_intel_bo_busy(buf->bo); | ||
354 | |||
355 | if (BRW_DUMP) | ||
356 | debug_printf(" --> %d\n", ret); | ||
357 | |||
358 | return ret; | ||
359 | } | ||
360 | |||
361 | static boolean | ||
362 | i965_libdrm_bo_references(struct brw_winsys_buffer *a, | ||
363 | struct brw_winsys_buffer *b) | ||
364 | { | ||
365 | struct i965_libdrm_buffer *bufa = i965_libdrm_buffer(a); | ||
366 | struct i965_libdrm_buffer *bufb = i965_libdrm_buffer(b); | ||
367 | boolean ret; | ||
368 | |||
369 | if (BRW_DUMP) | ||
370 | debug_printf("%s %p %p\n", __FUNCTION__, (void *)a, (void *)b); | ||
371 | |||
372 | ret = drm_intel_bo_references(bufa->bo, bufb->bo); | ||
373 | |||
374 | if (BRW_DUMP) | ||
375 | debug_printf(" --> %d\n", ret); | ||
376 | |||
377 | return ret; | ||
378 | } | ||
379 | |||
380 | /* XXX: couldn't this be handled by returning true/false on | ||
381 | * bo_emit_reloc? | ||
382 | */ | ||
383 | static enum pipe_error | ||
384 | i965_libdrm_check_aperture_space(struct brw_winsys_screen *iws, | ||
385 | struct brw_winsys_buffer **buffers, | ||
386 | unsigned count) | ||
387 | { | ||
388 | static drm_intel_bo *bos[128]; | ||
389 | int i; | ||
390 | int ret; | ||
391 | |||
392 | if (BRW_DUMP) | ||
393 | debug_printf("%s\n", __FUNCTION__); | ||
394 | |||
395 | if (count > Elements(bos)) { | ||
396 | assert(0); | ||
397 | return FALSE; | ||
398 | } | ||
399 | |||
400 | for (i = 0; i < count; i++) | ||
401 | bos[i] = i965_libdrm_buffer(buffers[i])->bo; | ||
402 | |||
403 | /* XXX: converting from ??? to pipe_error: | ||
404 | */ | ||
405 | ret = dri_bufmgr_check_aperture_space(bos, count); | ||
406 | |||
407 | if (BRW_DUMP) | ||
408 | debug_printf(" --> %d (ok == %d)\n", ret, PIPE_OK); | ||
409 | |||
410 | return ret; | ||
411 | } | ||
412 | |||
413 | static void * | ||
414 | i965_libdrm_bo_map(struct brw_winsys_buffer *buffer, | ||
415 | enum brw_buffer_data_type data_type, | ||
416 | unsigned offset, | ||
417 | unsigned length, | ||
418 | boolean write, | ||
419 | boolean discard, | ||
420 | boolean flush_explicit) | ||
421 | { | ||
422 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
423 | int ret; | ||
424 | |||
425 | |||
426 | if (BRW_DUMP) | ||
427 | debug_printf("%s %p %s %s\n", __FUNCTION__, (void *)buffer, | ||
428 | write ? "read/write" : "read", | ||
429 | write ? data_types[data_type] : ""); | ||
430 | |||
431 | if (!buf->map_count) { | ||
432 | if (buf->map_gtt) { | ||
433 | ret = drm_intel_gem_bo_map_gtt(buf->bo); | ||
434 | if (ret) | ||
435 | return NULL; | ||
436 | } | ||
437 | else { | ||
438 | ret = drm_intel_bo_map(buf->bo, write); | ||
439 | if (ret) | ||
440 | return NULL; | ||
441 | } | ||
442 | } | ||
443 | |||
444 | buf->data_type = data_type; | ||
445 | buf->map_count++; | ||
446 | return buf->bo->virtual; | ||
447 | } | ||
448 | |||
449 | static void | ||
450 | i965_libdrm_bo_flush_range(struct brw_winsys_buffer *buffer, | ||
451 | unsigned offset, | ||
452 | unsigned length) | ||
453 | { | ||
454 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
455 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(buffer->sws); | ||
456 | |||
457 | if (BRW_DUMP) | ||
458 | debug_printf("%s %s offset %d len %d\n", __FUNCTION__, | ||
459 | data_types[buf->data_type], | ||
460 | offset, length); | ||
461 | |||
462 | if (BRW_DUMP) | ||
463 | brw_dump_data( idws->base.pci_id, | ||
464 | buf->data_type, | ||
465 | buf->bo->offset + offset, | ||
466 | (char*)buf->bo->virtual + offset, | ||
467 | length, buffer->sws->gen ); | ||
468 | } | ||
469 | |||
470 | static void | ||
471 | i965_libdrm_bo_unmap(struct brw_winsys_buffer *buffer) | ||
472 | { | ||
473 | struct i965_libdrm_buffer *buf = i965_libdrm_buffer(buffer); | ||
474 | |||
475 | if (BRW_DUMP) | ||
476 | debug_printf("%s\n", __FUNCTION__); | ||
477 | |||
478 | if (--buf->map_count > 0) | ||
479 | return; | ||
480 | |||
481 | if (buf->map_gtt) | ||
482 | drm_intel_gem_bo_unmap_gtt(buf->bo); | ||
483 | else | ||
484 | drm_intel_bo_unmap(buf->bo); | ||
485 | } | ||
486 | |||
487 | void | ||
488 | i965_libdrm_winsys_init_buffer_functions(struct i965_libdrm_winsys *idws) | ||
489 | { | ||
490 | idws->base.bo_alloc = i965_libdrm_bo_alloc; | ||
491 | idws->base.bo_from_handle = i965_libdrm_bo_from_handle; | ||
492 | idws->base.bo_get_handle = i965_libdrm_bo_get_handle; | ||
493 | idws->base.bo_destroy = i965_libdrm_bo_destroy; | ||
494 | idws->base.bo_emit_reloc = i965_libdrm_bo_emit_reloc; | ||
495 | idws->base.bo_exec = i965_libdrm_bo_exec; | ||
496 | idws->base.bo_subdata = i965_libdrm_bo_subdata; | ||
497 | idws->base.bo_is_busy = i965_libdrm_bo_is_busy; | ||
498 | idws->base.bo_references = i965_libdrm_bo_references; | ||
499 | idws->base.check_aperture_space = i965_libdrm_check_aperture_space; | ||
500 | idws->base.bo_map = i965_libdrm_bo_map; | ||
501 | idws->base.bo_flush_range = i965_libdrm_bo_flush_range; | ||
502 | idws->base.bo_unmap = i965_libdrm_bo_unmap; | ||
503 | } | ||
diff --git a/src/gallium/winsys/i965/drm/i965_drm_public.h b/src/gallium/winsys/i965/drm/i965_drm_public.h deleted file mode 100644 index 2913b079747..00000000000 --- a/src/gallium/winsys/i965/drm/i965_drm_public.h +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | |||
2 | #ifndef I965_DRM_PUBLIC_H | ||
3 | #define I965_DRM_PUBLIC_H | ||
4 | |||
5 | struct brw_winsys_screen; | ||
6 | |||
7 | struct brw_winsys_screen * i965_drm_winsys_screen_create(int drmFD); | ||
8 | |||
9 | #endif | ||
diff --git a/src/gallium/winsys/i965/drm/i965_drm_winsys.c b/src/gallium/winsys/i965/drm/i965_drm_winsys.c deleted file mode 100644 index b08e622db94..00000000000 --- a/src/gallium/winsys/i965/drm/i965_drm_winsys.c +++ /dev/null | |||
@@ -1,74 +0,0 @@ | |||
1 | |||
2 | #include <stdio.h> | ||
3 | #include "state_tracker/drm_driver.h" | ||
4 | |||
5 | #include "i965_drm_winsys.h" | ||
6 | #include "i965_drm_public.h" | ||
7 | #include "util/u_memory.h" | ||
8 | |||
9 | /* | ||
10 | * Helper functions | ||
11 | */ | ||
12 | |||
13 | |||
14 | static void | ||
15 | i965_libdrm_get_device_id(unsigned int *device_id) | ||
16 | { | ||
17 | char path[512]; | ||
18 | FILE *file; | ||
19 | void *shutup_gcc; | ||
20 | |||
21 | /* | ||
22 | * FIXME: Fix this up to use a drm ioctl or whatever. | ||
23 | */ | ||
24 | |||
25 | snprintf(path, sizeof(path), "/sys/class/drm/card0/device/device"); | ||
26 | file = fopen(path, "r"); | ||
27 | if (!file) { | ||
28 | return; | ||
29 | } | ||
30 | |||
31 | shutup_gcc = fgets(path, sizeof(path), file); | ||
32 | sscanf(path, "%x", device_id); | ||
33 | fclose(file); | ||
34 | } | ||
35 | |||
36 | static void | ||
37 | i965_libdrm_winsys_destroy(struct brw_winsys_screen *iws) | ||
38 | { | ||
39 | struct i965_libdrm_winsys *idws = i965_libdrm_winsys(iws); | ||
40 | |||
41 | if (BRW_DUMP) | ||
42 | debug_printf("%s\n", __FUNCTION__); | ||
43 | |||
44 | drm_intel_bufmgr_destroy(idws->gem); | ||
45 | |||
46 | FREE(idws); | ||
47 | } | ||
48 | |||
49 | struct brw_winsys_screen * | ||
50 | i965_drm_winsys_screen_create(int drmFD) | ||
51 | { | ||
52 | struct i965_libdrm_winsys *idws; | ||
53 | |||
54 | debug_printf("%s\n", __FUNCTION__); | ||
55 | |||
56 | idws = CALLOC_STRUCT(i965_libdrm_winsys); | ||
57 | if (!idws) | ||
58 | return NULL; | ||
59 | |||
60 | i965_libdrm_get_device_id(&idws->base.pci_id); | ||
61 | |||
62 | i965_libdrm_winsys_init_buffer_functions(idws); | ||
63 | |||
64 | idws->fd = drmFD; | ||
65 | |||
66 | idws->base.destroy = i965_libdrm_winsys_destroy; | ||
67 | |||
68 | idws->gem = drm_intel_bufmgr_gem_init(idws->fd, BRW_BATCH_SIZE); | ||
69 | drm_intel_bufmgr_gem_enable_reuse(idws->gem); | ||
70 | |||
71 | idws->send_cmd = !debug_get_bool_option("BRW_NO_HW", FALSE); | ||
72 | |||
73 | return &idws->base; | ||
74 | } | ||
diff --git a/src/gallium/winsys/i965/drm/i965_drm_winsys.h b/src/gallium/winsys/i965/drm/i965_drm_winsys.h deleted file mode 100644 index 82dbe61cc51..00000000000 --- a/src/gallium/winsys/i965/drm/i965_drm_winsys.h +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | |||
2 | #ifndef INTEL_DRM_WINSYS_H | ||
3 | #define INTEL_DRM_WINSYS_H | ||
4 | |||
5 | #include "i965/brw_winsys.h" | ||
6 | |||
7 | #include "drm.h" | ||
8 | #include "intel_bufmgr.h" | ||
9 | |||
10 | |||
11 | |||
12 | /* | ||
13 | * Winsys | ||
14 | */ | ||
15 | |||
16 | |||
17 | struct i965_libdrm_winsys | ||
18 | { | ||
19 | struct brw_winsys_screen base; | ||
20 | drm_intel_bufmgr *gem; | ||
21 | |||
22 | boolean send_cmd; | ||
23 | |||
24 | int fd; /**< Drm file discriptor */ | ||
25 | }; | ||
26 | |||
27 | static INLINE struct i965_libdrm_winsys * | ||
28 | i965_libdrm_winsys(struct brw_winsys_screen *iws) | ||
29 | { | ||
30 | return (struct i965_libdrm_winsys *)iws; | ||
31 | } | ||
32 | |||
33 | void i965_libdrm_winsys_init_buffer_functions(struct i965_libdrm_winsys *idws); | ||
34 | |||
35 | |||
36 | /* Buffer. | ||
37 | */ | ||
38 | struct i965_libdrm_buffer { | ||
39 | struct brw_winsys_buffer base; | ||
40 | |||
41 | drm_intel_bo *bo; | ||
42 | |||
43 | void *ptr; | ||
44 | unsigned map_count; | ||
45 | unsigned data_type; /* valid while mapped */ | ||
46 | unsigned tiling; | ||
47 | |||
48 | boolean map_gtt; | ||
49 | boolean flinked; | ||
50 | unsigned flink; | ||
51 | }; | ||
52 | |||
53 | static INLINE struct i965_libdrm_buffer * | ||
54 | i965_libdrm_buffer(struct brw_winsys_buffer *buffer) | ||
55 | { | ||
56 | return (struct i965_libdrm_buffer *)buffer; | ||
57 | } | ||
58 | |||
59 | |||
60 | #endif | ||
diff --git a/src/gallium/winsys/i965/xlib/Makefile b/src/gallium/winsys/i965/xlib/Makefile deleted file mode 100644 index cc8249395c5..00000000000 --- a/src/gallium/winsys/i965/xlib/Makefile +++ /dev/null | |||
@@ -1,97 +0,0 @@ | |||
1 | # src/gallium/winsys/i965/xlib/Makefile | ||
2 | |||
3 | # This makefile produces a "stand-alone" libGL.so which is based on | ||
4 | # Xlib (no DRI HW acceleration) | ||
5 | |||
6 | |||
7 | TOP = ../../../../.. | ||
8 | include $(TOP)/configs/current | ||
9 | |||
10 | |||
11 | GL_MAJOR = 1 | ||
12 | GL_MINOR = 5 | ||
13 | GL_TINY = 0$(MESA_MAJOR)0$(MESA_MINOR)0$(MESA_TINY) | ||
14 | |||
15 | |||
16 | INCLUDE_DIRS = \ | ||
17 | -I$(TOP)/include \ | ||
18 | -I$(TOP)/src/mesa \ | ||
19 | -I$(TOP)/src/mesa/main \ | ||
20 | -I$(TOP)/src/gallium/include \ | ||
21 | -I$(TOP)/src/gallium/drivers \ | ||
22 | -I$(TOP)/src/gallium/drivers/i965 \ | ||
23 | -I$(TOP)/src/gallium/drivers/i965/include \ | ||
24 | -I$(TOP)/src/gallium/state_trackers/glx/xlib \ | ||
25 | -I$(TOP)/src/gallium/auxiliary \ | ||
26 | -I/usr/include/drm | ||
27 | |||
28 | XLIB_WINSYS_SOURCES = \ | ||
29 | xlib_i965.c \ | ||
30 | |||
31 | |||
32 | |||
33 | XLIB_WINSYS_OBJECTS = $(XLIB_WINSYS_SOURCES:.c=.o) | ||
34 | |||
35 | |||
36 | |||
37 | LIBS = \ | ||
38 | $(TOP)/src/gallium/drivers/i965/libi965.a \ | ||
39 | $(TOP)/src/gallium/drivers/trace/libtrace.a \ | ||
40 | $(TOP)/src/gallium/state_trackers/glx/xlib/libxlib.a \ | ||
41 | $(TOP)/src/mapi/glapi/libglapi.a \ | ||
42 | $(TOP)/src/mesa/libmesagallium.a \ | ||
43 | $(GALLIUM_AUXILIARIES) | ||
44 | |||
45 | # $(TOP)/src/gallium/drivers/i965/lib/libi9xx.a \ | ||
46 | |||
47 | .SUFFIXES : .cpp | ||
48 | |||
49 | .c.o: | ||
50 | $(CC) -c $(INCLUDE_DIRS) $(DEFINES) $(CFLAGS) $< -o $@ | ||
51 | |||
52 | .cpp.o: | ||
53 | $(CXX) -c $(INCLUDE_DIRS) $(DEFINES) $(CXXFLAGS) $< -o $@ | ||
54 | |||
55 | |||
56 | |||
57 | default: $(TOP)/$(LIB_DIR)/gallium $(TOP)/$(LIB_DIR)/gallium/$(GL_LIB_NAME) | ||
58 | |||
59 | $(TOP)/$(LIB_DIR)/gallium: | ||
60 | @ mkdir -p $(TOP)/$(LIB_DIR)/gallium | ||
61 | |||
62 | # Make the libGL.so library | ||
63 | $(TOP)/$(LIB_DIR)/gallium/$(GL_LIB_NAME): $(XLIB_WINSYS_OBJECTS) $(LIBS) Makefile | ||
64 | $(TOP)/bin/mklib -o $(GL_LIB) \ | ||
65 | -linker "$(CC)" \ | ||
66 | -major $(GL_MAJOR) -minor $(GL_MINOR) -patch $(GL_TINY) \ | ||
67 | -install $(TOP)/$(LIB_DIR)/gallium \ | ||
68 | $(MKLIB_OPTIONS) $(XLIB_WINSYS_OBJECTS) \ | ||
69 | -Wl,--start-group $(LIBS) -Wl,--end-group $(GL_LIB_DEPS) | ||
70 | |||
71 | |||
72 | depend: $(XLIB_WINSYS_SOURCES) | ||
73 | @ echo "running $(MKDEP)" | ||
74 | @ rm -f depend # workaround oops on gutsy?!? | ||
75 | @ touch depend | ||
76 | $(MKDEP) $(MKDEP_OPTIONS) $(DEFINES) $(INCLUDE_DIRS) $(XLIB_WINSYS_SOURCES) \ | ||
77 | > /dev/null 2>/dev/null | ||
78 | |||
79 | |||
80 | install: default | ||
81 | $(INSTALL) -d $(INSTALL_DIR)/include/GL | ||
82 | $(INSTALL) -d $(INSTALL_DIR)/$(LIB_DIR) | ||
83 | $(INSTALL) -m 644 $(TOP)/include/GL/*.h $(INSTALL_DIR)/include/GL | ||
84 | @if [ -e $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME) ]; then \ | ||
85 | $(MINSTALL) $(TOP)/$(LIB_DIR)/libGL* $(INSTALL_DIR)/$(LIB_DIR); \ | ||
86 | fi | ||
87 | |||
88 | |||
89 | # Emacs tags | ||
90 | tags: | ||
91 | etags `find . -name \*.[ch]` $(TOP)/include/GL/*.h | ||
92 | |||
93 | clean: | ||
94 | -rm -f *.o | ||
95 | |||
96 | |||
97 | include depend | ||
diff --git a/src/gallium/winsys/i965/xlib/xlib_i965.c b/src/gallium/winsys/i965/xlib/xlib_i965.c deleted file mode 100644 index c22df6643aa..00000000000 --- a/src/gallium/winsys/i965/xlib/xlib_i965.c +++ /dev/null | |||
@@ -1,508 +0,0 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2007 Tungsten Graphics, Inc., Bismarck, ND., USA | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
18 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
19 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
20 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * The above copyright notice and this permission notice (including the | ||
23 | * next paragraph) shall be included in all copies or substantial portions | ||
24 | * of the Software. | ||
25 | * | ||
26 | * | ||
27 | **************************************************************************/ | ||
28 | |||
29 | /* | ||
30 | * Authors: | ||
31 | * Keith Whitwell | ||
32 | * Brian Paul | ||
33 | */ | ||
34 | |||
35 | |||
36 | #include "util/u_memory.h" | ||
37 | #include "util/u_math.h" | ||
38 | #include "pipe/p_error.h" | ||
39 | #include "pipe/p_context.h" | ||
40 | |||
41 | #include "xm_public.h" | ||
42 | |||
43 | #include "i965/brw_winsys.h" | ||
44 | #include "i965/brw_screen.h" | ||
45 | #include "i965/brw_resource.h" | ||
46 | #include "i965/brw_reg.h" | ||
47 | #include "i965/brw_structs_dump.h" | ||
48 | |||
49 | #define MAX_VRAM (128*1024*1024) | ||
50 | |||
51 | |||
52 | |||
53 | extern int brw_disasm (FILE *file, | ||
54 | const struct brw_instruction *inst, | ||
55 | unsigned count ); | ||
56 | |||
57 | extern int intel_decode(const uint32_t *data, | ||
58 | int count, | ||
59 | uint32_t hw_offset, | ||
60 | uint32_t devid); | ||
61 | |||
62 | struct xlib_brw_buffer | ||
63 | { | ||
64 | struct brw_winsys_buffer base; | ||
65 | char *virtual; | ||
66 | unsigned offset; | ||
67 | unsigned type; | ||
68 | int map_count; | ||
69 | boolean modified; | ||
70 | }; | ||
71 | |||
72 | |||
73 | /** | ||
74 | * Subclass of brw_winsys_screen for Xlib winsys | ||
75 | */ | ||
76 | struct xlib_brw_winsys | ||
77 | { | ||
78 | struct brw_winsys_screen base; | ||
79 | struct brw_chipset chipset; | ||
80 | |||
81 | unsigned size; | ||
82 | unsigned used; | ||
83 | }; | ||
84 | |||
85 | static struct xlib_brw_winsys * | ||
86 | xlib_brw_winsys( struct brw_winsys_screen *screen ) | ||
87 | { | ||
88 | return (struct xlib_brw_winsys *)screen; | ||
89 | } | ||
90 | |||
91 | |||
92 | static struct xlib_brw_buffer * | ||
93 | xlib_brw_buffer( struct brw_winsys_buffer *buffer ) | ||
94 | { | ||
95 | return (struct xlib_brw_buffer *)buffer; | ||
96 | } | ||
97 | |||
98 | |||
99 | |||
100 | const char *names[BRW_BUFFER_TYPE_MAX] = { | ||
101 | "TEXTURE", | ||
102 | "SCANOUT", | ||
103 | "VERTEX", | ||
104 | "CURBE", | ||
105 | "QUERY", | ||
106 | "SHADER_CONSTANTS", | ||
107 | "WM_SCRATCH", | ||
108 | "BATCH", | ||
109 | "GENERAL_STATE", | ||
110 | "SURFACE_STATE", | ||
111 | "PIXEL", | ||
112 | "GENERIC", | ||
113 | }; | ||
114 | |||
115 | const char *usages[BRW_USAGE_MAX] = { | ||
116 | "STATE", | ||
117 | "QUERY_RESULT", | ||
118 | "RENDER_TARGET", | ||
119 | "DEPTH_BUFFER", | ||
120 | "BLIT_SOURCE", | ||
121 | "BLIT_DEST", | ||
122 | "SAMPLER", | ||
123 | "VERTEX", | ||
124 | "SCRATCH" | ||
125 | }; | ||
126 | |||
127 | |||
128 | const char *data_types[BRW_DATA_MAX] = | ||
129 | { | ||
130 | "GS: CC_VP", | ||
131 | "GS: CC_UNIT", | ||
132 | "GS: WM_PROG", | ||
133 | "GS: SAMPLER_DEFAULT_COLOR", | ||
134 | "GS: SAMPLER", | ||
135 | "GS: WM_UNIT", | ||
136 | "GS: SF_PROG", | ||
137 | "GS: SF_VP", | ||
138 | "GS: SF_UNIT", | ||
139 | "GS: VS_UNIT", | ||
140 | "GS: VS_PROG", | ||
141 | "GS: GS_UNIT", | ||
142 | "GS: GS_PROG", | ||
143 | "GS: CLIP_VP", | ||
144 | "GS: CLIP_UNIT", | ||
145 | "GS: CLIP_PROG", | ||
146 | "SS: SURFACE", | ||
147 | "SS: SURF_BIND", | ||
148 | "CONSTANT DATA", | ||
149 | "BATCH DATA", | ||
150 | "(untyped)" | ||
151 | }; | ||
152 | |||
153 | |||
154 | static enum pipe_error | ||
155 | xlib_brw_bo_alloc( struct brw_winsys_screen *sws, | ||
156 | enum brw_buffer_type type, | ||
157 | unsigned size, | ||
158 | unsigned alignment, | ||
159 | struct brw_winsys_buffer **bo_out ) | ||
160 | { | ||
161 | struct xlib_brw_winsys *xbw = xlib_brw_winsys(sws); | ||
162 | struct xlib_brw_buffer *buf; | ||
163 | |||
164 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
165 | debug_printf("%s type %s sz %d align %d\n", | ||
166 | __FUNCTION__, names[type], size, alignment ); | ||
167 | |||
168 | buf = CALLOC_STRUCT(xlib_brw_buffer); | ||
169 | if (!buf) | ||
170 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
171 | |||
172 | pipe_reference_init(&buf->base.reference, 1); | ||
173 | |||
174 | buf->offset = align(xbw->used, alignment); | ||
175 | buf->type = type; | ||
176 | buf->virtual = MALLOC(size); | ||
177 | buf->base.size = size; | ||
178 | buf->base.sws = sws; | ||
179 | |||
180 | xbw->used = align(xbw->used, alignment) + size; | ||
181 | if (xbw->used > MAX_VRAM) | ||
182 | goto err; | ||
183 | |||
184 | /* XXX: possibly rentrant call to bo_destroy: | ||
185 | */ | ||
186 | bo_reference(bo_out, &buf->base); | ||
187 | return PIPE_OK; | ||
188 | |||
189 | err: | ||
190 | assert(0); | ||
191 | FREE(buf->virtual); | ||
192 | FREE(buf); | ||
193 | return PIPE_ERROR_OUT_OF_MEMORY; | ||
194 | } | ||
195 | |||
196 | static void | ||
197 | xlib_brw_bo_destroy( struct brw_winsys_buffer *buffer ) | ||
198 | { | ||
199 | struct xlib_brw_buffer *buf = xlib_brw_buffer(buffer); | ||
200 | |||
201 | FREE(buf); | ||
202 | } | ||
203 | |||
204 | static int | ||
205 | xlib_brw_bo_emit_reloc( struct brw_winsys_buffer *buffer, | ||
206 | enum brw_buffer_usage usage, | ||
207 | unsigned delta, | ||
208 | unsigned offset, | ||
209 | struct brw_winsys_buffer *buffer2) | ||
210 | { | ||
211 | struct xlib_brw_buffer *buf = xlib_brw_buffer(buffer); | ||
212 | struct xlib_brw_buffer *buf2 = xlib_brw_buffer(buffer2); | ||
213 | |||
214 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
215 | debug_printf("%s buf %p offset %x val %x + %x buf2 %p/%s/%s\n", | ||
216 | __FUNCTION__, (void *)buffer, offset, | ||
217 | buf2->offset, delta, | ||
218 | (void *)buffer2, names[buf2->type], usages[usage]); | ||
219 | |||
220 | *(uint32_t *)(buf->virtual + offset) = buf2->offset + delta; | ||
221 | |||
222 | return 0; | ||
223 | } | ||
224 | |||
225 | static int | ||
226 | xlib_brw_bo_exec( struct brw_winsys_buffer *buffer, | ||
227 | unsigned bytes_used ) | ||
228 | { | ||
229 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
230 | debug_printf("execute buffer %p, bytes %d\n", (void *)buffer, bytes_used); | ||
231 | |||
232 | return 0; | ||
233 | } | ||
234 | |||
235 | |||
236 | |||
237 | |||
238 | static int | ||
239 | xlib_brw_bo_subdata(struct brw_winsys_buffer *buffer, | ||
240 | enum brw_buffer_data_type data_type, | ||
241 | size_t offset, | ||
242 | size_t size, | ||
243 | const void *data, | ||
244 | const struct brw_winsys_reloc *reloc, | ||
245 | unsigned nr_relocs) | ||
246 | { | ||
247 | struct xlib_brw_buffer *buf = xlib_brw_buffer(buffer); | ||
248 | struct xlib_brw_winsys *xbw = xlib_brw_winsys(buffer->sws); | ||
249 | unsigned i; | ||
250 | |||
251 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
252 | debug_printf("%s buf %p off %d sz %d %s relocs: %d\n", | ||
253 | __FUNCTION__, | ||
254 | (void *)buffer, offset, size, | ||
255 | data_types[data_type], | ||
256 | nr_relocs); | ||
257 | |||
258 | assert(buf->base.size >= offset + size); | ||
259 | memcpy(buf->virtual + offset, data, size); | ||
260 | |||
261 | /* Apply the relocations: | ||
262 | */ | ||
263 | for (i = 0; i < nr_relocs; i++) { | ||
264 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
265 | debug_printf("\treloc[%d] usage %s off %d value %x+%x\n", | ||
266 | i, usages[reloc[i].usage], reloc[i].offset, | ||
267 | xlib_brw_buffer(reloc[i].bo)->offset, reloc[i].delta); | ||
268 | |||
269 | *(unsigned *)(buf->virtual + offset + reloc[i].offset) = | ||
270 | xlib_brw_buffer(reloc[i].bo)->offset + reloc[i].delta; | ||
271 | } | ||
272 | |||
273 | if (BRW_DUMP) | ||
274 | brw_dump_data( xbw->chipset.pci_id, | ||
275 | data_type, | ||
276 | buf->offset + offset, | ||
277 | buf->virtual + offset, size ); | ||
278 | |||
279 | |||
280 | return 0; | ||
281 | } | ||
282 | |||
283 | |||
284 | static boolean | ||
285 | xlib_brw_bo_is_busy(struct brw_winsys_buffer *buffer) | ||
286 | { | ||
287 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
288 | debug_printf("%s %p\n", __FUNCTION__, (void *)buffer); | ||
289 | return TRUE; | ||
290 | } | ||
291 | |||
292 | static boolean | ||
293 | xlib_brw_bo_references(struct brw_winsys_buffer *a, | ||
294 | struct brw_winsys_buffer *b) | ||
295 | { | ||
296 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
297 | debug_printf("%s %p %p\n", __FUNCTION__, (void *)a, (void *)b); | ||
298 | return TRUE; | ||
299 | } | ||
300 | |||
301 | static enum pipe_error | ||
302 | xlib_brw_check_aperture_space( struct brw_winsys_screen *iws, | ||
303 | struct brw_winsys_buffer **buffers, | ||
304 | unsigned count ) | ||
305 | { | ||
306 | unsigned tot_size = 0; | ||
307 | unsigned i; | ||
308 | |||
309 | for (i = 0; i < count; i++) | ||
310 | tot_size += buffers[i]->size; | ||
311 | |||
312 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
313 | debug_printf("%s %d bufs, tot_size: %d kb\n", | ||
314 | __FUNCTION__, count, | ||
315 | (tot_size + 1023) / 1024); | ||
316 | |||
317 | return PIPE_OK; | ||
318 | } | ||
319 | |||
320 | static void * | ||
321 | xlib_brw_bo_map(struct brw_winsys_buffer *buffer, | ||
322 | enum brw_buffer_data_type data_type, | ||
323 | unsigned offset, | ||
324 | unsigned length, | ||
325 | boolean write, | ||
326 | boolean discard, | ||
327 | boolean explicit) | ||
328 | { | ||
329 | struct xlib_brw_buffer *buf = xlib_brw_buffer(buffer); | ||
330 | |||
331 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
332 | debug_printf("%s %p %s %s\n", __FUNCTION__, (void *)buffer, | ||
333 | write ? "read/write" : "read", | ||
334 | write ? data_types[data_type] : ""); | ||
335 | |||
336 | if (write) | ||
337 | buf->modified = 1; | ||
338 | |||
339 | buf->map_count++; | ||
340 | return buf->virtual; | ||
341 | } | ||
342 | |||
343 | |||
344 | static void | ||
345 | xlib_brw_bo_flush_range( struct brw_winsys_buffer *buffer, | ||
346 | unsigned offset, | ||
347 | unsigned length ) | ||
348 | { | ||
349 | } | ||
350 | |||
351 | |||
352 | static void | ||
353 | xlib_brw_bo_unmap(struct brw_winsys_buffer *buffer) | ||
354 | { | ||
355 | struct xlib_brw_buffer *buf = xlib_brw_buffer(buffer); | ||
356 | |||
357 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
358 | debug_printf("%s %p\n", __FUNCTION__, (void *)buffer); | ||
359 | |||
360 | --buf->map_count; | ||
361 | assert(buf->map_count >= 0); | ||
362 | |||
363 | if (buf->map_count == 0 && | ||
364 | buf->modified) { | ||
365 | |||
366 | buf->modified = 0; | ||
367 | |||
368 | /* Consider dumping new buffer contents here, using the | ||
369 | * flush-range info to minimize verbosity. | ||
370 | */ | ||
371 | } | ||
372 | } | ||
373 | |||
374 | |||
375 | static void | ||
376 | xlib_brw_bo_wait_idle( struct brw_winsys_buffer *buffer ) | ||
377 | { | ||
378 | } | ||
379 | |||
380 | |||
381 | static void | ||
382 | xlib_brw_winsys_destroy( struct brw_winsys_screen *sws ) | ||
383 | { | ||
384 | struct xlib_brw_winsys *xbw = xlib_brw_winsys(sws); | ||
385 | |||
386 | FREE(xbw); | ||
387 | } | ||
388 | |||
389 | static struct brw_winsys_screen * | ||
390 | xlib_create_brw_winsys_screen( void ) | ||
391 | { | ||
392 | struct xlib_brw_winsys *ws; | ||
393 | |||
394 | ws = CALLOC_STRUCT(xlib_brw_winsys); | ||
395 | if (!ws) | ||
396 | return NULL; | ||
397 | |||
398 | ws->used = 0; | ||
399 | ws->base.pci_id = PCI_CHIP_GM45_GM; | ||
400 | |||
401 | ws->base.destroy = xlib_brw_winsys_destroy; | ||
402 | ws->base.bo_alloc = xlib_brw_bo_alloc; | ||
403 | ws->base.bo_destroy = xlib_brw_bo_destroy; | ||
404 | ws->base.bo_emit_reloc = xlib_brw_bo_emit_reloc; | ||
405 | ws->base.bo_exec = xlib_brw_bo_exec; | ||
406 | ws->base.bo_subdata = xlib_brw_bo_subdata; | ||
407 | ws->base.bo_is_busy = xlib_brw_bo_is_busy; | ||
408 | ws->base.bo_references = xlib_brw_bo_references; | ||
409 | ws->base.check_aperture_space = xlib_brw_check_aperture_space; | ||
410 | ws->base.bo_map = xlib_brw_bo_map; | ||
411 | ws->base.bo_flush_range = xlib_brw_bo_flush_range; | ||
412 | ws->base.bo_unmap = xlib_brw_bo_unmap; | ||
413 | ws->base.bo_wait_idle = xlib_brw_bo_wait_idle; | ||
414 | |||
415 | return &ws->base; | ||
416 | } | ||
417 | |||
418 | |||
419 | /*********************************************************************** | ||
420 | * Implementation of Xlib co-state-tracker's winsys interface | ||
421 | */ | ||
422 | |||
423 | static void | ||
424 | xlib_i965_display_surface(struct xmesa_buffer *xm_buffer, | ||
425 | struct pipe_resource *resource, | ||
426 | unsigned level, unsigned layer) | ||
427 | { | ||
428 | struct brw_texture *tex = brw_texture(resource); | ||
429 | struct xlib_brw_buffer *bo = xlib_brw_buffer(tex->bo); | ||
430 | /* not sure if the resource is really useful here but | ||
431 | since it was never implemented anyway... */ | ||
432 | if (BRW_DEBUG & DEBUG_WINSYS) | ||
433 | debug_printf("%s level %u layer %u offset %x base sz %dx%d\n", __FUNCTION__, | ||
434 | level, layer, | ||
435 | bo->offset, | ||
436 | resource->width0, | ||
437 | resource->height0); | ||
438 | } | ||
439 | |||
440 | static void | ||
441 | xlib_i965_flush_frontbuffer(struct pipe_screen *screen, | ||
442 | struct pipe_resource *resource, | ||
443 | unsigned level, unsigned layer, | ||
444 | void *context_private) | ||
445 | { | ||
446 | xlib_i965_display_surface(NULL, resource, level, layer); | ||
447 | } | ||
448 | |||
449 | |||
450 | static struct pipe_screen * | ||
451 | xlib_create_i965_screen( void ) | ||
452 | { | ||
453 | struct brw_winsys_screen *winsys; | ||
454 | struct pipe_screen *screen; | ||
455 | |||
456 | winsys = xlib_create_brw_winsys_screen(); | ||
457 | if (winsys == NULL) | ||
458 | return NULL; | ||
459 | |||
460 | screen = brw_create_screen(winsys); | ||
461 | if (screen == NULL) | ||
462 | goto fail; | ||
463 | |||
464 | xlib_brw_winsys(winsys)->chipset = brw_screen(screen)->chipset; | ||
465 | |||
466 | screen->flush_frontbuffer = xlib_i965_flush_frontbuffer; | ||
467 | return screen; | ||
468 | |||
469 | fail: | ||
470 | if (winsys) | ||
471 | winsys->destroy( winsys ); | ||
472 | |||
473 | return NULL; | ||
474 | } | ||
475 | |||
476 | |||
477 | |||
478 | |||
479 | |||
480 | struct xm_driver xlib_i965_driver = | ||
481 | { | ||
482 | .create_pipe_screen = xlib_create_i965_screen, | ||
483 | .display_surface = xlib_i965_display_surface | ||
484 | }; | ||
485 | |||
486 | |||
487 | /* Register this driver at library load: | ||
488 | */ | ||
489 | static void _init( void ) __attribute__((constructor)); | ||
490 | static void _init( void ) | ||
491 | { | ||
492 | xmesa_set_driver( &xlib_i965_driver ); | ||
493 | } | ||
494 | |||
495 | |||
496 | |||
497 | /*********************************************************************** | ||
498 | * | ||
499 | * Butt-ugly hack to convince the linker not to throw away public GL | ||
500 | * symbols (they are all referenced from getprocaddress, I guess). | ||
501 | */ | ||
502 | extern void (*linker_foo(const unsigned char *procName))(); | ||
503 | extern void (*glXGetProcAddress(const unsigned char *procName))(); | ||
504 | |||
505 | extern void (*linker_foo(const unsigned char *procName))() | ||
506 | { | ||
507 | return glXGetProcAddress(procName); | ||
508 | } | ||