diff options
author | Stuart Bennett <sb476@cam.ac.uk> | 2008-01-28 22:59:26 +0000 |
---|---|---|
committer | Stuart Bennett <sb476@cam.ac.uk> | 2008-02-04 16:38:31 +0000 |
commit | a0781e762295ce3d5f6e839d437a0de505cefa3b (patch) | |
tree | 94e5a0e0b2cdff721ded7bfbc6152fcaf98c5c52 | |
parent | 733e07663e50087ca1e9af8e9b5def556521e3b5 (diff) |
nouveau: make nv34 work every time, not just every 2nd time
And make nv30_graph_init a bit more like mmio-traces
-rw-r--r-- | shared-core/nv20_graph.c | 45 |
1 files changed, 32 insertions, 13 deletions
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 37a147b5..ad73ea91 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c | |||
@@ -804,7 +804,7 @@ void nv20_graph_takedown(struct drm_device *dev) | |||
804 | int nv30_graph_init(struct drm_device *dev) | 804 | int nv30_graph_init(struct drm_device *dev) |
805 | { | 805 | { |
806 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 806 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
807 | uint32_t vramsz, tmp; | 807 | // uint32_t vramsz, tmp; |
808 | int ret, i; | 808 | int ret, i; |
809 | 809 | ||
810 | NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & | 810 | NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & |
@@ -834,6 +834,7 @@ int nv30_graph_init(struct drm_device *dev) | |||
834 | NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); | 834 | NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000); |
835 | NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); | 835 | NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); |
836 | NV_WRITE(0x400B80, 0x1003d888); | 836 | NV_WRITE(0x400B80, 0x1003d888); |
837 | NV_WRITE(0x400B84, 0x0c000000); | ||
837 | NV_WRITE(0x400098, 0x00000000); | 838 | NV_WRITE(0x400098, 0x00000000); |
838 | NV_WRITE(0x40009C, 0x0005ad00); | 839 | NV_WRITE(0x40009C, 0x0005ad00); |
839 | NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 | 840 | NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2 |
@@ -843,30 +844,47 @@ int nv30_graph_init(struct drm_device *dev) | |||
843 | NV_WRITE(0x400ba0, 0x002f8685); | 844 | NV_WRITE(0x400ba0, 0x002f8685); |
844 | NV_WRITE(0x400ba4, 0x00231f3f); | 845 | NV_WRITE(0x400ba4, 0x00231f3f); |
845 | NV_WRITE(0x4008a4, 0x40000020); | 846 | NV_WRITE(0x4008a4, 0x40000020); |
846 | NV_WRITE(0x400B84, 0x0c000000); | 847 | |
847 | NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f); | 848 | if (dev_priv->chipset == 0x34) { |
849 | NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004); | ||
850 | NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201); | ||
851 | NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008); | ||
852 | NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008); | ||
853 | NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000); | ||
854 | NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032); | ||
855 | NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004); | ||
856 | NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002); | ||
857 | } | ||
858 | |||
848 | NV_WRITE(0x4000c0, 0x00000016); | 859 | NV_WRITE(0x4000c0, 0x00000016); |
849 | 860 | ||
850 | /* copy tile info from PFB */ | 861 | /* copy tile info from PFB */ |
851 | for (i=0; i<NV10_PFB_TILE__SIZE; i++) { | 862 | for (i = 0; i < NV10_PFB_TILE__SIZE; i++) { |
852 | NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i))); | 863 | NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i))); |
853 | NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i))); | 864 | /* which is NV40_PGRAPH_TLIMIT0(i) ?? */ |
854 | NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i))); | 865 | NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i))); |
855 | NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i))); | 866 | /* which is NV40_PGRAPH_TSIZE0(i) ?? */ |
867 | NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i))); | ||
868 | /* which is NV40_PGRAPH_TILE0(i) ?? */ | ||
856 | } | 869 | } |
857 | 870 | ||
858 | NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); | 871 | NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100); |
859 | NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); | 872 | NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); |
873 | NV_WRITE(0x0040075c , 0x00000001); | ||
860 | NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); | 874 | NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); |
861 | 875 | ||
862 | /* begin RAM config */ | 876 | /* begin RAM config */ |
863 | vramsz = drm_get_resource_len(dev, 0) - 1; | 877 | // vramsz = drm_get_resource_len(dev, 0) - 1; |
864 | NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); | 878 | NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0)); |
865 | NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); | 879 | NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1)); |
866 | NV_WRITE(0x400750, 0x00EA0000); | 880 | if (dev_priv->chipset != 0x34) { |
867 | NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0)); | 881 | NV_WRITE(0x400750, 0x00EA0000); |
868 | NV_WRITE(0x400750, 0x00EA0004); | 882 | NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0)); |
869 | NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1)); | 883 | NV_WRITE(0x400750, 0x00EA0004); |
884 | NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1)); | ||
885 | } | ||
886 | |||
887 | #if 0 | ||
870 | NV_WRITE(0x400820, 0); | 888 | NV_WRITE(0x400820, 0); |
871 | NV_WRITE(0x400824, 0); | 889 | NV_WRITE(0x400824, 0); |
872 | NV_WRITE(0x400864, vramsz-1); | 890 | NV_WRITE(0x400864, vramsz-1); |
@@ -885,6 +903,7 @@ int nv30_graph_init(struct drm_device *dev) | |||
885 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); | 903 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); |
886 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); | 904 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); |
887 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); | 905 | NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); |
906 | #endif | ||
888 | 907 | ||
889 | return 0; | 908 | return 0; |
890 | } | 909 | } |