nouveau: NV40 can/should now be able to run after the blob.

- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.

2 files changed, 8 insertions, 0 deletions

diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index a2506146..283977b3 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -138,6 +138,7 @@
 #define NV40_PFB_TLIMIT(i)                                 (0x00100604 + (i*16))
 #define NV40_PFB_TSIZE(i)                                  (0x00100608 + (i*16))
 #define NV40_PFB_TSTATUS(i)                                (0x0010060C + (i*16))
+#define NV40_PFB_UNK_800                                        0x00100800
 
 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 #define NV04_PGRAPH_DEBUG_1                                0x00400084
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c
index ceae8079..ae784cb8 100644
--- a/shared-core/nv40_fb.c
+++ b/shared-core/nv40_fb.c
@@ -11,6 +11,13 @@ nv40_fb_init(struct drm_device *dev)
         int num_tiles;
         int i;
 
+        /* This is strictly a NV4x register (don't know about NV5x). */
+        /* The blob sets these to all kinds of values, and they mess up our setup. */
+        /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
+        /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
+        /* Any idea what this is? */
+        NV_WRITE(NV40_PFB_UNK_800, 0x1);
+
         switch (dev_priv->chipset) {
         case 0x40:
         case 0x45: