diff options
| author | Stuart Bennett <stuart@freedesktop.org> | 2009-03-24 16:42:36 +0000 |
|---|---|---|
| committer | Stuart Bennett <stuart@freedesktop.org> | 2009-03-25 02:50:34 +0000 |
| commit | b71f3f114e6f0e94e15958c0aa12e804392f9df2 (patch) | |
| tree | df9109eea852512e7af9debd5e76edb8f3125fe6 | |
| parent | d6ad0dba01a8246b9e7c96388f747c8ed9631ce4 (diff) | |
nouveau: use PFB_CSTATUS naming from ddx (reg introduced with nv10)
NV04 had a PFB_FIFO_DATA at the same address, which we don't use, so
remove it to reduce confusion
| -rw-r--r-- | shared-core/nouveau_mem.c | 6 | ||||
| -rw-r--r-- | shared-core/nouveau_reg.h | 8 | ||||
| -rw-r--r-- | shared-core/nv40_mc.c | 2 |
3 files changed, 7 insertions, 9 deletions
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 64125b61..6d928f45 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -300,9 +300,9 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) } else { uint64_t mem; - mem = (NV_READ(NV04_FIFO_DATA) & - NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> - NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; + mem = (NV_READ(NV10_PFB_CSTATUS) & + NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK) >> + NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT; return mem*1024*1024; } break; diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 060abe0a..eade44e5 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -11,10 +11,6 @@ # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 -#define NV04_FIFO_DATA 0x0010020c -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 - #define NV_RAMIN 0x00700000 #define NV_RAMHT_HANDLE_OFFSET 0 @@ -131,7 +127,9 @@ #define NV04_PFB_CFG0 0x00100200 #define NV04_PFB_CFG1 0x00100204 -#define NV40_PFB_020C 0x0010020C +#define NV10_PFB_CSTATUS 0x0010020C +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK 0xfff00000 +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT 20 #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) #define NV10_PFB_TILE__SIZE 8 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c index ead6f87f..cca8bf58 100644 --- a/shared-core/nv40_mc.c +++ b/shared-core/nv40_mc.c @@ -19,7 +19,7 @@ nv40_mc_init(struct drm_device *dev) case 0x46: /* G72 */ case 0x4e: case 0x4c: /* C51_G7X */ - tmp = NV_READ(NV40_PFB_020C); + tmp = NV_READ(NV10_PFB_CSTATUS); NV_WRITE(NV40_PMC_1700, tmp); NV_WRITE(NV40_PMC_1704, 0); NV_WRITE(NV40_PMC_1708, 0); |