nouveau: use consistant register access macros

We had quite a variety, name them all similarly and add a few new
ones that'll be needed for modesetting.

36 files changed, 912 insertions, 904 deletions

diff --git a/linux-core/nouveau_backlight.c b/linux-core/nouveau_backlight.c
index 51c747a3..e5aa9e03 100644
--- a/linux-core/nouveau_backlight.c
+++ b/linux-core/nouveau_backlight.c
@@ -43,7 +43,7 @@ static int nv40_get_intensity(struct backlight_device *bd)
 {
 	struct drm_device *dev = bl_get_data(bd);
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	int val = (NV_READ(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16;
+	int val = (nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16;
 
 	return val;
 }
@@ -53,9 +53,9 @@ static int nv40_set_intensity(struct backlight_device *bd)
 	struct drm_device *dev = bl_get_data(bd);
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int val = bd->props.brightness;
-	int reg = NV_READ(NV40_PMC_BACKLIGHT);
+	int reg = nv_rd32(NV40_PMC_BACKLIGHT);
 
-	NV_WRITE(NV40_PMC_BACKLIGHT,
+	nv_wr32(NV40_PMC_BACKLIGHT,
 		 (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK));
 
 	return 0;
@@ -74,7 +74,7 @@ static int nv50_get_intensity(struct backlight_device *bd)
 	struct drm_device *dev = bl_get_data(bd);
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	return NV_READ(NV50_PDISPLAY_BACKLIGHT);
+	return nv_rd32(NV50_PDISPLAY_BACKLIGHT);
 }
 
 static int nv50_set_intensity(struct backlight_device *bd)
@@ -83,7 +83,7 @@ static int nv50_set_intensity(struct backlight_device *bd)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int val = bd->props.brightness;
 
-	NV_WRITE(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE);
+	nv_wr32(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE);
 
 	return 0;
 }
@@ -101,7 +101,7 @@ static int nouveau_nv40_backlight_init(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct backlight_device *bd;
 	
-	if (!(NV_READ(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
+	if (!(nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
 		return 0;
 
 	bd = backlight_device_register("nv_backlight", &dev->pdev->dev, dev,
@@ -122,7 +122,7 @@ static int nouveau_nv50_backlight_init(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct backlight_device *bd;
 
-	if (!NV_READ(NV50_PDISPLAY_BACKLIGHT))
+	if (!nv_rd32(NV50_PDISPLAY_BACKLIGHT))
 		return 0;
 
 	bd = backlight_device_register("nv_backlight", &dev->pdev->dev, dev,
diff --git a/linux-core/nouveau_bios.c b/linux-core/nouveau_bios.c
index faa2b2b0..bcbedb7d 100644
--- a/linux-core/nouveau_bios.c
+++ b/linux-core/nouveau_bios.c
@@ -69,20 +69,20 @@ static void nv_shadow_bios_rom(struct drm_device *dev, uint8_t *data)
 	int i;
 
 	/* enable access to rom */
-	NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
+	nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
 
 	/* This is also valid for pre-NV50, it just happened to be the only define already present. */
 	for (i=0; i < NV50_PROM__ESIZE; i++) {
 		/* Appearantly needed for a 6600GT/6800LE bug. */
-		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-		data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
+		data[i] = nv_rd08(NV50_PROM + i);
+		data[i] = nv_rd08(NV50_PROM + i);
+		data[i] = nv_rd08(NV50_PROM + i);
+		data[i] = nv_rd08(NV50_PROM + i);
+		data[i] = nv_rd08(NV50_PROM + i);
 	}
 
 	/* disable access to rom */
-	NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
+	nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
 }
 
 static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data)
@@ -93,20 +93,20 @@ static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data)
 
 	/* Move the bios copy to the start of ramin? */
 	if (dev_priv->card_type >= NV_50) {
-		uint32_t vbios_vram = (NV_READ(0x619f04) & ~0xff) << 8;
+		uint32_t vbios_vram = (nv_rd32(0x619f04) & ~0xff) << 8;
 
 		if (!vbios_vram)
-			vbios_vram = (NV_READ(0x1700) << 16) + 0xf0000;
+			vbios_vram = (nv_rd32(0x1700) << 16) + 0xf0000;
 
-		old_bar0_pramin = NV_READ(0x1700);
-		NV_WRITE(0x1700, vbios_vram >> 16);
+		old_bar0_pramin = nv_rd32(0x1700);
+		nv_wr32(0x1700, vbios_vram >> 16);
 	}
 
 	for (i=0; i < NV50_PROM__ESIZE; i++)
-		data[i] = DRM_READ8(dev_priv->mmio, NV04_PRAMIN + i);
+		data[i] = nv_rd08(NV04_PRAMIN + i);
 
 	if (dev_priv->card_type >= NV_50)
-		NV_WRITE(0x1700, old_bar0_pramin);
+		nv_wr32(0x1700, old_bar0_pramin);
 }
 
 static bool nv_shadow_bios(struct drm_device *dev, uint8_t *data)
@@ -640,7 +640,7 @@ bool get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lim
 	if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
 		bios->chip_version != 0x1a && bios->chip_version != 0x20)
 		crystal_strap_mask |= 1 << 22;
-	crystal_straps = NV_READ(NV50_PEXTDEV + 0x0) & crystal_strap_mask;
+	crystal_straps = nv_rd32(NV50_PEXTDEV + 0x0) & crystal_strap_mask;
 
 	switch (pll_lim_ver) {
 	/* we use version 0 to indicate a pre limit table bios (single stage pll)
diff --git a/linux-core/nouveau_fence.c b/linux-core/nouveau_fence.c
index 3529bffb..26f98c08 100644
--- a/linux-core/nouveau_fence.c
+++ b/linux-core/nouveau_fence.c
@@ -93,7 +93,7 @@ nouveau_fence_poll(struct drm_device *dev, uint32_t class, uint32_t waiting_type
 	}
 
 	if (1) {
-		uint32_t sequence = NV_READ(chan->ref_cnt);
+		uint32_t sequence = nv_rd32(chan->ref_cnt);
 
 		DRM_DEBUG("got 0x%08x\n", sequence);
 		drm_fence_handler(dev, class, sequence, waiting_types, 0);
diff --git a/linux-core/nv50_connector.c b/linux-core/nv50_connector.c
index 9836e1b0..16ab7fbd 100644
--- a/linux-core/nv50_connector.c
+++ b/linux-core/nv50_connector.c
@@ -111,7 +111,7 @@ static int nv50_connector_hpd_detect(struct nv50_connector *connector)
 	}
 
 	/* Check hotplug pins. */
-	reg = NV_READ(NV50_PCONNECTOR_HOTPLUG_STATE);
+	reg = nv_rd32(NV50_PCONNECTOR_HOTPLUG_STATE);
 	if (reg & (NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 << (4 * connector->i2c_chan->index)))
 		present = 1;
 
diff --git a/linux-core/nv50_crtc.c b/linux-core/nv50_crtc.c
index 009219a1..37b0555e 100644
--- a/linux-core/nv50_crtc.c
+++ b/linux-core/nv50_crtc.c
@@ -401,12 +401,12 @@ static int nv50_crtc_set_clock(struct nv50_crtc *crtc)
 
 	uint32_t N1 = 0, N2 = 0, M1 = 0, M2 = 0, log2P = 0;
 
-	uint32_t reg1 = NV_READ(pll_reg + 4);
-	uint32_t reg2 = NV_READ(pll_reg + 8);
+	uint32_t reg1 = nv_rd32(pll_reg + 4);
+	uint32_t reg2 = nv_rd32(pll_reg + 8);
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(pll_reg, NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED | 0x10000011);
+	nv_wr32(pll_reg, NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED | 0x10000011);
 
 	/* The other bits are typically empty, but let's be on the safe side. */
 	reg1 &= 0xff00ff00;
@@ -420,8 +420,8 @@ static int nv50_crtc_set_clock(struct nv50_crtc *crtc)
 	reg1 |= (M1 << 16) | N1;
 	reg2 |= (log2P << 28) | (M2 << 16) | N2;
 
-	NV_WRITE(pll_reg + 4, reg1);
-	NV_WRITE(pll_reg + 8, reg2);
+	nv_wr32(pll_reg + 4, reg1);
+	nv_wr32(pll_reg + 8, reg2);
 
 	return 0;
 }
@@ -433,7 +433,7 @@ static int nv50_crtc_set_clock_mode(struct nv50_crtc *crtc)
 	DRM_DEBUG("\n");
 
 	/* This acknowledges a clock request. */
-	NV_WRITE(NV50_PDISPLAY_CRTC_CLK_CLK_CTRL2(crtc->index), 0);
+	nv_wr32(NV50_PDISPLAY_CRTC_CLK_CLK_CTRL2(crtc->index), 0);
 
 	return 0;
 }
diff --git a/linux-core/nv50_cursor.c b/linux-core/nv50_cursor.c
index f0ac73b2..073b407d 100644
--- a/linux-core/nv50_cursor.c
+++ b/linux-core/nv50_cursor.c
@@ -34,11 +34,11 @@ static int nv50_cursor_enable(struct nv50_crtc *crtc)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0x2000);
-	while(NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK);
+	nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0x2000);
+	while(nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK);
 
-	NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
-	while((NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK)
+	nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
+	while((nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK)
 		!= NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE);
 
 	crtc->cursor->enabled = true;
@@ -52,8 +52,8 @@ static int nv50_cursor_disable(struct nv50_crtc *crtc)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0);
-	while(NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK);
+	nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0);
+	while(nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK);
 
 	crtc->cursor->enabled = false;
 
@@ -98,9 +98,9 @@ static int nv50_cursor_set_pos(struct nv50_crtc *crtc, int x, int y)
 {
 	struct drm_nouveau_private *dev_priv = crtc->base.dev->dev_private;
 
-	NV_WRITE(NV50_HW_CURSOR_POS(crtc->index), ((y & 0xFFFF) << 16) | (x & 0xFFFF));
+	nv_wr32(NV50_HW_CURSOR_POS(crtc->index), ((y & 0xFFFF) << 16) | (x & 0xFFFF));
 	/* Needed to make the cursor move. */
-	NV_WRITE(NV50_HW_CURSOR_POS_CTRL(crtc->index), 0);
+	nv_wr32(NV50_HW_CURSOR_POS_CTRL(crtc->index), 0);
 
 	return 0;
 }
diff --git a/linux-core/nv50_dac.c b/linux-core/nv50_dac.c
index 0404aaca..4cd1a05f 100644
--- a/linux-core/nv50_dac.c
+++ b/linux-core/nv50_dac.c
@@ -92,7 +92,7 @@ static int nv50_dac_set_clock_mode(struct nv50_output *output)
 
 	DRM_DEBUG("or %d\n", output->or);
 
-	NV_WRITE(NV50_PDISPLAY_DAC_CLK_CLK_CTRL2(output->or),  0);
+	nv_wr32(NV50_PDISPLAY_DAC_CLK_CLK_CTRL2(output->or),  0);
 
 	return 0;
 }
@@ -106,9 +106,9 @@ static int nv50_dac_set_power_mode(struct nv50_output *output, int mode)
 	DRM_DEBUG("or %d\n", or);
 
 	/* wait for it to be done */
-	while (NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
+	while (nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
 
-	val = NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & ~0x7F;
+	val = nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & ~0x7F;
 
 	if (mode != DRM_MODE_DPMS_ON)
 		val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_BLANKED;
@@ -129,7 +129,7 @@ static int nv50_dac_set_power_mode(struct nv50_output *output, int mode)
 		break;
 	}
 
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
 
 	return 0;
 }
@@ -141,11 +141,11 @@ static int nv50_dac_detect(struct nv50_output *output)
 	uint32_t dpms_state, load_pattern, load_state;
 	int or = output->or;
 
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(or), 0x00000001);
-	dpms_state = NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or));
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(or), 0x00000001);
+	dpms_state = nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or));
 
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), 0x00150000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
-	while (NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), 0x00150000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
+	while (nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
 
 	/* Use bios provided value if possible. */
 	if (dev_priv->bios.dactestval) {
@@ -156,12 +156,12 @@ static int nv50_dac_detect(struct nv50_output *output)
 		DRM_DEBUG("Using default load_pattern of %d\n", load_pattern);
 	}
 
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_ACTIVE | load_pattern);
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_ACTIVE | load_pattern);
 	udelay(10000); /* give it some time to process */
-	load_state = NV_READ(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or));
+	load_state = nv_rd32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or));
 
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), 0);
-	NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), dpms_state);
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), 0);
+	nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), dpms_state);
 
 	if ((load_state & NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT) == NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT)
 		present = 1;
diff --git a/linux-core/nv50_display.c b/linux-core/nv50_display.c
index e0f95878..5500e201 100644
--- a/linux-core/nv50_display.c
+++ b/linux-core/nv50_display.c
@@ -40,46 +40,46 @@ static int nv50_display_pre_init(struct nv50_display *display)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(0x00610184, NV_READ(0x00614004));
+	nv_wr32(0x00610184, nv_rd32(0x00614004));
 	/*
 	 * I think the 0x006101XX range is some kind of main control area that enables things.
 	 */
 	/* CRTC? */
-	NV_WRITE(0x00610190 + 0 * 0x10, NV_READ(0x00616100 + 0 * 0x800));
-	NV_WRITE(0x00610190 + 1 * 0x10, NV_READ(0x00616100 + 1 * 0x800));
-	NV_WRITE(0x00610194 + 0 * 0x10, NV_READ(0x00616104 + 0 * 0x800));
-	NV_WRITE(0x00610194 + 1 * 0x10, NV_READ(0x00616104 + 1 * 0x800));
-	NV_WRITE(0x00610198 + 0 * 0x10, NV_READ(0x00616108 + 0 * 0x800));
-	NV_WRITE(0x00610198 + 1 * 0x10, NV_READ(0x00616108 + 1 * 0x800));
-	NV_WRITE(0x0061019c + 0 * 0x10, NV_READ(0x0061610c + 0 * 0x800));
-	NV_WRITE(0x0061019c + 1 * 0x10, NV_READ(0x0061610c + 1 * 0x800));
+	nv_wr32(0x00610190 + 0 * 0x10, nv_rd32(0x00616100 + 0 * 0x800));
+	nv_wr32(0x00610190 + 1 * 0x10, nv_rd32(0x00616100 + 1 * 0x800));
+	nv_wr32(0x00610194 + 0 * 0x10, nv_rd32(0x00616104 + 0 * 0x800));
+	nv_wr32(0x00610194 + 1 * 0x10, nv_rd32(0x00616104 + 1 * 0x800));
+	nv_wr32(0x00610198 + 0 * 0x10, nv_rd32(0x00616108 + 0 * 0x800));
+	nv_wr32(0x00610198 + 1 * 0x10, nv_rd32(0x00616108 + 1 * 0x800));
+	nv_wr32(0x0061019c + 0 * 0x10, nv_rd32(0x0061610c + 0 * 0x800));
+	nv_wr32(0x0061019c + 1 * 0x10, nv_rd32(0x0061610c + 1 * 0x800));
 	/* DAC */
-	NV_WRITE(0x006101d0 + 0 * 0x4, NV_READ(0x0061a000 + 0 * 0x800));
-	NV_WRITE(0x006101d0 + 1 * 0x4, NV_READ(0x0061a000 + 1 * 0x800));
-	NV_WRITE(0x006101d0 + 2 * 0x4, NV_READ(0x0061a000 + 2 * 0x800));
+	nv_wr32(0x006101d0 + 0 * 0x4, nv_rd32(0x0061a000 + 0 * 0x800));
+	nv_wr32(0x006101d0 + 1 * 0x4, nv_rd32(0x0061a000 + 1 * 0x800));
+	nv_wr32(0x006101d0 + 2 * 0x4, nv_rd32(0x0061a000 + 2 * 0x800));
 	/* SOR */
-	NV_WRITE(0x006101e0 + 0 * 0x4, NV_READ(0x0061c000 + 0 * 0x800));
-	NV_WRITE(0x006101e0 + 1 * 0x4, NV_READ(0x0061c000 + 1 * 0x800));
+	nv_wr32(0x006101e0 + 0 * 0x4, nv_rd32(0x0061c000 + 0 * 0x800));
+	nv_wr32(0x006101e0 + 1 * 0x4, nv_rd32(0x0061c000 + 1 * 0x800));
 	/* Something not yet in use, tv-out maybe. */
-	NV_WRITE(0x006101f0 + 0 * 0x4, NV_READ(0x0061e000 + 0 * 0x800));
-	NV_WRITE(0x006101f0 + 1 * 0x4, NV_READ(0x0061e000 + 1 * 0x800));
-	NV_WRITE(0x006101f0 + 2 * 0x4, NV_READ(0x0061e000 + 2 * 0x800));
+	nv_wr32(0x006101f0 + 0 * 0x4, nv_rd32(0x0061e000 + 0 * 0x800));
+	nv_wr32(0x006101f0 + 1 * 0x4, nv_rd32(0x0061e000 + 1 * 0x800));
+	nv_wr32(0x006101f0 + 2 * 0x4, nv_rd32(0x0061e000 + 2 * 0x800));
 
 	for (i = 0; i < 3; i++) {
-		NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
-		NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001);
+		nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
+		nv_wr32(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001);
 	}
 
 	/* This used to be in crtc unblank, but seems out of place there. */
-	NV_WRITE(NV50_PDISPLAY_UNK_380, 0);
+	nv_wr32(NV50_PDISPLAY_UNK_380, 0);
 	/* RAM is clamped to 256 MiB. */
 	ram_amount = nouveau_mem_fb_amount(display->dev);
 	DRM_DEBUG("ram_amount %d\n", ram_amount);
 	if (ram_amount > 256*1024*1024)
 		ram_amount = 256*1024*1024;
-	NV_WRITE(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
-	NV_WRITE(NV50_PDISPLAY_UNK_388, 0x150000);
-	NV_WRITE(NV50_PDISPLAY_UNK_38C, 0);
+	nv_wr32(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
+	nv_wr32(NV50_PDISPLAY_UNK_388, 0x150000);
+	nv_wr32(NV50_PDISPLAY_UNK_38C, 0);
 
 	display->preinit_done = true;
 
@@ -95,26 +95,26 @@ static int nv50_display_init(struct nv50_display *display)
 	DRM_DEBUG("\n");
 
 	/* The precise purpose is unknown, i suspect it has something to do with text mode. */
-	if (NV_READ(NV50_PDISPLAY_SUPERVISOR) & 0x100) {
-		NV_WRITE(NV50_PDISPLAY_SUPERVISOR, 0x100);
-		NV_WRITE(0x006194e8, NV_READ(0x006194e8) & ~1);
-		while (NV_READ(0x006194e8) & 2);
+	if (nv_rd32(NV50_PDISPLAY_SUPERVISOR) & 0x100) {
+		nv_wr32(NV50_PDISPLAY_SUPERVISOR, 0x100);
+		nv_wr32(0x006194e8, nv_rd32(0x006194e8) & ~1);
+		while (nv_rd32(0x006194e8) & 2);
 	}
 
 	/* taken from nv bug #12637 */
-	NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x2b00);
+	nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0x2b00);
 	do {
-		val = NV_READ(NV50_PDISPLAY_UNK200_CTRL);
+		val = nv_rd32(NV50_PDISPLAY_UNK200_CTRL);
 		if ((val & 0x9f0000) == 0x20000)
-			NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000);
+			nv_wr32(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000);
 
 		if ((val & 0x3f0000) == 0x30000)
-			NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000);
+			nv_wr32(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000);
 	} while (val & 0x1e0000);
 
-	NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
-	NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03);
-	while (!(NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000));
+	nv_wr32(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
+	nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03);
+	while (!(nv_rd32(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000));
 
 	/* For the moment this is just a wrapper, which should be replaced with a real fifo at some point. */
 	OUT_MODE(NV50_UNK84, 0);
@@ -125,10 +125,10 @@ static int nv50_display_init(struct nv50_display *display)
 	OUT_MODE(NV50_CRTC0_UNK82C, 0);
 
 	/* enable clock change interrupts. */
-	NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70);
+	nv_wr32(NV50_PDISPLAY_SUPERVISOR_INTR, nv_rd32(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70);
 
 	/* enable hotplug interrupts */
-	NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0x7FFF7FFF);
+	nv_wr32(NV50_PCONNECTOR_HOTPLUG_INTR, 0x7FFF7FFF);
 
 	display->init_done = true;
 
@@ -164,24 +164,24 @@ static int nv50_display_disable(struct nv50_display *display)
 			else
 				mask = NV50_PDISPLAY_SUPERVISOR_CRTC0;
 
-			NV_WRITE(NV50_PDISPLAY_SUPERVISOR, mask);
-			while (!(NV_READ(NV50_PDISPLAY_SUPERVISOR) & mask));
+			nv_wr32(NV50_PDISPLAY_SUPERVISOR, mask);
+			while (!(nv_rd32(NV50_PDISPLAY_SUPERVISOR) & mask));
 		}
 	}
 
-	NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0);
-	NV_WRITE(NV50_PDISPLAY_CTRL_STATE, 0);
-	while ((NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0);
+	nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0);
+	nv_wr32(NV50_PDISPLAY_CTRL_STATE, 0);
+	while ((nv_rd32(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0);
 
 	for (i = 0; i < 2; i++) {
-		while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT);
+		while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT);
 	}
 
 	/* disable clock change interrupts. */
-	NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70);
+	nv_wr32(NV50_PDISPLAY_SUPERVISOR_INTR, nv_rd32(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70);
 
 	/* disable hotplug interrupts */
-	NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0);
+	nv_wr32(NV50_PCONNECTOR_HOTPLUG_INTR, 0);
 
 	display->init_done = false;
 
@@ -415,12 +415,12 @@ void nv50_display_command(struct drm_nouveau_private *dev_priv,
 
 	DRM_DEBUG("mthd 0x%03X val 0x%08X\n", mthd, val);
 
-	NV_WRITE(NV50_PDISPLAY_CTRL_VAL, val);
-	NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING |
+	nv_wr32(NV50_PDISPLAY_CTRL_VAL, val);
+	nv_wr32(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING |
 					   NV50_PDISPLAY_CTRL_STATE_ENABLE |
 					   0x10000 | mthd);
 
-	while (NV_READ(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) {
+	while (nv_rd32(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) {
 		counter++;
 		if (counter > 1000000) {
 			DRM_ERROR("You probably need a reboot now\n");
diff --git a/linux-core/nv50_i2c.c b/linux-core/nv50_i2c.c
index 30e317c5..7a918739 100644
--- a/linux-core/nv50_i2c.c
+++ b/linux-core/nv50_i2c.c
@@ -71,7 +71,7 @@ static void nv50_i2c_set_bits(struct nv50_i2c_channel *chan, int clock_high, int
 	if (!port)
 		return;
 
-	NV_WRITE(port, 4 | (data_high << 1) | clock_high);
+	nv_wr32(port, 4 | (data_high << 1) | clock_high);
 }
 
 static void nv50_i2c_get_bits(struct nv50_i2c_channel *chan, int *clock_high, int *data_high)
@@ -83,7 +83,7 @@ static void nv50_i2c_get_bits(struct nv50_i2c_channel *chan, int *clock_high, in
 	if (!port)
 		return;
 
-	val = NV_READ(port);
+	val = nv_rd32(port);
 
 	if (val & 1)
 		*clock_high = 1;
diff --git a/linux-core/nv50_sor.c b/linux-core/nv50_sor.c
index 544af867..42d39a55 100644
--- a/linux-core/nv50_sor.c
+++ b/linux-core/nv50_sor.c
@@ -109,7 +109,7 @@ static int nv50_sor_set_clock_mode(struct nv50_output *output)
 
 	/* 0x70000 was a late addition to nv, mentioned as fixing tmds initialisation on certain gpu's. */
 	/* I presume it's some kind of clock setting, but what precisely i do not know. */
-	NV_WRITE(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0));
+	nv_wr32(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0));
 
 	return 0;
 }
@@ -123,16 +123,16 @@ static int nv50_sor_set_power_mode(struct nv50_output *output, int mode)
 	DRM_DEBUG("or %d\n", output->or);
 
 	/* wait for it to be done */
-	while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
+	while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
 
-	val = NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
+	val = nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
 
 	if (mode == DRM_MODE_DPMS_ON)
 		val |= NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
 	else
 		val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
 
-	NV_WRITE(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
+	nv_wr32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
 
 	return 0;
 }
@@ -207,10 +207,10 @@ int nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
 	if (output->base.encoder_type == DRM_MODE_ENCODER_TMDS) {
 		int or = output->or;
 
-		NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700);
-		NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f);
-		NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_014(or), 0x00000000);
-		NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_018(or), 0x00245af8);
+		nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700);
+		nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f);
+		nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_014(or), 0x00000000);
+		nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_018(or), 0x00245af8);
 	}
 
 	return 0;
diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c
index e8afda88..276575a7 100644
--- a/shared-core/nouveau_dma.c
+++ b/shared-core/nouveau_dma.c
@@ -146,8 +146,8 @@ nouveau_dma_channel_setup(struct nouveau_channel *chan)
 	return 0;
 }
 
-#define READ_GET() ((NV_READ(chan->get) - chan->pushbuf_base) >> 2)
-#define WRITE_PUT(val) NV_WRITE(chan->put, ((val) << 2) + chan->pushbuf_base)
+#define READ_GET() ((nv_rd32(chan->get) - chan->pushbuf_base) >> 2)
+#define WRITE_PUT(val) nv_wr32(chan->put, ((val) << 2) + chan->pushbuf_base)
 
 int
 nouveau_dma_wait(struct nouveau_channel *chan, int size)
diff --git a/shared-core/nouveau_dma.h b/shared-core/nouveau_dma.h
index 424716d2..21c69b1f 100644
--- a/shared-core/nouveau_dma.h
+++ b/shared-core/nouveau_dma.h
@@ -92,7 +92,7 @@ FIRE_RING(struct nouveau_channel *chan)
 
 	DRM_MEMORYBARRIER();
 	chan->dma.put = chan->dma.cur;
-	NV_WRITE(chan->put, (chan->dma.put << 2) + chan->pushbuf_base);
+	nv_wr32(chan->put, (chan->dma.put << 2) + chan->pushbuf_base);
 }
 
 /* This should allow easy switching to a real fifo in the future. */
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index e18eb5b6..b0b15a35 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -688,23 +688,31 @@ extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
 				      struct drm_file *);
 
 #if defined(__powerpc__)
-#define NV_READ(reg)        in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
-#define NV_WRITE(reg,val)   out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
+#define nv_out32(map,reg,val) out_be32((void __iomem *)(map)->handle + (reg), (val))
+#define nv_out16(map,reg,val) out_be16((void __iomem *)(map)->handle + (reg), (val))
+#define nv_in32(map,reg) in_be32((void __iomem *)(map)->handle + (reg))
+#define nv_in16(map,reg) in_be16((void __iomem *)(map)->handle + (reg))
 #else
-#define NV_READ(reg)        DRM_READ32(  dev_priv->mmio, (reg) )
-#define NV_WRITE(reg,val)   DRM_WRITE32( dev_priv->mmio, (reg), (val) )
+#define nv_out32(map,reg,val) DRM_WRITE32((map), (reg), (val))
+#define nv_out16(map,reg,val) DRM_WRITE16((map), (reg), (val))
+#define nv_in32(map,reg) DRM_READ32((map), (reg))
+#define nv_in16(map,reg) DRM_READ16((map), (reg))
 #endif
-
+#define nv_out08(map,rev,val) DRM_WRITE8((map), (reg), (val))
+#define nv_in08(map,reg) DRM_READ8((map), (reg))
+
+/* register access */
+#define nv_rd32(reg) nv_in32(dev_priv->mmio, (reg))
+#define nv_wr32(reg,val) nv_out32(dev_priv->mmio, (reg), (val))
+#define nv_rd16(reg) nv_in16(dev_priv->mmio, (reg))
+#define nv_wr16(reg,val) nv_out16(dev_priv->mmio, (reg), (val))
+#define nv_rd08(reg) nv_in08(dev_priv->mmio, (reg))
+#define nv_wr08(reg,val) nv_out08(dev_priv->mmio, (reg), (val))
 /* PRAMIN access */
-#if defined(__powerpc__)
-#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
-#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
-#else
-#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
-#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
-#endif
-
-#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
-#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
+#define nv_ri32(reg) nv_in32(dev_priv->ramin, (reg))
+#define nv_wi32(reg,val) nv_out32(dev_priv->ramin, (reg), (val))
+/* object access */
+#define INSTANCE_RD(o,i) nv_ri32((o)->im_pramin->start + ((i)<<2))
+#define INSTANCE_WR(o,i,v) nv_wi32((o)->im_pramin->start + ((i)<<2), (v))
 
 #endif /* __NOUVEAU_DRV_H__ */
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 9bd5afbb..abc710d9 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -50,13 +50,13 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV03_PFIFO_RAMHT,
+	nv_wr32(NV03_PFIFO_RAMHT,
 			(0x03 << 24) /* search 128 */ |
 			((dev_priv->ramht_bits - 9) << 16) |
 			(dev_priv->ramht_offset >> 8)
 			);
 
-	NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
+	nv_wr32(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
 
 	switch(dev_priv->card_type)
 	{
@@ -65,28 +65,28 @@ static int nouveau_fifo_instmem_configure(struct drm_device *dev)
 			case 0x47:
 			case 0x49:
 			case 0x4b:
-				NV_WRITE(0x2230, 1);
+				nv_wr32(0x2230, 1);
 				break;
 			default:
 				break;
 			}
-			NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
+			nv_wr32(NV40_PFIFO_RAMFC, 0x30002);
 			break;
 		case NV_44:
-			NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
+			nv_wr32(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
 					(2 << 16));
 			break;
 		case NV_30:
 		case NV_20:
 		case NV_17:
-			NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
+			nv_wr32(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
 					(1 << 16) /* 64 Bytes entry*/);
 			/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
 			break;
 		case NV_11:
 		case NV_10:
 		case NV_04:
-			NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
+			nv_wr32(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
 			break;
 	}
 
@@ -98,16 +98,16 @@ int nouveau_fifo_init(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int ret;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PFIFO);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PFIFO);
 
 	/* Enable PFIFO error reporting */
-	NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
-	NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
+	nv_wr32(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
+	nv_wr32(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000000);
 
 	ret = nouveau_fifo_instmem_configure(dev);
 	if (ret) {
@@ -120,27 +120,27 @@ int nouveau_fifo_init(struct drm_device *dev)
 	DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
 
 	/* All channels into PIO mode */
-	NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
+	nv_wr32(NV04_PFIFO_MODE, 0x00000000);
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 	/* Channel 0 active, PIO mode */
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
 	/* PUT and GET to 0 */
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
 	/* No cmdbuf object */
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
-	NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
-	NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
-	NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
-
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE0_PULL0, 0x00000000);
+	nv_wr32(NV04_PFIFO_SIZE, 0x0000FFFF);
+	nv_wr32(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
+	nv_wr32(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
+
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
 				      NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 				      NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
 #ifdef __BIG_ENDIAN
@@ -148,27 +148,27 @@ int nouveau_fifo_init(struct drm_device *dev)
 #endif
 				      0x00000000);
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
 
 	/* FIXME on NV04 */
 	if (dev_priv->card_type >= NV_10) {
-		NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
-		NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
+		nv_wr32(NV10_PGRAPH_CTX_USER, 0x0);
+		nv_wr32(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
 		if (dev_priv->card_type >= NV_40)
-			NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
+			nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
 		else
-			NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
+			nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
 	} else {
-		NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
-		NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
-		NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
+		nv_wr32(NV04_PGRAPH_CTX_USER, 0x0);
+		nv_wr32(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
+		nv_wr32(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
 	}
 
-	NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
+	nv_wr32(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000001);
 	return 0;
 }
 
@@ -347,10 +347,10 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
 	nouveau_wait_for_idle(dev);
 
 	/* disable the fifo caches */
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH, nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 
 	/* Create a graphics context for new channel */
 	ret = engine->graph.create_context(chan);
@@ -369,8 +369,8 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
 	/* setup channel's default get/put values
 	 * XXX: quite possibly extremely pointless..
 	 */
-	NV_WRITE(chan->get, chan->pushbuf_base);
-	NV_WRITE(chan->put, chan->pushbuf_base);
+	nv_wr32(chan->get, chan->pushbuf_base);
+	nv_wr32(chan->put, chan->pushbuf_base);
 
 	/* If this is the first channel, setup PFIFO ourselves.  For any
 	 * other case, the GPU will handle this when it switches contexts.
@@ -390,14 +390,14 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
 		}
 	}
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
 
 	/* reenable the fifo caches */
-	NV_WRITE(NV03_PFIFO_CACHES, 1);
+	nv_wr32(NV03_PFIFO_CACHES, 1);
 
 	if (dev_priv->mm_enabled) {
 		ret = nouveau_dma_channel_setup(chan);
@@ -426,8 +426,8 @@ nouveau_channel_idle(struct nouveau_channel *chan)
 		return 1;
 	}
 
-	caches = NV_READ(NV03_PFIFO_CACHES);
-	NV_WRITE(NV03_PFIFO_CACHES, caches & ~1);
+	caches = nv_rd32(NV03_PFIFO_CACHES);
+	nv_wr32(NV03_PFIFO_CACHES, caches & ~1);
 
 	if (engine->fifo.channel_id(dev) != chan->id) {
 		struct nouveau_gpuobj *ramfc =
@@ -443,11 +443,11 @@ nouveau_channel_idle(struct nouveau_channel *chan)
 		else
 			idle = 1;
 	} else {
-		idle = (NV_READ(NV04_PFIFO_CACHE1_DMA_GET) ==
-			NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
+		idle = (nv_rd32(NV04_PFIFO_CACHE1_DMA_GET) ==
+			nv_rd32(NV04_PFIFO_CACHE1_DMA_PUT));
 	}
 
-	NV_WRITE(NV03_PFIFO_CACHES, caches);
+	nv_wr32(NV03_PFIFO_CACHES, caches);
 	return idle;
 }
 
@@ -476,10 +476,10 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
 	 */
 
 	/* disable the fifo caches */
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH, nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 
 	// FIXME XXX needs more code
 
@@ -489,11 +489,11 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
 	engine->graph.destroy_context(chan);
 
 	/* reenable the fifo caches */
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000001);
 
 	/* Deallocate push buffer */
 	nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index c754ba23..cc7a03c5 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -50,7 +50,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	/* Master disable */
-	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
+	nv_wr32(NV03_PMC_INTR_EN_0, 0);
 }
 
 int
@@ -59,7 +59,7 @@ nouveau_irq_postinstall(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	/* Master enable */
-	NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
+	nv_wr32(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
 
 	return 0;
 }
@@ -70,7 +70,7 @@ nouveau_irq_uninstall(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	/* Master disable */
-	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
+	nv_wr32(NV03_PMC_INTR_EN_0, 0);
 }
 
 static void
@@ -80,14 +80,14 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
 	struct nouveau_engine *engine = &dev_priv->Engine;
 	uint32_t status, reassign;
 
-	reassign = NV_READ(NV03_PFIFO_CACHES) & 1;
-	while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
+	reassign = nv_rd32(NV03_PFIFO_CACHES) & 1;
+	while ((status = nv_rd32(NV03_PFIFO_INTR_0))) {
 		uint32_t chid, get;
 
-		NV_WRITE(NV03_PFIFO_CACHES, 0);
+		nv_wr32(NV03_PFIFO_CACHES, 0);
 
 		chid = engine->fifo.channel_id(dev);
-		get  = NV_READ(NV03_PFIFO_CACHE1_GET);
+		get  = nv_rd32(NV03_PFIFO_CACHE1_GET);
 
 		if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 			uint32_t mthd, data;
@@ -95,45 +95,45 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
 
 			ptr = get >> 2;
 			if (dev_priv->card_type < NV_40) {
-				mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
-				data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr));
+				mthd = nv_rd32(NV04_PFIFO_CACHE1_METHOD(ptr));
+				data = nv_rd32(NV04_PFIFO_CACHE1_DATA(ptr));
 			} else {
-				mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr));
-				data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr));
+				mthd = nv_rd32(NV40_PFIFO_CACHE1_METHOD(ptr));
+				data = nv_rd32(NV40_PFIFO_CACHE1_DATA(ptr));
 			}
 
 			DRM_INFO("PFIFO_CACHE_ERROR - "
 				 "Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
 				 chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
 
-			NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4);
-			NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1);
+			nv_wr32(NV03_PFIFO_CACHE1_GET, get + 4);
+			nv_wr32(NV04_PFIFO_CACHE1_PULL0, 1);
 
 			status &= ~NV_PFIFO_INTR_CACHE_ERROR;
-			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
+			nv_wr32(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
 		}
 
 		if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 			DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid);
 
 			status &= ~NV_PFIFO_INTR_DMA_PUSHER;
-			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
+			nv_wr32(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
 
-			NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
-			if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get)
-				NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
+			nv_wr32(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+			if (nv_rd32(NV04_PFIFO_CACHE1_DMA_PUT) != get)
+				nv_wr32(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
 		}
 
 		if (status) {
 			DRM_INFO("Unhandled PFIFO_INTR - 0x%08x\n", status);
-			NV_WRITE(NV03_PFIFO_INTR_0, status);
-			NV_WRITE(NV03_PMC_INTR_EN_0, 0);
+			nv_wr32(NV03_PFIFO_INTR_0, status);
+			nv_wr32(NV03_PMC_INTR_EN_0, 0);
 		}
 
-		NV_WRITE(NV03_PFIFO_CACHES, reassign);
+		nv_wr32(NV03_PFIFO_CACHES, reassign);
 	}
 
-	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
+	nv_wr32(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 }
 
 struct nouveau_bitfield_names {
@@ -208,9 +208,9 @@ nouveau_graph_chid_from_grctx(struct drm_device *dev)
 		return dev_priv->Engine.fifo.channels;
 	else
 	if (dev_priv->card_type < NV_50)
-		inst = (NV_READ(0x40032c) & 0xfffff) << 4;
+		inst = (nv_rd32(0x40032c) & 0xfffff) << 4;
 	else
-		inst = NV_READ(0x40032c) & 0xfffff;
+		inst = nv_rd32(0x40032c) & 0xfffff;
 
 	for (i = 0; i < dev_priv->Engine.fifo.channels; i++) {
 		struct nouveau_channel *chan = dev_priv->fifos[i];
@@ -238,10 +238,10 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
 	int channel;
 
 	if (dev_priv->card_type < NV_10)
-		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
+		channel = (nv_rd32(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
 	else
 	if (dev_priv->card_type < NV_40)
-		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
+		channel = (nv_rd32(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
 	else
 		channel = nouveau_graph_chid_from_grctx(dev);
 
@@ -271,31 +271,31 @@ nouveau_graph_trap_info(struct drm_device *dev,
 
 	trap->nsource = trap->nstatus = 0;
 	if (dev_priv->card_type < NV_50) {
-		trap->nsource = NV_READ(NV03_PGRAPH_NSOURCE);
-		trap->nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
+		trap->nsource = nv_rd32(NV03_PGRAPH_NSOURCE);
+		trap->nstatus = nv_rd32(NV03_PGRAPH_NSTATUS);
 	}
 
 	if (nouveau_graph_trapped_channel(dev, &trap->channel))
 		trap->channel = -1;
-	address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
+	address = nv_rd32(NV04_PGRAPH_TRAPPED_ADDR);
 
 	trap->mthd = address & 0x1FFC;
-	trap->data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
+	trap->data = nv_rd32(NV04_PGRAPH_TRAPPED_DATA);
 	if (dev_priv->card_type < NV_10) {
 		trap->subc  = (address >> 13) & 0x7;
 	} else {
 		trap->subc  = (address >> 16) & 0x7;
-		trap->data2 = NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
+		trap->data2 = nv_rd32(NV10_PGRAPH_TRAPPED_DATA_HIGH);
 	}
 
 	if (dev_priv->card_type < NV_10) {
-		trap->class = NV_READ(0x400180 + trap->subc*4) & 0xFF;
+		trap->class = nv_rd32(0x400180 + trap->subc*4) & 0xFF;
 	} else if (dev_priv->card_type < NV_40) {
-		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFF;
+		trap->class = nv_rd32(0x400160 + trap->subc*4) & 0xFFF;
 	} else if (dev_priv->card_type < NV_50) {
-		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFFF;
+		trap->class = nv_rd32(0x400160 + trap->subc*4) & 0xFFFF;
 	} else {
-		trap->class = NV_READ(0x400814);
+		trap->class = nv_rd32(0x400814);
 	}
 }
 
@@ -408,41 +408,41 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t status;
 
-	while ((status = NV_READ(NV03_PGRAPH_INTR))) {
-		uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE);
+	while ((status = nv_rd32(NV03_PGRAPH_INTR))) {
+		uint32_t nsource = nv_rd32(NV03_PGRAPH_NSOURCE);
 
 		if (status & NV_PGRAPH_INTR_NOTIFY) {
 			nouveau_pgraph_intr_notify(dev, nsource);
 
 			status &= ~NV_PGRAPH_INTR_NOTIFY;
-			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
+			nv_wr32(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 		}
 
 		if (status & NV_PGRAPH_INTR_ERROR) {
 			nouveau_pgraph_intr_error(dev, nsource);
 
 			status &= ~NV_PGRAPH_INTR_ERROR;
-			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
+			nv_wr32(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
 		}
 
 		if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 			nouveau_pgraph_intr_context_switch(dev);
 
 			status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-			NV_WRITE(NV03_PGRAPH_INTR,
+			nv_wr32(NV03_PGRAPH_INTR,
 				 NV_PGRAPH_INTR_CONTEXT_SWITCH);
 		}
 
 		if (status) {
 			DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
-			NV_WRITE(NV03_PGRAPH_INTR, status);
+			nv_wr32(NV03_PGRAPH_INTR, status);
 		}
 
-		if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
-			NV_WRITE(NV04_PGRAPH_FIFO, 1);
+		if ((nv_rd32(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
+			nv_wr32(NV04_PGRAPH_FIFO, 1);
 	}
 
-	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
+	nv_wr32(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 }
 
 static void
@@ -451,15 +451,15 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t status, nsource;
 
-	status = NV_READ(NV03_PGRAPH_INTR);
-	nsource = NV_READ(NV03_PGRAPH_NSOURCE);
+	status = nv_rd32(NV03_PGRAPH_INTR);
+	nsource = nv_rd32(NV03_PGRAPH_NSOURCE);
 
 	if (status & 0x00000020) {
 		nouveau_pgraph_intr_error(dev,
 					  NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
 
 		status &= ~0x00000020;
-		NV_WRITE(NV03_PGRAPH_INTR, 0x00000020);
+		nv_wr32(NV03_PGRAPH_INTR, 0x00000020);
 	}
 
 	if (status & 0x00100000) {
@@ -467,7 +467,7 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
 					  NV03_PGRAPH_NSOURCE_DATA_ERROR);
 
 		status &= ~0x00100000;
-		NV_WRITE(NV03_PGRAPH_INTR, 0x00100000);
+		nv_wr32(NV03_PGRAPH_INTR, 0x00100000);
 	}
 
 	if (status & 0x00200000) {
@@ -478,38 +478,38 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
 
 		DRM_ERROR("magic set 1:\n");
 		for (r = 0x408900; r <= 0x408910; r += 4)
-			DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r));
-		NV_WRITE(0x408900, NV_READ(0x408904) | 0xc0000000);
+			DRM_ERROR("\t0x%08x: 0x%08x\n", r, nv_rd32(r));
+		nv_wr32(0x408900, nv_rd32(0x408904) | 0xc0000000);
 		for (r = 0x408e08; r <= 0x408e24; r += 4)
-			DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r));
-		NV_WRITE(0x408e08, NV_READ(0x408e08) | 0xc0000000);
+			DRM_ERROR("\t0x%08x: 0x%08x\n", r, nv_rd32(r));
+		nv_wr32(0x408e08, nv_rd32(0x408e08) | 0xc0000000);
 
 		DRM_ERROR("magic set 2:\n");
 		for (r = 0x409900; r <= 0x409910; r += 4)
-			DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r));
-		NV_WRITE(0x409900, NV_READ(0x409904) | 0xc0000000);
+			DRM_ERROR("\t0x%08x: 0x%08x\n", r, nv_rd32(r));
+		nv_wr32(0x409900, nv_rd32(0x409904) | 0xc0000000);
 		for (r = 0x409e08; r <= 0x409e24; r += 4)
-			DRM_ERROR("\t0x%08x: 0x%08x\n", r, NV_READ(r));
-		NV_WRITE(0x409e08, NV_READ(0x409e08) | 0xc0000000);
+			DRM_ERROR("\t0x%08x: 0x%08x\n", r, nv_rd32(r));
+		nv_wr32(0x409e08, nv_rd32(0x409e08) | 0xc0000000);
 
 		status &= ~0x00200000;
-		NV_WRITE(NV03_PGRAPH_NSOURCE, nsource);
-		NV_WRITE(NV03_PGRAPH_INTR, 0x00200000);
+		nv_wr32(NV03_PGRAPH_NSOURCE, nsource);
+		nv_wr32(NV03_PGRAPH_INTR, 0x00200000);
 	}
 
 	if (status) {
 		DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
-		NV_WRITE(NV03_PGRAPH_INTR, status);
+		nv_wr32(NV03_PGRAPH_INTR, status);
 	}
 
 	{
 		const int isb = (1 << 16) | (1 << 0);
 
-		if ((NV_READ(0x400500) & isb) != isb)
-			NV_WRITE(0x400500, NV_READ(0x400500) | isb);
+		if ((nv_rd32(0x400500) & isb) != isb)
+			nv_wr32(0x400500, nv_rd32(0x400500) | isb);
 	}
 
-	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
+	nv_wr32(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 }
 
 static void
@@ -518,11 +518,11 @@ nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	if (crtc&1) {
-		NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
+		nv_wr32(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
 	}
 
 	if (crtc&2) {
-		NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
+		nv_wr32(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
 	}
 }
 
@@ -530,7 +530,7 @@ static void
 nouveau_nv50_display_irq_handler(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	uint32_t val = NV_READ(NV50_PDISPLAY_SUPERVISOR);
+	uint32_t val = nv_rd32(NV50_PDISPLAY_SUPERVISOR);
 	struct drm_encoder *drm_encoder;
 	struct drm_crtc *drm_crtc;
 
@@ -538,7 +538,7 @@ nouveau_nv50_display_irq_handler(struct drm_device *dev)
 
 	/* vblank interrupts */
 	if (val & NV50_PDISPLAY_SUPERVISOR_CRTCn) {
-		NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CRTCn);
+		nv_wr32(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CRTCn);
 		val &= ~NV50_PDISPLAY_SUPERVISOR_CRTCn;
 	}
 
@@ -555,7 +555,7 @@ nouveau_nv50_display_irq_handler(struct drm_device *dev)
 			struct nv50_crtc *crtc = NULL;
 			int crtc_index;
 
-			uint32_t unk30 = NV_READ(NV50_PDISPLAY_UNK30_CTRL);
+			uint32_t unk30 = nv_rd32(NV50_PDISPLAY_UNK30_CTRL);
 
 			for (crtc_index = 0; crtc_index < 2; crtc_index++) {
 				bool clock_change = false;
@@ -601,8 +601,8 @@ nouveau_nv50_display_irq_handler(struct drm_device *dev)
 			}
 		}
 
-		NV_WRITE(NV50_PDISPLAY_UNK30_CTRL, NV50_PDISPLAY_UNK30_CTRL_PENDING);
-		NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CLK_MASK);
+		nv_wr32(NV50_PDISPLAY_UNK30_CTRL, NV50_PDISPLAY_UNK30_CTRL_PENDING);
+		nv_wr32(NV50_PDISPLAY_SUPERVISOR, val & NV50_PDISPLAY_SUPERVISOR_CLK_MASK);
 
 		val &= ~NV50_PDISPLAY_SUPERVISOR_CLK_MASK;
 	}
@@ -610,7 +610,7 @@ nouveau_nv50_display_irq_handler(struct drm_device *dev)
 	if (val)
 		DRM_ERROR("unsupported NV50_DISPLAY_INTR - 0x%08X\n", val);
 
-	NV_WRITE(NV50_PDISPLAY_SUPERVISOR, val);
+	nv_wr32(NV50_PDISPLAY_SUPERVISOR, val);
 }
 
 static void
@@ -619,10 +619,10 @@ nouveau_nv50_i2c_irq_handler(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	DRM_DEBUG("NV50_PCONNECTOR_HOTPLUG_CTRL - 0x%08X\n",
-		  NV_READ(NV50_PCONNECTOR_HOTPLUG_CTRL));
+		  nv_rd32(NV50_PCONNECTOR_HOTPLUG_CTRL));
 
 	/* This seems to be the way to acknowledge an interrupt. */
-	NV_WRITE(NV50_PCONNECTOR_HOTPLUG_CTRL, 0x7FFF7FFF);
+	nv_wr32(NV50_PCONNECTOR_HOTPLUG_CTRL, 0x7FFF7FFF);
 
 	/* Do a "dumb" detect all */
 	nv50_connector_detect_all(dev);
@@ -635,7 +635,7 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t status;
 
-	status = NV_READ(NV03_PMC_INTR_0);
+	status = nv_rd32(NV03_PMC_INTR_0);
 	if (!status)
 		return IRQ_NONE;
 
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c
index 12d8e340..43eca753 100644
--- a/shared-core/nouveau_mem.c
+++ b/shared-core/nouveau_mem.c
@@ -281,10 +281,10 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
 	{
 		case NV_04:
 		case NV_05:
-			if (NV_READ(NV03_BOOT_0) & 0x00000100) {
-				return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024;
+			if (nv_rd32(NV03_BOOT_0) & 0x00000100) {
+				return (((nv_rd32(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024;
 			} else
-			switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT)
+			switch(nv_rd32(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT)
 			{
 				case NV04_BOOT_0_RAM_AMOUNT_32MB:
 					return 32*1024*1024;
@@ -310,7 +310,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
 			} else {
 				uint64_t mem;
 
-				mem = (NV_READ(NV04_FIFO_DATA) &
+				mem = (nv_rd32(NV04_FIFO_DATA) &
 				       NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
 				      NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
 				return mem*1024*1024;
@@ -327,25 +327,25 @@ static void nouveau_mem_reset_agp(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
 
-	saved_pci_nv_1 = NV_READ(NV04_PBUS_PCI_NV_1);
-	saved_pci_nv_19 = NV_READ(NV04_PBUS_PCI_NV_19);
+	saved_pci_nv_1 = nv_rd32(NV04_PBUS_PCI_NV_1);
+	saved_pci_nv_19 = nv_rd32(NV04_PBUS_PCI_NV_19);
 
 	/* clear busmaster bit */
-	NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
+	nv_wr32(NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 	/* clear SBA and AGP bits */
-	NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
+	nv_wr32(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
 
 	/* power cycle pgraph, if enabled */
-	pmc_enable = NV_READ(NV03_PMC_ENABLE);
+	pmc_enable = nv_rd32(NV03_PMC_ENABLE);
 	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
-		NV_WRITE(NV03_PMC_ENABLE, pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
-		NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+		nv_wr32(NV03_PMC_ENABLE, pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
+		nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 				NV_PMC_ENABLE_PGRAPH);
 	}
 
 	/* and restore (gives effect of resetting AGP) */
-	NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
-	NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
+	nv_wr32(NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
+	nv_wr32(NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 }
 
 static int
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index 69049199..7818bcd1 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -248,7 +248,7 @@ nouveau_card_init(struct drm_device *dev)
 		dev_priv->chipset = dev_priv->card_type;
 	else
 		dev_priv->chipset =
-			(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
+			(nv_rd32(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
 
 	/* Initialise internal driver API hooks */
 	ret = nouveau_init_engine_ptrs(dev);
@@ -447,8 +447,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
 
 #if defined(__powerpc__)
 	/* Put the card in BE mode if it's not */
-	if (NV_READ(NV03_PMC_BOOT_1))
-		NV_WRITE(NV03_PMC_BOOT_1,0x00000001);
+	if (nv_rd32(NV03_PMC_BOOT_1))
+		nv_wr32(NV03_PMC_BOOT_1,0x00000001);
 
 	DRM_MEMORYBARRIER();
 
@@ -466,7 +466,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
 		{
 			int i;
 			for(i=0;i<size;i+=4)
-				NV_WI32(i, bios[i/4]);
+				nv_wi32(i, bios[i/4]);
 			DRM_INFO("OF bios successfully copied (%d bytes)\n",size);
 		}
 		else
@@ -477,7 +477,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
 #endif
 
 	/* Time to determine the card architecture */
-	reg0 = NV_READ(NV03_PMC_BOOT_0);
+	reg0 = nv_rd32(NV03_PMC_BOOT_0);
 
 	/* We're dealing with >=NV10 */
 	if ((reg0 & 0x0f000000) > 0 ) {
@@ -738,9 +738,9 @@ void nouveau_wait_for_idle(struct drm_device *dev)
 		uint64_t stopped = started;
 		uint32_t status;
 		do {
-			uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
+			uint32_t pmc_e = nv_rd32(NV03_PMC_ENABLE);
 			(void)pmc_e;
-			status = NV_READ(NV04_PGRAPH_STATUS);
+			status = nv_rd32(NV04_PGRAPH_STATUS);
 			if (!status)
 				break;
 			stopped = dev_priv->Engine.timer.read(dev);
@@ -787,22 +787,22 @@ static int nouveau_suspend(struct drm_device *dev)
 	}
 	nouveau_wait_for_idle(dev);
 
-	NV_WRITE(NV04_PGRAPH_FIFO, 0);
+	nv_wr32(NV04_PGRAPH_FIFO, 0);
 	/* disable the fifo caches */
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 
-	susres->fifo_mode = NV_READ(NV04_PFIFO_MODE);
+	susres->fifo_mode = nv_rd32(NV04_PFIFO_MODE);
 
 	if (dev_priv->card_type >= NV_10) {
-		susres->graph_state = NV_READ(NV10_PGRAPH_STATE);
-		susres->graph_ctx_control = NV_READ(NV10_PGRAPH_CTX_CONTROL);
+		susres->graph_state = nv_rd32(NV10_PGRAPH_STATE);
+		susres->graph_ctx_control = nv_rd32(NV10_PGRAPH_CTX_CONTROL);
 	} else {
-		susres->graph_state = NV_READ(NV04_PGRAPH_STATE);
-		susres->graph_ctx_control = NV_READ(NV04_PGRAPH_CTX_CONTROL);
+		susres->graph_state = nv_rd32(NV04_PGRAPH_STATE);
+		susres->graph_ctx_control = nv_rd32(NV04_PGRAPH_CTX_CONTROL);
 	}
 
 	engine->fifo.save_context(dev_priv->fifos[engine->fifo.channel_id(dev)]);
@@ -810,15 +810,15 @@ static int nouveau_suspend(struct drm_device *dev)
 	nouveau_wait_for_idle(dev);
 
 	for (i = 0; i < susres->ramin_size / 4; i++)
-		susres->ramin_copy[i] = NV_RI32(i << 2);
+		susres->ramin_copy[i] = nv_ri32(i << 2);
 
 	/* reenable the fifo caches */
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
-	NV_WRITE(NV04_PGRAPH_FIFO, 1);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000001);
+	nv_wr32(NV04_PGRAPH_FIFO, 1);
 
 	return 0;
 }
@@ -852,7 +852,7 @@ static int nouveau_resume(struct drm_device *dev)
 	}
 
 	for (i = 0; i < susres->ramin_size / 4; i++)
-		NV_WI32(i << 2, susres->ramin_copy[i]);
+		nv_wi32(i << 2, susres->ramin_copy[i]);
 
 	engine->mc.init(dev);
 	engine->timer.init(dev);
@@ -860,41 +860,41 @@ static int nouveau_resume(struct drm_device *dev)
 	engine->graph.init(dev);
 	engine->fifo.init(dev);
 
-	NV_WRITE(NV04_PGRAPH_FIFO, 0);
+	nv_wr32(NV04_PGRAPH_FIFO, 0);
 	/* disable the fifo caches */
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) & ~1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 
 	/* PMC power cycling PFIFO in init clobbers some of the stuff stored in
 	 * PRAMIN (such as NV04_PFIFO_CACHE1_DMA_INSTANCE). this is unhelpful
 	 */
 	for (i = 0; i < susres->ramin_size / 4; i++)
-		NV_WI32(i << 2, susres->ramin_copy[i]);
+		nv_wi32(i << 2, susres->ramin_copy[i]);
 
 	engine->fifo.load_context(dev_priv->fifos[0]);
-	NV_WRITE(NV04_PFIFO_MODE, susres->fifo_mode);
+	nv_wr32(NV04_PFIFO_MODE, susres->fifo_mode);
 
 	engine->graph.load_context(dev_priv->fifos[0]);
 	nouveau_wait_for_idle(dev);
 
 	if (dev_priv->card_type >= NV_10) {
-		NV_WRITE(NV10_PGRAPH_STATE, susres->graph_state);
-		NV_WRITE(NV10_PGRAPH_CTX_CONTROL, susres->graph_ctx_control);
+		nv_wr32(NV10_PGRAPH_STATE, susres->graph_state);
+		nv_wr32(NV10_PGRAPH_CTX_CONTROL, susres->graph_ctx_control);
 	} else {
-		NV_WRITE(NV04_PGRAPH_STATE, susres->graph_state);
-		NV_WRITE(NV04_PGRAPH_CTX_CONTROL, susres->graph_ctx_control);
+		nv_wr32(NV04_PGRAPH_STATE, susres->graph_state);
+		nv_wr32(NV04_PGRAPH_CTX_CONTROL, susres->graph_ctx_control);
 	}
 
 	/* reenable the fifo caches */
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
-		 NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
-	NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
-	NV_WRITE(NV04_PGRAPH_FIFO, 0x1);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUSH,
+		 nv_rd32(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+	nv_wr32(NV03_PFIFO_CACHES, 0x00000001);
+	nv_wr32(NV04_PGRAPH_FIFO, 0x1);
 
 	if (dev->irq_enabled)
 		nouveau_irq_postinstall(dev);
diff --git a/shared-core/nouveau_swmthd.c b/shared-core/nouveau_swmthd.c
index c3666bfd..855a4cf6 100644
--- a/shared-core/nouveau_swmthd.c
+++ b/shared-core/nouveau_swmthd.c
@@ -48,7 +48,7 @@ typedef struct{
 One function for all because they are very similar.*/
 static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t oclass, uint32_t mthd) {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	uint32_t inst_loc = NV_READ(NV04_PGRAPH_CTX_SWITCH4) & 0xFFFF;
+	uint32_t inst_loc = nv_rd32(NV04_PGRAPH_CTX_SWITCH4) & 0xFFFF;
 	uint32_t value_to_set = 0, bit_to_set = 0;
 
 	switch ( oclass ) {
@@ -62,7 +62,7 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
 					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
 					break;
 				case 0x2fc :
-					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
+					bit_to_set = nv_rd32(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
 					break;
 				default : ;
 				};
@@ -80,7 +80,7 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
 					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
 					break;
 				case 0x2fc :
-					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
+					bit_to_set = nv_rd32(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
 					break;
 			};
 			break;
@@ -100,7 +100,7 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
 					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
 					break;
 				case 0x2fc :
-					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
+					bit_to_set = nv_rd32(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
 					break;
 			};
 			break;
@@ -117,7 +117,7 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
 					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
 					break;
 				case 0x2fc :
-					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
+					bit_to_set = nv_rd32(NV04_PGRAPH_TRAPPED_DATA) << 15; /*PATCH_CONFIG = NV04_PGRAPH_TRAPPED_DATA*/
 					break;
 			};
 			break;
@@ -127,24 +127,24 @@ static void nouveau_NV04_setcontext_sw_method(struct drm_device *dev, uint32_t o
 					bit_to_set = 1 << 24; /*PATCH_STATUS_VALID*/
 					break;
 				case 0x304 :
-					bit_to_set = NV_READ(NV04_PGRAPH_TRAPPED_DATA) << 15; //PATCH_CONFIG
+					bit_to_set = nv_rd32(NV04_PGRAPH_TRAPPED_DATA) << 15; //PATCH_CONFIG
 					break;
 			};
 			break;
 		default :;
 		};
 
-	value_to_set = (NV_READ(0x00700000 | inst_loc << 4))| bit_to_set;
+	value_to_set = (nv_rd32(0x00700000 | inst_loc << 4))| bit_to_set;
 
 	/*RAMIN*/
 	nouveau_wait_for_idle(dev);
-	NV_WRITE(0x00700000 | inst_loc << 4, value_to_set);
+	nv_wr32(0x00700000 | inst_loc << 4, value_to_set);
 
-	/*DRM_DEBUG("CTX_SWITCH1 value is %#x\n", NV_READ(NV04_PGRAPH_CTX_SWITCH1));*/
-	NV_WRITE(NV04_PGRAPH_CTX_SWITCH1, value_to_set);
+	/*DRM_DEBUG("CTX_SWITCH1 value is %#x\n", nv_rd32(NV04_PGRAPH_CTX_SWITCH1));*/
+	nv_wr32(NV04_PGRAPH_CTX_SWITCH1, value_to_set);
 
-	/*DRM_DEBUG("CTX_CACHE1 + xxx value is %#x\n", NV_READ(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2)));*/
-	NV_WRITE(NV04_PGRAPH_CTX_CACHE1 + (((NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2), value_to_set);
+	/*DRM_DEBUG("CTX_CACHE1 + xxx value is %#x\n", nv_rd32(NV04_PGRAPH_CTX_CACHE1 + (((nv_rd32(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2)));*/
+	nv_wr32(NV04_PGRAPH_CTX_CACHE1 + (((nv_rd32(NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7) << 2), value_to_set);
 }
 
  nouveau_software_method_t nouveau_sw_methods[] = {
diff --git a/shared-core/nv04_fb.c b/shared-core/nv04_fb.c
index 58a92470..0a13b04b 100644
--- a/shared-core/nv04_fb.c
+++ b/shared-core/nv04_fb.c
@@ -12,7 +12,7 @@ nv04_fb_init(struct drm_device *dev)
 	 * nvidia reading PFB_CFG_0, then writing back its original value.
 	 * (which was 0x701114 in this case)
 	 */
-	NV_WRITE(NV04_PFB_CFG0, 0x1114);
+	nv_wr32(NV04_PFB_CFG0, 0x1114);
 
 	return 0;
 }
diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c
index 88186fe3..3463e073 100644
--- a/shared-core/nv04_fifo.c
+++ b/shared-core/nv04_fifo.c
@@ -40,7 +40,7 @@ nv04_fifo_channel_id(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+	return (nv_rd32(NV03_PFIFO_CACHE1_PUSH1) &
 			NV03_PFIFO_CACHE1_PUSH1_CHID_MASK);
 }
 
@@ -71,7 +71,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan)
 			     0));
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE,nv_rd32(NV04_PFIFO_MODE) | (1<<chan->id));
 	return 0;
 }
 
@@ -81,7 +81,7 @@ nv04_fifo_destroy_context(struct nouveau_channel *chan)
 	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE, nv_rd32(NV04_PFIFO_MODE)&~(1<<chan->id));
 
 	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
@@ -93,24 +93,24 @@ nv04_fifo_load_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH1,
 		 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
 
 	tmp = RAMFC_RD(DMA_INSTANCE);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
-	NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
+	nv_wr32(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
+	nv_wr32(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
 
 	/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
-	tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
+	tmp = nv_rd32(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 
 	return 0;
 }
@@ -122,17 +122,17 @@ nv04_fifo_save_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	RAMFC_WR(DMA_PUT, NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
-	RAMFC_WR(DMA_GET, NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+	RAMFC_WR(DMA_PUT, nv_rd32(NV04_PFIFO_CACHE1_DMA_PUT));
+	RAMFC_WR(DMA_GET, nv_rd32(NV04_PFIFO_CACHE1_DMA_GET));
 
-	tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
-	tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);
+	tmp  = nv_rd32(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
+	tmp |= nv_rd32(NV04_PFIFO_CACHE1_DMA_INSTANCE);
 	RAMFC_WR(DMA_INSTANCE, tmp);
 
-	RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
-	RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
-	RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
-	RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
+	RAMFC_WR(DMA_STATE, nv_rd32(NV04_PFIFO_CACHE1_DMA_STATE));
+	RAMFC_WR(DMA_FETCH, nv_rd32(NV04_PFIFO_CACHE1_DMA_FETCH));
+	RAMFC_WR(ENGINE, nv_rd32(NV04_PFIFO_CACHE1_ENGINE));
+	RAMFC_WR(PULL1_ENGINE, nv_rd32(NV04_PFIFO_CACHE1_PULL1));
 
 	return 0;
 }
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c
index 6caae257..a1342f7d 100644
--- a/shared-core/nv04_graph.c
+++ b/shared-core/nv04_graph.c
@@ -379,7 +379,7 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
 		return;
 	}
 
-	chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
+	chid = (nv_rd32(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
 	last = dev_priv->fifos[chid];
 
 	if (!last) {
@@ -390,32 +390,32 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
 		         last->id, next->id);
 	}
 
-/*	NV_WRITE(NV03_PFIFO_CACHES, 0x0);
-	NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/
-	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+/*	nv_wr32(NV03_PFIFO_CACHES, 0x0);
+	nv_wr32(NV04_PFIFO_CACHE0_PULL0, 0x0);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x0);*/
+	nv_wr32(NV04_PGRAPH_FIFO,0x0);
 
 	if (last)
 		nv04_graph_save_context(last);
 
 	nouveau_wait_for_idle(dev);
 
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
-	NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
+	nv_wr32(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
+	nv_wr32(NV04_PGRAPH_CTX_USER, (nv_rd32(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
 
 	nouveau_wait_for_idle(dev);
 
 	nv04_graph_load_context(next);
 
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
-	NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24);
-	NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
+	nv_wr32(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+	nv_wr32(NV04_PGRAPH_CTX_USER, next->id << 24);
+	nv_wr32(NV04_PGRAPH_FFINTFC_ST2, nv_rd32(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
 
-/*	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
-	NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
-	NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/
-	NV_WRITE(NV04_PGRAPH_FIFO,0x1);
+/*	nv_wr32(NV04_PGRAPH_FIFO,0x0);
+	nv_wr32(NV04_PFIFO_CACHE0_PULL0, 0x0);
+	nv_wr32(NV04_PFIFO_CACHE1_PULL0, 0x1);
+	nv_wr32(NV03_PFIFO_CACHES, 0x1);*/
+	nv_wr32(NV04_PGRAPH_FIFO,0x1);
 }
 
 int nv04_graph_create_context(struct nouveau_channel *chan) {
@@ -431,8 +431,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan) {
 	//dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
 	pgraph_ctx->nv04[0] = 0x0001ffff;
 	/* is it really needed ??? */
-	//dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
-	//dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
+	//dev_priv->fifos[channel].pgraph_ctx[1] = nv_rd32(NV_PGRAPH_DEBUG_4);
+	//dev_priv->fifos[channel].pgraph_ctx[2] = nv_rd32(0x004006b0);
 
 	return 0;
 }
@@ -453,7 +453,7 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
 	int i;
 
 	for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
-		NV_WRITE(nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
+		nv_wr32(nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
 
 	return 0;
 }
@@ -466,7 +466,7 @@ int nv04_graph_save_context(struct nouveau_channel *chan)
 	int i;
 
 	for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
-		pgraph_ctx->nv04[i] = NV_READ(nv04_graph_ctx_regs[i]);
+		pgraph_ctx->nv04[i] = nv_rd32(nv04_graph_ctx_regs[i]);
 
 	return 0;
 }
@@ -474,39 +474,39 @@ int nv04_graph_save_context(struct nouveau_channel *chan)
 int nv04_graph_init(struct drm_device *dev) {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PGRAPH);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PGRAPH);
 
 	/* Enable PGRAPH interrupts */
-	NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
-	NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	NV_WRITE(NV04_PGRAPH_VALID1, 0);
-	NV_WRITE(NV04_PGRAPH_VALID2, 0);
-	/*NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000);
+	nv_wr32(NV03_PGRAPH_INTR, 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+	nv_wr32(NV04_PGRAPH_VALID1, 0);
+	nv_wr32(NV04_PGRAPH_VALID2, 0);
+	/*nv_wr32(NV04_PGRAPH_DEBUG_0, 0x000001FF);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x1231c000);
 	/*1231C000 blob, 001 haiku*/
 	//*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
-	NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111100);
+	nv_wr32(NV04_PGRAPH_DEBUG_1, 0x72111100);
 	/*0x72111100 blob , 01 haiku*/
-	/*NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
-	NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f071);
+	/*nv_wr32(NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
+	nv_wr32(NV04_PGRAPH_DEBUG_2, 0x11d5f071);
 	/*haiku same*/
 
-	/*NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
+	/*nv_wr32(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
+	nv_wr32(NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
 	/*haiku and blob 10d4*/
 
-	NV_WRITE(NV04_PGRAPH_STATE        , 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_CTX_CONTROL  , 0x10010100);
-	NV_WRITE(NV04_PGRAPH_FIFO         , 0x00000001);
+	nv_wr32(NV04_PGRAPH_STATE        , 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_CTX_CONTROL  , 0x10010100);
+	nv_wr32(NV04_PGRAPH_FIFO         , 0x00000001);
 
 	/* These don't belong here, they're part of a per-channel context */
-	NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
+	nv_wr32(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 
 	return 0;
 }
diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c
index 09751806..fb4a178c 100644
--- a/shared-core/nv04_instmem.c
+++ b/shared-core/nv04_instmem.c
@@ -36,7 +36,7 @@ nv04_instmem_determine_amount(struct drm_device *dev)
 
 	/* Clear all of it, except the BIOS image that's in the first 64KiB */
 	for (i=(64*1024); i<dev_priv->ramin_rsvd_vram; i+=4)
-		NV_WI32(i, 0x00000000);
+		nv_wi32(i, 0x00000000);
 }
 
 static void
diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c
index 24c1f7b3..23fac41d 100644
--- a/shared-core/nv04_mc.c
+++ b/shared-core/nv04_mc.c
@@ -11,7 +11,7 @@ nv04_mc_init(struct drm_device *dev)
 	/* Power up everything, resetting each individual unit will
 	 * be done later if needed.
 	 */
-	NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
+	nv_wr32(NV03_PMC_ENABLE, 0xFFFFFFFF);
 
 	return 0;
 }
diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c
index 616f197b..f7511d07 100644
--- a/shared-core/nv04_timer.c
+++ b/shared-core/nv04_timer.c
@@ -8,8 +8,8 @@ nv04_timer_init(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
-	NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
+	nv_wr32(NV04_PTIMER_INTR_EN_0, 0x00000000);
+	nv_wr32(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
 
 	/* Just use the pre-existing values when possible for now; these regs
 	 * are not written in nv (driver writer missed a /4 on the address), and
@@ -18,9 +18,9 @@ nv04_timer_init(struct drm_device *dev)
 	 * A correct solution (involving calculations with the GPU PLL) can
 	 * be done when kernel modesetting lands
 	 */
-	if (!NV_READ(NV04_PTIMER_NUMERATOR) || !NV_READ(NV04_PTIMER_DENOMINATOR)) {
-		NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
-		NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
+	if (!nv_rd32(NV04_PTIMER_NUMERATOR) || !nv_rd32(NV04_PTIMER_DENOMINATOR)) {
+		nv_wr32(NV04_PTIMER_NUMERATOR, 0x00000008);
+		nv_wr32(NV04_PTIMER_DENOMINATOR, 0x00000003);
 	}
 
 	return 0;
@@ -37,12 +37,12 @@ nv04_timer_read(struct drm_device *dev)
 	 * advances between high and low dword reads and may corrupt the
 	 * result. Not confirmed.
 	 */
-	uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
+	uint32_t high2 = nv_rd32(NV04_PTIMER_TIME_1);
 	uint32_t high1;
 	do {
 		high1 = high2;
-		low = NV_READ(NV04_PTIMER_TIME_0);
-		high2 = NV_READ(NV04_PTIMER_TIME_1);
+		low = nv_rd32(NV04_PTIMER_TIME_0);
+		high2 = nv_rd32(NV04_PTIMER_TIME_1);
 	} while(high1 != high2);
 	return (((uint64_t)high2) << 32) | (uint64_t)low;
 }
diff --git a/shared-core/nv10_fb.c b/shared-core/nv10_fb.c
index 6e0773ac..3a4ae09b 100644
--- a/shared-core/nv10_fb.c
+++ b/shared-core/nv10_fb.c
@@ -12,8 +12,8 @@ nv10_fb_init(struct drm_device *dev)
 
 	fb_bar_size = drm_get_resource_len(dev, 0) - 1;
 	for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
-		NV_WRITE(NV10_PFB_TILE(i), 0);
-		NV_WRITE(NV10_PFB_TLIMIT(i), fb_bar_size);
+		nv_wr32(NV10_PFB_TILE(i), 0);
+		nv_wr32(NV10_PFB_TLIMIT(i), fb_bar_size);
 	}
 
 	return 0;
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c
index 6d50b6ca..b2245585 100644
--- a/shared-core/nv10_fifo.c
+++ b/shared-core/nv10_fifo.c
@@ -41,7 +41,7 @@ nv10_fifo_channel_id(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+	return (nv_rd32(NV03_PFIFO_CACHE1_PUSH1) &
 			NV10_PFIFO_CACHE1_PUSH1_CHID_MASK);
 }
 
@@ -74,7 +74,7 @@ nv10_fifo_create_context(struct nouveau_channel *chan)
 				 0);
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE,nv_rd32(NV04_PFIFO_MODE)|(1<<chan->id));
 	return 0;
 }
 
@@ -84,7 +84,7 @@ nv10_fifo_destroy_context(struct nouveau_channel *chan)
 	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE, nv_rd32(NV04_PFIFO_MODE)&~(1<<chan->id));
 
 	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
@@ -96,38 +96,38 @@ nv10_fifo_load_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH1,
 		 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
-	NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
+	nv_wr32(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
 
 	tmp = RAMFC_RD(DMA_INSTANCE);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE     , tmp & 0xFFFF);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT       , tmp >> 16);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_INSTANCE     , tmp & 0xFFFF);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_DCOUNT       , tmp >> 16);
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH        , RAMFC_RD(DMA_FETCH));
-	NV_WRITE(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_FETCH        , RAMFC_RD(DMA_FETCH));
+	nv_wr32(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
+	nv_wr32(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
 
 	if (dev_priv->chipset >= 0x17) {
-		NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
+		nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
 			 RAMFC_RD(ACQUIRE_VALUE));
-		NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
+		nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
 			 RAMFC_RD(ACQUIRE_TIMESTAMP));
-		NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
+		nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
 			 RAMFC_RD(ACQUIRE_TIMEOUT));
-		NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
+		nv_wr32(NV10_PFIFO_CACHE1_SEMAPHORE,
 			 RAMFC_RD(SEMAPHORE));
-		NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
+		nv_wr32(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
 			 RAMFC_RD(DMA_SUBROUTINE));
 	}
 
 	/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
-	tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
+	tmp = nv_rd32(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 
 	return 0;
 }
@@ -139,30 +139,30 @@ nv10_fifo_save_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
-	RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
-	RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
+	RAMFC_WR(DMA_PUT          , nv_rd32(NV04_PFIFO_CACHE1_DMA_PUT));
+	RAMFC_WR(DMA_GET          , nv_rd32(NV04_PFIFO_CACHE1_DMA_GET));
+	RAMFC_WR(REF_CNT          , nv_rd32(NV10_PFIFO_CACHE1_REF_CNT));
 
-	tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
-	tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
+	tmp  = nv_rd32(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
+	tmp |= (nv_rd32(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
 	RAMFC_WR(DMA_INSTANCE     , tmp);
 
-	RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
-	RAMFC_WR(DMA_FETCH	  , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
-	RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
-	RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
+	RAMFC_WR(DMA_STATE        , nv_rd32(NV04_PFIFO_CACHE1_DMA_STATE));
+	RAMFC_WR(DMA_FETCH	  , nv_rd32(NV04_PFIFO_CACHE1_DMA_FETCH));
+	RAMFC_WR(ENGINE           , nv_rd32(NV04_PFIFO_CACHE1_ENGINE));
+	RAMFC_WR(PULL1_ENGINE     , nv_rd32(NV04_PFIFO_CACHE1_PULL1));
 
 	if (dev_priv->chipset >= 0x17) {
 		RAMFC_WR(ACQUIRE_VALUE,
-			 NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+			 nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 		RAMFC_WR(ACQUIRE_TIMESTAMP,
-			 NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+			 nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 		RAMFC_WR(ACQUIRE_TIMEOUT,
-			 NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+			 nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 		RAMFC_WR(SEMAPHORE,
-			 NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+			 nv_rd32(NV10_PFIFO_CACHE1_SEMAPHORE));
 		RAMFC_WR(DMA_SUBROUTINE,
-			 NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+			 nv_rd32(NV04_PFIFO_CACHE1_DMA_GET));
 	}
 
 	return 0;
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index d0c2285f..b2b2e4b5 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -399,9 +399,9 @@ static void nv10_graph_save_pipe(struct nouveau_channel *chan) {
 	int i;
 #define PIPE_SAVE(addr) \
 	do { \
-		NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
+		nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, addr); \
 		for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
-			fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \
+			fifo_pipe_state->pipe_##addr[i] = nv_rd32(NV10_PGRAPH_PIPE_DATA); \
 	} while (0)
 
 	PIPE_SAVE(0x4400);
@@ -427,42 +427,42 @@ static void nv10_graph_load_pipe(struct nouveau_channel *chan) {
 	uint32_t xfmode0, xfmode1;
 #define PIPE_RESTORE(addr) \
 	do { \
-		NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
+		nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, addr); \
 		for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
-			NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
+			nv_wr32(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
 	} while (0)
 
 
 	nouveau_wait_for_idle(dev);
 	/* XXX check haiku comments */
-	xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0);
-	xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1);
-	NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
-	NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
-	NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+	xfmode0 = nv_rd32(NV10_PGRAPH_XFMODE0);
+	xfmode1 = nv_rd32(NV10_PGRAPH_XFMODE1);
+	nv_wr32(NV10_PGRAPH_XFMODE0, 0x10000000);
+	nv_wr32(NV10_PGRAPH_XFMODE1, 0x00000000);
+	nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
 	for (i = 0; i < 4; i++)
-		NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+		nv_wr32(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
 	for (i = 0; i < 4; i++)
-		NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+		nv_wr32(NV10_PGRAPH_PIPE_DATA, 0x00000000);
 
-	NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+	nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
 	for (i = 0; i < 3; i++)
-		NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+		nv_wr32(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
 
-	NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+	nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
 	for (i = 0; i < 3; i++)
-		NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+		nv_wr32(NV10_PGRAPH_PIPE_DATA, 0x00000000);
 
-	NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
-	NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
+	nv_wr32(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+	nv_wr32(NV10_PGRAPH_PIPE_DATA, 0x00000008);
 
 
 	PIPE_RESTORE(0x0200);
 	nouveau_wait_for_idle(dev);
 
 	/* restore XFMODE */
-	NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0);
-	NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1);
+	nv_wr32(NV10_PGRAPH_XFMODE0, xfmode0);
+	nv_wr32(NV10_PGRAPH_XFMODE1, xfmode1);
 	PIPE_RESTORE(0x6400);
 	PIPE_RESTORE(0x6800);
 	PIPE_RESTORE(0x6c00);
@@ -659,10 +659,10 @@ int nv10_graph_load_context(struct nouveau_channel *chan)
 	int i;
 
 	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
-		NV_WRITE(nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]);
+		nv_wr32(nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]);
 	if (dev_priv->chipset>=0x17) {
 		for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++)
-			NV_WRITE(nv17_graph_ctx_regs[i], pgraph_ctx->nv17[i]);
+			nv_wr32(nv17_graph_ctx_regs[i], pgraph_ctx->nv17[i]);
 	}
 
 	nv10_graph_load_pipe(chan);
@@ -678,10 +678,10 @@ int nv10_graph_save_context(struct nouveau_channel *chan)
 	int i;
 
 	for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
-		pgraph_ctx->nv10[i] = NV_READ(nv10_graph_ctx_regs[i]);
+		pgraph_ctx->nv10[i] = nv_rd32(nv10_graph_ctx_regs[i]);
 	if (dev_priv->chipset>=0x17) {
 		for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++)
-			pgraph_ctx->nv17[i] = NV_READ(nv17_graph_ctx_regs[i]);
+			pgraph_ctx->nv17[i] = nv_rd32(nv17_graph_ctx_regs[i]);
 	}
 
 	nv10_graph_save_pipe(chan);
@@ -711,7 +711,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 	}
 	engine = &dev_priv->Engine;
 
-	chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) &
+	chid = (nv_rd32(NV04_PGRAPH_TRAPPED_ADDR) >> 20) &
 		(engine->fifo.channels - 1);
 	next = dev_priv->fifos[chid];
 
@@ -720,7 +720,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 		return;
 	}
 
-	chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & 
+	chid = (nv_rd32(NV10_PGRAPH_CTX_USER) >> 24) & 
 		(engine->fifo.channels - 1);
 	last = dev_priv->fifos[chid];
 
@@ -732,7 +732,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 		         last->id, next->id);
 	}
 
-	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+	nv_wr32(NV04_PGRAPH_FIFO,0x0);
 	if (last) {
 		nouveau_wait_for_idle(dev);
 		nv10_graph_save_context(last);
@@ -740,15 +740,15 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
 
 	nouveau_wait_for_idle(dev);
 
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
 
 	nouveau_wait_for_idle(dev);
 
 	nv10_graph_load_context(next);
 
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_FIFO,0x1);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+	nv_wr32(NV10_PGRAPH_FFINTFC_ST2, nv_rd32(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+	nv_wr32(NV04_PGRAPH_FIFO,0x1);
 }
 
 #define NV_WRITE_CTX(reg, val) do { \
@@ -780,12 +780,12 @@ int nv10_graph_create_context(struct nouveau_channel *chan) {
 #if 0
 	uint32_t tmp, vramsz;
 	/* per channel init from ddx */
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
 	/*XXX the original ddx code, does this in 2 steps :
-	 * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-	 * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
-	 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+	 * tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	 * nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+	 * tmp = nv_rd32(NV10_PGRAPH_SURFACE) | 0x00020100;
+	 * nv_wr32(NV10_PGRAPH_SURFACE, tmp);
 	 */
 	tmp |= 0x00020100;
 	NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp);
@@ -814,8 +814,8 @@ int nv10_graph_create_context(struct nouveau_channel *chan) {
 	NV_WRITE_CTX(0x00400e34, 0x00080008);
 	if (dev_priv->chipset>=0x17) {
 		/* is it really needed ??? */
-		NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4));
-		NV17_WRITE_CTX(0x004006b0, NV_READ(0x004006b0));
+		NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, nv_rd32(NV10_PGRAPH_DEBUG_4));
+		NV17_WRITE_CTX(0x004006b0, nv_rd32(0x004006b0));
 		NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
 		NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
 		NV17_WRITE_CTX(0x00400ec0, 0x00000080);
@@ -838,7 +838,7 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
 	drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER);
 	chan->pgraph_ctx = NULL;
 
-	chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
+	chid = (nv_rd32(NV10_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
 
 	/* This code seems to corrupt the 3D pipe, but blob seems to do similar things ????
 	 */
@@ -846,7 +846,7 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
 	/* does this avoid a potential context switch while we are written graph
 	 * reg, or we should mask graph interrupt ???
 	 */
-	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+	nv_wr32(NV04_PGRAPH_FIFO,0x0);
 	if (chid == chan->id) {
 		DRM_INFO("cleanning a channel with graph in current context\n");
 		nouveau_wait_for_idle(dev);
@@ -855,7 +855,7 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
 		//nv10_graph_create_context(chan);
 		nv10_graph_load_context(chan);
 	}
-	NV_WRITE(NV04_PGRAPH_FIFO, 0x1);
+	nv_wr32(NV04_PGRAPH_FIFO, 0x1);
 #else
 	if (chid == chan->id) {
 		DRM_INFO("cleanning a channel with graph in current context\n");
@@ -867,44 +867,44 @@ int nv10_graph_init(struct drm_device *dev) {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int i;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PGRAPH);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PGRAPH);
 
-	NV_WRITE(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
-	//NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */
-	NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x00000000);
+	nv_wr32(NV04_PGRAPH_DEBUG_1, 0x00118700);
+	//nv_wr32(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */
+	nv_wr32(NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
+	nv_wr32(NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
 				      (1<<29) |
 				      (1<<31));
 	if (dev_priv->chipset>=0x17) {
-		NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000);
-		NV_WRITE(0x004006b0, 0x40000020);
+		nv_wr32(NV10_PGRAPH_DEBUG_4, 0x1f000000);
+		nv_wr32(0x004006b0, 0x40000020);
 	}
 	else
-		NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
+		nv_wr32(NV10_PGRAPH_DEBUG_4, 0x00000000);
 
 	/* copy tile info from PFB */
 	for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
-		NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
-		NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
-		NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
-		NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
+		nv_wr32(NV10_PGRAPH_TILE(i), nv_rd32(NV10_PFB_TILE(i)));
+		nv_wr32(NV10_PGRAPH_TLIMIT(i), nv_rd32(NV10_PFB_TLIMIT(i)));
+		nv_wr32(NV10_PGRAPH_TSIZE(i), nv_rd32(NV10_PFB_TSIZE(i)));
+		nv_wr32(NV10_PGRAPH_TSTATUS(i), nv_rd32(NV10_PFB_TSTATUS(i)));
 	}
 
-	NV_WRITE(NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
-	NV_WRITE(NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
-	NV_WRITE(NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
-	NV_WRITE(NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
+	nv_wr32(NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
+	nv_wr32(NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
+	nv_wr32(NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
+	nv_wr32(NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+	nv_wr32(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_FIFO       , 0x00000001);
 
 	return 0;
 }
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index d862debb..122bfb58 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -639,10 +639,10 @@ int nv20_graph_load_context(struct nouveau_channel *chan)
 		return -EINVAL;
 	inst = chan->ramin_grctx->instance >> 4;
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_XFER,
 		 NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 
 	nouveau_wait_for_idle(dev);
 	return 0;
@@ -658,8 +658,8 @@ int nv20_graph_save_context(struct nouveau_channel *chan)
 		return -EINVAL;
 	inst = chan->ramin_grctx->instance >> 4;
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_XFER,
 		 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
 
 	nouveau_wait_for_idle(dev);
@@ -676,9 +676,9 @@ static void nv20_graph_rdi(struct drm_device *dev) {
 		writecount = 15;
 	}
 
-	NV_WRITE(NV10_PGRAPH_RDI_INDEX, rdi_index);
+	nv_wr32(NV10_PGRAPH_RDI_INDEX, rdi_index);
 	for (i = 0; i < writecount; i++)
-		NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
+		nv_wr32(NV10_PGRAPH_RDI_DATA, 0);
 
 	nouveau_wait_for_idle(dev);
 }
@@ -689,9 +689,9 @@ int nv20_graph_init(struct drm_device *dev) {
 	uint32_t tmp, vramsz;
 	int ret, i;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PGRAPH);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PGRAPH);
 
 	if (!dev_priv->ctx_table) {
@@ -704,94 +704,94 @@ int nv20_graph_init(struct drm_device *dev) {
 			return ret;
 	}
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE,
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_TABLE,
 		 dev_priv->ctx_table->instance >> 4);
 
 	nv20_graph_rdi(dev);
 
-	NV_WRITE(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
-	NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
-	NV_WRITE(0x40009C           , 0x00000040);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x00000000);
+	nv_wr32(NV04_PGRAPH_DEBUG_1, 0x00118700);
+	nv_wr32(NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
+	nv_wr32(NV10_PGRAPH_DEBUG_4, 0x00000000);
+	nv_wr32(0x40009C           , 0x00000040);
 
 	if (dev_priv->chipset >= 0x25) {
-		NV_WRITE(0x400890, 0x00080000);
-		NV_WRITE(0x400610, 0x304B1FB6);
-		NV_WRITE(0x400B80, 0x18B82880);
-		NV_WRITE(0x400B84, 0x44000000);
-		NV_WRITE(0x400098, 0x40000080);
-		NV_WRITE(0x400B88, 0x000000ff);
+		nv_wr32(0x400890, 0x00080000);
+		nv_wr32(0x400610, 0x304B1FB6);
+		nv_wr32(0x400B80, 0x18B82880);
+		nv_wr32(0x400B84, 0x44000000);
+		nv_wr32(0x400098, 0x40000080);
+		nv_wr32(0x400B88, 0x000000ff);
 	} else {
-		NV_WRITE(0x400880, 0x00080000); /* 0x0008c7df */
-		NV_WRITE(0x400094, 0x00000005);
-		NV_WRITE(0x400B80, 0x45CAA208); /* 0x45eae20e */
-		NV_WRITE(0x400B84, 0x24000000);
-		NV_WRITE(0x400098, 0x00000040);
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
+		nv_wr32(0x400880, 0x00080000); /* 0x0008c7df */
+		nv_wr32(0x400094, 0x00000005);
+		nv_wr32(0x400B80, 0x45CAA208); /* 0x45eae20e */
+		nv_wr32(0x400B84, 0x24000000);
+		nv_wr32(0x400098, 0x00000040);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00000030);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00E10038);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00000030);
 	}
 
 	/* copy tile info from PFB */
 	for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-		NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i)));
+		nv_wr32(0x00400904 + i*0x10, nv_rd32(NV10_PFB_TLIMIT(i)));
 			/* which is NV40_PGRAPH_TLIMIT0(i) ?? */
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0030+i*4);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TLIMIT(i)));
-		NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i)));
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0030+i*4);
+		nv_wr32(NV10_PGRAPH_RDI_DATA, nv_rd32(NV10_PFB_TLIMIT(i)));
+		nv_wr32(0x00400908 + i*0x10, nv_rd32(NV10_PFB_TSIZE(i)));
 			/* which is NV40_PGRAPH_TSIZE0(i) ?? */
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0050+i*4);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TSIZE(i)));
-		NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i)));
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0050+i*4);
+		nv_wr32(NV10_PGRAPH_RDI_DATA, nv_rd32(NV10_PFB_TSIZE(i)));
+		nv_wr32(0x00400900 + i*0x10, nv_rd32(NV10_PFB_TILE(i)));
 			/* which is NV40_PGRAPH_TILE0(i) ?? */
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TILE(i)));
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4);
+		nv_wr32(NV10_PGRAPH_RDI_DATA, nv_rd32(NV10_PFB_TILE(i)));
 	}
 	for (i = 0; i < 8; i++) {
-		NV_WRITE(0x400980+i*4, NV_READ(0x100300+i*4));
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0090+i*4);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100300+i*4));
+		nv_wr32(0x400980+i*4, nv_rd32(0x100300+i*4));
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0090+i*4);
+		nv_wr32(NV10_PGRAPH_RDI_DATA, nv_rd32(0x100300+i*4));
 	}
-	NV_WRITE(0x4009a0, NV_READ(0x100324));
-	NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
-	NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100324));
+	nv_wr32(0x4009a0, nv_rd32(0x100324));
+	nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
+	nv_wr32(NV10_PGRAPH_RDI_DATA, nv_rd32(0x100324));
 
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+	nv_wr32(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_FIFO       , 0x00000001);
 
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) | 0x00020100;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
 
 	/* begin RAM config */
 	vramsz = drm_get_resource_len(dev, 0) - 1;
-	NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
-	NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
-	NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
-	NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0));
-	NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
-	NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1));
-	NV_WRITE(0x400820, 0);
-	NV_WRITE(0x400824, 0);
-	NV_WRITE(0x400864, vramsz-1);
-	NV_WRITE(0x400868, vramsz-1);
+	nv_wr32(0x4009A4, nv_rd32(NV04_PFB_CFG0));
+	nv_wr32(0x4009A8, nv_rd32(NV04_PFB_CFG1));
+	nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+	nv_wr32(NV10_PGRAPH_RDI_DATA , nv_rd32(NV04_PFB_CFG0));
+	nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+	nv_wr32(NV10_PGRAPH_RDI_DATA , nv_rd32(NV04_PFB_CFG1));
+	nv_wr32(0x400820, 0);
+	nv_wr32(0x400824, 0);
+	nv_wr32(0x400864, vramsz-1);
+	nv_wr32(0x400868, vramsz-1);
 
 	/* interesting.. the below overwrites some of the tile setup above.. */
-	NV_WRITE(0x400B20, 0x00000000);
-	NV_WRITE(0x400B04, 0xFFFFFFFF);
+	nv_wr32(0x400B20, 0x00000000);
+	nv_wr32(0x400B04, 0xFFFFFFFF);
 
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 
 	return 0;
 }
@@ -809,9 +809,9 @@ int nv30_graph_init(struct drm_device *dev)
 //	uint32_t vramsz, tmp;
 	int ret, i;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PGRAPH);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PGRAPH);
 
 	if (!dev_priv->ctx_table) {
@@ -824,89 +824,89 @@ int nv30_graph_init(struct drm_device *dev)
 			return ret;
 	}
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE,
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_TABLE,
 			dev_priv->ctx_table->instance >> 4);
 
-	NV_WRITE(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);
-	NV_WRITE(0x400890, 0x01b463ff);
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf2de0475);
-	NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
-	NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
-	NV_WRITE(0x400B80, 0x1003d888);
-	NV_WRITE(0x400B84, 0x0c000000);
-	NV_WRITE(0x400098, 0x00000000);
-	NV_WRITE(0x40009C, 0x0005ad00);
-	NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2
-	NV_WRITE(0x4000a0, 0x00000000);
-	NV_WRITE(0x4000a4, 0x00000008);
-	NV_WRITE(0x4008a8, 0xb784a400);
-	NV_WRITE(0x400ba0, 0x002f8685);
-	NV_WRITE(0x400ba4, 0x00231f3f);
-	NV_WRITE(0x4008a4, 0x40000020);
+	nv_wr32(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x00000000);
+	nv_wr32(NV04_PGRAPH_DEBUG_1, 0x401287c0);
+	nv_wr32(0x400890, 0x01b463ff);
+	nv_wr32(NV04_PGRAPH_DEBUG_3, 0xf2de0475);
+	nv_wr32(NV10_PGRAPH_DEBUG_4, 0x00008000);
+	nv_wr32(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
+	nv_wr32(0x400B80, 0x1003d888);
+	nv_wr32(0x400B84, 0x0c000000);
+	nv_wr32(0x400098, 0x00000000);
+	nv_wr32(0x40009C, 0x0005ad00);
+	nv_wr32(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2
+	nv_wr32(0x4000a0, 0x00000000);
+	nv_wr32(0x4000a4, 0x00000008);
+	nv_wr32(0x4008a8, 0xb784a400);
+	nv_wr32(0x400ba0, 0x002f8685);
+	nv_wr32(0x400ba4, 0x00231f3f);
+	nv_wr32(0x4008a4, 0x40000020);
 
 	if (dev_priv->chipset == 0x34) {
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201);
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008);
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032);
-		NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004);
-		NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00200201);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00000008);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00000032);
+		nv_wr32(NV10_PGRAPH_RDI_INDEX, 0x00E00004);
+		nv_wr32(NV10_PGRAPH_RDI_DATA , 0x00000002);
 	}
 
-	NV_WRITE(0x4000c0, 0x00000016);
+	nv_wr32(0x4000c0, 0x00000016);
 
 	/* copy tile info from PFB */
 	for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
-		NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i)));
+		nv_wr32(0x00400904 + i*0x10, nv_rd32(NV10_PFB_TLIMIT(i)));
 			/* which is NV40_PGRAPH_TLIMIT0(i) ?? */
-		NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i)));
+		nv_wr32(0x00400908 + i*0x10, nv_rd32(NV10_PFB_TSIZE(i)));
 			/* which is NV40_PGRAPH_TSIZE0(i) ?? */
-		NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i)));
+		nv_wr32(0x00400900 + i*0x10, nv_rd32(NV10_PFB_TILE(i)));
 			/* which is NV40_PGRAPH_TILE0(i) ?? */
 	}
 
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	NV_WRITE(0x0040075c             , 0x00000001);
-	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+	nv_wr32(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
+	nv_wr32(0x0040075c             , 0x00000001);
+	nv_wr32(NV04_PGRAPH_FIFO       , 0x00000001);
 
 	/* begin RAM config */
 //	vramsz = drm_get_resource_len(dev, 0) - 1;
-	NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
-	NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
+	nv_wr32(0x4009A4, nv_rd32(NV04_PFB_CFG0));
+	nv_wr32(0x4009A8, nv_rd32(NV04_PFB_CFG1));
 	if (dev_priv->chipset != 0x34) {
-		NV_WRITE(0x400750, 0x00EA0000);
-		NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0));
-		NV_WRITE(0x400750, 0x00EA0004);
-		NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1));
+		nv_wr32(0x400750, 0x00EA0000);
+		nv_wr32(0x400754, nv_rd32(NV04_PFB_CFG0));
+		nv_wr32(0x400750, 0x00EA0004);
+		nv_wr32(0x400754, nv_rd32(NV04_PFB_CFG1));
 	}
 
 #if 0
-	NV_WRITE(0x400820, 0);
-	NV_WRITE(0x400824, 0);
-	NV_WRITE(0x400864, vramsz-1);
-	NV_WRITE(0x400868, vramsz-1);
+	nv_wr32(0x400820, 0);
+	nv_wr32(0x400824, 0);
+	nv_wr32(0x400864, vramsz-1);
+	nv_wr32(0x400868, vramsz-1);
 
-	NV_WRITE(0x400B20, 0x00000000);
-	NV_WRITE(0x400B04, 0xFFFFFFFF);
+	nv_wr32(0x400B20, 0x00000000);
+	nv_wr32(0x400B04, 0xFFFFFFFF);
 
 	/* per-context state, doesn't belong here */
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) | 0x00020100;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 #endif
 
 	return 0;
diff --git a/shared-core/nv40_fb.c b/shared-core/nv40_fb.c
index ae784cb8..530bbeed 100644
--- a/shared-core/nv40_fb.c
+++ b/shared-core/nv40_fb.c
@@ -16,13 +16,13 @@ nv40_fb_init(struct drm_device *dev)
 	/* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
 	/* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
 	/* Any idea what this is? */
-	NV_WRITE(NV40_PFB_UNK_800, 0x1);
+	nv_wr32(NV40_PFB_UNK_800, 0x1);
 
 	switch (dev_priv->chipset) {
 	case 0x40:
 	case 0x45:
-		tmp = NV_READ(NV10_PFB_CLOSE_PAGE2);
-		NV_WRITE(NV10_PFB_CLOSE_PAGE2, tmp & ~(1<<15));
+		tmp = nv_rd32(NV10_PFB_CLOSE_PAGE2);
+		nv_wr32(NV10_PFB_CLOSE_PAGE2, tmp & ~(1<<15));
 		num_tiles = NV10_PFB_TILE__SIZE;
 		break;
 	case 0x46: /* G72 */
@@ -41,14 +41,14 @@ nv40_fb_init(struct drm_device *dev)
 	switch (dev_priv->chipset) {
 	case 0x40:
 		for (i=0; i<num_tiles; i++) {
-			NV_WRITE(NV10_PFB_TILE(i), 0);
-			NV_WRITE(NV10_PFB_TLIMIT(i), fb_bar_size);
+			nv_wr32(NV10_PFB_TILE(i), 0);
+			nv_wr32(NV10_PFB_TLIMIT(i), fb_bar_size);
 		}
 		break;
 	default:
 		for (i=0; i<num_tiles; i++) {
-			NV_WRITE(NV40_PFB_TILE(i), 0);
-			NV_WRITE(NV40_PFB_TLIMIT(i), fb_bar_size);
+			nv_wr32(NV40_PFB_TILE(i), 0);
+			nv_wr32(NV40_PFB_TLIMIT(i), fb_bar_size);
 		}
 		break;
 	}
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index 7f9d5e31..983b346d 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -68,7 +68,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
 	RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
 
 	/* enable the fifo dma operation */
-	NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE,nv_rd32(NV04_PFIFO_MODE)|(1<<chan->id));
 	return 0;
 }
 
@@ -78,7 +78,7 @@ nv40_fifo_destroy_context(struct nouveau_channel *chan)
 	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
+	nv_wr32(NV04_PFIFO_MODE, nv_rd32(NV04_PFIFO_MODE)&~(1<<chan->id));
 
 	if (chan->ramfc)
 		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
@@ -91,56 +91,56 @@ nv40_fifo_load_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp, tmp2;
 
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
-	NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE     , RAMFC_RD(DMA_INSTANCE));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT       , RAMFC_RD(DMA_DCOUNT));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
+	nv_wr32(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_INSTANCE     , RAMFC_RD(DMA_INSTANCE));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_DCOUNT       , RAMFC_RD(DMA_DCOUNT));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
 
 	/* No idea what 0x2058 is.. */
 	tmp   = RAMFC_RD(DMA_FETCH);
-	tmp2  = NV_READ(0x2058) & 0xFFF;
+	tmp2  = nv_rd32(0x2058) & 0xFFF;
 	tmp2 |= (tmp & 0x30000000);
-	NV_WRITE(0x2058, tmp2);
+	nv_wr32(0x2058, tmp2);
 	tmp  &= ~0x30000000;
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH        , tmp);
-
-	NV_WRITE(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
-	NV_WRITE(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
-	NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE    , RAMFC_RD(ACQUIRE_VALUE));
-	NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP));
-	NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT  , RAMFC_RD(ACQUIRE_TIMEOUT));
-	NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE        , RAMFC_RD(SEMAPHORE));
-	NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE   , RAMFC_RD(DMA_SUBROUTINE));
-	NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE          , RAMFC_RD(GRCTX_INSTANCE));
-	NV_WRITE(0x32e4, RAMFC_RD(UNK_40));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_FETCH        , tmp);
+
+	nv_wr32(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
+	nv_wr32(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
+	nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_VALUE    , RAMFC_RD(ACQUIRE_VALUE));
+	nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP));
+	nv_wr32(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT  , RAMFC_RD(ACQUIRE_TIMEOUT));
+	nv_wr32(NV10_PFIFO_CACHE1_SEMAPHORE        , RAMFC_RD(SEMAPHORE));
+	nv_wr32(NV10_PFIFO_CACHE1_DMA_SUBROUTINE   , RAMFC_RD(DMA_SUBROUTINE));
+	nv_wr32(NV40_PFIFO_GRCTX_INSTANCE          , RAMFC_RD(GRCTX_INSTANCE));
+	nv_wr32(0x32e4, RAMFC_RD(UNK_40));
 	/* NVIDIA does this next line twice... */
-	NV_WRITE(0x32e8, RAMFC_RD(UNK_44));
-	NV_WRITE(0x2088, RAMFC_RD(UNK_4C));
-	NV_WRITE(0x3300, RAMFC_RD(UNK_50));
+	nv_wr32(0x32e8, RAMFC_RD(UNK_44));
+	nv_wr32(0x2088, RAMFC_RD(UNK_4C));
+	nv_wr32(0x3300, RAMFC_RD(UNK_50));
 
 	/* not sure what part is PUT, and which is GET.. never seen a non-zero
 	 * value appear in a mmio-trace yet..
 	 */
 #if 0
-	tmp = NV_READ(UNK_84);
-	NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???);
-	NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???);
+	tmp = nv_rd32(UNK_84);
+	nv_wr32(NV_PFIFO_CACHE1_GET, tmp ???);
+	nv_wr32(NV_PFIFO_CACHE1_PUT, tmp ???);
 #endif
 
 	/* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
-	tmp  = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
+	tmp  = nv_rd32(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
 	tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF;
-	NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
+	nv_wr32(NV04_PFIFO_DMA_TIMESLICE, tmp);
 
 	/* Set channel active, and in DMA mode */
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH1,
 		 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 
 	/* Reset DMA_CTL_AT_INFO to INVALID */
-	tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
+	tmp = nv_rd32(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 
 	return 0;
 }
@@ -152,43 +152,43 @@ nv40_fifo_save_context(struct nouveau_channel *chan)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
-	RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
-	RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
-	RAMFC_WR(DMA_INSTANCE     , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
-	RAMFC_WR(DMA_DCOUNT       , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT));
-	RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+	RAMFC_WR(DMA_PUT          , nv_rd32(NV04_PFIFO_CACHE1_DMA_PUT));
+	RAMFC_WR(DMA_GET          , nv_rd32(NV04_PFIFO_CACHE1_DMA_GET));
+	RAMFC_WR(REF_CNT          , nv_rd32(NV10_PFIFO_CACHE1_REF_CNT));
+	RAMFC_WR(DMA_INSTANCE     , nv_rd32(NV04_PFIFO_CACHE1_DMA_INSTANCE));
+	RAMFC_WR(DMA_DCOUNT       , nv_rd32(NV04_PFIFO_CACHE1_DMA_DCOUNT));
+	RAMFC_WR(DMA_STATE        , nv_rd32(NV04_PFIFO_CACHE1_DMA_STATE));
 
-	tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH);
-	tmp |= NV_READ(0x2058) & 0x30000000;
+	tmp  = nv_rd32(NV04_PFIFO_CACHE1_DMA_FETCH);
+	tmp |= nv_rd32(0x2058) & 0x30000000;
 	RAMFC_WR(DMA_FETCH	  , tmp);
 
-	RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
-	RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
-	RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
-	tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
+	RAMFC_WR(ENGINE           , nv_rd32(NV04_PFIFO_CACHE1_ENGINE));
+	RAMFC_WR(PULL1_ENGINE     , nv_rd32(NV04_PFIFO_CACHE1_PULL1));
+	RAMFC_WR(ACQUIRE_VALUE    , nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+	tmp = nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
 	RAMFC_WR(ACQUIRE_TIMESTAMP, tmp);
-	RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
-	RAMFC_WR(SEMAPHORE        , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+	RAMFC_WR(ACQUIRE_TIMEOUT  , nv_rd32(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+	RAMFC_WR(SEMAPHORE        , nv_rd32(NV10_PFIFO_CACHE1_SEMAPHORE));
 
 	/* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
 	 * more involved depending on the value of 0x3228?
 	 */
-	RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+	RAMFC_WR(DMA_SUBROUTINE   , nv_rd32(NV04_PFIFO_CACHE1_DMA_GET));
 
-	RAMFC_WR(GRCTX_INSTANCE   , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
+	RAMFC_WR(GRCTX_INSTANCE   , nv_rd32(NV40_PFIFO_GRCTX_INSTANCE));
 
 	/* No idea what the below is for exactly, ripped from a mmio-trace */
-	RAMFC_WR(UNK_40           , NV_READ(NV40_PFIFO_UNK32E4));
+	RAMFC_WR(UNK_40           , nv_rd32(NV40_PFIFO_UNK32E4));
 
 	/* NVIDIA do this next line twice.. bug? */
-	RAMFC_WR(UNK_44           , NV_READ(0x32e8));
-	RAMFC_WR(UNK_4C           , NV_READ(0x2088));
-	RAMFC_WR(UNK_50           , NV_READ(0x3300));
+	RAMFC_WR(UNK_44           , nv_rd32(0x32e8));
+	RAMFC_WR(UNK_4C           , nv_rd32(0x2088));
+	RAMFC_WR(UNK_50           , nv_rd32(0x3300));
 
 #if 0 /* no real idea which is PUT/GET in UNK_48.. */
-	tmp  = NV_READ(NV04_PFIFO_CACHE1_GET);
-	tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16);
+	tmp  = nv_rd32(NV04_PFIFO_CACHE1_GET);
+	tmp |= (nv_rd32(NV04_PFIFO_CACHE1_PUT) << 16);
 	RAMFC_WR(UNK_48           , tmp);
 #endif
 
@@ -204,6 +204,6 @@ nv40_fifo_init(struct drm_device *dev)
 	if ((ret = nouveau_fifo_init(dev)))
 		return ret;
 
-	NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
+	nv_wr32(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
 	return 0;
 }
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 4c378a05..b0340c5a 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -1532,35 +1532,35 @@ nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
 	uint32_t old_cp, tv = 1000, tmp;
 	int i;
 
-	old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	old_cp = nv_rd32(NV20_PGRAPH_CHANNEL_CTX_POINTER);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 
-	tmp  = NV_READ(NV40_PGRAPH_CTXCTL_0310);
+	tmp  = nv_rd32(NV40_PGRAPH_CTXCTL_0310);
 	tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
 		      NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
-	NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp);
+	nv_wr32(NV40_PGRAPH_CTXCTL_0310, tmp);
 
-	tmp  = NV_READ(NV40_PGRAPH_CTXCTL_0304);
+	tmp  = nv_rd32(NV40_PGRAPH_CTXCTL_0304);
 	tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
-	NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp);
+	nv_wr32(NV40_PGRAPH_CTXCTL_0304, tmp);
 
 	nouveau_wait_for_idle(dev);
 
 	for (i = 0; i < tv; i++) {
-		if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
+		if (nv_rd32(NV40_PGRAPH_CTXCTL_030C) == 0)
 			break;
 	}
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
 
 	if (i == tv) {
-		uint32_t ucstat = NV_READ(NV40_PGRAPH_CTXCTL_UCODE_STAT);
+		uint32_t ucstat = nv_rd32(NV40_PGRAPH_CTXCTL_UCODE_STAT);
 		DRM_ERROR("Failed: Instance=0x%08x Save=%d\n", inst, save);
 		DRM_ERROR("IP: 0x%02x, Opcode: 0x%08x\n",
 			  ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
 			  ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
 		DRM_ERROR("0x40030C = 0x%08x\n",
-			  NV_READ(NV40_PGRAPH_CTXCTL_030C));
+			  nv_rd32(NV40_PGRAPH_CTXCTL_030C));
 		return -EBUSY;
 	}
 
@@ -1603,15 +1603,15 @@ nv40_graph_load_context(struct nouveau_channel *chan)
 	 * unknown as to what bit 24 does.  The nv ddx has it set, so we will
 	 * set it here too.
 	 */
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
-	NV_WRITE(NV40_PGRAPH_CTXCTL_CUR,
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	nv_wr32(NV40_PGRAPH_CTXCTL_CUR,
 		 (inst & NV40_PGRAPH_CTXCTL_CUR_INST_MASK) |
 		  NV40_PGRAPH_CTXCTL_CUR_LOADED);
 	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
 	 * context.  If at any time this doesn't match 0x40032C, you will
 	 * recieve PGRAPH_INTR_CONTEXT_SWITCH
 	 */
-	NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
+	nv_wr32(NV40_PFIFO_GRCTX_INSTANCE, inst);
 	return 0;
 }
 
@@ -1960,9 +1960,9 @@ nv40_graph_init(struct drm_device *dev)
 	uint32_t vramsz, tmp;
 	int i, j;
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) &
 			~NV_PMC_ENABLE_PGRAPH);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |
 			 NV_PMC_ENABLE_PGRAPH);
 
 	switch (dev_priv->chipset) {
@@ -1989,110 +1989,110 @@ nv40_graph_init(struct drm_device *dev)
 	DRM_DEBUG("Loading context program\n");
 
 	i = 0;
-	NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+	nv_wr32(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 	while (ctx_prog[i] != ~0) {
-		NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_prog[i]);
+		nv_wr32(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_prog[i]);
 		i++;
 	}
 
 	/* No context present currently */
-	NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
+	nv_wr32(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 
-	NV_WRITE(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	NV_WRITE(NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
+	nv_wr32(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
+	nv_wr32(NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
-	NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xe0de8055);
-	NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
-	NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_DEBUG_0, 0x00000000);
+	nv_wr32(NV04_PGRAPH_DEBUG_1, 0x401287c0);
+	nv_wr32(NV04_PGRAPH_DEBUG_3, 0xe0de8055);
+	nv_wr32(NV10_PGRAPH_DEBUG_4, 0x00008000);
+	nv_wr32(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 
-	NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-	NV_WRITE(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	NV_WRITE(NV04_PGRAPH_FIFO       , 0x00000001);
+	nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+	nv_wr32(NV10_PGRAPH_STATE      , 0xFFFFFFFF);
+	nv_wr32(NV04_PGRAPH_FIFO       , 0x00000001);
 
-	j = NV_READ(0x1540) & 0xff;
+	j = nv_rd32(0x1540) & 0xff;
 	if (j) {
 		for (i=0; !(j&1); j>>=1, i++);
-		NV_WRITE(0x405000, i);
+		nv_wr32(0x405000, i);
 	}
 
 	if (dev_priv->chipset == 0x40) {
-		NV_WRITE(0x4009b0, 0x83280fff);
-		NV_WRITE(0x4009b4, 0x000000a0);
+		nv_wr32(0x4009b0, 0x83280fff);
+		nv_wr32(0x4009b4, 0x000000a0);
 	} else {
-		NV_WRITE(0x400820, 0x83280eff);
-		NV_WRITE(0x400824, 0x000000a0);
+		nv_wr32(0x400820, 0x83280eff);
+		nv_wr32(0x400824, 0x000000a0);
 	}
 
 	switch (dev_priv->chipset) {
 	case 0x40:
 	case 0x45:
-		NV_WRITE(0x4009b8, 0x0078e366);
-		NV_WRITE(0x4009bc, 0x0000014c);
+		nv_wr32(0x4009b8, 0x0078e366);
+		nv_wr32(0x4009bc, 0x0000014c);
 		break;
 	case 0x41:
 	case 0x42: /* pciid also 0x00Cx */
 //	case 0x0120: //XXX (pciid)
-		NV_WRITE(0x400828, 0x007596ff);
-		NV_WRITE(0x40082c, 0x00000108);
+		nv_wr32(0x400828, 0x007596ff);
+		nv_wr32(0x40082c, 0x00000108);
 		break;
 	case 0x43:
-		NV_WRITE(0x400828, 0x0072cb77);
-		NV_WRITE(0x40082c, 0x00000108);
+		nv_wr32(0x400828, 0x0072cb77);
+		nv_wr32(0x40082c, 0x00000108);
 		break;
 	case 0x44:
 	case 0x46: /* G72 */
 	case 0x4a:
 	case 0x4c: /* G7x-based C51 */
 	case 0x4e:
-		NV_WRITE(0x400860, 0);
-		NV_WRITE(0x400864, 0);
+		nv_wr32(0x400860, 0);
+		nv_wr32(0x400864, 0);
 		break;
 	case 0x47: /* G70 */
 	case 0x49: /* G71 */
 	case 0x4b: /* G73 */
-		NV_WRITE(0x400828, 0x07830610);
-		NV_WRITE(0x40082c, 0x0000016A);
+		nv_wr32(0x400828, 0x07830610);
+		nv_wr32(0x40082c, 0x0000016A);
 		break;
 	default:
 		break;
 	}
 
-	NV_WRITE(0x400b38, 0x2ffff800);
-	NV_WRITE(0x400b3c, 0x00006000);
+	nv_wr32(0x400b38, 0x2ffff800);
+	nv_wr32(0x400b3c, 0x00006000);
 
 	/* copy tile info from PFB */
 	switch (dev_priv->chipset) {
 	case 0x40: /* vanilla NV40 */
 		for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
-			tmp = NV_READ(NV10_PFB_TILE(i));
-			NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
-			tmp = NV_READ(NV10_PFB_TLIMIT(i));
-			NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
-			tmp = NV_READ(NV10_PFB_TSIZE(i));
-			NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
-			tmp = NV_READ(NV10_PFB_TSTATUS(i));
-			NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
+			tmp = nv_rd32(NV10_PFB_TILE(i));
+			nv_wr32(NV40_PGRAPH_TILE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TILE1(i), tmp);
+			tmp = nv_rd32(NV10_PFB_TLIMIT(i));
+			nv_wr32(NV40_PGRAPH_TLIMIT0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TLIMIT1(i), tmp);
+			tmp = nv_rd32(NV10_PFB_TSIZE(i));
+			nv_wr32(NV40_PGRAPH_TSIZE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSIZE1(i), tmp);
+			tmp = nv_rd32(NV10_PFB_TSTATUS(i));
+			nv_wr32(NV40_PGRAPH_TSTATUS0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSTATUS1(i), tmp);
 		}
 		break;
 	case 0x44:
 	case 0x4a:
 	case 0x4e: /* NV44-based cores don't have 0x406900? */
 		for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {
-			tmp = NV_READ(NV40_PFB_TILE(i));
-			NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
-			tmp = NV_READ(NV40_PFB_TLIMIT(i));
-			NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSIZE(i));
-			NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSTATUS(i));
-			NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TILE(i));
+			nv_wr32(NV40_PGRAPH_TILE0(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TLIMIT(i));
+			nv_wr32(NV40_PGRAPH_TLIMIT0(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSIZE(i));
+			nv_wr32(NV40_PGRAPH_TSIZE0(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSTATUS(i));
+			nv_wr32(NV40_PGRAPH_TSTATUS0(i), tmp);
 		}
 		break;
 	case 0x46:
@@ -2100,34 +2100,34 @@ nv40_graph_init(struct drm_device *dev)
 	case 0x49:
 	case 0x4b: /* G7X-based cores */
 		for (i=0; i<NV40_PFB_TILE__SIZE_1; i++) {
-			tmp = NV_READ(NV40_PFB_TILE(i));
-			NV_WRITE(NV47_PGRAPH_TILE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TLIMIT(i));
-			NV_WRITE(NV47_PGRAPH_TLIMIT0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSIZE(i));
-			NV_WRITE(NV47_PGRAPH_TSIZE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSTATUS(i));
-			NV_WRITE(NV47_PGRAPH_TSTATUS0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TILE(i));
+			nv_wr32(NV47_PGRAPH_TILE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TILE1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TLIMIT(i));
+			nv_wr32(NV47_PGRAPH_TLIMIT0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TLIMIT1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSIZE(i));
+			nv_wr32(NV47_PGRAPH_TSIZE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSIZE1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSTATUS(i));
+			nv_wr32(NV47_PGRAPH_TSTATUS0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSTATUS1(i), tmp);
 		}
 		break;
 	default: /* everything else */
 		for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {
-			tmp = NV_READ(NV40_PFB_TILE(i));
-			NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TLIMIT(i));
-			NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSIZE(i));
-			NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
-			tmp = NV_READ(NV40_PFB_TSTATUS(i));
-			NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
-			NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TILE(i));
+			nv_wr32(NV40_PGRAPH_TILE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TILE1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TLIMIT(i));
+			nv_wr32(NV40_PGRAPH_TLIMIT0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TLIMIT1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSIZE(i));
+			nv_wr32(NV40_PGRAPH_TSIZE0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSIZE1(i), tmp);
+			tmp = nv_rd32(NV40_PFB_TSTATUS(i));
+			nv_wr32(NV40_PGRAPH_TSTATUS0(i), tmp);
+			nv_wr32(NV40_PGRAPH_TSTATUS1(i), tmp);
 		}
 		break;
 	}
@@ -2136,14 +2136,14 @@ nv40_graph_init(struct drm_device *dev)
 	vramsz = drm_get_resource_len(dev, 0) - 1;
 	switch (dev_priv->chipset) {
 	case 0x40:
-		NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
-		NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
-		NV_WRITE(0x4069A4, NV_READ(NV04_PFB_CFG0));
-		NV_WRITE(0x4069A8, NV_READ(NV04_PFB_CFG1));
-		NV_WRITE(0x400820, 0);
-		NV_WRITE(0x400824, 0);
-		NV_WRITE(0x400864, vramsz);
-		NV_WRITE(0x400868, vramsz);
+		nv_wr32(0x4009A4, nv_rd32(NV04_PFB_CFG0));
+		nv_wr32(0x4009A8, nv_rd32(NV04_PFB_CFG1));
+		nv_wr32(0x4069A4, nv_rd32(NV04_PFB_CFG0));
+		nv_wr32(0x4069A8, nv_rd32(NV04_PFB_CFG1));
+		nv_wr32(0x400820, 0);
+		nv_wr32(0x400824, 0);
+		nv_wr32(0x400864, vramsz);
+		nv_wr32(0x400868, vramsz);
 		break;
 	default:
 		switch (dev_priv->chipset) {
@@ -2151,36 +2151,36 @@ nv40_graph_init(struct drm_device *dev)
 		case 0x47:
 		case 0x49:
 		case 0x4b:
-			NV_WRITE(0x400DF0, NV_READ(NV04_PFB_CFG0));
-			NV_WRITE(0x400DF4, NV_READ(NV04_PFB_CFG1));
+			nv_wr32(0x400DF0, nv_rd32(NV04_PFB_CFG0));
+			nv_wr32(0x400DF4, nv_rd32(NV04_PFB_CFG1));
 			break;
 		default:
-			NV_WRITE(0x4009F0, NV_READ(NV04_PFB_CFG0));
-			NV_WRITE(0x4009F4, NV_READ(NV04_PFB_CFG1));
+			nv_wr32(0x4009F0, nv_rd32(NV04_PFB_CFG0));
+			nv_wr32(0x4009F4, nv_rd32(NV04_PFB_CFG1));
 			break;
 		}
-		NV_WRITE(0x4069F0, NV_READ(NV04_PFB_CFG0));
-		NV_WRITE(0x4069F4, NV_READ(NV04_PFB_CFG1));
-		NV_WRITE(0x400840, 0);
-		NV_WRITE(0x400844, 0);
-		NV_WRITE(0x4008A0, vramsz);
-		NV_WRITE(0x4008A4, vramsz);
+		nv_wr32(0x4069F0, nv_rd32(NV04_PFB_CFG0));
+		nv_wr32(0x4069F4, nv_rd32(NV04_PFB_CFG1));
+		nv_wr32(0x400840, 0);
+		nv_wr32(0x400844, 0);
+		nv_wr32(0x4008A0, vramsz);
+		nv_wr32(0x4008A4, vramsz);
 		break;
 	}
 
 	/* per-context state, doesn't belong here */
-	NV_WRITE(0x400B20, 0x00000000);
-	NV_WRITE(0x400B04, 0xFFFFFFFF);
-
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-	tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
-	NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
-
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
-	NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+	nv_wr32(0x400B20, 0x00000000);
+	nv_wr32(0x400B04, 0xFFFFFFFF);
+
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+	tmp = nv_rd32(NV10_PGRAPH_SURFACE) | 0x00020100;
+	nv_wr32(NV10_PGRAPH_SURFACE, tmp);
+
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+	nv_wr32(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 
 	return 0;
 }
diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c
index ead6f87f..87c62133 100644
--- a/shared-core/nv40_mc.c
+++ b/shared-core/nv40_mc.c
@@ -12,18 +12,18 @@ nv40_mc_init(struct drm_device *dev)
 	/* Power up everything, resetting each individual unit will
 	 * be done later if needed.
 	 */
-	NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
+	nv_wr32(NV03_PMC_ENABLE, 0xFFFFFFFF);
 
 	switch (dev_priv->chipset) {
 	case 0x44:
 	case 0x46: /* G72 */
 	case 0x4e:
 	case 0x4c: /* C51_G7X */
-		tmp = NV_READ(NV40_PFB_020C);
-		NV_WRITE(NV40_PMC_1700, tmp);
-		NV_WRITE(NV40_PMC_1704, 0);
-		NV_WRITE(NV40_PMC_1708, 0);
-		NV_WRITE(NV40_PMC_170C, tmp);
+		tmp = nv_rd32(NV40_PFB_020C);
+		nv_wr32(NV40_PMC_1700, tmp);
+		nv_wr32(NV40_PMC_1704, 0);
+		nv_wr32(NV40_PMC_1708, 0);
+		nv_wr32(NV40_PMC_170C, tmp);
 		break;
 	default:
 		break;
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index 59a7b101..07d6b9d8 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -54,9 +54,9 @@ nv50_fifo_init_thingo(struct drm_device *dev)
 			INSTANCE_WR(cur->gpuobj, nr++, i);
 		}
 	}
-	NV_WRITE(0x32f4, cur->instance >> 12);
-	NV_WRITE(0x32ec, nr);
-	NV_WRITE(0x2500, 0x101);
+	nv_wr32(0x32f4, cur->instance >> 12);
+	nv_wr32(0x32ec, nr);
+	nv_wr32(0x2500, 0x101);
 }
 
 static int
@@ -73,7 +73,7 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
 
 	if (IS_G80) inst = chan->ramfc->instance >> 12;
 	else        inst = chan->ramfc->instance >> 8;
-	NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
+	nv_wr32(NV50_PFIFO_CTX_TABLE(channel),
 		 inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
 
 	if (!nt) nv50_fifo_init_thingo(dev);
@@ -90,7 +90,7 @@ nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
 
 	if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
 	else        inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
-	NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
+	nv_wr32(NV50_PFIFO_CTX_TABLE(channel), inst);
 
 	if (!nt) nv50_fifo_init_thingo(dev);
 }
@@ -103,8 +103,8 @@ nv50_fifo_init_reset(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |  pmc_e);
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) & ~pmc_e);
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |  pmc_e);
 }
 
 static void
@@ -114,8 +114,8 @@ nv50_fifo_init_intr(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
-	NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
+	nv_wr32(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
+	nv_wr32(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 }
 
 static void
@@ -137,7 +137,7 @@ nv50_fifo_init_regs__nv(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(0x250c, 0x6f3cfc34);
+	nv_wr32(0x250c, 0x6f3cfc34);
 }
 
 static void
@@ -147,12 +147,12 @@ nv50_fifo_init_regs(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(0x2500, 0);
-	NV_WRITE(0x3250, 0);
-	NV_WRITE(0x3220, 0);
-	NV_WRITE(0x3204, 0);
-	NV_WRITE(0x3210, 0);
-	NV_WRITE(0x3270, 0);
+	nv_wr32(0x2500, 0);
+	nv_wr32(0x3250, 0);
+	nv_wr32(0x3220, 0);
+	nv_wr32(0x3204, 0);
+	nv_wr32(0x3210, 0);
+	nv_wr32(0x3270, 0);
 
 	/* Enable dummy channels setup by nv50_instmem.c */
 	nv50_fifo_channel_enable(dev, 0, 1);
@@ -220,7 +220,7 @@ nv50_fifo_channel_id(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+	return (nv_rd32(NV03_PFIFO_CACHE1_PUSH1) &
 			NV50_PFIFO_CACHE1_PUSH1_CHID_MASK);
 }
 
@@ -299,8 +299,8 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
 	if (chan->id == 0)
 		nv50_fifo_channel_disable(dev, 127, 0);
 
-	if ((NV_READ(NV03_PFIFO_CACHE1_PUSH1) & 0xffff) == chan->id)
-		NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 127);
+	if ((nv_rd32(NV03_PFIFO_CACHE1_PUSH1) & 0xffff) == chan->id)
+		nv_wr32(NV03_PFIFO_CACHE1_PUSH1, 127);
 
 	nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
@@ -316,21 +316,21 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
 
 	/*XXX: incomplete, only touches the regs that NV does */
 
-	NV_WRITE(0x3244, INSTANCE_RD(ramfc, 0x08/4));
-	NV_WRITE(0x3240, INSTANCE_RD(ramfc, 0x10/4));
+	nv_wr32(0x3244, INSTANCE_RD(ramfc, 0x08/4));
+	nv_wr32(0x3240, INSTANCE_RD(ramfc, 0x10/4));
 
-	NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4));
-	NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4));
-	NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4));
-	NV_WRITE(0x3254, 1);
-	NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4));
+	nv_wr32(0x3224, INSTANCE_RD(ramfc, 0x3c/4));
+	nv_wr32(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4));
+	nv_wr32(0x3234, INSTANCE_RD(ramfc, 0x4c/4));
+	nv_wr32(0x3254, 1);
+	nv_wr32(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4));
 
 	if (!IS_G80) {
-		NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4));
-		NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4));
+		nv_wr32(0x340c, INSTANCE_RD(ramfc, 0x88/4));
+		nv_wr32(0x3410, INSTANCE_RD(ramfc, 0x98/4));
 	}
 
-	NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
+	nv_wr32(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
 	return 0;
 }
 
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index 2cb06a2c..a4c7e1b1 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -39,8 +39,8 @@ nv50_graph_init_reset(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
-	NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |  pmc_e);
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) & ~pmc_e);
+	nv_wr32(NV03_PMC_ENABLE, nv_rd32(NV03_PMC_ENABLE) |  pmc_e);
 }
 
 static void
@@ -49,9 +49,9 @@ nv50_graph_init_intr(struct drm_device *dev)
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	DRM_DEBUG("\n");
-	NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff);
-	NV_WRITE(0x400138, 0xffffffff);
-	NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff);
+	nv_wr32(NV03_PGRAPH_INTR, 0xffffffff);
+	nv_wr32(0x400138, 0xffffffff);
+	nv_wr32(NV40_PGRAPH_INTR_EN, 0xffffffff);
 }
 
 static void
@@ -61,17 +61,17 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(0x400804, 0xc0000000);
-	NV_WRITE(0x406800, 0xc0000000);
-	NV_WRITE(0x400c04, 0xc0000000);
-	NV_WRITE(0x401804, 0xc0000000);
-	NV_WRITE(0x405018, 0xc0000000);
-	NV_WRITE(0x402000, 0xc0000000);
+	nv_wr32(0x400804, 0xc0000000);
+	nv_wr32(0x406800, 0xc0000000);
+	nv_wr32(0x400c04, 0xc0000000);
+	nv_wr32(0x401804, 0xc0000000);
+	nv_wr32(0x405018, 0xc0000000);
+	nv_wr32(0x402000, 0xc0000000);
 
-	NV_WRITE(0x400108, 0xffffffff);
+	nv_wr32(0x400108, 0xffffffff);
 
-	NV_WRITE(0x400824, 0x00004000);
-	NV_WRITE(0x400500, 0x00010001);
+	nv_wr32(0x400824, 0x00004000);
+	nv_wr32(0x400500, 0x00010001);
 }
 
 static void
@@ -81,7 +81,7 @@ nv50_graph_init_regs(struct drm_device *dev)
 
 	DRM_DEBUG("\n");
 
-	NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */);
+	nv_wr32(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */);
 }
 
 static int
@@ -123,15 +123,15 @@ nv50_graph_init_ctxctl(struct drm_device *dev)
 		return -EINVAL;
 	}
 
-	NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+	nv_wr32(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 	while (*voodoo != ~0) {
-		NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
+		nv_wr32(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
 		voodoo++;
 	}
 
-	NV_WRITE(0x400320, 4);
-	NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0);
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
+	nv_wr32(0x400320, 4);
+	nv_wr32(NV40_PGRAPH_CTXCTL_CUR, 0);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 
 	return 0;
 }
@@ -268,23 +268,23 @@ nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
 
 	DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save);
 
-	old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
-	NV_WRITE(0x400824, NV_READ(0x400824) |
+	old_cp = nv_rd32(NV20_PGRAPH_CHANNEL_CTX_POINTER);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	nv_wr32(0x400824, nv_rd32(0x400824) |
 		 (save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
 			 NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
-	NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
+	nv_wr32(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
 
 	for (i = 0; i < tv; i++) {
-		if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
+		if (nv_rd32(NV40_PGRAPH_CTXCTL_030C) == 0)
 			break;
 	}
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
 
 	if (i == tv) {
 		DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save);
 		DRM_ERROR("0x40030C = 0x%08x\n",
-			  NV_READ(NV40_PGRAPH_CTXCTL_030C));
+			  nv_rd32(NV40_PGRAPH_CTXCTL_030C));
 		return -EBUSY;
 	}
 
@@ -306,9 +306,9 @@ nv50_graph_load_context(struct nouveau_channel *chan)
 		return ret;
 #endif
 
-	NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
-	NV_WRITE(0x400320, 4);
-	NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31));
+	nv_wr32(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
+	nv_wr32(0x400320, 4);
+	nv_wr32(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31));
 
 	return 0;
 }
diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c
index d76ebf38..e89df2e5 100644
--- a/shared-core/nv50_instmem.c
+++ b/shared-core/nv50_instmem.c
@@ -51,7 +51,7 @@ typedef struct {
 		offset += (g)->im_pramin->start;                  \
 	}                                                         \
 	offset += (o);                                            \
-	NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v));             \
+	nv_wr32(NV_RAMIN + (offset & 0xfffff), (v));             \
 } while(0)
 
 int
@@ -71,7 +71,7 @@ nv50_instmem_init(struct drm_device *dev)
 
 	/* Save state, will restore at takedown. */
 	for (i = 0x1700; i <= 0x1710; i+=4)
-		priv->save1700[(i-0x1700)/4] = NV_READ(i);
+		priv->save1700[(i-0x1700)/4] = nv_rd32(i);
 
 	/* Reserve the last MiB of VRAM, we should probably try to avoid
 	 * setting up the below tables over the top of the VBIOS image at
@@ -86,12 +86,12 @@ nv50_instmem_init(struct drm_device *dev)
 	pt_size  = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size);
 
 	DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset);
-	DRM_DEBUG("    VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8);
+	DRM_DEBUG("    VBIOS image: 0x%08x\n", (nv_rd32(0x619f04)&~0xff)<<8);
 	DRM_DEBUG("  Aperture size: %d MiB\n",
 		  (uint32_t)dev_priv->ramin->size >> 20);
 	DRM_DEBUG("        PT size: %d KiB\n", pt_size >> 10);
 
-	NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
+	nv_wr32(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
 
 	/* Create a fake channel, and use it as our "dummy" channels 0/127.
 	 * The main reason for creating a channel is so we can use the gpuobj
@@ -166,18 +166,18 @@ nv50_instmem_init(struct drm_device *dev)
 	BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
 
 	/* Poke the relevant regs, and pray it works :) */
-	NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
-	NV_WRITE(NV50_PUNK_UNK1710, 0);
-	NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
+	nv_wr32(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
+	nv_wr32(NV50_PUNK_UNK1710, 0);
+	nv_wr32(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 					 NV50_PUNK_BAR_CFG_BASE_VALID);
-	NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0);
-	NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
+	nv_wr32(NV50_PUNK_BAR1_CTXDMA, 0);
+	nv_wr32(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 					NV50_PUNK_BAR3_CTXDMA_VALID);
 
 	/* Assume that praying isn't enough, check that we can re-read the
 	 * entire fake channel back from the PRAMIN BAR */
 	for (i = 0; i < c_size; i+=4) {
-		if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) {
+		if (nv_rd32(NV_RAMIN + i) != nv_ri32(i)) {
 			DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i);
 			return -EINVAL;
 		}
@@ -212,7 +212,7 @@ nv50_instmem_takedown(struct drm_device *dev)
 
 	/* Restore state from before init */
 	for (i = 0x1700; i <= 0x1710; i+=4)
-		NV_WRITE(i, priv->save1700[(i-0x1700)/4]);
+		nv_wr32(i, priv->save1700[(i-0x1700)/4]);
 
 	nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
 	nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
@@ -297,12 +297,12 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 		vram += NV50_INSTMEM_PAGE_SIZE;
 	}
 
-	NV_WRITE(0x070000, 0x00000001);
-	while(NV_READ(0x070000) & 1);
-	NV_WRITE(0x100c80, 0x00040001);
-	while(NV_READ(0x100c80) & 1);
-	NV_WRITE(0x100c80, 0x00060001);
-	while(NV_READ(0x100c80) & 1);
+	nv_wr32(0x070000, 0x00000001);
+	while(nv_rd32(0x070000) & 1);
+	nv_wr32(0x100c80, 0x00040001);
+	while(nv_rd32(0x100c80) & 1);
+	nv_wr32(0x100c80, 0x00060001);
+	while(nv_rd32(0x100c80) & 1);
 
 	gpuobj->im_bound = 1;
 	return 0;
diff --git a/shared-core/nv50_mc.c b/shared-core/nv50_mc.c
index b111826b..0843473c 100644
--- a/shared-core/nv50_mc.c
+++ b/shared-core/nv50_mc.c
@@ -33,7 +33,7 @@ nv50_mc_init(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
+	nv_wr32(NV03_PMC_ENABLE, 0xFFFFFFFF);
 
 	return 0;
 }