CHV: Add cherryview support in the runtime.

Cherryview's EU configurations is not decided by pciid, must get from kernel by libdrm.
Thanks for Jeff adding this support in the kernel and libdrm.

V2: Add the warning when can't get configurations.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>

7 files changed, 71 insertions, 7 deletions

diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c
index 711b9439..f8d89e06 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -1136,13 +1136,13 @@ int gen_disasm (FILE *file, const void *inst, uint32_t deviceID, uint32_t compac
 {
   int err = 0;
   int space = 0;
-  if (IS_IVYBRIDGE(deviceID)) {
+  if (IS_GEN7(deviceID)) {
     gen_version = 70;
-  } else if (IS_HASWELL(deviceID)) {
+  } else if (IS_GEN75(deviceID)) {
     gen_version = 75;
-  } else if (IS_BROADWELL(deviceID)) {
+  } else if (IS_GEN8(deviceID)) {
     gen_version = 80;
-  } else if (IS_SKYLAKE(deviceID)) {
+  } else if (IS_GEN9(deviceID)) {
     gen_version = 90;
   }
 
diff --git a/backend/src/backend/gen_program.cpp b/backend/src/backend/gen_program.cpp
index f4c74f86..f53d5fb6 100644
--- a/backend/src/backend/gen_program.cpp
+++ b/backend/src/backend/gen_program.cpp
@@ -166,6 +166,8 @@ namespace gbe {
       ctx = GBE_NEW(Gen75Context, unit, name, deviceID, relaxMath);
     } else if (IS_BROADWELL(deviceID)) {
       ctx = GBE_NEW(Gen8Context, unit, name, deviceID, relaxMath);
+    } else if (IS_CHERRYVIEW(deviceID)) {
+      ctx = GBE_NEW(Gen8Context, unit, name, deviceID, relaxMath);
     } else if (IS_SKYLAKE(deviceID)) {
       ctx = GBE_NEW(Gen9Context, unit, name, deviceID, relaxMath);
     }
@@ -210,6 +212,7 @@ namespace gbe {
                                       (IS_BAYTRAIL_T(typeA) && !strcmp(src_hw_info, "BYT")) ||  \
                                       (IS_HASWELL(typeA) && !strcmp(src_hw_info, "HSW")) ||  \
                                       (IS_BROADWELL(typeA) && !strcmp(src_hw_info, "BDW")) ||  \
+                                      (IS_CHERRYVIEW(typeA) && !strcmp(src_hw_info, "CHV")) ||  \
                                       (IS_SKYLAKE(typeA) && !strcmp(src_hw_info, "SKL")) )
 
   static gbe_program genProgramNewFromBinary(uint32_t deviceID, const char *binary, size_t size) {
@@ -316,6 +319,10 @@ namespace gbe {
         src_hw_info[0]='B';
         src_hw_info[1]='D';
         src_hw_info[2]='W';
+      }else if(IS_CHERRYVIEW(prog->deviceID)){
+        src_hw_info[0]='C';
+        src_hw_info[1]='H';
+        src_hw_info[2]='V';
       }else if(IS_SKYLAKE(prog->deviceID)){
         src_hw_info[0]='S';
         src_hw_info[1]='K';
diff --git a/backend/src/gbe_bin_generater.cpp b/backend/src/gbe_bin_generater.cpp
index 8d411137..86197e19 100644
--- a/backend/src/gbe_bin_generater.cpp
+++ b/backend/src/gbe_bin_generater.cpp
@@ -178,6 +178,10 @@ void program_build_instance::serialize_program(void) throw(int)
         src_hw_info[0]='B';
         src_hw_info[1]='D';
         src_hw_info[2]='W';
+    }else if(IS_CHERRYVIEW(gen_pci_id)){
+        src_hw_info[0]='C';
+        src_hw_info[1]='H';
+        src_hw_info[2]='V';
     }else if(IS_SKYLAKE(gen_pci_id)){
         src_hw_info[0]='S';
         src_hw_info[1]='K';
diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index d6f82096..b7b64c04 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -228,7 +228,18 @@
    devid == PCI_CHIP_BROADWLL_U_GT3)
 
 #define IS_BROADWELL(devid) (IS_BRW_GT1(devid) || IS_BRW_GT2(devid) || IS_BRW_GT3(devid))
-#define IS_GEN8(devid)      IS_BROADWELL(devid)
+
+#define PCI_CHIP_CHV_0 0x22B0
+#define PCI_CHIP_CHV_1 0x22B1
+#define PCI_CHIP_CHV_2 0x22B2
+#define PCI_CHIP_CHV_3 0x22B3
+#define IS_CHERRYVIEW(devid) \
+  (devid == PCI_CHIP_CHV_0 ||   \
+   devid == PCI_CHIP_CHV_1 || \
+   devid == PCI_CHIP_CHV_2 || \
+   devid == PCI_CHIP_CHV_3)
+
+#define IS_GEN8(devid)      (IS_BROADWELL(devid) || IS_CHERRYVIEW(devid))
 
 /* SKL */
 #define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906   /* Intel(R) Skylake ULT - GT1 */
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index fefcef3d..6aa6b3b3 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -140,6 +140,18 @@ static struct _cl_device_id intel_brw_gt3_device = {
 #include "cl_gen75_device.h"
 };
 
+//Cherryview has the same pciid, must get the max_compute_unit and max_thread_per_unit from drm
+static struct _cl_device_id intel_chv_device = {
+  INIT_ICD(dispatch)
+  .max_compute_unit = 8,
+  .max_thread_per_unit = 7,
+  .sub_slice_count = 2,
+  .max_work_item_sizes = {512, 512, 512},
+  .max_work_group_size = 512,
+  .max_clock_frequency = 1000,
+#include "cl_gen75_device.h"
+};
+
 /* XXX we clone brw now */
 static struct _cl_device_id intel_skl_gt1_device = {
   INIT_ICD(dispatch)
@@ -423,6 +435,18 @@ brw_gt3_break:
       ret = &intel_brw_gt3_device;
       break;
 
+    case PCI_CHIP_CHV_0:
+    case PCI_CHIP_CHV_1:
+    case PCI_CHIP_CHV_2:
+    case PCI_CHIP_CHV_3:
+      DECL_INFO_STRING(chv_break, intel_chv_device, name, "Intel(R) HD Graphics Cherryview");
+chv_break:
+      intel_chv_device.vendor_id = device_id;
+      intel_chv_device.platform = intel_platform;
+      ret = &intel_chv_device;
+      break;
+
+
 	  case PCI_CHIP_SKYLAKE_ULT_GT1:
 		DECL_INFO_STRING(skl_gt1_break, intel_skl_gt1_device, name, "Intel(R) HD Graphics Skylake ULT GT1");
 	  case PCI_CHIP_SKYLAKE_ULX_GT1:
@@ -590,6 +614,7 @@ cl_get_device_info(cl_device_id     device,
                device != &intel_brw_gt1_device &&
                device != &intel_brw_gt2_device &&
                device != &intel_brw_gt3_device &&
+               device != &intel_chv_device &&
                device != &intel_skl_gt1_device &&
                device != &intel_skl_gt2_device &&
                device != &intel_skl_gt3_device &&
@@ -699,6 +724,7 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
                device != &intel_brw_gt1_device &&
                device != &intel_brw_gt2_device &&
                device != &intel_brw_gt3_device &&
+               device != &intel_chv_device &&
                device != &intel_skl_gt1_device &&
                device != &intel_skl_gt2_device &&
                device != &intel_skl_gt3_device &&
@@ -714,7 +740,7 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
         || device == &intel_hsw_gt3_device) {
     *ver = 75;
   } else if (device == &intel_brw_gt1_device || device == &intel_brw_gt2_device
-        || device == &intel_brw_gt3_device) {
+        || device == &intel_brw_gt3_device || device == &intel_chv_device) {
     *ver = 8;
   } else if (device == &intel_skl_gt1_device || device == &intel_skl_gt2_device
         || device == &intel_skl_gt3_device || device == &intel_skl_gt4_device) {
@@ -801,6 +827,7 @@ cl_get_kernel_workgroup_info(cl_kernel kernel,
                device != &intel_brw_gt1_device &&
                device != &intel_brw_gt2_device &&
                device != &intel_brw_gt3_device &&
+               device != &intel_chv_device &&
                device != &intel_skl_gt1_device &&
                device != &intel_skl_gt2_device &&
                device != &intel_skl_gt3_device &&
diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
index 5adf09bc..1bebd9a3 100644
--- a/src/intel/intel_driver.c
+++ b/src/intel/intel_driver.c
@@ -764,6 +764,8 @@ static int intel_buffer_set_tiling(cl_buffer bo,
   return ret;
 }
 
+#define CHV_CONFIG_WARNING \
+        "Warning: can't get GPU's configurations, will use the minimal one. Please update your drm to 2.4.59+ and linux kernel to 4.0.0+.\n"
 static void
 intel_update_device_info(cl_device_id device)
 {
@@ -800,6 +802,11 @@ intel_update_device_info(cl_device_id device)
   /* Prefer driver-queried max compute units if supported */
   if (!drm_intel_get_eu_total(driver->fd, &eu_total))
     device->max_compute_unit = eu_total;
+  else if (IS_CHERRYVIEW(device->vendor_id))
+    printf(CHV_CONFIG_WARNING);
+#else
+  if (IS_CHERRYVIEW(device->vendor_id))
+    printf(CHV_CONFIG_WARNING);
 #endif
 
 #ifdef HAS_SUBSLICE_TOTAL
@@ -808,6 +815,11 @@ intel_update_device_info(cl_device_id device)
   /* Prefer driver-queried subslice count if supported */
   if (!drm_intel_get_subslice_total(driver->fd, &subslice_total))
     device->sub_slice_count = subslice_total;
+  else if (IS_CHERRYVIEW(device->vendor_id))
+    printf(CHV_CONFIG_WARNING);
+#else
+  if (IS_CHERRYVIEW(device->vendor_id))
+    printf(CHV_CONFIG_WARNING);
 #endif
 
   intel_driver_context_destroy(driver);
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 3bb494e1..ab4545e0 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -1135,6 +1135,7 @@ static uint32_t get_surface_type(intel_gpgpu_t *gpgpu, int index, cl_mem_object_
   if (((IS_IVYBRIDGE(gpgpu->drv->device_id) ||
         IS_HASWELL(gpgpu->drv->device_id) ||
         IS_BROADWELL(gpgpu->drv->device_id) ||
+        IS_CHERRYVIEW(gpgpu->drv->device_id) ||
         IS_SKYLAKE(gpgpu->drv->device_id))) &&
       index >= BTI_WORKAROUND_IMAGE_OFFSET + BTI_RESERVED_NUM &&
       type == CL_MEM_OBJECT_IMAGE1D_ARRAY)
@@ -2149,13 +2150,15 @@ intel_set_gpgpu_callbacks(int device_id)
   cl_gpgpu_set_printf_info = (cl_gpgpu_set_printf_info_cb *)intel_gpgpu_set_printf_info;
   cl_gpgpu_get_printf_info = (cl_gpgpu_get_printf_info_cb *)intel_gpgpu_get_printf_info;
 
-  if (IS_BROADWELL(device_id)) {
+  if (IS_BROADWELL(device_id) || IS_CHERRYVIEW(device_id)) {
     cl_gpgpu_bind_image = (cl_gpgpu_bind_image_cb *) intel_gpgpu_bind_image_gen8;
     intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen8;
     cl_gpgpu_get_cache_ctrl = (cl_gpgpu_get_cache_ctrl_cb *)intel_gpgpu_get_cache_ctrl_gen8;
     intel_gpgpu_get_scratch_index = intel_gpgpu_get_scratch_index_gen8;
     intel_gpgpu_post_action = intel_gpgpu_post_action_gen7; //BDW need not restore SLM, same as gen7
     intel_gpgpu_read_ts_reg = intel_gpgpu_read_ts_reg_gen7;
+    if(IS_CHERRYVIEW(device_id))
+      intel_gpgpu_read_ts_reg = intel_gpgpu_read_ts_reg_baytrail;
     intel_gpgpu_set_base_address = intel_gpgpu_set_base_address_gen8;
     intel_gpgpu_setup_bti = intel_gpgpu_setup_bti_gen8;
     intel_gpgpu_load_vfe_state = intel_gpgpu_load_vfe_state_gen8;