diff options
| author | Ruiling Song <ruiling.song@intel.com> | 2014-07-14 17:24:37 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-07-15 09:02:35 +0800 |
| commit | 080eff26694e3dd34c99012efd5b79d8e3c176ed (patch) | |
| tree | cd7605483707c1735559c6c5431ffa19dbe93eb3 | |
| parent | 9c469bc4b6319debde6d0264c1aacaee71eb076d (diff) | |
GBE: Use varying register to save one instruction
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 2a2476e0..4d356520 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2804,12 +2804,11 @@ namespace gbe GBE_ASSERT(elemSize == GEN_BYTE_SCATTER_WORD || elemSize == GEN_BYTE_SCATTER_BYTE); Register tmpReg = sel.reg(FAMILY_DWORD, simdWidth == 1); - GenRegister tmpAddr = GenRegister::udxgrf(simdWidth, sel.reg(FAMILY_DWORD, simdWidth == 1)); + GenRegister tmpAddr = GenRegister::udxgrf(simdWidth, sel.reg(FAMILY_DWORD)); GenRegister tmpData = GenRegister::udxgrf(simdWidth, tmpReg); // Get dword aligned addr sel.push(); if (simdWidth == 1) { - sel.curr.execWidth = 1; sel.curr.noMask = 1; } sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UD), GenRegister::immud(0xfffffffc)); |